Difference between revisions of "Address Card firmware"

From MCEWiki
(→‎Revision 2.0.9)
 
(28 intermediate revisions by 5 users not shown)
Line 1: Line 1:
−
= Recommended Firmware Revisions =
+
{{Related|Address Card Firmware}}
−
* Please see the [http://e-mode.phas.ubc.ca/mcewiki/index.php/Compatible_Versions_(CC,RC,BC,AC) recommend firmware revisions] page.
+
* [[Pre-v5 firmware#Address Card|Pre-v5 firmware]]
  
 
= Firmware Revision Listing =
 
= Firmware Revision Listing =
−
== Revision 5.0.1 ==
+
== Revision 6.0.1 ==
−
* '''Filename:'''  ac_v05000001_14sep2009.sof
+
;Filename
 +
: ac_v06000001_20160408.sof
 +
: ac_v06000001_20160408.pof
 +
;Features
 +
: added 64-element rb/wb suuport by introducing virtual card-ids. When the virtual card_id is used, a tga offset of 32 is applied when writing to a parameter id.
 +
: also merged some of the changes in ac 5.0.3 to optimize logic utilization
 +
== Revision 5.0.4 (Stable) ==
 +
* '''Filename:'''  ac_v05000004_16feb2010.sof
 +
 
 +
* '''Features:'''
 +
** Based on 5.0.0 with added support for new temperature chip (max1618) installed on Rev. D Address cards.
 +
** temporary release, better apply this patch to rev. 5.0.3 after testing 5.0.3.
 +
** missing scuba2 heater commands
 +
 
 +
* '''Bugs:'''
 +
** None yet reported
 +
 
 +
* '''FPGA Resource Usage''' (addr_card.fit.rpt):
 +
 
 +
== Revision 5.0.3 (test) ==
 +
* '''Filename:'''  ac_v05000003_19nov2009.sof
  
 
* '''To Do:'''
 
* '''To Do:'''
Line 10: Line 30:
  
 
* '''Features:'''
 
* '''Features:'''
−
** The resource usage on the AC has now reached a level where there isn't enough left to implement Signal Tap.  To enable SignalTap, comment out the largest usage of RAM/LE's: "ram : tpram_32bit_x_64" in ac_dac_ctrl.vhd.  Remember to uncomment this when running the final synthesis before committal.
+
** Based on both ac v5.0.2 and v2.0.a
−
** Based on ac_v5.0.0.
+
** Reduces the usage of RAM and Logic Elements in the design so that there is margin for new features and space for SignalTap
−
** Implements the bias_start command for different bias heating across rows on SCUBA2 arrays.
 
 
** IMPORTANT:  Must be used in conjunction with firmware v05000000+ of all other cards.
 
** IMPORTANT:  Must be used in conjunction with firmware v05000000+ of all other cards.
  
 
* '''Details:'''
 
* '''Details:'''
−
** Differences between ac_v5.0.0 and ac_v5.0.1
+
** Differences between ac_v5.0.2 and ac_v5.0.3
−
  U system/test/source/tb/tb_cc_rcs_bcs_ac.vhd
+
  addr_card.vhd
−
U addr_card/ac_dac_ctrl/source/rtl/ac_dac_ctrl.vhd
+
  ac_dac_ctrl.vhd
−
  U addr_card/ac_dac_ctrl/source/rtl/ac_dac_ctrl_pack.vhd
 
−
U addr_card/addr_card/source/rtl/addr_card.vhd
 
−
U addr_card/addr_card/source/rtl/addr_card_self_test.vhd
 
−
U addr_card/addr_card/synth/addr_card.fit.rpt
 
−
U addr_card/addr_card/synth/addr_card.fit.summary
 
−
U addr_card/addr_card/synth/addr_card.map.rpt
 
−
U addr_card/addr_card/synth/addr_card.qsf
 
−
U addr_card/addr_card/synth/addr_card.sof
 
−
U addr_card/addr_card/synth/addr_card.tan.rpt
 
−
U addr_card/addr_card/synth/addr_card.tan.summary
 
−
U all_cards/all_cards/source/rtl/all_cards_pack.vhd
 
−
U all_cards/async/source/rtl/async_pack.vhd
 
−
U all_cards/async/source/rtl/lvds_rx.vhd
 
−
U all_cards/dispatch/source/rtl/dispatch.vhd
 
−
U all_cards/dispatch/source/rtl/dispatch_cmd_receive.vhd
 
−
U all_cards/frame_timing/source/rtl/frame_timing.vhd
 
−
U all_cards/frame_timing/source/rtl/frame_timing_core.vhd
 
−
U all_cards/frame_timing/source/rtl/frame_timing_pack.vhd
 
−
U library/sys_param/source/rtl/data_types_pack.vhd
 
−
U library/sys_param/source/rtl/wishbone_pack.vhd
 
  
 
* '''Bugs:'''
 
* '''Bugs:'''
−
** None yet reported
+
** does not support new temperature chip on Rev. D address Cards. (Max1618)
  
 
* '''FPGA Resource Usage''' (addr_card.fit.rpt):
 
* '''FPGA Resource Usage''' (addr_card.fit.rpt):
Line 47: Line 46:
 
  ; Fitter Summary                                                          ;
 
  ; Fitter Summary                                                          ;
 
  +--------------------------+-----------------------------------------------+
 
  +--------------------------+-----------------------------------------------+
−
  ; Fitter Status            ; Successful - Mon Sep 14 13:46:41 2009        ;
+
  ; Fitter Status            ; Successful - Thu Nov 19 11:48:29 2009        ;
 
  ; Quartus II Version      ; 9.0 Build 235 06/17/2009 SP 2 SJ Full Version ;
 
  ; Quartus II Version      ; 9.0 Build 235 06/17/2009 SP 2 SJ Full Version ;
 
  ; Revision Name            ; addr_card                                    ;
 
  ; Revision Name            ; addr_card                                    ;
Line 54: Line 53:
 
  ; Device                  ; EP1S10F780C5                                  ;
 
  ; Device                  ; EP1S10F780C5                                  ;
 
  ; Timing Models            ; Final                                        ;
 
  ; Timing Models            ; Final                                        ;
−
  ; Total logic elements    ; 9,370 / 10,570 ( 89 % )                      ;
+
  ; Total logic elements    ; 7,324 / 10,570 ( 69 % )                      ;
 
  ; Total pins              ; 279 / 427 ( 65 % )                            ;
 
  ; Total pins              ; 279 / 427 ( 65 % )                            ;
 
  ; Total virtual pins      ; 0                                            ;
 
  ; Total virtual pins      ; 0                                            ;
−
  ; Total memory bits        ; 199,168 / 920,448 ( 22 % )                    ;
+
  ; Total memory bits        ; 135,808 / 920,448 ( 15 % )                    ;
 
  ; DSP block 9-bit elements ; 8 / 48 ( 17 % )                              ;
 
  ; DSP block 9-bit elements ; 8 / 48 ( 17 % )                              ;
 
  ; Total PLLs              ; 1 / 6 ( 17 % )                                ;
 
  ; Total PLLs              ; 1 / 6 ( 17 % )                                ;
Line 72: Line 71:
 
  ; Worst-case tco                                          ; N/A      ;
 
  ; Worst-case tco                                          ; N/A      ;
 
  ; Worst-case th                                            ; N/A      ;
 
  ; Worst-case th                                            ; N/A      ;
−
  ; Clock Setup: 'ac_pll:pll0|altpll:altpll_component|_clk0' ; 3.361 ns ;
+
  ; Clock Setup: 'ac_pll:pll0|altpll:altpll_component|_clk0' ; 2.853 ns ;
−
  ; Clock Setup: 'ac_pll:pll0|altpll:altpll_component|_clk2' ; 4.142 ns ;
+
  ; Clock Setup: 'ac_pll:pll0|altpll:altpll_component|_clk2' ; 3.742 ns ;
−
  ; Clock Hold: 'ac_pll:pll0|altpll:altpll_component|_clk0'  ; 0.528 ns ;
+
  ; Clock Hold: 'ac_pll:pll0|altpll:altpll_component|_clk0'  ; 0.531 ns ;
−
  ; Clock Hold: 'ac_pll:pll0|altpll:altpll_component|_clk2'  ; 0.562 ns ;
+
  ; Clock Hold: 'ac_pll:pll0|altpll:altpll_component|_clk2'  ; 0.556 ns ;
−
  ; Total number of failed paths                            ;          ;  
+
  ; Total number of failed paths                            ;          ;
 
  +----------------------------------------------------------+----------+
 
  +----------------------------------------------------------+----------+
  
−
== Revision 5.0.0 ==
+
== Revision 5.0.2 ==
−
* '''Filename:'''  ac_v05000000_22dec2008.sof (tagged as sys_v05000000_22dec2008)
+
* '''Filename:'''  ac_v05000002_16oct2009.sof
  
 
* '''To Do:'''
 
* '''To Do:'''
Line 86: Line 85:
  
 
* '''Features:'''
 
* '''Features:'''
 +
** Based on ac_v5.0.1
 +
** Adds HEATER_BIAS and HEATER_BIAS_LEN parameters for Tc-flattening on SCUBA-2.
 
** IMPORTANT:  Must be used in conjunction with firmware v05000000+ of all other cards.
 
** IMPORTANT:  Must be used in conjunction with firmware v05000000+ of all other cards.
−
** To increase data bandwidth, the spare LVDS line from each card to the Clock Card is now used
 
  
 
* '''Details:'''
 
* '''Details:'''
−
** ---
 
−
 
 
* '''Bugs:'''
 
* '''Bugs:'''
 
** None yet reported
 
** None yet reported
  
 
* '''FPGA Resource Usage''' (addr_card.fit.rpt):
 
* '''FPGA Resource Usage''' (addr_card.fit.rpt):
−
  +---------------------------------------------------------------------+
+
  +--------------------------------------------------------------------------+
−
  ; Fitter Summary                                                     ;
+
  ; Fitter Summary                                                           ;
−
  +--------------------------+------------------------------------------+
+
  +--------------------------+-----------------------------------------------+
−
  ; Fitter Status            ; Successful - Tue Jan 13 16:19:16 2009   ;
+
  ; Fitter Status            ; Successful - Fri Oct 16 16:41:47 2009         ;
−
  ; Quartus II Version      ; 8.1 Build 163 10/28/2008 SJ Full Version ;
+
  ; Quartus II Version      ; 9.0 Build 235 06/17/2009 SP 2 SJ Full Version ;
−
  ; Revision Name            ; addr_card                               ;
+
  ; Revision Name            ; addr_card                                     ;
−
  ; Top-level Entity Name    ; addr_card                               ;
+
  ; Top-level Entity Name    ; addr_card                                     ;
−
  ; Family                  ; Stratix                                 ;
+
  ; Family                  ; Stratix                                       ;
−
  ; Device                  ; EP1S10F780C5                             ;
+
  ; Device                  ; EP1S10F780C5                                 ;
−
  ; Timing Models            ; Final                                   ;
+
  ; Timing Models            ; Final                                         ;
−
  ; Total logic elements    ; 9,383 / 10,570 ( 89 % )                 ;
+
  ; Total logic elements    ; 10,524 / 10,570 ( 100 % )                     ;
−
  ; Total pins              ; 279 / 427 ( 65 % )                       ;
+
  ; Total pins              ; 279 / 427 ( 65 % )                           ;
−
  ; Total virtual pins      ; 0                                       ;
+
  ; Total virtual pins      ; 0                                             ;
−
  ; Total memory bits        ; 196,096 / 920,448 ( 21 % )               ;
+
  ; Total memory bits        ; 199,168 / 920,448 ( 22 % )                   ;
−
  ; DSP block 9-bit elements ; 8 / 48 ( 17 % )                         ;
+
  ; DSP block 9-bit elements ; 8 / 48 ( 17 % )                               ;
−
  ; Total PLLs              ; 1 / 6 ( 17 % )                           ;
+
  ; Total PLLs              ; 1 / 6 ( 17 % )                               ;
−
  ; Total DLLs              ; 0 / 2 ( 0 % )                           ;
+
  ; Total DLLs              ; 0 / 2 ( 0 % )                                 ;
−
  +--------------------------+------------------------------------------+
+
  +--------------------------+-----------------------------------------------+
  
 
* '''Timing Analyzer Summary''' (addr_card.tan.rpt):
 
* '''Timing Analyzer Summary''' (addr_card.tan.rpt):
Line 124: Line 122:
 
  ; Worst-case tco                                          ; N/A      ;
 
  ; Worst-case tco                                          ; N/A      ;
 
  ; Worst-case th                                            ; N/A      ;
 
  ; Worst-case th                                            ; N/A      ;
−
  ; Clock Setup: 'ac_pll:pll0|altpll:altpll_component|_clk0' ; 2.617 ns ;
+
  ; Clock Setup: 'ac_pll:pll0|altpll:altpll_component|_clk0' ; 2.267 ns ;
−
  ; Clock Setup: 'ac_pll:pll0|altpll:altpll_component|_clk2' ; 4.588 ns ;
+
  ; Clock Setup: 'ac_pll:pll0|altpll:altpll_component|_clk2' ; 3.582 ns ;
−
  ; Clock Hold: 'ac_pll:pll0|altpll:altpll_component|_clk0'  ; 0.539 ns ;
+
  ; Clock Hold: 'ac_pll:pll0|altpll:altpll_component|_clk0'  ; 0.538 ns ;
−
  ; Clock Hold: 'ac_pll:pll0|altpll:altpll_component|_clk2'  ; 0.658 ns ;
+
  ; Clock Hold: 'ac_pll:pll0|altpll:altpll_component|_clk2'  ; 0.665 ns ;
 
  ; Total number of failed paths                            ;          ;
 
  ; Total number of failed paths                            ;          ;
 
  +----------------------------------------------------------+----------+
 
  +----------------------------------------------------------+----------+
  
−
== Revision 2.0.10 (2.0.a) ==
+
== Revision 5.0.1 ==
−
* '''Filename:'''  ac_v02000008_16sep2009.sof
+
* '''Filename:'''  ac_v05000001_14sep2009.sof
  
 
* '''To Do:'''
 
* '''To Do:'''
Line 138: Line 136:
  
 
* '''Features:'''
 
* '''Features:'''
−
** Based on ac_v2.0.8
+
** The resource usage on the AC has now reached a level where there isn't enough left to implement Signal Tap.  To enable SignalTap, comment out the largest usage of RAM/LE's: "ram : tpram_32bit_x_64" in ac_dac_ctrl.vhd.  Remember to uncomment this when running the final synthesis before committal.
−
** Adds the BIAS_START parameter for delaying the application of the ON_BIAS when ENBL_MUX = 1.
+
** Based on ac_v5.0.0.
−
** Adds a new multplexing mode mode (ENBL_MUX = 3) that allows users to apply a gradient of heater biases across the MUX wafer using the HEATER_BIAS and HEATER_BIAS_LEN parameters.
+
** Implements the bias_start command for different bias heating across rows on SCUBA2 arrays.
 +
** IMPORTANT:  Must be used in conjunction with firmware v05000000+ of all other cards.
  
 
* '''Details:'''
 
* '''Details:'''
 +
** Differences between ac_v5.0.0 and ac_v5.0.1
 +
U system/test/source/tb/tb_cc_rcs_bcs_ac.vhd
 +
U addr_card/ac_dac_ctrl/source/rtl/ac_dac_ctrl.vhd
 +
U addr_card/ac_dac_ctrl/source/rtl/ac_dac_ctrl_pack.vhd
 +
U addr_card/addr_card/source/rtl/addr_card.vhd
 +
U addr_card/addr_card/source/rtl/addr_card_self_test.vhd
 +
U addr_card/addr_card/synth/addr_card.fit.rpt
 +
U addr_card/addr_card/synth/addr_card.fit.summary
 +
U addr_card/addr_card/synth/addr_card.map.rpt
 +
U addr_card/addr_card/synth/addr_card.qsf
 +
U addr_card/addr_card/synth/addr_card.sof
 +
U addr_card/addr_card/synth/addr_card.tan.rpt
 +
U addr_card/addr_card/synth/addr_card.tan.summary
 +
U all_cards/all_cards/source/rtl/all_cards_pack.vhd
 +
U all_cards/async/source/rtl/async_pack.vhd
 +
U all_cards/async/source/rtl/lvds_rx.vhd
 +
U all_cards/dispatch/source/rtl/dispatch.vhd
 +
U all_cards/dispatch/source/rtl/dispatch_cmd_receive.vhd
 +
U all_cards/frame_timing/source/rtl/frame_timing.vhd
 +
U all_cards/frame_timing/source/rtl/frame_timing_core.vhd
 +
U all_cards/frame_timing/source/rtl/frame_timing_pack.vhd
 +
U library/sys_param/source/rtl/data_types_pack.vhd
 +
U library/sys_param/source/rtl/wishbone_pack.vhd
  
 
* '''Bugs:'''
 
* '''Bugs:'''
Line 151: Line 173:
 
  ; Fitter Summary                                                          ;
 
  ; Fitter Summary                                                          ;
 
  +--------------------------+-----------------------------------------------+
 
  +--------------------------+-----------------------------------------------+
−
  ; Fitter Status            ; Successful - Fri Oct 16 11:52:16 2009        ;
+
  ; Fitter Status            ; Successful - Mon Sep 14 13:46:41 2009        ;
 
  ; Quartus II Version      ; 9.0 Build 235 06/17/2009 SP 2 SJ Full Version ;
 
  ; Quartus II Version      ; 9.0 Build 235 06/17/2009 SP 2 SJ Full Version ;
 
  ; Revision Name            ; addr_card                                    ;
 
  ; Revision Name            ; addr_card                                    ;
Line 158: Line 180:
 
  ; Device                  ; EP1S10F780C5                                  ;
 
  ; Device                  ; EP1S10F780C5                                  ;
 
  ; Timing Models            ; Final                                        ;
 
  ; Timing Models            ; Final                                        ;
−
  ; Total logic elements    ; 10,349 / 10,570 ( 98 % )                     ;
+
  ; Total logic elements    ; 9,370 / 10,570 ( 89 % )                       ;
 
  ; Total pins              ; 279 / 427 ( 65 % )                            ;
 
  ; Total pins              ; 279 / 427 ( 65 % )                            ;
 
  ; Total virtual pins      ; 0                                            ;
 
  ; Total virtual pins      ; 0                                            ;
−
  ; Total memory bits        ; 198,656 / 920,448 ( 22 % )                    ;
+
  ; Total memory bits        ; 199,168 / 920,448 ( 22 % )                    ;
 
  ; DSP block 9-bit elements ; 8 / 48 ( 17 % )                              ;
 
  ; DSP block 9-bit elements ; 8 / 48 ( 17 % )                              ;
 
  ; Total PLLs              ; 1 / 6 ( 17 % )                                ;
 
  ; Total PLLs              ; 1 / 6 ( 17 % )                                ;
Line 176: Line 198:
 
  ; Worst-case tco                                          ; N/A      ;
 
  ; Worst-case tco                                          ; N/A      ;
 
  ; Worst-case th                                            ; N/A      ;
 
  ; Worst-case th                                            ; N/A      ;
−
  ; Clock Setup: 'ac_pll:pll0|altpll:altpll_component|_clk0' ; 3.053 ns ;
+
  ; Clock Setup: 'ac_pll:pll0|altpll:altpll_component|_clk0' ; 3.361 ns ;
−
  ; Clock Setup: 'ac_pll:pll0|altpll:altpll_component|_clk2' ; 3.790 ns ;
+
  ; Clock Setup: 'ac_pll:pll0|altpll:altpll_component|_clk2' ; 4.142 ns ;
−
  ; Clock Hold: 'ac_pll:pll0|altpll:altpll_component|_clk2'  ; 0.540 ns ;
+
  ; Clock Hold: 'ac_pll:pll0|altpll:altpll_component|_clk0'  ; 0.528 ns ;
−
  ; Clock Hold: 'ac_pll:pll0|altpll:altpll_component|_clk0'  ; 0.542 ns ;
+
  ; Clock Hold: 'ac_pll:pll0|altpll:altpll_component|_clk2'  ; 0.562 ns ;
 
  ; Total number of failed paths                            ;          ;  
 
  ; Total number of failed paths                            ;          ;  
 
  +----------------------------------------------------------+----------+
 
  +----------------------------------------------------------+----------+
  
−
== Revision 2.0.8 ==
+
== Revision 5.0.0 ==
−
* '''Filename:'''  ac_v02000008_16sep2009.sof
+
* '''Filename:'''  ac_v05000000_22dec2008.sof (tagged as sys_v05000000_22dec2008)
  
 
* '''To Do:'''
 
* '''To Do:'''
Line 190: Line 212:
  
 
* '''Features:'''
 
* '''Features:'''
−
** Based on ac_v2.0.7
+
** IMPORTANT:  Must be used in conjunction with firmware v05000000+ of all other cards.
−
** Implements the bias_start command for different bias heating across rows on SCUBA2 arrays.
+
** To increase data bandwidth, the spare LVDS line from each card to the Clock Card is now used
  
 
* '''Details:'''
 
* '''Details:'''
−
** Differences between ac_v2.0.7 and ac_v2.0.8
+
** ---
−
U system/test/source/tb/tb_cc_rcs_bcs_ac.vhd
 
−
U addr_card/ac_dac_ctrl/source/rtl/ac_dac_ctrl.vhd
 
−
U addr_card/ac_dac_ctrl/source/rtl/ac_dac_ctrl_pack.vhd
 
−
U addr_card/addr_card/source/rtl/addr_card.vhd
 
−
U addr_card/addr_card/source/rtl/addr_card_self_test.vhd
 
−
U addr_card/addr_card/synth/addr_card.fit.rpt
 
−
U addr_card/addr_card/synth/addr_card.fit.summary
 
−
U addr_card/addr_card/synth/addr_card.map.rpt
 
−
C addr_card/addr_card/synth/addr_card.qws
 
−
U addr_card/addr_card/synth/addr_card.qsf
 
−
U addr_card/addr_card/synth/addr_card.sof
 
−
U addr_card/addr_card/synth/addr_card.tan.rpt
 
−
U addr_card/addr_card/synth/addr_card.tan.summary
 
−
U all_cards/all_cards/source/rtl/all_cards.vhd
 
−
U all_cards/all_cards/source/rtl/all_cards_pack.vhd
 
−
U all_cards/frame_timing/source/rtl/frame_timing.vhd
 
−
U all_cards/frame_timing/source/rtl/frame_timing_core.vhd
 
−
U all_cards/frame_timing/source/rtl/frame_timing_pack.vhd
 
−
U all_cards/frame_timing/source/rtl/frame_timing_wbs.vhd
 
−
U library/components/source/rtl/parallel_crc.vhd
 
−
U library/sys_param/source/rtl/data_types_pack.vhd
 
−
U library/sys_param/source/rtl/wishbone_pack.vhd
 
  
 
* '''Bugs:'''
 
* '''Bugs:'''
Line 225: Line 225:
 
  ; Fitter Summary                                                      ;
 
  ; Fitter Summary                                                      ;
 
  +--------------------------+------------------------------------------+
 
  +--------------------------+------------------------------------------+
−
  ; Fitter Status            ; Successful - Wed Sep 16 13:03:57 2009    ;
+
  ; Fitter Status            ; Successful - Tue Jan 13 16:19:16 2009    ;
 
  ; Quartus II Version      ; 8.1 Build 163 10/28/2008 SJ Full Version ;
 
  ; Quartus II Version      ; 8.1 Build 163 10/28/2008 SJ Full Version ;
 
  ; Revision Name            ; addr_card                                ;
 
  ; Revision Name            ; addr_card                                ;
Line 232: Line 232:
 
  ; Device                  ; EP1S10F780C5                            ;
 
  ; Device                  ; EP1S10F780C5                            ;
 
  ; Timing Models            ; Final                                    ;
 
  ; Timing Models            ; Final                                    ;
−
  ; Total logic elements    ; 9,141 / 10,570 ( 86 % )                  ;
+
  ; Total logic elements    ; 9,383 / 10,570 ( 89 % )                  ;
 
  ; Total pins              ; 279 / 427 ( 65 % )                      ;
 
  ; Total pins              ; 279 / 427 ( 65 % )                      ;
 
  ; Total virtual pins      ; 0                                        ;
 
  ; Total virtual pins      ; 0                                        ;
−
  ; Total memory bits        ; 198,656 / 920,448 ( 22 % )              ;
+
  ; Total memory bits        ; 196,096 / 920,448 ( 21 % )              ;
 
  ; DSP block 9-bit elements ; 8 / 48 ( 17 % )                          ;
 
  ; DSP block 9-bit elements ; 8 / 48 ( 17 % )                          ;
 
  ; Total PLLs              ; 1 / 6 ( 17 % )                          ;
 
  ; Total PLLs              ; 1 / 6 ( 17 % )                          ;
Line 250: Line 250:
 
  ; Worst-case tco                                          ; N/A      ;
 
  ; Worst-case tco                                          ; N/A      ;
 
  ; Worst-case th                                            ; N/A      ;
 
  ; Worst-case th                                            ; N/A      ;
−
  ; Clock Setup: 'ac_pll:pll0|altpll:altpll_component|_clk0' ; 1.971 ns ;
+
  ; Clock Setup: 'ac_pll:pll0|altpll:altpll_component|_clk0' ; 2.617 ns ;
−
  ; Clock Setup: 'ac_pll:pll0|altpll:altpll_component|_clk2' ; 4.506 ns ;
+
  ; Clock Setup: 'ac_pll:pll0|altpll:altpll_component|_clk2' ; 4.588 ns ;
 
  ; Clock Hold: 'ac_pll:pll0|altpll:altpll_component|_clk0'  ; 0.539 ns ;
 
  ; Clock Hold: 'ac_pll:pll0|altpll:altpll_component|_clk0'  ; 0.539 ns ;
−
  ; Clock Hold: 'ac_pll:pll0|altpll:altpll_component|_clk2'  ; 0.549 ns ;
+
  ; Clock Hold: 'ac_pll:pll0|altpll:altpll_component|_clk2'  ; 0.658 ns ;
 
  ; Total number of failed paths                            ;          ;
 
  ; Total number of failed paths                            ;          ;
 
  +----------------------------------------------------------+----------+
 
  +----------------------------------------------------------+----------+
  
−
== Revision 2.0.7 ==
+
= Firmware repository =
−
Features:
+
* http://e-mode.phas.ubc.ca/mce_firmware/
−
* Added the const_val39 command to support internal TES Bias ramping
 
−
Bugs:
 
−
* None so far
 
−
 
 
−
= Firmware Links =
 
−
* [http://www.phas.ubc.ca/~mce/mcedocs/firmware/ac_fpga_programming_file_catalogue.pdf  Address Card Firmware Catalog]
 
−
* [http://www.phas.ubc.ca/~mce/mcedocs/firmware/ Firmware Downloads]
 
  
−
== Wiki Links ==
+
[[Category:Address Card Firmware| ]]
−
* [http://e-mode.phas.ubc.ca/mcewiki/index.php/MCE_firmware  MCE Firmware Page]
 
−
* [http://e-mode.phas.ubc.ca/mcewiki/index.php/Main_Page  MCE Main Page]
 

Latest revision as of 17:43, 7 November 2016

Firmware Revision Listing

Revision 6.0.1

Filename
ac_v06000001_20160408.sof
ac_v06000001_20160408.pof
Features
added 64-element rb/wb suuport by introducing virtual card-ids. When the virtual card_id is used, a tga offset of 32 is applied when writing to a parameter id.
also merged some of the changes in ac 5.0.3 to optimize logic utilization

Revision 5.0.4 (Stable)

  • Filename: ac_v05000004_16feb2010.sof
  • Features:
    • Based on 5.0.0 with added support for new temperature chip (max1618) installed on Rev. D Address cards.
    • temporary release, better apply this patch to rev. 5.0.3 after testing 5.0.3.
    • missing scuba2 heater commands
  • Bugs:
    • None yet reported
  • FPGA Resource Usage (addr_card.fit.rpt):

Revision 5.0.3 (test)

  • Filename: ac_v05000003_19nov2009.sof
  • To Do:
    • ---
  • Features:
    • Based on both ac v5.0.2 and v2.0.a
    • Reduces the usage of RAM and Logic Elements in the design so that there is margin for new features and space for SignalTap
    • IMPORTANT: Must be used in conjunction with firmware v05000000+ of all other cards.
  • Details:
    • Differences between ac_v5.0.2 and ac_v5.0.3
addr_card.vhd
ac_dac_ctrl.vhd
  • Bugs:
    • does not support new temperature chip on Rev. D address Cards. (Max1618)
  • FPGA Resource Usage (addr_card.fit.rpt):
+--------------------------------------------------------------------------+
; Fitter Summary                                                           ;
+--------------------------+-----------------------------------------------+
; Fitter Status            ; Successful - Thu Nov 19 11:48:29 2009         ;
; Quartus II Version       ; 9.0 Build 235 06/17/2009 SP 2 SJ Full Version ;
; Revision Name            ; addr_card                                     ;
; Top-level Entity Name    ; addr_card                                     ;
; Family                   ; Stratix                                       ;
; Device                   ; EP1S10F780C5                                  ;
; Timing Models            ; Final                                         ;
; Total logic elements     ; 7,324 / 10,570 ( 69 % )                       ;
; Total pins               ; 279 / 427 ( 65 % )                            ;
; Total virtual pins       ; 0                                             ;
; Total memory bits        ; 135,808 / 920,448 ( 15 % )                    ;
; DSP block 9-bit elements ; 8 / 48 ( 17 % )                               ;
; Total PLLs               ; 1 / 6 ( 17 % )                                ;
; Total DLLs               ; 0 / 2 ( 0 % )                                 ;
+--------------------------+-----------------------------------------------+
  • Timing Analyzer Summary (addr_card.tan.rpt):
+----------------------------------------------------------------------
; Timing Analyzer Summary                                              
+----------------------------------------------------------+----------+
; Type                                                     ; Slack    ;
+----------------------------------------------------------+----------+
; Worst-case tsu                                           ; N/A      ;
; Worst-case tco                                           ; N/A      ;
; Worst-case th                                            ; N/A      ;
; Clock Setup: 'ac_pll:pll0|altpll:altpll_component|_clk0' ; 2.853 ns ;
; Clock Setup: 'ac_pll:pll0|altpll:altpll_component|_clk2' ; 3.742 ns ;
; Clock Hold: 'ac_pll:pll0|altpll:altpll_component|_clk0'  ; 0.531 ns ;
; Clock Hold: 'ac_pll:pll0|altpll:altpll_component|_clk2'  ; 0.556 ns ;
; Total number of failed paths                             ;          ;
+----------------------------------------------------------+----------+

Revision 5.0.2

  • Filename: ac_v05000002_16oct2009.sof
  • To Do:
    • ---
  • Features:
    • Based on ac_v5.0.1
    • Adds HEATER_BIAS and HEATER_BIAS_LEN parameters for Tc-flattening on SCUBA-2.
    • IMPORTANT: Must be used in conjunction with firmware v05000000+ of all other cards.
  • Details:
  • Bugs:
    • None yet reported
  • FPGA Resource Usage (addr_card.fit.rpt):
+--------------------------------------------------------------------------+
; Fitter Summary                                                           ;
+--------------------------+-----------------------------------------------+
; Fitter Status            ; Successful - Fri Oct 16 16:41:47 2009         ;
; Quartus II Version       ; 9.0 Build 235 06/17/2009 SP 2 SJ Full Version ;
; Revision Name            ; addr_card                                     ;
; Top-level Entity Name    ; addr_card                                     ;
; Family                   ; Stratix                                       ;
; Device                   ; EP1S10F780C5                                  ;
; Timing Models            ; Final                                         ;
; Total logic elements     ; 10,524 / 10,570 ( 100 % )                     ;
; Total pins               ; 279 / 427 ( 65 % )                            ;
; Total virtual pins       ; 0                                             ;
; Total memory bits        ; 199,168 / 920,448 ( 22 % )                    ;
; DSP block 9-bit elements ; 8 / 48 ( 17 % )                               ;
; Total PLLs               ; 1 / 6 ( 17 % )                                ;
; Total DLLs               ; 0 / 2 ( 0 % )                                 ;
+--------------------------+-----------------------------------------------+
  • Timing Analyzer Summary (addr_card.tan.rpt):
+----------------------------------------------------------------------
; Timing Analyzer Summary                                              
+----------------------------------------------------------+----------+
; Type                                                     ; Slack    ;
+----------------------------------------------------------+----------+
; Worst-case tsu                                           ; N/A      ;
; Worst-case tco                                           ; N/A      ;
; Worst-case th                                            ; N/A      ;
; Clock Setup: 'ac_pll:pll0|altpll:altpll_component|_clk0' ; 2.267 ns ;
; Clock Setup: 'ac_pll:pll0|altpll:altpll_component|_clk2' ; 3.582 ns ;
; Clock Hold: 'ac_pll:pll0|altpll:altpll_component|_clk0'  ; 0.538 ns ;
; Clock Hold: 'ac_pll:pll0|altpll:altpll_component|_clk2'  ; 0.665 ns ;
; Total number of failed paths                             ;          ;
+----------------------------------------------------------+----------+

Revision 5.0.1

  • Filename: ac_v05000001_14sep2009.sof
  • To Do:
    • ---
  • Features:
    • The resource usage on the AC has now reached a level where there isn't enough left to implement Signal Tap. To enable SignalTap, comment out the largest usage of RAM/LE's: "ram : tpram_32bit_x_64" in ac_dac_ctrl.vhd. Remember to uncomment this when running the final synthesis before committal.
    • Based on ac_v5.0.0.
    • Implements the bias_start command for different bias heating across rows on SCUBA2 arrays.
    • IMPORTANT: Must be used in conjunction with firmware v05000000+ of all other cards.
  • Details:
    • Differences between ac_v5.0.0 and ac_v5.0.1
U system/test/source/tb/tb_cc_rcs_bcs_ac.vhd
U addr_card/ac_dac_ctrl/source/rtl/ac_dac_ctrl.vhd
U addr_card/ac_dac_ctrl/source/rtl/ac_dac_ctrl_pack.vhd
U addr_card/addr_card/source/rtl/addr_card.vhd
U addr_card/addr_card/source/rtl/addr_card_self_test.vhd
U addr_card/addr_card/synth/addr_card.fit.rpt
U addr_card/addr_card/synth/addr_card.fit.summary
U addr_card/addr_card/synth/addr_card.map.rpt
U addr_card/addr_card/synth/addr_card.qsf
U addr_card/addr_card/synth/addr_card.sof
U addr_card/addr_card/synth/addr_card.tan.rpt
U addr_card/addr_card/synth/addr_card.tan.summary
U all_cards/all_cards/source/rtl/all_cards_pack.vhd
U all_cards/async/source/rtl/async_pack.vhd
U all_cards/async/source/rtl/lvds_rx.vhd
U all_cards/dispatch/source/rtl/dispatch.vhd
U all_cards/dispatch/source/rtl/dispatch_cmd_receive.vhd
U all_cards/frame_timing/source/rtl/frame_timing.vhd
U all_cards/frame_timing/source/rtl/frame_timing_core.vhd
U all_cards/frame_timing/source/rtl/frame_timing_pack.vhd
U library/sys_param/source/rtl/data_types_pack.vhd
U library/sys_param/source/rtl/wishbone_pack.vhd
  • Bugs:
    • None yet reported
  • FPGA Resource Usage (addr_card.fit.rpt):
+--------------------------------------------------------------------------+
; Fitter Summary                                                           ;
+--------------------------+-----------------------------------------------+
; Fitter Status            ; Successful - Mon Sep 14 13:46:41 2009         ;
; Quartus II Version       ; 9.0 Build 235 06/17/2009 SP 2 SJ Full Version ;
; Revision Name            ; addr_card                                     ;
; Top-level Entity Name    ; addr_card                                     ;
; Family                   ; Stratix                                       ;
; Device                   ; EP1S10F780C5                                  ;
; Timing Models            ; Final                                         ;
; Total logic elements     ; 9,370 / 10,570 ( 89 % )                       ;
; Total pins               ; 279 / 427 ( 65 % )                            ;
; Total virtual pins       ; 0                                             ;
; Total memory bits        ; 199,168 / 920,448 ( 22 % )                    ;
; DSP block 9-bit elements ; 8 / 48 ( 17 % )                               ;
; Total PLLs               ; 1 / 6 ( 17 % )                                ;
; Total DLLs               ; 0 / 2 ( 0 % )                                 ;
+--------------------------+-----------------------------------------------+
  • Timing Analyzer Summary (addr_card.tan.rpt):
+----------------------------------------------------------------------
; Timing Analyzer Summary                                              
+----------------------------------------------------------+----------+
; Type                                                     ; Slack    ;
+----------------------------------------------------------+----------+
; Worst-case tsu                                           ; N/A      ;
; Worst-case tco                                           ; N/A      ;
; Worst-case th                                            ; N/A      ;
; Clock Setup: 'ac_pll:pll0|altpll:altpll_component|_clk0' ; 3.361 ns ;
; Clock Setup: 'ac_pll:pll0|altpll:altpll_component|_clk2' ; 4.142 ns ;
; Clock Hold: 'ac_pll:pll0|altpll:altpll_component|_clk0'  ; 0.528 ns ;
; Clock Hold: 'ac_pll:pll0|altpll:altpll_component|_clk2'  ; 0.562 ns ;
; Total number of failed paths                             ;          ; 
+----------------------------------------------------------+----------+

Revision 5.0.0

  • Filename: ac_v05000000_22dec2008.sof (tagged as sys_v05000000_22dec2008)
  • To Do:
    • ---
  • Features:
    • IMPORTANT: Must be used in conjunction with firmware v05000000+ of all other cards.
    • To increase data bandwidth, the spare LVDS line from each card to the Clock Card is now used
  • Details:
    • ---
  • Bugs:
    • None yet reported
  • FPGA Resource Usage (addr_card.fit.rpt):
+---------------------------------------------------------------------+
; Fitter Summary                                                      ;
+--------------------------+------------------------------------------+
; Fitter Status            ; Successful - Tue Jan 13 16:19:16 2009    ;
; Quartus II Version       ; 8.1 Build 163 10/28/2008 SJ Full Version ;
; Revision Name            ; addr_card                                ;
; Top-level Entity Name    ; addr_card                                ;
; Family                   ; Stratix                                  ;
; Device                   ; EP1S10F780C5                             ;
; Timing Models            ; Final                                    ;
; Total logic elements     ; 9,383 / 10,570 ( 89 % )                  ;
; Total pins               ; 279 / 427 ( 65 % )                       ;
; Total virtual pins       ; 0                                        ;
; Total memory bits        ; 196,096 / 920,448 ( 21 % )               ;
; DSP block 9-bit elements ; 8 / 48 ( 17 % )                          ;
; Total PLLs               ; 1 / 6 ( 17 % )                           ;
; Total DLLs               ; 0 / 2 ( 0 % )                            ;
+--------------------------+------------------------------------------+
  • Timing Analyzer Summary (addr_card.tan.rpt):
+----------------------------------------------------------------------
; Timing Analyzer Summary                                              
+----------------------------------------------------------+----------+
; Type                                                     ; Slack    ;
+----------------------------------------------------------+----------+
; Worst-case tsu                                           ; N/A      ;
; Worst-case tco                                           ; N/A      ;
; Worst-case th                                            ; N/A      ;
; Clock Setup: 'ac_pll:pll0|altpll:altpll_component|_clk0' ; 2.617 ns ;
; Clock Setup: 'ac_pll:pll0|altpll:altpll_component|_clk2' ; 4.588 ns ;
; Clock Hold: 'ac_pll:pll0|altpll:altpll_component|_clk0'  ; 0.539 ns ;
; Clock Hold: 'ac_pll:pll0|altpll:altpll_component|_clk2'  ; 0.658 ns ;
; Total number of failed paths                             ;          ;
+----------------------------------------------------------+----------+

Firmware repository

Retrieved from "https://e-mode.phas.ubc.ca/mcewiki/index.php?title=Address_Card_firmware&oldid=6841"