Pre-v5 firmware

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The following describes an obsolete procedure or component.  See MCE firmware for a more recent alternative.

Address Card

Revision 2.0.a

  • Filename: ac_v02000008_16sep2009.sof
  • To Do:
    • ---
  • Features:
    • Based on ac_v2.0.8
    • Adds the BIAS_START parameter for delaying the application of the ON_BIAS when ENBL_MUX = 1.
    • Adds a new multplexing mode mode (ENBL_MUX = 3) that allows users to apply a gradient of heater biases across the MUX wafer using the HEATER_BIAS and HEATER_BIAS_LEN parameters.
  • Details:
  • Bugs:
    • None yet reported
  • FPGA Resource Usage (addr_card.fit.rpt):
+--------------------------------------------------------------------------+
; Fitter Summary                                                           ;
+--------------------------+-----------------------------------------------+
; Fitter Status            ; Successful - Fri Oct 16 11:52:16 2009         ;
; Quartus II Version       ; 9.0 Build 235 06/17/2009 SP 2 SJ Full Version ;
; Revision Name            ; addr_card                                     ;
; Top-level Entity Name    ; addr_card                                     ;
; Family                   ; Stratix                                       ;
; Device                   ; EP1S10F780C5                                  ;
; Timing Models            ; Final                                         ;
; Total logic elements     ; 10,349 / 10,570 ( 98 % )                      ;
; Total pins               ; 279 / 427 ( 65 % )                            ;
; Total virtual pins       ; 0                                             ;
; Total memory bits        ; 198,656 / 920,448 ( 22 % )                    ;
; DSP block 9-bit elements ; 8 / 48 ( 17 % )                               ;
; Total PLLs               ; 1 / 6 ( 17 % )                                ;
; Total DLLs               ; 0 / 2 ( 0 % )                                 ;
+--------------------------+-----------------------------------------------+
  • Timing Analyzer Summary (addr_card.tan.rpt):
+----------------------------------------------------------------------
; Timing Analyzer Summary                                              
+----------------------------------------------------------+----------+
; Type                                                     ; Slack    ;
+----------------------------------------------------------+----------+
; Worst-case tsu                                           ; N/A      ;
; Worst-case tco                                           ; N/A      ;
; Worst-case th                                            ; N/A      ;
; Clock Setup: 'ac_pll:pll0|altpll:altpll_component|_clk0' ; 3.053 ns ;
; Clock Setup: 'ac_pll:pll0|altpll:altpll_component|_clk2' ; 3.790 ns ;
; Clock Hold: 'ac_pll:pll0|altpll:altpll_component|_clk2'  ; 0.540 ns ;
; Clock Hold: 'ac_pll:pll0|altpll:altpll_component|_clk0'  ; 0.542 ns ;
; Total number of failed paths                             ;          ; 
+----------------------------------------------------------+----------+

Revision 2.0.8

  • Filename: ac_v02000008_16sep2009.sof
  • To Do:
    • ---
  • Features:
    • Based on ac_v2.0.7
    • Implements the bias_start command for different bias heating across rows on SCUBA2 arrays.
  • Details:
    • Differences between ac_v2.0.7 and ac_v2.0.8
U system/test/source/tb/tb_cc_rcs_bcs_ac.vhd
U addr_card/ac_dac_ctrl/source/rtl/ac_dac_ctrl.vhd
U addr_card/ac_dac_ctrl/source/rtl/ac_dac_ctrl_pack.vhd
U addr_card/addr_card/source/rtl/addr_card.vhd
U addr_card/addr_card/source/rtl/addr_card_self_test.vhd
U addr_card/addr_card/synth/addr_card.fit.rpt
U addr_card/addr_card/synth/addr_card.fit.summary
U addr_card/addr_card/synth/addr_card.map.rpt
C addr_card/addr_card/synth/addr_card.qws
U addr_card/addr_card/synth/addr_card.qsf
U addr_card/addr_card/synth/addr_card.sof
U addr_card/addr_card/synth/addr_card.tan.rpt
U addr_card/addr_card/synth/addr_card.tan.summary
U all_cards/all_cards/source/rtl/all_cards.vhd
U all_cards/all_cards/source/rtl/all_cards_pack.vhd
U all_cards/frame_timing/source/rtl/frame_timing.vhd
U all_cards/frame_timing/source/rtl/frame_timing_core.vhd
U all_cards/frame_timing/source/rtl/frame_timing_pack.vhd
U all_cards/frame_timing/source/rtl/frame_timing_wbs.vhd
U library/components/source/rtl/parallel_crc.vhd
U library/sys_param/source/rtl/data_types_pack.vhd
U library/sys_param/source/rtl/wishbone_pack.vhd
  • Bugs:
    • None yet reported
  • FPGA Resource Usage (addr_card.fit.rpt):
+---------------------------------------------------------------------+
; Fitter Summary                                                      ;
+--------------------------+------------------------------------------+
; Fitter Status            ; Successful - Wed Sep 16 13:03:57 2009    ;
; Quartus II Version       ; 8.1 Build 163 10/28/2008 SJ Full Version ;
; Revision Name            ; addr_card                                ;
; Top-level Entity Name    ; addr_card                                ;
; Family                   ; Stratix                                  ;
; Device                   ; EP1S10F780C5                             ;
; Timing Models            ; Final                                    ;
; Total logic elements     ; 9,141 / 10,570 ( 86 % )                  ;
; Total pins               ; 279 / 427 ( 65 % )                       ;
; Total virtual pins       ; 0                                        ;
; Total memory bits        ; 198,656 / 920,448 ( 22 % )               ;
; DSP block 9-bit elements ; 8 / 48 ( 17 % )                          ;
; Total PLLs               ; 1 / 6 ( 17 % )                           ;
; Total DLLs               ; 0 / 2 ( 0 % )                            ;
+--------------------------+------------------------------------------+
  • Timing Analyzer Summary (addr_card.tan.rpt):
+----------------------------------------------------------------------
; Timing Analyzer Summary                                              
+----------------------------------------------------------+----------+
; Type                                                     ; Slack    ;
+----------------------------------------------------------+----------+
; Worst-case tsu                                           ; N/A      ;
; Worst-case tco                                           ; N/A      ;
; Worst-case th                                            ; N/A      ;
; Clock Setup: 'ac_pll:pll0|altpll:altpll_component|_clk0' ; 1.971 ns ;
; Clock Setup: 'ac_pll:pll0|altpll:altpll_component|_clk2' ; 4.506 ns ;
; Clock Hold: 'ac_pll:pll0|altpll:altpll_component|_clk0'  ; 0.539 ns ;
; Clock Hold: 'ac_pll:pll0|altpll:altpll_component|_clk2'  ; 0.549 ns ;
; Total number of failed paths                             ;          ;
+----------------------------------------------------------+----------+

Revision 2.0.7

Features:

  • Added the const_val39 command to support internal TES Bias ramping

Bugs:

  • None so far

Bias Card

Revision 1.4.2

  • bc_v01040002_15jul2008.sof

Features:

  • Added the tga_i signal to the sensitivity list for the bc_dac_ctrl FSM
  • potential bug may have been introduced with resetting the DAC counter due to inadvertently using the wrong bc_dac_ctrl_core.vhd version.

Revision 1.4.1

  • bc_v01040001_25jan2008.sof

Features:

  • Added card_type and scratch commands
  • Integrated fw_rev and slot_id as part of all_cards
  • Added provisions for safe state machines to fix the reset problem.
  • Added lvds_tx = 0 so clock-card can check whether the card is plugged in using this spare lvds line.

Bugs: None so far

Clock Card

Revision 4.0.c

  • Filename: cc_v0400000c_24aug2009.sof
  • To Do:
    • ---
  • Features:
    • Header Version 6
    • Based on v4.0.b and in parallel with 5.0.2 (equivalent version)
    • The Sync Box PLL was re-instated to the top level and routed to dv_rx. It was mistakenly removed after v4.0.9, which means that the sync box sequence number decoding has not worked since then! When collecting data while triggering off the Sync Box DV, the Clock Card would also sporadically trigger in between data frames.
  • Details:
    • clk_card.vhd: re-instantiated the manchester PLL, and routed the manch_clk to dv_rx.
  • Bugs:
    • None yet.
  • FPGA Resource Usage (clk_card.fit.rpt):
; Total logic elements     ; 14,965 / 32,470 ( 46 % )                      ;
; Total pins               ; 254 / 598 ( 42 % )                            ;
; Total virtual pins       ; 0                                             ;
; Total memory bits        ; 812,544 / 3,317,184 ( 24 % )                  ;
; DSP block 9-bit elements ; 10 / 96 ( 10 % )                              ;
; Total PLLs               ; 2 / 6 ( 33 % )                                ;
; Total DLLs               ; 0 / 2 ( 0 % )                                 ;
  • Timing Analyzer Summary (clk_card.tan.rpt):
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk0' ; 1.646 ns  ;
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk1' ; 2.167 ns  ;
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk2' ; 2.919 ns  ;

Revision 4.0.b (buggy)

  • Filename: cc_v0400000b_03jun2009.sof
  • Features:
    • Header Version 6
    • Based on v4.0.a and in parallel with 5.0.1 (equivalent version, but without the dual-LVDS feature).
    • STOP commands are meant to work in this revision. The successful execution of STOP commands through the system depends also on the PCI card firmware, and PCI driver. Modifications have been made to these, and their version numbers have been bumped to...
    • This firmware is a hybrid version that implements a single LVDS line, but has STOP and On-The-Fly capabilities built in. The purpose of this firmware is to give SCUBA-2 these features without forcing them to upgrade the firmware on all their other cards.
  • Bugs:
    • There may be a problem with decoding sync numbers from the sync box.
  • FPGA Resource Usage (clk_card.fit.rpt):
; Total logic elements     ; 15,023 / 32,470 ( 46 % )                 ;
; Total pins               ; 254 / 598 ( 42 % )                       ;
; Total virtual pins       ; 0                                        ;
; Total memory bits        ; 812,544 / 3,317,184 ( 24 % )             ;
; DSP block 9-bit elements ; 10 / 96 ( 10 % )                         ;
; Total PLLs               ; 1 / 6 ( 17 % )                           ;
; Total DLLs               ; 0 / 2 ( 0 % )                            ;
  • Timing Analyzer Summary (clk_card.tan.rpt):
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk1' ; 1.328 ns  ;
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk0' ; 1.442 ns  ;
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk2' ; 3.383 ns  ;

Revision 4.0.a (UBC only)

  • Filename: cc_v0400000a_16oct2008
  • To Do:
    • Make sure that the errno word, and the cards to report word in the data frame header agree with cards_to_report
  • Features:
    • Header Version 6
    • Based on 4.0.9
    • Added stop_dly, rcs_to_report_data, and cards_to_report commands
    • Added support for commands to the MCE during data acquisition
  • Details:
    • clk_card.vhd: incremented the firmware version number, and added cards_to_report interface signals; added support for the stop_dly, rcs_to_report_data, and cards_to_report commands; Removed the Manchester PLL because the only way to ensure that packets are received without trouble is for the main PLL to be locked on the Manchester clock. The Manchester PLL was a failed attempted around this.
    • clock_card_pack.vhd: added support for the stop_dly, rcs_to_report_data, and cards_to_report commands
    • issue_reply.vhd: added support for the stop_dly, rcs_to_report_data, and cards_to_report commands
    • cmd_translator.vhd: split up command registers so that it can handle WB/RB/RS commands while acquiring data based on a GO command.
    • issue_reply_pack.vhd: added indexing constants.
    • reply_queue.vhd: modified the logic for calculating the reply data size, in response to the addition of the rcs_to_report_data, and cards_to_report commands
    • reply_queue_sequencer.vhd: modified the logic for reading the data from the reply queues; modified the logic for determining when to stop readout from a card queue to ease timing constraints. Changed to logic for multiplexing the data buses from the reply queues to combinatorial logic to ease timing constraints.
    • reply_translator.vhd: added a stop_delay counter for delaying the replies to 'stop ret_dat' commands; added the QUICK_REPLY and QUICK_REPLY_PAUSE states to pause the return of replies to stop commands; added extra handling to the LD_STATUS state to avoid mixing stop replies, and replies to data or simple commands; added stop reply pause logic to DONE state
    • ret_dat_wbs.vhd: added the stop_delay_o, rcs_to_report_data, and cards_to_report_o interfaces; implemented a custom register from cards_to_report and stop_delay; removed the register for ret_dat_card_addr which was a special case of cards_to_report.
    • ret_dat_wbs_pack: added the constant DEFAULT_CARDS_TO_REPORT
  • Bugs:
    • Reading back rcs_to_report_data returns zero (fixed)
    • Can't issue simple commands during data taking
    • Can't read from RC4 (fixed)
    • There may be a problem with decoding sync numbers from the sync box.
  • FPGA Resource Usage (clk_card.fit.rpt):
; Total logic elements     ; 14,542 / 32,470 ( 45 % )                      ;
; Total pins               ; 254 / 598 ( 42 % )                            ;
; Total virtual pins       ; 0                                             ;
; Total memory bits        ; 812,544 / 3,317,184 ( 24 % )                  ;
; DSP block 9-bit elements ; 8 / 96 ( 8 % )                                ;
; Total PLLs               ; 1 / 6 ( 17 % )                                ;
; Total DLLs               ; 0 / 2 ( 0 % )                                 ;
  • Timing Analyzer Summary (clk_card.tan.rpt):
; Clock Setup: 'clk_switchover:t|_clk0' ; 1.712 ns  ;
; Clock Setup: 'clk_switchover:t|_clk1' ; 2.632 ns  ;
; Clock Setup: 'clk_switchover:t|_clk2' ; 3.884 ns  ;

Revision 4.0.9

  • Filename: cc_v04000009
  • Features:
    • Header Version 6
    • Integrated a bug fix for the sram_ctrl block
    • Integrated new all_cards block of code which was causing a synthesis warning in ModelSim
    • Two new commands added: card_type, scratch.
  • Bugs:
    • None to report so far
  • FPGA Resource Usage (clk_card.fit.rpt):
; Total logic elements     ; 14,144 / 32,470 ( 44 % )                 ;
; Total pins               ; 254 / 598 ( 42 % )                       ;
; Total virtual pins       ; 0                                        ;
; Total memory bits        ; 812,544 / 3,317,184 ( 24 % )             ;
; DSP block 9-bit elements ; 8 / 96 ( 8 % )                           ;
; Total PLLs               ; 2 / 6 ( 33 % )                           ;
; Total DLLs               ; 0 / 2 ( 0 % )                            ;
  • Timing Analyzer Summary (clk_card.tan.rpt):
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk1' ; 0.294 ns  ;
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk0' ; 2.091 ns  ;
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk2' ; 2.711 ns  ;

Readout Card

Revision 4.0.f (Filter + Raw, 1 LVDS)

  • Filename:
    • rc_v0400000f_12feb2010.sof
  • Features:
    • Based on 4.0.e and in parallel with 5.0.9 (equivalent version, clamping is not included)
    • Incorporates fixes that were done to flux-jumping between 5.0.2 - 5.0.4 - 5.0.9. Namely:
      • Changes a multiplier from signed to unsigned (in fsfb_corr_multplier.vhd).
      • Changes sign extension from signed to unsigned (in flux_quanta_ram_admin.vhd).
  • Details:
  • Bugs:
    • None reported yet.
  • Synthesis Notes:
    • The quartus.ini file was present in the synth directory during synthesis.
  • FPGA Resource Usage (readout_card.fit.rpt):
; Total logic elements     ; 26,773 / 41,250 ( 65 % )                      ;
; Total memory bits        ; 1,321,984 / 3,423,744 ( 39 % )                ;
  • FPGA Timing Analysis (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.539 ns  ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 4.118 ns  ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 17.318 ns ;

Revision 4.0.e (Filter + Raw, 1 LVDS)

  • Filename:
    • rc_v0400000e_27apr2009.sof
  • Features:
    • Based on 4.0.d
    • Combines both raw- and filtered-data modes.
    • fpga_temp, card_temp, card_id commands are disabled.
    • Tested by Matt Hasselfield.
  • Details:
  • Bugs:
    • fpga_temp, card_temp, card_id commands are disabled.
  • Synthesis Notes:
    • The quartus.ini file was present in the synth directory during synthesis.
  • FPGA Resource Usage (readout_card.fit.rpt):
; Total logic elements     ; 27,048 / 41,250 ( 66 % )                 ;
; Total memory bits        ; 1,321,984 / 3,423,744 ( 39 % )           ;
  • FPGA Timing Analysis (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.675 ns  ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.907 ns  ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.728 ns ;

Revision 4.0.d (Raw Only, 1 LVDS)

  • Filename: rc_v0400000d_20090417.sof
  • Features:
    • Based on v4.0.c, but has the filter removed, and implements a single 65536-index RAM block for storing 50 MHz raw-data samples.
    • The firmware takes a new command called readout_col_index which specifies which column to capture raw data from.
    • Other than readout_col_index, the firmware functions the same as previous raw-data firmware, including then need to issue a capture_raw command.
    • For more information on raw-data, see Raw-mode readout
    • This firmware also integrates some of the improvements that were implemented in 4.4.0, like the removal of the tga_o signal from an FSM in dispatch_wishbone.vhd.
  • Details:
    • Differences between 4.0.c and 4.0.d
U system/test/source/tb/tb_cc_rcs_bcs_ac.vhd
U all_cards/dispatch/source/rtl/dispatch_wishbone.vhd
U library/sys_param/source/rtl/wishbone_pack.vhd
U readout_card/adc_sample_coadd/source/rtl/adc_sample_coadd.vhd
U readout_card/adc_sample_coadd/source/rtl/adc_sample_coadd_pack.vhd
U readout_card/flux_loop/source/rtl/flux_loop.vhd
U readout_card/flux_loop/source/rtl/flux_loop_pack.vhd
U readout_card/flux_loop_ctrl/source/rtl/flux_loop_ctrl.vhd
U readout_card/flux_loop_ctrl/source/rtl/flux_loop_ctrl_pack.vhd
U readout_card/flux_loop_ctrl/source/tb/tb1_flux_loop_ctrl.vhd
U readout_card/flux_loop_ctrl/source/tb/tb2_flux_loop_ctrl.vhd
U readout_card/fsfb_calc/source/rtl/fsfb_fltr_regs.vhd
U readout_card/fsfb_corr/source/rtl/fsfb_corr.vhd
U readout_card/readout_card/source/rtl/readout_card.vhd
U readout_card/readout_card/source/rtl/readout_card_pack.vhd
U readout_card/wbs_frame_data/source/rtl/wbs_frame_data.vhd
U readout_card/wbs_frame_data/source/rtl/wbs_frame_data_pack.vhd
  • Bugs:
    • None so far.
    • fpga_temp, card_temp, card_id commands are not supported.
  • Synthesis Notes:
    • The quartus.ini file was present in the synth directory during synthesis.
  • FPGA Resource Usage (readout_card.fit.rpt):
; Total logic elements     ; 24,554 / 41,250 ( 60 % )                 ;
; Total memory bits        ; 1,262,592 / 3,423,744 ( 37 % )           ;
  • FPGA Timing Analysis (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.991 ns  ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.864 ns  ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 17.052 ns ;

Revision 4.4.1

  • Filename: rc_v04040001_21nov2008
  • Features:
    • Fixes a bug that froze up the firmware if any of the following commands were issued: CARD_ID_ADDR, CARD_TEMP_ADDR, FPGA_TEMP_ADDR in 4.4.0 only.
  • Details:
    • The bug fix include adding more logic to the wishbone ack path (readout_card.vhd), which subsequently decreased the minimum clock setup time to 1.588ns. The new logic will catch errors that the old logic wouldn't have, and is now consistent with the firmware on all the other cards. However, if timing becomes an issue, the logic may have to revert back to that which was in version 4.0.c.
  • Bugs:
    • None so far.
  • Synthesis Notes:
    • The quartus.ini file was not present in the synth directory during synthesis.
  • FPGA Resource Usage (readout_card.fit.rpt):
; Total logic elements     ; 27,241 / 41,250 ( 66 % )                      ;
; Total memory bits        ; 405,504 / 3,423,744 ( 12 % )                  ;
  • FPGA Timing Analysis (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.588 ns  ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.585 ns  ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 17.057 ns ;

Revision 4.4.0 (buggy)

  • Filename: rc_v04040000_02oct2008
  • Features:
    • Reinstated the data modes in wbs_frame_data.vhd that were removed in 4.0.c. This firmware has the following modes: 0, 1, 2, 4, 5, 7, 10. The modes that are not present are: 3 (raw data), 6 (replaced by data_mode = 7), 8 (replaced by data_mode = 10), 9 (replaced by data_mode = 10). For more information on data modes, see Data mode.
    • Re-integrated the id_thermo and fpga_thermo block in the readout_card.vhd top level that was removed in 4.0.c.
    • Removed the sticky bit in fsfb_corr.vhd, which was enabled when flux-jumping was turned on. Because the feedback is signed, the sticky bit would usually reflect the value of the 14th bit, except in situations when the number of flux quanta to jump was greater than 1 (i.e. cosmic rays, IV-curves, etc). Flux jumps are made at a maximum rate of one per frame period, so that if the First-Stage Feedback increased past the 13th bit, it would not be reflected in the feedback applied. Now it is.
  • Details:
    • Simplified the FSM logic in wbs_frame_data.vhd that determines when to transition from IDLE to WSS1. This was done to lower the number of gates in that path, and ease the timing.
    • Removed the z_dat_i port in fsfb_processor.vhd and fsfb_calc_pack.vhd to the fsfb_proc_pidz block, in an effort to make it clearer within that block that the z-term is always = 0.
    • Removed the z-term sign extension in fsfb_proc_pidz.vhd, and the [d-term + z-term] adder to free up DSP resources since the z-term is always = 0.
    • Adjusted the indentation in fsfb_io_controller.vhd to make the file more readable.
    • Moved the tga_o signal out of the dispatch_wishbone.vhd FSM, and made it a continuous assignment. This signal had one of the highest fan-out counts in the RTL design, and actually was impossible to route in Stratix III chips in its previous configuration because of the number of gates on the fan-out. As a consequence of making it a continuous assignment, the Stratix III fitter was able to succeed, and the Stratix I timing characteristics were greatly improved. This is the most significant change in this revision. This change single-handedly increased the minimum slack from 1.282 ns in v0400000c to 2.372 ns (or 56.7 MHz max) in this revision.
  • Bugs:
    • The following commands lock up the Readout Card firmware: CARD_ID_ADDR, CARD_TEMP_ADDR, FPGA_TEMP_ADDR.
    • fb_const0 commands to channel 0 do not work. The value is stored in the register, but not applied to the DAC. Thus, read-back returns the correct value, but the DAC does not
  • Synthesis Notes:
    • The quartus.ini file was not present in the synth directory during synthesis.
  • FPGA Resource Usage (readout_card.fit.rpt):
; Total logic elements     ; 27,099 / 41,250 ( 66 % )                      ;
; Total memory bits        ; 406,016 / 3,423,744 ( 12 % )                  ;
  • FPGA Timing Analysis (readout_card.tan.rpt):
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.372 ns  ;
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 4.052 ns  ;
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.066 ns ;

Revision 4.0.c

  • Filename: rc_v0400000c_15aug2008.sof
  • Features:
    • Only has data modes 0, 1, 4, and 10.
    • Fixed the bug that exists in 4.0.b, 4.0.a, and 4.0.9 that prevented the fb_const value from being applied to channel zero (wbs_fb_data.vhd).
  • Details:
    • Changed a counter in the dispatch block to ease timing constraints in synthesis (dispatch_wishbone.vhd)
    • Updated the tagged versions of dispatch.vhd , dispatch_cmd_receive.vhd, and dispatch_reply_transmit.vhd to the version that is used by all the other cards.
    • Removed the fpga_termo (command: fpga_temp) and id_thermo (commands: card_temp, card_id) to ease timing constraints in synthesis (readout_card.vhd)
    • Updated the tagged version of fpga_termo.vhd to include the new 'stale bit' feature
    • Updated the tagged version of frame_timing_core.vhd to include the new 'err_o' interface
  • Bugs:
    • None reported yet
  • Synthesis Notes:
    • The quartus.ini file was not present in the synth directory during synthesis.
  • FPGA Resource Usage:
Total logic elements : 25,058 / 41,250 ( 61 % )
Total memory bits : 400,896 / 3,423,744 ( 12 % )
  • Timing Analysis (readout_card.tan.rpt):
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.282 ns  ;
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.736 ns  ;
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.665 ns ;

Revision 4.0.b (buggy)

Note: This revision is on a watch list, after the bug detected 15 July 2008. See the bug section for more details.

  • Filename : rc_v0400000b_04aug2008.sof
  • Features
    • data_mode 10 is added to provide more filtfb bits (compared to data mode 9) for planet observations. filtered_dat(27 downto 3) & flux_cnt_dat(6 downto 0)
  • Bugs
    • An unexplained bug that appeared in 4.0.a and may still be present in 4.0.b is a problem with the readout of channels being clipped out of data reporting. Bug 1 Notes
  • Synthesis note
    • Quartus.ini removed.

Revision 4.0.a (buggy)

Note: This revision is on a watch list, after the bug detected 15 July 2008. See the bug section for more details.

  • Filename : rc_v0400000a_07jul2008.sof
  • Bug Fix
    • mce_status and adc_offset/flx_quanta commands do not fail after power up.
  • Synthesis note
    • Quartus.ini removed.
  • Bugs
    • Seems to clip out channel 0 from data reporting.

Revision 4.0.9 (buggy)

  • Filename : rc_v04000009_26jun2008.sof
  • Features
    • sa_bias and offset DACs only refreshed when new values are written. (in previous versions, DACs were refreshed every frame)
  • Bugs
    • fb_const0 commands to channel 0 do not work. The value is stored in the register, but not applied to the DAC. Thus, read-back returns the correct value, but the DAC does not.
    • reading flx_quanta and adc_offset right after power up hangs the reply datapath to CC. resetmce clears this error as temporary solution. the problem is caused by first read ack of the wishbone slave.

Revision 4.0.8

  • Filename : rc_v04000008_26jun2008.sof
  • Features
    • The gaini, gainp, gaind resolution increased to 12-bit, i.e. -2048 to 2047 (formerly 10-bit).
  • Bug fix
    • the bug associated with gainpid read before mce_reset is fixed.
  • Synthesis note
    • Quartus.ini removed.

Revision 4.3.7

  • Filename : rc_v04030007_26may2008_raw.sof
  • Features
    • 14-bit raw mode enabled to buffer a snapshot of 50MHz samples for 2 frames of row_len * num_rows samples.
    • In order to extend the raw-mode to 14-bit, an assumption is made that the raw buffer is not written to while being read. Therefore, make sure there is at least 2*row_len*num_rows*20ns between issuing captr_raw command and reading back the raw data.
    • In order to save RAM for raw mode, two memory-intensive features are disabled:
      • low-pass filter disabled ( mixed filtfb data modes 6, 7, 9 are also disabled)
      • PID (gainp0, gaini0, gaind0) readback disabled. one can still set PID values and run servo, but can not read back the values.

Revision 4.2.7

  • Filename : rc_v04020007_24may2008_raw.sof
  • Features
    • raw mode enabled to buffer a snapshot of 50MHz samples for 2 frames of row_len * num_rows samples.
    • In order to save RAM for raw mode, two memory-intensive features are disabled:
      • low-pass filter disabled ( mixed filtfb data modes 6, 7, 9 are also disabled)
      • PID (gainp0, gaini0, gaind0) readback disabled. one can still set PID values and run servo, but can not read back the values.
  • Bug fix
    • the bug associated with reading from raw-buffer is fixed.

Revision 4.1.7

  • Filename : rc_v04010007_25apr2008_raw.sof
  • Features
    • raw mode enabled to buffer a snapshot of 50MHz samples for 2 frames of row_len * num_rows samples.
    • In order to save RAM for raw mode, two memory-intensive features are disabled:
      • low-pass filter disabled ( mixed filtfb data modes 6, 7, 9 are also disabled)
      • PID (gainp0, gaini0, gaind0) readback disabled. one can still set PID values and run servo, but can not read back the values.
  • Bugs
    • after each readout frame, raw-buffer readout counter falls behind by 3 and this causes skipping 3 50MHz samples in the data stream and column-data being messed up in subsequent frames. Data can be rearranged by post processing.

Revision 4.0.6 (buggy)

  • Filename : rc_v04000006_15feb2008.sof or .pof
  • Features
    • bugfix: unreliable reset due to unsafe and incomplete state machines is fixed.
    • bugfix: flux_jump sign problem fixed, so far proved in const_mode, to be tested in servo_mode with cold setup.
    • servo_mode=2 or ramp previously only went from 0 to ramp_amp, but now goes from -8192 to -8192+ramp_amp
    • new commands are added: scratch and card_type. Scratch takes 8 values and can be used by software to detect reset.
    • slot_id and fw_rev are now integrated as part of all_cards.vhd
    • lvds_tx_b=0, This will allow Clock Card to use the secondary backplane lvds line and check whether RC is plugged in.
    • filter_coeff in misc_banks_admin commented as it is not implemented and causes timing problems.
  • Bugs
    • reading gainp/gaini/gaind right after power up hangs the reply datapath to CC. resetmce clears this error as temporary solution. the problem is caused by first read ack of pid_ram_admin.
    • slot_id is only set after a resetmce is issued. (using the latest all_cards in the next revision will fix this)
    • has spurious spikes on channel 7 data, which max out the integral, and cause the detectors to come unlocked. This firmware officially meets timing requirements, but the bug could be due to marginal timing on the longest data paths, i.e. ~0.1 ns in some cases.

Revision 4.0.5

  • Filename : rc_v04000005_01nov2007.sof or .pof
  • Features
    • data mode 9 (mixed filt + flux jump) with windowing readjusted compared to data mode 8
  • Bugs
    • unreliable resetmce. Sometimes, firmware waked up non-responsive on lvds lines.
    • In data mode 5 and 9, flux-jump counter is not reported properly due to a sign error. However, flux jumping works fine.

Revision 3.0.19

  • Filename : rc_v03000019_16feb2007_raw.sof (no pof as one is not likely to run with this as regular firmware)
  • Features
    • data mode 3 is enabled.
    • filter is disabled as a compromise to fit the raw-mode buffer.
  • Bugs
    • unreliable resetmce. Sometimes, firmware waked up non-responsive on lvds lines.

Old Firmware Revisions

  • 4.0.4: rc_v04000004_11oct2007.sof data mode 8 added (mixed filt + flux jump)
  • 4.0.3: rc_v04000003_19sep2007.sof data mode 7 bit split readjusted to 10b error being bit 4 to 14
  • 4.0.2: rc_v04000002_11sep2007.sof pid resolution increased to 10b, data mode 7 added
  • 4.0.1: rc_v04000001_06sep2007.sof
  • 4.0.0: rc_v04000000_29aug2007.sof supports readout_row_index
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