MCE commands
From MCEWiki
This document lists the commands used to communicate with the MCE over the fibre-optic interface. These are low-level commands sent directly to the cards in command packets. In general, MAS abstracts these commands, providing a higher-level interface to MCE commanding. In MAS, mce_cmd is used to issue commands to the MCE, and the MCE commands and their encodings are defined in the hardware description file: mce.cfg.
Contents
Firmware version 6 updates
Firmware version 6 increases the maximum number of rows supported from 41 to 64. Unfortunately, the MCE protocol command packet has a fixed size, allowing at most 58 parameter elements to be written at once. To enable parameters with 64 elements in a backwards-compatible way, firmware version six adds upper Card IDs which can be used to address the top portion of the parameter array. Upper card IDs exist for the readout cards, bias cards and address card only. An upper card IDs are is the original (lower) Card ID with 0x10 added (so, for RC1, whose lower card ID is 0x03, the upper card ID is 0x13). Accessing an upper card ID has the effect of offsetting the parameter element index by 32 (e.g. writing, say, five values to an upper card ID will store them in elements 32 through 36 of the specified parameter).
Parameters which have more than 58 parameter elements, and so require the upper Card ID to write the upper portion of the data, are marked in the table below with an asterisk in the Data column.
Note: When commanding via MAS, the library handles splitting commands across the lower and upper card IDs. Users need not worry about which underlying card ID is used (unless using raw commanding via bare numeric addresses).
Command list
The following list omits unimplemented commands and commands obsoleted before firmware version 5. In the lists below, in general, the type column indicates whether the parameter can be read from (rb) or written to (wb) or both (rb,wb). A few commands are interacted with in other ways (indicated by rs or go,st); for these special commands see the discussion of low-level MCE commands in the mce_cmd description.
The command ID listed here is the name given to the command by MAS in the hardware description file (mce.cfg). These IDs are not used in the command packets; only the register address (given in the Addr. column) is used to identify commands in the command packet. As a result, these IDs are not part of the low-level MCE command protocol and other MCE documentation may refer to any given command register by a different name. Because the MCE command protocol deals only with register addresses, changing the name does not affect the purpose or action associated with the register.
The Data column indicates the data consumed by a write (wb) or returned by a read (rb). A few commands only permit a single word with a value of 1 for the command data. These are indicated by a bold-faced 1. The Version 6 Firmware increases the size of row-sized parameters to 64 from 41. This is noted in the tables below with an asterisk in this column.
In general, the FW Rev. provides the range of firmware release supporting the command. It may omit a few pre-v5 firmware releases.
General card commands
These commands can be issued to any card in the MCE (cc, rc1 to rc4, bc1, bc2, bc3, ac).
| ID | Addr. | Type | Data | Description | FW Rev. |
|---|---|---|---|---|---|
| fpga_temp | 0x91 | rb | FPGA temp. | Return the FPGA temperature of a card | all |
| card_temp | 0x92 | rb | card temp. | Return the card temperature from a IC sensor | all |
| card_id | 0x93 | rb | card ID | Return card ID from on-board silicon-ID chip | all |
| card_type | 0x94 | rb | card type | Return Card Type and PCB revision: Early firmware and hardware revisions do not report PCB revision. | all |
| slot_id | 0x95 | rb | slot ID | Return slot ID: | all |
| fw_rev | 0x96 | rb | revision | Return firmware revision, eg 0x0501000D for rev.5.1.d:
| all |
| led | 0x99 | rb,wb | status | Set and return the status of the front-panel LEDs. When writing to the LEDs, the value supplied is XOR’d with the current value of the LED status to produce the new status (i.e. a 1 bit toggles the corresponding LED). So, passing 0 will return the value of the LEDs without changing them. | all |
| scratch | 0x9A | rb,wb | word[0..7] | These are read/write registers to be used for arbitrary purposes. An example is to use one to detect undesired reset of MCE. | all |
| critical_error_rst | 0x9B | wb | 1 | Writing to this register triggers a reconfiguration of the FPGA from it's configuration device and therefore the card is unresponsive for a few seconds. | ≥5.2.0 |
| fpga_clr | 0x9C | wb | 1 | Writing to this register clears all the registers in firmware, but not the RAM blocks in the FPGA. | ≥5.2.0 |
System Commands
These commands affect the timing of the system – which means that they must be issued to all cards in the MCE at the same time. They are addressed to every card in the MCE by using the "sys" card address.
| ID | Addr. | Type | Data | Description | FW Rev. |
|---|---|---|---|---|---|
| row_len | 0x30 | rb,wb | # cycles | number of 50MHz clock cycles that are spent per row during multiplexing. Default = 64. Maximum = 65,535 | all |
| num_rows | 0x31 | rb,wb | # rows | number of rows to be multiplexed. Default = 41. Maximum = 2147483647/row_len, although version 5 firmware cannot servo more than 64 rows (41 in v5 firmware) | all |
Clock card commands
| ID | Addr. | Type | Data | Description | FW Rev. |
|---|---|---|---|---|---|
| config_app | 0x52 | rs | 1 | Configure the FPGA with the image in the application configuration device (EPC16). | ≥3.0.1 |
| config_fac | 0x51 | rs | 1 | Configure the FPGA with the image in the factory configuration device (EPC16). | ≥3.0.1 |
| ret_dat_s | 0x53 | rb,wb | start, stop | Specify the starting and ending sequence-numbers for data frames that the MCE is to return. Each frame of data will have a sequence number affixed to it. Sequence numbers will be assigned to data frames in increasing order, beginning with the starting sequence number, and finishing with the ending sequence number. Both parameters may range between 0x00000000 and 0xFFFFFFFF. If both starting and ending sequence numbers are the same, then a single frame of data will be returned. If the starting sequence number is larger than the ending sequence number, then frames will be returned until the sequence number has wrapped around and reached the stopping sequence number. Starting and stopping sequence numbers are expected for all modes of data acquisition—including for DV pulses. | all |
| use_dv | 0x54 | rb,wb | mode | Set the DV mode. The Clock Card can return data frames at an internal rate specified by data_rate, or in response to Data-Valid pulses from the Sync Box manchester input.† Default = 0. Allowed values:
| all |
| array_id | 0x58 | rb | array ID | Read the ID of the sub-array that a MCE box is connected to, if equipped with an IR array ID reader. | all |
| box_id | 0x59 | rb | box ID | Read the identification of the sub-rack. Each production sub-rack has a unique Silicon ID IC mounted on the Bus Backplane. | all |
| sram_data | 0x5C | rb,wb | word[0..n] | Read/write a block of 32-bit data to SRAM at address specified by the sram_addr parameter. | ≥4.0.9 |
| sram_addr | 0x5E | rb,wb | address | Specify the starting address for subsequent read/write operation to the 1024k x 32-bit SRAM. The, physical addresses range between 0x00000000 and 0x000FFFFF | ≥4.0.9 |
| data_rate | 0xA0 | rb,wb | # periods | Specify the rate at which data frames are collected by the MCE if DV pulses are not being used (see use_dv). The rate is specified as the time between data packets measured in frame periods, i.e. a value of 11 will return one data packet every 11 frame periods. A frame period is the amount of time required for the multiplexer to address all the rows on a MUX. Default = 47 | all |
| mce_bclr | 0xAB | rs | 1 | Clear the registers on all the cards in the MCE, including the Clock Card | ≥3.0.4 |
| cc_bclr | 0xAC | rs | 1 | Clear the registers on the clock card only | ≥3.0.4 |
| box_temp | 0xA8 | rb | box temp. | Return the temperature measured by the sensor on the bus backplane. | all |
| crc_err_en | 0xA9 | rb,wb | mode | Set the reply packet CRC mode:
| ≥3.0.1 |
| use_sync | 0xA1 | rb,wb | mode | Specify the sync mode. The Clock Card can return to address 0 using its internal timing, or in response to sync pulses from the Manchester input.† Default = 0. Allowed values:
| all |
| select_clk | 0xA2 | rb,wb | source | Select the source of the clock input to the Clock Card's PLL, either the Manchester input clock, or the on-board crystal clock. Both are nominally 25 MHz.† Default = 0. Allowed values:
| all |
| internal_cmd_mode | 0xB0 | rb,wb | mode | Enable or disable internal housekeeping/ramping commands. Default = 0. Allowed values:
| ≥4.0.0 |
| ramp_step_period | 0xB1 | rb,wb | # periods | Specify the number of frame periods between each ramp step. | ≥4.0.0 |
| ramp_min_val | 0xB2 | rb,wb | value | Specify the minimum value of the ramp that is to be applied. Must be less than ramp_max_val | ≥4.0.0 |
| ramp_step_size | 0xB3 | rb,wb | step | Specify the ramp step size. If step = ramp_max_val – ramp_min_val, then the ramp will be a square wave | ≥4.0.0 |
| ramp_max_val | 0xB4 | rb,wb | value | Specify the maximum value of the ramp that is to be applied. Must be greater than ramp_min_val | ≥4.0.0 |
| ramp_param_id | 0xB5 | rb,wb | address | Specify the parameter ID (register address) of the register to be ramped | ≥4.0.0 |
| ramp_card_addr | 0xB6 | rb,wb | address | Specify the card address of the register to be ramped | ≥4.0.0 |
| ramp_step_data_num | 0xB7 | rb,wb | count | Specify the number of data that are to be written per ramp command | ≥4.0.0 |
| ramp_step_phase | 0xBB | rb,wb | offset | Specify the phase offset of the start of the ramp | ≥5.0.b |
| awg_sequence_len | 0xB9 | rb,wb | length | Specify the length of the Arbitrary Waveform Generator (AWG) sequence that is loaded in RAM. This parameter tells the internal commanding FSM how many values to apply before restarting at the beginning | ≥5.0.3 |
| awg_data | 0xBA | rb,wb | datum[0..n] | Load the Arbitrary Waveform Generator (AWG) sequence into RAM on the Clock Card. The RAM has 8192 indices. This may be expanded later if there are enough resources still available on the Clock Card | ≥5.0.3 |
| awg_addr | 0xBC | rb,wb | address | Specify the starting address for reading from or writing to the Arbitrary Waveform Generator (AWG) RAM. This parameter also affects the memory address of the internal commanding FSM | ≥5.0.3 |
| cards_present | 0x5A | rb | card list | Report which cards are present in the MCE:
| ≥4.0.8 |
| cards_to_report | 0x5B | rb,wb | card list | Specify which cards are present in the MCE subrack, and will return data over the bus backplane. This command can be used in situations where certain cards are not present in the subrack, and should not return data in replies. The default value for this register is 1 for every possible card. To stop a card from returning data, set its corresponding bit to 0. See cards_present for bit assignments | ≥4.0.a |
| rcs_to_report_data | 0x5F | rb,wb | card list | This command is not redundant with cards_to_report. It applies only to Readout Cards, and only for data taking (ret_dat) commands. This register sets which Readout Cards return data during a data run. This command allows the selective return of data without affecting which cards respond to all other commands, which is useful if a data run fails. See cards_present for bit assignments, but note that only RC bits are honoured | ≥4.0.a |
| stop_dly | 0xB8 | rb,wb | delay | Specify the time delay between the return of the next data frame and the return of the reply to a stop command. The time specified is in microseconds. This command is used to test the robustness of the PCI card to replies following immediately on the heels of a data packet. | ≥4.0.a |
| num_rows_reported | 0x55 | rb,wb | # rows | number of rows of data that are reported in a data packet. This parameter is set also available on readout cards; see: rc num_rows_reported. See also num_cols_reported. Default = 41 | ≥4.0.0 |
| run_id | 0x56 | rb,wb | value | Specify an ID number that will be stored in every data packet header returned to the PC. On ACT, the ID number corresponds to the C time at which data acquisition began. ACT's data files are also named by the same C time, so that the data pipeline can easily track which files the data are from | ≥4.0.2 |
| user_word | 0x57 | rb,wb | value | Specify a value that will be stored in every data packet header returned to the PC. This register is used by ACT to store a combination of array_id and data_mode information. At Caltech, it is used during IV curves to store the value of the TES bias applied. | ≥4.0.2 |
| upload_fw | 0x50 | wb | count, datum[0..n] | Specify count (≤57) doublets of packed JTAG data. The first word of the command specifies the total number of [TMS,TDI] doublets contained in the rest of the data. The rest of the words consist of count [TMS,TDI] doublets starting from the LSB. The TCK signal is implied. The JTAG FSM automatically runs through a TCK cycle after asserting each new doublet consisting of one TMS and one TDI bit. Command execution:
| ≥5.0.5 |
| config_jtag | 0xAA | rb | datum[0..n] | Read back ≤57 bits of packed JTAG data. Unlike the upload_fw command above, the first word returned does not contain the number of bits read out. It is assumed that following every upload_fw command, this command will be called and will thus return the same number of single bits as there were doublets of [TMS,TDI] data transmitted. Every new upload_fw command overwrites the TDO data from the previous upload_fw command. The mce_jam player can ignore TDO data that is not important. | ≥5.0.5 |
| num_cols_reported | 0xAD | wb | # columns | number of columns of data that are reported in a data packet. This parameter is also available on readout cards; see: rc num_cols_reported. See also num_rows_reported. Default = 8 | ≥5.0.0 |
| tdo_sample_dly | 0xAE | rb,wb | delay | Specify the number of clock cycles after the assertion of TCK that TDO should be sampled. Default = 2. The default value is tuned to the MCE, so leave this as is | ≥5.0.5 |
| tck_half_period | 0xAF | rb,wb | ½ period | Specify the number of clock cycles that TCK should remain high, and then remain low. Default = 8. The default value is tuned to the MCE, so leave this as is | ≥5.0.5 |
- †: If select_clk=0, then the user must set use_sync=0 and use_dv=0, otherwise timing artifacts will appear in data. The following combinations are OK:
select_clk use_sync use_dv 0 0 0 1 2 0 1 0 0 1 2 2 1 0 2
Readout card commands
Similar to the sys card used to issue commands to all cards, MAS provides the special physical card rca which can be used to issue rb or wb commands to all installed readout cards. The firmware also implements the special physical card rcs which is used to issue commands to the ret_dat register on all cards.
| ID | Addr. | Type | Data | Description | FW Rev. |
|---|---|---|---|---|---|
| sa_bias | 0x10 | rb,wb | bias[0..7] | Read/write the SA bias values for all columns on a readout card | all |
| offset | 0x11 | rb,wb | offset[0..7] | Read/write the SA offset values for all columns on a readout card | all |
| gainp0 | 0x70 | rb,wb | gainp[0..40] | Read/write the Readout Card's P coefficients for any given column. P gains are signed 10-bit values | all |
| gainp1 | 0x71 | ||||
| gainp2 | 0x72 | ||||
| gainp3 | 0x73 | ||||
| gainp4 | 0x74 | gainp[0..63]* | ≥6.0.0 | ||
| gainp5 | 0x75 | ||||
| gainp6 | 0x76 | ||||
| gainp7 | 0x77 | ||||
| gaini0 | 0x78 | rb,wb | gaini[0..40] | Read/write the Readout Card's I coefficients for any given column. I gains are signed 10-bit values | all |
| gaini1 | 0x79 | ||||
| gaini2 | 0x7A | ||||
| gaini3 | 0x7B | ||||
| gaini4 | 0x7C | gaini[0..63]* | ≥6.0.0 | ||
| gaini5 | 0x7D | ||||
| gaini6 | 0x7E | ||||
| gaini7 | 0x7F | ||||
| flx_quanta0 | 0x80 | rb,wb | quantum[0..40] | Read/write the Readout Card's flux quanta for any given column. Flux Quanta are used to calculate the SQ1 feedback value | all |
| flx_quanta1 | 0x81 | ||||
| flx_quanta2 | 0x82 | ||||
| flx_quanta3 | 0x83 | ||||
| flx_quanta4 | 0x84 | quantum[0..63]* | ≥6.0.0 | ||
| flx_quanta5 | 0x85 | ||||
| flx_quanta6 | 0x86 | ||||
| flx_quanta7 | 0x87 | ||||
| gaind0 | 0x88 | rb,wb | gaind[0..40] | Read/write the Readout Card's D coefficients for any given column. D gains are signed 10-bit values | all |
| gaind1 | 0x89 | ||||
| gaind2 | 0x8A | ||||
| gaind3 | 0x8B | ||||
| gaind4 | 0x8C | gaind[0..63]* | ≥6.0.0 | ||
| gaind5 | 0x8D | ||||
| gaind6 | 0x8E | ||||
| gaind7 | 0x8F | ||||
| adc_offset0 | 0x68 | rb,wb | offset[0..40] | Read/write the Readout Card's ADC offsets for any given column. The ADC Offset coefficients are used to digitally offset each 50 MHz ADC sample on the Readout Cards | all |
| adc_offset1 | 0x69 | ||||
| adc_offset2 | 0x6A | ||||
| adc_offset3 | 0x6B | ||||
| adc_offset4 | 0x6C | offset[0..63]* | ≥6.0.0 | ||
| adc_offset5 | 0x6D | ||||
| adc_offset6 | 0x6E | ||||
| adc_offset7 | 0x6F | ||||
| readout_row_index | 0x13 | rb,wb | index | Specify the starting row index of data to be returned in a data block. Default = 0. Note: if num_rows_reported > num_rows – readout_row_index – 1, then the readout row index will wrap around to 0 during readout | ≥4.0.0 |
| ret_dat | 0x16 | go,st | 1 | Return data frames. Prior to this command, the Clock Card expects a ret_dat_s command to set up how many frames are to be collected and what sequence numbers to assign. Following that, a single ret_dat command triggers the return of all requested data frames. To simultaneously start or stop data return for all cards, this parameter should be accessed via the special rcs card. | all |
| en_fb_jump | 0x15 | rb,wb | enabled | Enable (=1) or disable (=0) flux jumping on the Readout Card. The size of flux jumps is specified by the flx_quanta# commands | all |
| data_mode | 0x17 | rb,wb | mode | Set/return data mode. Not all data modes are supported by all firmware revisions. | all |
| captr_raw | 0x18 | rb,wb | enabled | Capture (=1) a 64k timestream snapshot of the error signal when Address-Return-to-Zero is asserted. 65,536 50MHz ADC samples from the channel specified by readout_col_index are stored in the raw-data buffer on the Readout Card | ≥5.0.1 |
| servo_mode | 0x1B | rb,wb | mode[0..7] | Set the per-column servo mode on the Readout Cards. Available modes are:
| all |
| ramp_dly | 0x1C | rb,wb | # frames | Specify the number of frame-periods before the next step in a ramp function. This delay can be tuned to the data-frame readout rate (data_rate), so that one frame of data is read out per ramp step | all |
| ramp_amp | 0x1D | rb,wb | value | Specify the maximum ramp value, in 14-bits | all |
| ramp_step | 0x1E | rb,wb | step | Specify what the step size of each step in the ramp is, max 14-bit | all |
| fb_const | 0x1F | rb,wb | fb_const[0..7] | Specify the constant feedback DAC value for a each column when the servo is in constant mode (see servo_mode). Applied to SQ1 feedback. Range: -8192 to 8191. The constant value is applied to the Readout Card DAC repetitively for every new row | all |
| sample_dly | 0x32 | rb,wb | # cycles | Specify the number of 50MHz clock cycles from the start of a row during which ADC samples do not contribute to a co-added value on the Readout Cards | all |
| sample_num | 0x33 | rb,wb | count | Specify the number of 50MHz samples which are co-added during a row-period on the Readout Cards. Co-addition begins after the sample delay, and one value is co-added per 50MHz clock cycle. Note that default is 0 and therefore you need to explicitly set this parameter | all |
| fb_dly | 0x34 | rb,wb | # cycles | Specify the number of 50MHz clock-cycles between the start of a row and the assertion of the row's feed-back value on the Readout Cards. (minimum is 7 with flux-jumping off, 10 or 18 (depending on firmware revision) when flux-jumping is on). | all |
| flx_lp_init | 0x37 | wb | 1 | Initialize/reset the PID loop calculations on the Readout Cards for new PID parameters to take effect | all |
| readout_col_index | 0x19 | rb,wb | column | Specify the starting column index of data to be returned in a data block. Default = 0. Note: if num_rows_reported > num_rows – readout_row_index – 1, then the readout row index will wrap around to 0 during readout. During raw readout, this parameter specifies the index of the column for which raw data is stored | ≥5.0.1 |
| num_rows_reported | 0x55 | rb,wb | # rows | number of rows of data that are reported in a data packet. This parameter is set in conjunction with the readout_row_index. This parameter is also available on clock cards; see: cc num_rows_reported. See also num_cols_reported, readout_col_index. Default = 41 | ≥4.0.0 |
| num_cols_reported | 0xAD | wb | # columns | number of columns of data that are reported in a data packet. This parameter is set in conjunction with the readout_col_index. This parameter is also available on clock cards; see: cc num_cols_reported. See also num_rows_reported, readout_row_index. Default = 8 | ≥5.0.0 |
| integral_clamp | 0x66 | rb,wb | value | This parameter is used to clamp the integral term used in SQ1 feedback calculation. Once this value is reached, the integral term is permanently clamped and can only be reset by issuing a flx_lp_init command or reset. This is invented to prevent ramping of unlocked pixels and mitigate the adverse effects of the ramping pixels on locked pixels. See integral clamp. | ≥5.0.9 |
| servo_rst_arm | 0xF8 | wb | 1 | When set to 1, the flux-loop servo on all detectors flagged by servo_rst_col# are reset; see Flux-loop reset per detector | ≥5.2.0 |
| servo_rst_col0 | 0xF0 | rb,wb | reset_row[0..40] | A per-detector flag indicating which pixels to reset when servo_rst_arm is set to 1; see Flux-loop reset per detector | ≥5.2.0 |
| servo_rst_col1 | 0xF1 | ||||
| servo_rst_col2 | 0xF2 | ||||
| servo_rst_col3 | 0xF3 | ||||
| servo_rst_col4 | 0xF4 | reset_row[0..63]* | ≥6.0.0 | ||
| servo_rst_col5 | 0xF5 | ||||
| servo_rst_col6 | 0xF6 | ||||
| servo_rst_col7 | 0xF7 | ||||
| fltr_rst | 0x14 | wb | 1 | Reset the filter data pipeline. Triggering flx_lp_init also automatically triggers fltr_rst | all |
| fltr_coeff | 0x1A | rb,wb | b11, b12, b21, b22, k1, k2 | Specifies a set of 6 filter parameters for the low-pass Butterworth filter, the first 4 are the biquad coefficients followed by k1 and k2; see Digital 4-pole Butterworth Low-pass filter | ≥5.1.0 |
| fltr_type | 0x65 | rb,wb | type | Specify the filter type. Default is 1. Allowed values:
| ≥5.0.a |
| pterm_decay_bits | 0x64 | rb,wb | bit count | This is the value k in the p-term calculation: <math>p_n = \mathrm{err}_n + \left(1 - \frac{1}{2^k}\right) p_{n-1}</math>. Setting this to zero (the default) disables the decay, which is the behaviour in older firmwares. | ≥5.1.a |
Bias card commands
| ID | Addr. | Type | Data | Description | FW Rev. |
|---|---|---|---|---|---|
| flux_fb | 0x20 | rb,wb | flux_fb[0..31] | Specify the flux feedback for all 32 16-bit DAC channels on the Bias Cards. The mapping between DAC channels and SQUIDs is hardware dependent. For 32-column systems (72-HP subracks):
For most 16-column systems (48-HP subracks):
For 16-column systems with only two bias cards, the TES bias mapping is, instead:
| all |
| bias | 0x21 | rb,wb | bias[0..11] | Read/Write the low-noise LVDS 16-bit DACs that are typically used to supply TES bias or pixel heater currents. Rev. E and later Bias Cards have 12 low-noise bias lines while Rev D. and earlier have only one, with the nominal mapping of [BC1 bias ↔ Pixel Heater] and [BC2 bias ↔ TES Bias] Firmware revisions before 5.0.4 support only one value for this register. | all |
| flux_fb_upper | 0x24 | rb,wb | flux_fb[16..31] | Specify the flux feedback for 16 upper 16-bit DACs, i.e. channel 16 to 31 on bias cards. This command was implemented to match the cryostat wiring for the MCEv2 subracks, which use the upper 16 channels of BC1 to supply the SQ2 Bias. See flux_fb above. | ≥1.4.0 |
| fb_col0 | 0xC0 | rb,wb | fb_row[0..40] | When enbl_mux = 1 or multiplexing mode is enabled, then these commands specify the per-row multiplexing values for each of the 32 DAC channels (fb_col#) on the bias card | ≥5.0.3 |
| fb_col1 | 0xC1 | ||||
| fb_col2 | 0xC2 | ||||
| fb_col3 | 0xC3 | ||||
| fb_col4 | 0xC4 | ||||
| fb_col5 | 0xC5 | ||||
| fb_col6 | 0xC6 | ||||
| fb_col7 | 0xC7 | ||||
| fb_col8 | 0xC8 | ||||
| fb_col9 | 0xC9 | ||||
| fb_col10 | 0xCA | ||||
| fb_col11 | 0xCB | ||||
| fb_col12 | 0xCC | ||||
| fb_col13 | 0xCD | ||||
| fb_col14 | 0xCE | ||||
| fb_col15 | 0xCF | ||||
| fb_col16 | 0xD0 | fb_row[0..63]* | ≥6.0.0 | ||
| fb_col17 | 0xD1 | ||||
| fb_col18 | 0xD2 | ||||
| fb_col19 | 0xD3 | ||||
| fb_col20 | 0xD4 | ||||
| fb_col21 | 0xD5 | ||||
| fb_col22 | 0xD6 | ||||
| fb_col23 | 0xD7 | ||||
| fb_col24 | 0xD8 | ||||
| fb_col25 | 0xD9 | ||||
| fb_col26 | 0xDA | ||||
| fb_col27 | 0xDB | ||||
| fb_col28 | 0xDC | ||||
| fb_col29 | 0xDD | ||||
| fb_col30 | 0xDE | ||||
| fb_col31 | 0xDF | ||||
| enbl_mux | 0x05 | rb,wb | mode[0..31] | enable/disable per-column multiplexing DAC values. Default = 0. Allowed values:
| ≥5.0.3 |
| enbl_flux_fb_mod | 0x25 | rb,wb | enabled[0..31] | Enable (=1) or disable (=0) the per-column addition of mod_val to flux_fb values for regular DACs | ≥5.3.0 |
| enbl_bias_mod | 0x26 | rb,wb | enabled[0..31] | Enable (=1) or disable (=0) the per-column addition of mod_val to bias values for low-noise bias DACs | ≥5.3.0 |
| mod_val | 0x27 | rb,wb | value | Modulation value to be added to either of flux_fb or bias values depending on whether modulation is enabled or not. (see enbl_flux_fb_mod and enbl_bias_mod) | ≥5.3.0 |
| num_rows_idle | 0x28 | rb,wb | # rows | number of rows at the start of each ARZ that no bias is applied, only valid when multiplexing is enabled or (enbl_mux is 1). | ≥5.3.5 |
Address card commands
| ID | Addr. | Type | Data | Description | FW Rev. |
|---|---|---|---|---|---|
| row_order | 0x01 | rb,wb | row_num[0..40] | This command is relevant when enbl_mux = 1 or 2. Read/write the row-addressing order. A sequence of up to 41 (v5 firmware) or 64 (v6 firmware) rows is specified at once. The row numbers that are specified with this command refer to the physical channel numbers on the Address Card. Note: After this command is issued, a flx_lp_init command must be issued to all the readout cards to discard previous PID-loop calculations and to clean out the rest of the data pipeline. Default = 0,0,0,... | all |
| row_num[0..63]* | ≥6.0.0 | ||||
| on_bias | 0x02 | rb,wb | bias_row[0..40] | Applies when enbl_mux = 1 or 3. Read/write the14-bit on-bias values for all 41 channels of the DACs on the Address Card. Bias values are stored in the order of physical channels on the Address card – which is not necessarily the multiplexing order specified with row_order. This command is nominally is used to specify the SQ1 "on" biases, and are applied one at a time in the sequence specified by row_order. Default = 0,0,0,... | all |
| off_bias | 0x03 | rb,wb | bias_row[0..40] | Applies when enbl_mux = 1 or 3. Read/write the 14-bit off-bias values for all 41 channels of the row-addressing DACs on the Address Card. Bias values are stored in the order of physical channels on the Address card – which is not necessarily the multiplexing order specified with row_order. This command is nominally is used to specify the SQ1 "off" biases. Default = 0,0,0,... | all |
| enbl_mux | 0x05 | rb,wb | mode | Start/stop array multiplexing. Default: 0. Allowed values:
| all |
| bias_start | 0x09 | rb,wb | start[0..40] | Applies only when enbl_mux = 1. Specify the point during each row dwell period when the SQ1 bias is applied. This is specified on a row-by-row basis so that SCUBA2 can do differential bias heating across the rows of their arrays. | ≥5.0.1 |
| heater_bias | 0x0A | rb,wb | bias[0..40] | When enbl_mux=3, specify the magnitude of the SQ1-bias heating pulse in DAC units (0 to 16383) during the initial heater_bias_len period of each row visit. | ≥5.0.2 |
| heater_bias_len | 0x0B | rb,wb | # cycles | When enbl_mux=3, specify the length of the SQ1 bias heating pulses at the beginning of every new row period. | ≥5.0.2 |
| fb_col0 | 0xE3 | rb,wb | fb_row[0..40] | These commands are relevant when enbl_mux = 2. Specifies the 41 multiplexing values for each DAC channel on the Address Card, and for each row that the channel is to multiplex. There are 41 channels on the Address Card, and up to 41 rows per channel that need to be specified. These commands are used only when the address card is used from a bias card slot (see Biasing Address Card). | ≥2.0.5 |
| fb_col1 | 0xE1 | ||||
| fb_col2 | 0xDF | ||||
| fb_col3 | 0xDD | ||||
| fb_col4 | 0xDB | ||||
| fb_col5 | 0xD9 | ||||
| fb_col6 | 0xD7 | ||||
| fb_col7 | 0xD5 | ||||
| fb_col8 | 0xD3 | ||||
| fb_col9 | 0xD1 | ||||
| fb_col10 | 0xCF | ||||
| fb_col11 | 0xCD | ||||
| fb_col12 | 0xCB | ||||
| fb_col13 | 0xC9 | ||||
| fb_col14 | 0xC7 | ||||
| fb_col15 | 0xC5 | ||||
| fb_col16 | 0xE2 | ||||
| fb_col17 | 0xE0 | ||||
| fb_col18 | 0xDE | ||||
| fb_col19 | 0xDC | ||||
| fb_col20 | 0xDA | ||||
| fb_col21 | 0xD8 | ||||
| fb_col22 | 0xD6 | ||||
| fb_col23 | 0xD4 | ||||
| fb_col24 | 0xD2 | ||||
| fb_col25 | 0xD0 | ||||
| fb_col26 | 0xCE | ||||
| fb_col27 | 0xCC | ||||
| fb_col28 | 0xCA | ||||
| fb_col29 | 0xC8 | ||||
| fb_col30 | 0xC6 | ||||
| fb_col31 | 0xC4 | ||||
| const_mode | 0x06 | rb,wb | mode[0..40] | Specify which DAC channels are held at a constant value regardless of the value of enbl_mux. A constant value is applied once only, and is specified by const_val. In addition, DACs for which const_mode=1 do not receive data strobes during multiplexing – so that there are no glitches or excess noise on the DAC outputs.
| ≥2.0.6 |
| const_val | 0x07 | rb,wb | val[0..40] | Specify values for the DACs that are held constant. val[n] is asserted by DAC n when const_mode[n] = 1. In addition, all constant values are applied to each respective DAC when enbl_mux = 0. When enbl_mux, const_mode, or const_val values are changed, all the DACs that are being held constant have their values re-strobed (Biasing Address Card only) | ≥2.0.6 |
Legacy documents
The document linked below provides the same information as this page, except that it includes obsolete and unimplemented commands. It was last updated in April of 2013, an does not list any command added after that time. In some instances the command names listed in the following document are different than the command names used by MAS (which are listed above). The description of some commands may be obsolete.
