Difference between revisions of "Clock Card firmware"

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−
Clock Card firmware revisions may implement different data packet header formats.  All of the different formats are documented [http://www.phas.ubc.ca/%7Emce/mcedocs/Software/SC2_ELE_S580_526_mce_file_format.pdf here].
+
{{Related|Clock Card Firmware}}
 +
* [[Pre-v5 firmware#Clock Card|Pre-v5 firmware]]
 +
== Firmware links ==
 +
* [http://e-mode.phas.ubc.ca/mce_firmware/ Firmware Programming Files]
 +
* Clock Card firmware revisions may implement different data packet header formats.  All of the different formats are documented at [[MCE flat-file format]]
  
−
= Recommended Firmware Revisions =
+
== Firmware Revision Listing ==
−
* Please see the [http://e-mode.phas.ubc.ca/mcewiki/index.php/Compatible_Versions_(CC,RC,BC,AC) recommend firmware revisions] page.
+
=== Revision 6.0.2 ===
 +
* '''Filename:'''  cc_v06000002_20160530.sof
  
−
= Firmware Revision Listing =
+
* '''Features:''' support of upper 32 word needs an additional wait cycle for ack_read
 +
* '''Features:'''fpga_clr and critical_error_rst commands added
 +
* Note: skip 6.0.1 due to losing track of all_cards
 +
* '''bug:''' When [[STOP|stop]] command is issued, two frames are sent with both last-frame-bit and stop-bit set. This is currently benign as mas ignores the extra frame, but needs to be fixed regardless.
 +
* '''bug:''' When data-timing-err bit is set, the last-frame-bit gets set but then the ret_dat counter doesn't not get reset, so when sync-dv starts coming in, clock card continues to send out frames again.
  
−
== Revision 5.0.4 ==
+
=== Revision 5.0.e (stable) ===
−
* '''Filename:'''  cc_v05000004_13jan2010.sof
+
* '''Filename:'''  cc_v0500000e_15may2012.sof
  
−
* '''To Do:'''
+
* '''Features:''' added pcb_rev interface to be able to read pcb revision starting RevC Clock Card.
 +
* '''bugfix:''' awg is now realigned with data-acquisition and the phase can be adjusted using ramp_step_phase.
 +
* '''bugfix:''' A time-delay is added between assertion of epc_sel and config_n to remedy the occasional failure of {{param|cc|config_app}} and {{param|cc|config_fac}} commands.
 +
* '''bug:''' When [[STOP|stop]] command is issued, two frames are sent with both last-frame-bit and stop-bit set. This is currently benign as mas ignores the extra frame, but needs to be fixed regardless.
 +
* '''bug:''' When data-timing-err bit is set, the last-frame-bit gets set but then the ret_dat counter doesn't not get reset, so when sync-dv starts coming in, clock card continues to send out frames again.
 +
 
 +
==== Revision 5.0.d (test) ====
 +
* '''Filename:'''  cc_v0500000d_10may2012.sof
 +
 
 +
* '''Features:''' Internal commands are issued at address-return-to-zero (ARZ) to provide more deterministic timing. This means the data_rate has to be at least 2, or internal commands will stop with a data_rate of 1. In previous versions, internal commands were being issued asynchronous to ARZ. The phase of the ramp or awg can be adjusted using {{param|cc|ramp_step_phase}}.
 +
 
 +
* '''bugfix:''' [[STOP|stop]] cmd works now and sets the stop-bit and last-frame-bit properly in the frame status word of the last frame.
 +
* '''bugfix:''' the ramp/awg value reported in the header is the one applied last. Previous versions reported what was going to be applied in the next iteration. If the command was not issued due to collision, then the value in the header was still being updated which was a bug.
 +
 
 +
* '''bug:''' awg mode doesn't work properly.
 +
 
 +
==== Revision 5.0.c (test) ====
 +
* '''Filename:'''  cc_v0500000c_26mar2012.sof
 +
 
 +
* '''Features:''' frame header revision 7 with dv_pulse_fibre_i encoded as bit 9 of the frame-status word in the header.
 +
** Based on 5.0.a
 +
 
 +
* '''Bugs:''' stop cmd may be broken?!It works but stop bit and last-frame bits are not set and a [[mce_cmd#FAKESTOP|fakestop]] needs to be issued in mas.
 +
 
 +
==== Revision 5.0.b (test) ====
 +
* '''Filename:'''  cc_v0500000b_06feb2012.sof
 +
 
 +
* '''Features:''' based on 5.0.a, frame header revision 7 with dv_pulse_fibre_i encoded as bit 9 of the frame-status word in the header.
 +
 
 +
* '''Bugs:''' stop cmd may be broken?!It works but stop bit is not set and a fakestop needs to be issued in mas.
 +
==== Revision 5.0.a (test) ====
 +
* '''Filename:'''  cc_v0500000a_06feb2012.sof
 +
 
 +
* '''Features:''' Based on 5.0.9
 +
 
 +
* ''' Bugfix:''' last-frame-bit was not being set in 5.0.9 and it returns right number of frames!
 +
 
 +
* '''Bugs:''' stop cmd may be broken. It works but stop bit is not set.
 +
 
 +
==== Revision 5.0.9 (test) ====
 +
* '''Filename:'''  cc_v05000009_26jan2012.sof
 +
 
 +
* '''Features:'''
 +
** added {{param|cc|ramp_step_phase}} command (par_id=xBB) to adjust the phase of [[Ramp Generator]] or [[Arbitrary Waveform Generator]] relative to data acquisition.
 +
** Based on 5.0.7
 +
 
 +
* ''' Bugfix:'''
 +
** Internal housekeeping and internal ramp/awg commands can be run as tight as possible ({{param|cc|data_rate}}=2 and {{param|cc|ramp_step_period}}=2) alongside data acquisition without affecting data timing. Previous versions would hold the ramp-value refresh till data was collected first. In this version when there is a collision between ret_dat and ramp-command, the ramp value is still increased, so the next time it is due, it would apply the right value.
 +
 
 +
* '''Bugs:'''
 +
** {{param|cc|config_app}} command is broken, it works in 5.0.3, but not in this version. to be investigated.
 +
** command issue/reply translator blocks are overhauled, so watch out for bugs related to stop command. None discovered yet though.
 +
 
 +
==== Revision 5.0.8 (not issued) ====
 +
* '''Filename:'''  cc_v05000008_12jul2011.sof
 +
 
 +
* '''Features:'''
 +
** This tag was a place holder for the final version of Clock Cards with '''Ethernet''' support (CCwE).  This tag currently references unfinished code in CVS.  The Quartus project file in this tag is designed for the Altera Stratix I Development Board.
 +
** Header Version 6
 +
** Based on 5.0.7
 +
 
 +
=== Revision 5.0.7 (stable) ===
 +
* '''Filename:'''  cc_v05000007_14may2010.sof
 +
 
 +
* '''Features:'''
 +
** Header Version 6
 +
** Based on 5.0.6
 +
** Compatible with MCE Jam Player -- SVN revision 16 (~/jp_25/mce_jam/trunk)
 +
** Simulation compatible with firmware v5.0.0 for the other cards.
 +
** Fixed a bug that caused a Clock Card with version 5.x.x firmware installed to return stale data for cards that had version 4.x.x. firmware installed on them.
 +
** Fixed a bug that caused a Clock Card to return stale data if a card was not present, or not configured.  Now the Clock Card returns 0x00000000.
 +
 
 +
* '''Bugs:'''
 +
** internal_ramp and internal_awg only refresh on readout-frame rate (data_rate). So effective {{param|cc|ramp_step_period}} is {{param|cc|data_rate}}.
 +
** When both internal and data commands are scheduled to be issued on multiplexing frame N, then at ARZ, data command is issued first, followed by the internal command. This may cause problems when the internal command is not completed (too many words and {{param|sys|row_len}} x {{param|sys|num_rows}} not long enough) before next ARZ.
 +
** {{param|cc|config_app}} command is broken (sometimes fails), it works in 5.0.3, but not in this version.
 +
 
 +
* '''FPGA Resource Usage''' (clk_card.fit.rpt):
 +
; Total logic elements    ; 18,745 / 32,470 ( 58 % )                      ;
 +
; Total pins              ; 243 / 598 ( 41 % )                            ;
 +
; Total virtual pins      ; 0                                            ;
 +
; Total memory bits        ; 957,952 / 3,317,184 ( 29 % )                  ;
 +
; DSP block 9-bit elements ; 10 / 96 ( 10 % )                              ;
 +
; Total PLLs              ; 2 / 6 ( 33 % )                                ;
 +
; Total DLLs              ; 0 / 2 ( 0 % )                                ;
 +
 
 +
* '''Timing Analyzer Summary''' (clk_card.tan.rpt):
 +
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk1' ; 0.279 ns  ;
 +
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk0' ; 0.437 ns  ;
 +
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk2' ; 3.224 ns  ;
 +
 
 +
==== Revision 5.0.6 (buggy) ====
 +
* '''Filename:'''  cc_v05000006_21apr2010.sof
 +
 
 +
* '''Features:'''
 +
** Header Version 6
 +
** Based on 5.0.5
 +
** Fixed a bug that prevented the Clock Card from loading firmware from its Factory Configuration Device when sw1:p1 is set to open (to enable remote configuration).
 +
** This version of firmware works in conjunction with modified Jam Player code that was recently committed to SVN tag: '''~/jp_25/mce_jam/trunk : revision 16.'''
 +
 
 +
* '''Details:'''
 +
** To learn how to use remote configuration:  [[Remote Firmware Update]].
 +
** For .jam file conversions, see:  [[MCE Programming File Conversions]].
 +
** Removed crc_error functionality for now.  It will get added back in when it is working.  It was found to conflict with the Remote Configuration functionality by preventing the Clock Card from configuring from its Factory Configuration Device.
 +
 
 +
* '''Bugs:'''
 +
** Has a bug that causes the Clock Card with version 5.x.x firmware installed to return stale data for cards that have version 4.x.x. firmware installed on them.
 +
** Has a bug that causes the Clock Card to return stale data if a card is not present, or not configured.
 +
 
 +
* '''FPGA Resource Usage''' (clk_card.fit.rpt):
 +
; Total logic elements    ; 18,652 / 32,470 ( 57 % )                      ;
 +
; Total pins              ; 243 / 598 ( 41 % )                            ;
 +
; Total virtual pins      ; 0                                            ;
 +
; Total memory bits        ; 957,952 / 3,317,184 ( 29 % )                  ;
 +
; DSP block 9-bit elements ; 10 / 96 ( 10 % )                              ;
 +
; Total PLLs              ; 2 / 6 ( 33 % )                                ;
 +
; Total DLLs              ; 0 / 2 ( 0 % )                                ;
 +
 
 +
* '''Timing Analyzer Summary''' (clk_card.tan.rpt):
 +
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk0' ; 0.590 ns
 +
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk1' ; 1.683 ns 
 +
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk2' ; 3.277 ns
 +
 
 +
==== Revision 5.0.5 (buggy) ====
 +
* '''Filename:'''  cc_v05000005_05mar2010.sof
 +
 
 +
* '''Features:'''
 +
** Header Version 6
 +
** Based on 5.0.4
 +
** Implemented unpacking logic for TMS and TDI signals, and inferring logic for TCK.  This is the solution to the JTAG packing problem.
 +
** This version of firmware works in conjunction with modified Jam Player code that was recently committed to SVN tag: '''~/jp_25/mce_jam/trunk : revision 8.'''
 +
 
 +
* '''Details:'''
 +
** Added the following commands: {{param|cc|upload_fw}}, {{param|cc|config_jtag}}, {{param|cc|tdo_sample_dly}}, {{param|cc|tck_half_period}}
 +
** This firmware solves the TMS and TDI packing problem such that a "wb cc {{param|cc|upload_fw}}" command contains the following:
 +
*** Word 0: total number of valid bits contained in words 1-n
 +
*** Word 1-n: (tms,tdi) pairs starting from word 1 (bits 1,0), word 1 (bits 3,2), etc.
 +
** The TDO packing is done differently: the tdo bits are captured by a shift register, and shifted from LSB to MSB, up to a maximum of 16 TDO bits per 32-bit fibre word.
 +
 
 +
* '''Bugs:'''
 +
** Does not configure from its Factory Configuration Device upon power-up
 +
** (non-critical) when a card does not return a valid reply, the clock card does not send an error reply back to the PC. Instead, it fills the data with whatever it had in its buffer from previous command and sends it to mas.
 +
 
 +
* '''FPGA Resource Usage''' (clk_card.fit.rpt):
 +
; Total logic elements    ; 18,699 / 32,470 ( 58 % )                      ;
 +
; Total pins              ; 261 / 598 ( 44 % )                            ;
 +
; Total virtual pins      ; 0                                            ;
 +
; Total memory bits        ; 957,952 / 3,317,184 ( 29 % )                  ;
 +
; DSP block 9-bit elements ; 10 / 96 ( 10 % )                              ;
 +
; Total PLLs              ; 2 / 6 ( 33 % )                                ;
 +
; Total DLLs              ; 0 / 2 ( 0 % )                                ;
 +
 
 +
* '''Timing Analyzer Summary''' (clk_card.tan.rpt):
 +
** Note that the clock slack on clk0 has diminished significantly over the past few revisions.  However, on this version, it increased again to a reasonable level.
 +
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk1' ; 1.164 ns  ;
 +
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk0' ; 1.276 ns  ;
 +
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk2' ; 3.299 ns  ;
 +
 
 +
==== Revision 5.0.4 (buggy) ====
 +
* '''Filename:''' cc_v05000004_26feb2010.sof
  
 
* '''Features:'''
 
* '''Features:'''
Line 15: Line 183:
 
** Based on 5.0.3
 
** Based on 5.0.3
 
** Added JTAG control registers that emulated a parallel port to allow Jam Player software to write to the MCE from a MAS PC and configure devices via JTAG.
 
** Added JTAG control registers that emulated a parallel port to allow Jam Player software to write to the MCE from a MAS PC and configure devices via JTAG.
 +
*** JTAG0 -- Output data
 +
*** JTAG1 -- Input data
 +
*** JTAG2 -- JTAG Chain control 
  
 
* '''Details:'''
 
* '''Details:'''
−
** [http://e-mode.phas.ubc.ca/intmcewiki/index.php/Remote_Firmware_Update Remote Firmware Update].
 
 
** This version of firmware is compatible with ported JAM Player software that has been temporarily committed to CVS under \\mce\cards\clk_card\config_fpga\source\unix_code.
 
** This version of firmware is compatible with ported JAM Player software that has been temporarily committed to CVS under \\mce\cards\clk_card\config_fpga\source\unix_code.
  
 
* '''Bugs:'''
 
* '''Bugs:'''
 +
** Does not configure from its Factory Configuration Device upon power-up
 
** (non-critical) when a card does not return a valid reply, the clock card does not send an error reply back to the PC. Instead, it fills the data with whatever it had in its buffer from previous command and sends it to mas.
 
** (non-critical) when a card does not return a valid reply, the clock card does not send an error reply back to the PC. Instead, it fills the data with whatever it had in its buffer from previous command and sends it to mas.
  
 
* '''FPGA Resource Usage''' (clk_card.fit.rpt):
 
* '''FPGA Resource Usage''' (clk_card.fit.rpt):
−
+--------------------------------------------------------------------------+
 
−
; Fitter Summary                                                          ;
 
−
+--------------------------+-----------------------------------------------+
 
−
; Fitter Status            ; Successful - Thu Feb 25 19:22:18 2010        ;
 
−
; Quartus II Version      ; 9.1 Build 304 01/25/2010 SP 1 SJ Full Version ;
 
−
; Revision Name            ; clk_card                                      ;
 
−
; Top-level Entity Name    ; clk_card                                      ;
 
−
; Family                  ; Stratix                                      ;
 
−
; Device                  ; EP1S30F780C5                                  ;
 
−
; Timing Models            ; Final                                        ;
 
 
  ; Total logic elements    ; 17,827 / 32,470 ( 55 % )                      ;
 
  ; Total logic elements    ; 17,827 / 32,470 ( 55 % )                      ;
 
  ; Total pins              ; 261 / 598 ( 44 % )                            ;
 
  ; Total pins              ; 261 / 598 ( 44 % )                            ;
Line 41: Line 202:
 
  ; Total PLLs              ; 2 / 6 ( 33 % )                                ;
 
  ; Total PLLs              ; 2 / 6 ( 33 % )                                ;
 
  ; Total DLLs              ; 0 / 2 ( 0 % )                                ;
 
  ; Total DLLs              ; 0 / 2 ( 0 % )                                ;
−
+--------------------------+-----------------------------------------------+
+
  ; M512s                   ; 66 / 295 ( 22 % )           
−
  ; M512s                                       ; 66 / 295 ( 22 % )           
+
  ; M4Ks                     ; 171 / 171 ( 100 % )         
−
  ; M4Ks                                       ; 171 / 171 ( 100 % )         
+
  ; M-RAMs                   ; 3 / 4 ( 75 % )               
−
  ; M-RAMs                                     ; 3 / 4 ( 75 % )               
 
  
 
* '''Timing Analyzer Summary''' (clk_card.tan.rpt):
 
* '''Timing Analyzer Summary''' (clk_card.tan.rpt):
−
+-----------------------------------------------------------------------------------------------------------
 
−
; Timing Analyzer Summary                                                                                 
 
−
+----------------------------------------------------------------------------------------------+-----------+
 
−
; Type                                                                                        ; Slack    ;
 
−
+----------------------------------------------------------------------------------------------+-----------+
 
 
  ; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk0' ; 0.771 ns  ;
 
  ; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk0' ; 0.771 ns  ;
 
  ; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk1' ; 1.576 ns  ;
 
  ; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk1' ; 1.576 ns  ;
 
  ; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk2' ; 2.859 ns  ;
 
  ; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk2' ; 2.859 ns  ;
−
; Clock Setup: 'fibre_rx_clkr'                                                                ; 13.822 ns ;
 
−
; Clock Setup: 'manch_pll:manch_pll_block|altpll:altpll_component|_clk0'                      ; 18.801 ns ;
 
−
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk3' ; 35.630 ns ;
 
−
; Clock Hold: 'fibre_rx_clkr'                                                                  ; 0.445 ns  ;
 
−
; Clock Hold: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk0'  ; 0.643 ns  ;
 
−
; Clock Hold: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk3'  ; 0.665 ns  ;
 
−
; Clock Hold: 'manch_pll:manch_pll_block|altpll:altpll_component|_clk0'                        ; 0.676 ns  ;
 
−
; Clock Hold: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk2'  ; 0.679 ns  ;
 
−
; Clock Hold: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk1'  ; 2.989 ns  ;
 
−
; Total number of failed paths                                                                ;          ;
 
−
+----------------------------------------------------------------------------------------------+-----------+
 
  
−
== Revision 5.0.3 ==
+
==== Revision 5.0.3 (tested) ====
 
* '''Filename:'''  cc_v05000003_13jan2010.sof
 
* '''Filename:'''  cc_v05000003_13jan2010.sof
−
 
−
* '''To Do:'''
 
−
** ---
 
  
 
* '''Features:'''
 
* '''Features:'''
Line 81: Line 222:
  
 
* '''Details:'''
 
* '''Details:'''
−
** [[ Arbitrary Waveform Generator ]] (i.e. Maximum Length Sequences for Complex Impedance Measurements)
+
** [[Arbitrary Waveform Generator]] (i.e. Maximum Length Sequences for Complex Impedance Measurements)
  
 
* '''Bugs:'''
 
* '''Bugs:'''
Line 87: Line 228:
  
 
* '''FPGA Resource Usage''' (clk_card.fit.rpt):
 
* '''FPGA Resource Usage''' (clk_card.fit.rpt):
−
+--------------------------------------------------------------------------+
 
−
; Fitter Summary                                                          ;
 
−
+--------------------------+-----------------------------------------------+
 
−
; Fitter Status            ; Successful - Mon Jan 25 20:10:18 2010        ;
 
−
; Quartus II Version      ; 9.0 Build 235 06/17/2009 SP 2 SJ Full Version ;
 
−
; Revision Name            ; clk_card                                      ;
 
−
; Top-level Entity Name    ; clk_card                                      ;
 
−
; Family                  ; Stratix                                      ;
 
−
; Device                  ; EP1S30F780C5                                  ;
 
−
; Timing Models            ; Final                                        ;
 
 
  ; Total logic elements    ; 18,095 / 32,470 ( 56 % )                      ;
 
  ; Total logic elements    ; 18,095 / 32,470 ( 56 % )                      ;
 
  ; Total pins              ; 255 / 598 ( 43 % )                            ;
 
  ; Total pins              ; 255 / 598 ( 43 % )                            ;
Line 104: Line 235:
 
  ; Total PLLs              ; 2 / 6 ( 33 % )                                ;
 
  ; Total PLLs              ; 2 / 6 ( 33 % )                                ;
 
  ; Total DLLs              ; 0 / 2 ( 0 % )                                ;
 
  ; Total DLLs              ; 0 / 2 ( 0 % )                                ;
−
+--------------------------+-----------------------------------------------+
 
  
 
* '''Timing Analyzer Summary''' (clk_card.tan.rpt):
 
* '''Timing Analyzer Summary''' (clk_card.tan.rpt):
−
+-----------------------------------------------------------------------------------------------------------
 
−
; Timing Analyzer Summary                                                                                 
 
−
+----------------------------------------------------------------------------------------------+-----------+
 
−
; Type                                                                                        ; Slack    ;
 
−
+----------------------------------------------------------------------------------------------+-----------+
 
−
; Worst-case tsu                                                                              ; N/A      ;
 
−
; Worst-case tco                                                                              ; N/A      ;
 
−
; Worst-case tpd                                                                              ; N/A      ;
 
−
; Worst-case th                                                                                ; N/A      ;
 
 
  ; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk0' ; 1.547 ns  ;
 
  ; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk0' ; 1.547 ns  ;
 
  ; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk2' ; 1.985 ns  ;
 
  ; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk2' ; 1.985 ns  ;
 
  ; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk1' ; 2.067 ns  ;
 
  ; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk1' ; 2.067 ns  ;
−
; Clock Setup: 'fibre_rx_clkr'                                                                ; 15.116 ns ;
 
−
; Clock Setup: 'manch_pll:manch_pll_block|altpll:altpll_component|_clk0'                      ; 18.723 ns ;
 
−
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk3' ; 36.327 ns ;
 
−
; Clock Hold: 'fibre_rx_clkr'                                                                  ; 0.445 ns  ;
 
−
; Clock Hold: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk0'  ; 0.643 ns  ;
 
−
; Clock Hold: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk3'  ; 0.643 ns  ;
 
−
; Clock Hold: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk2'  ; 0.689 ns  ;
 
−
; Clock Hold: 'manch_pll:manch_pll_block|altpll:altpll_component|_clk0'                        ; 0.693 ns  ;
 
−
; Clock Hold: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk1'  ; 2.989 ns  ;
 
−
; Total number of failed paths                                                                ;          ;
 
−
+----------------------------------------------------------------------------------------------+-----------+
 
  
−
== Revision 5.0.2 ==
+
==== Revision 5.0.2 ====
 
* '''Filename:'''  cc_v05000002_test00_tagged.sof
 
* '''Filename:'''  cc_v05000002_test00_tagged.sof
−
 
−
* '''To Do:'''
 
−
** ---
 
  
 
* '''Features:'''
 
* '''Features:'''
Line 141: Line 248:
 
** Based off of 5.0.1 and in parallel with 4.0.c (equivalent version)
 
** Based off of 5.0.1 and in parallel with 4.0.c (equivalent version)
 
** The Sync Box PLL was re-instated to the top level and routed to dv_rx.  It was mistakenly removed after v4.0.9, which means that the sync box sequence number decoding has not worked since then!  When collecting data while triggering off the Sync Box DV, the Clock Card would also sporadically trigger in between data frames.
 
** The Sync Box PLL was re-instated to the top level and routed to dv_rx.  It was mistakenly removed after v4.0.9, which means that the sync box sequence number decoding has not worked since then!  When collecting data while triggering off the Sync Box DV, the Clock Card would also sporadically trigger in between data frames.
−
** Fixed a bug in ret_dat_wbs that did not handle wb num_rows_reported and wb num_cols_reported commands correctly.
+
** Fixed a bug in ret_dat_wbs that did not handle wb {{param|cc|num_rows_reported}} and wb {{param|cc|num_cols_reported}} commands correctly.
−
 
 
−
* '''Details:'''
 
  
 
* '''Bugs:'''
 
* '''Bugs:'''
Line 149: Line 254:
  
 
* '''FPGA Resource Usage''' (clk_card.fit.rpt):
 
* '''FPGA Resource Usage''' (clk_card.fit.rpt):
−
+--------------------------------------------------------------------------+
 
−
; Fitter Summary                                                          ;
 
−
+--------------------------+-----------------------------------------------+
 
−
; Fitter Status            ; Successful - Wed Jul 15 13:40:33 2009        ;
 
−
; Quartus II Version      ; 9.0 Build 235 06/17/2009 SP 2 SJ Full Version ;
 
−
; Revision Name            ; clk_card                                      ;
 
−
; Top-level Entity Name    ; clk_card                                      ;
 
−
; Family                  ; Stratix                                      ;
 
−
; Device                  ; EP1S30F780C5                                  ;
 
−
; Timing Models            ; Final                                        ;
 
 
  ; Total logic elements    ; 17,598 / 32,470 ( 54 % )                      ;
 
  ; Total logic elements    ; 17,598 / 32,470 ( 54 % )                      ;
 
  ; Total pins              ; 254 / 598 ( 42 % )                            ;
 
  ; Total pins              ; 254 / 598 ( 42 % )                            ;
Line 166: Line 261:
 
  ; Total PLLs              ; 2 / 6 ( 33 % )                                ;
 
  ; Total PLLs              ; 2 / 6 ( 33 % )                                ;
 
  ; Total DLLs              ; 0 / 2 ( 0 % )                                ;
 
  ; Total DLLs              ; 0 / 2 ( 0 % )                                ;
−
+--------------------------+-----------------------------------------------+
 
  
 
* '''Timing Analyzer Summary''' (clk_card.tan.rpt):
 
* '''Timing Analyzer Summary''' (clk_card.tan.rpt):
−
+-----------------------------------------------------------------------------------------------------------
 
−
; Timing Analyzer Summary                                                                                 
 
−
+----------------------------------------------------------------------------------------------+-----------+
 
−
; Type                                                                                        ; Slack    ;
 
−
+----------------------------------------------------------------------------------------------+-----------+
 
−
; Worst-case tsu                                                                              ; N/A      ;
 
−
; Worst-case tco                                                                              ; N/A      ;
 
−
; Worst-case tpd                                                                              ; N/A      ;
 
−
; Worst-case th                                                                                ; N/A      ;
 
 
  ; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk0' ; 1.965 ns  ;
 
  ; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk0' ; 1.965 ns  ;
 
  ; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk1' ; 2.041 ns  ;
 
  ; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk1' ; 2.041 ns  ;
 
  ; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk2' ; 3.548 ns  ;
 
  ; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk2' ; 3.548 ns  ;
−
; Clock Setup: 'fibre_rx_clkr'                                                                ; 14.442 ns ;
 
−
; Clock Setup: 'manch_pll:manch_pll_block|altpll:altpll_component|_clk0'                      ; 19.107 ns ;
 
−
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk3' ; 35.792 ns ;
 
−
; Clock Hold: 'fibre_rx_clkr'                                                                  ; 0.445 ns  ;
 
−
; Clock Hold: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk0'  ; 0.526 ns  ;
 
−
; Clock Hold: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk2'  ; 0.540 ns  ;
 
−
; Clock Hold: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk3'  ; 0.544 ns  ;
 
−
; Clock Hold: 'manch_pll:manch_pll_block|altpll:altpll_component|_clk0'                        ; 0.547 ns  ;
 
−
; Clock Hold: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk1'  ; 2.989 ns  ;
 
−
; Total number of failed paths                                                                ;          ;
 
−
+----------------------------------------------------------------------------------------------+-----------+
 
  
−
== Revision 5.0.1 (Buggy) ==
+
==== Revision 5.0.1 (buggy) ====
 
* '''Filename:'''  cc_v05000001_12may2009.sof
 
* '''Filename:'''  cc_v05000001_12may2009.sof
−
 
−
* '''To Do:'''
 
−
** ---
 
  
 
* '''Features:'''
 
* '''Features:'''
Line 211: Line 282:
  
 
* '''FPGA Resource Usage''' (clk_card.fit.rpt):
 
* '''FPGA Resource Usage''' (clk_card.fit.rpt):
−
+---------------------------------------------------------------------+
 
−
; Fitter Summary                                                      ;
 
−
+--------------------------+------------------------------------------+
 
−
; Fitter Status            ; Successful - Tue May 12 16:12:06 2009    ;
 
−
; Quartus II Version      ; 8.1 Build 163 10/28/2008 SJ Full Version ;
 
−
; Revision Name            ; clk_card                                ;
 
−
; Top-level Entity Name    ; clk_card                                ;
 
−
; Family                  ; Stratix                                  ;
 
−
; Device                  ; EP1S30F780C5                            ;
 
−
; Timing Models            ; Final                                    ;
 
 
  ; Total logic elements    ; 18,286 / 32,470 ( 56 % )                ;
 
  ; Total logic elements    ; 18,286 / 32,470 ( 56 % )                ;
 
  ; Total pins              ; 259 / 598 ( 43 % )                      ;
 
  ; Total pins              ; 259 / 598 ( 43 % )                      ;
Line 228: Line 289:
 
  ; Total PLLs              ; 1 / 6 ( 17 % )                          ;
 
  ; Total PLLs              ; 1 / 6 ( 17 % )                          ;
 
  ; Total DLLs              ; 0 / 2 ( 0 % )                            ;
 
  ; Total DLLs              ; 0 / 2 ( 0 % )                            ;
−
+--------------------------+------------------------------------------+
 
  
 
* '''Timing Analyzer Summary''' (clk_card.tan.rpt):
 
* '''Timing Analyzer Summary''' (clk_card.tan.rpt):
−
+-----------------------------------------------------------------------------------------------------------
 
−
; Timing Analyzer Summary                                                                                 
 
−
+----------------------------------------------------------------------------------------------+-----------+
 
−
; Type                                                                                        ; Slack    ;
 
−
+----------------------------------------------------------------------------------------------+-----------+
 
−
; Worst-case tsu                                                                              ; N/A      ;
 
−
; Worst-case tco                                                                              ; N/A      ;
 
−
; Worst-case tpd                                                                              ; N/A      ;
 
−
; Worst-case th                                                                                ; N/A      ;
 
 
  ; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk0' ; 1.995 ns  ;
 
  ; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk0' ; 1.995 ns  ;
 
  ; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk2' ; 3.585 ns  ;
 
  ; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk2' ; 3.585 ns  ;
 
  ; Clock Setup: 'altera_internal_jtag~TCKUTAP'                                                  ; 5.644 ns  ;
 
  ; Clock Setup: 'altera_internal_jtag~TCKUTAP'                                                  ; 5.644 ns  ;
−
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk1' ; 9.234 ns  ;
 
−
; Clock Setup: 'fibre_rx_clkr'                                                                ; 14.381 ns ;
 
−
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk3' ; 34.916 ns ;
 
−
; Clock Hold: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk0'  ; 0.445 ns  ;
 
−
; Clock Hold: 'fibre_rx_clkr'                                                                  ; 0.445 ns  ;
 
−
; Clock Hold: 'altera_internal_jtag~TCKUTAP'                                                  ; 0.534 ns  ;
 
−
; Clock Hold: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk3'  ; 0.544 ns  ;
 
−
; Clock Hold: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk2'  ; 0.658 ns  ;
 
−
; Clock Hold: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk1'  ; 10.656 ns ;
 
−
; Total number of failed paths                                                                ;          ;
 
−
+----------------------------------------------------------------------------------------------+-----------+
 
  
−
== Revision 5.0.0 (Buggy) ==
+
==== Revision 5.0.0 (buggy) ====
 
* '''Filename:'''  cc_v05000000_22dec2008.sof (tagged as sys_v05000000_22dec2008)
 
* '''Filename:'''  cc_v05000000_22dec2008.sof (tagged as sys_v05000000_22dec2008)
−
 
−
* '''To Do:'''
 
−
** ---
 
  
 
* '''Features:'''
 
* '''Features:'''
Line 266: Line 303:
 
** This version is based on 4.0.a.  That is, it includes all of the features that were under development in 4.0.a, even though 4.0.a was not released for telescope use.
 
** This version is based on 4.0.a.  That is, it includes all of the features that were under development in 4.0.a, even though 4.0.a was not released for telescope use.
 
** Added the ability to read out a single column of data continuously from one Readout Card
 
** Added the ability to read out a single column of data continuously from one Readout Card
−
** New commands include: readout_col_index, readout_priority, num_cols_reported
+
** New commands include: readout_col_index, readout_priority, {{param|cc|num_cols_reported}}
 
** To allow enough data bandwidth, the spare LVDS line from each card to the Clock Card is now used
 
** To allow enough data bandwidth, the spare LVDS line from each card to the Clock Card is now used
  
Line 275: Line 312:
  
 
* '''FPGA Resource Usage''' (clk_card.fit.rpt):
 
* '''FPGA Resource Usage''' (clk_card.fit.rpt):
−
+---------------------------------------------------------------------+
 
−
; Fitter Summary                                                      ;
 
−
+--------------------------+------------------------------------------+
 
−
; Fitter Status            ; Successful - Thu Jan 15 17:18:34 2009    ;
 
−
; Quartus II Version      ; 8.1 Build 163 10/28/2008 SJ Full Version ;
 
−
; Revision Name            ; readout_card                            ;
 
−
; Top-level Entity Name    ; readout_card                            ;
 
−
; Family                  ; Stratix                                  ;
 
−
; Device                  ; EP1S40F780C6                            ;
 
−
; Timing Models            ; Final                                    ;
 
 
  ; Total logic elements    ; 26,607 / 41,250 ( 65 % )                ;
 
  ; Total logic elements    ; 26,607 / 41,250 ( 65 % )                ;
 
  ; Total pins              ; 358 / 616 ( 58 % )                      ;
 
  ; Total pins              ; 358 / 616 ( 58 % )                      ;
Line 292: Line 319:
 
  ; Total PLLs              ; 1 / 6 ( 17 % )                          ;
 
  ; Total PLLs              ; 1 / 6 ( 17 % )                          ;
 
  ; Total DLLs              ; 0 / 2 ( 0 % )                            ;
 
  ; Total DLLs              ; 0 / 2 ( 0 % )                            ;
−
+--------------------------+------------------------------------------+
 
  
 
* '''Timing Analyzer Summary''' (clk_card.tan.rpt):
 
* '''Timing Analyzer Summary''' (clk_card.tan.rpt):
−
+---------------------------------------------------------------------------
 
−
; Timing Analyzer Summary
 
−
+--------------------------------------------------------------+-----------+
 
−
; Type                                                        ; Slack    ;
 
−
+--------------------------------------------------------------+-----------+
 
−
; Worst-case tsu                                              ; N/A      ;
 
−
; Worst-case tco                                              ; N/A      ;
 
−
; Worst-case th                                                ; N/A      ;
 
 
  ; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.558 ns  ;
 
  ; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.558 ns  ;
 
  ; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.892 ns  ;
 
  ; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.892 ns  ;
 
  ; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.987 ns ;
 
  ; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.987 ns ;
−
; Clock Hold: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0'  ; 0.741 ns  ;
 
−
; Clock Hold: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2'  ; 0.762 ns  ;
 
−
; Clock Hold: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3'  ; 0.763 ns  ;
 
−
; Total number of failed paths                                ;          ;
 
−
+--------------------------------------------------------------+-----------+
 
−
 
−
== Revision 4.0.c ==
 
−
* '''Filename:'''  cc_v0400000c_24aug2009.sof
 
−
 
−
* '''To Do:'''
 
−
** ---
 
−
 
−
* '''Features:'''
 
−
** Header Version 6
 
−
** Based on v4.0.b, with a fix to the sync box interface for a bug that caused the Clock Card data collection logic to trigger sporadically.
 
−
 
−
* '''Details:'''
 
−
** clk_card.vhd:  re-instantiated the manchester PLL, and routed the manch_clk to dv_rx.
 
−
 
−
* '''Bugs:'''
 
−
** None yet.
 
−
 
−
* '''FPGA Resource Usage''' (clk_card.fit.rpt):
 
−
+--------------------------------------------------------------------------+
 
−
; Fitter Summary                                                          ;
 
−
+--------------------------+-----------------------------------------------+
 
−
; Fitter Status            ; Successful - Mon Aug 24 14:18:05 2009        ;
 
−
; Quartus II Version      ; 9.0 Build 235 06/17/2009 SP 2 SJ Full Version ;
 
−
; Revision Name            ; clk_card                                      ;
 
−
; Top-level Entity Name    ; clk_card                                      ;
 
−
; Family                  ; Stratix                                      ;
 
−
; Device                  ; EP1S30F780C5                                  ;
 
−
; Timing Models            ; Final                                        ;
 
−
; Total logic elements    ; 14,965 / 32,470 ( 46 % )                      ;
 
−
; Total pins              ; 254 / 598 ( 42 % )                            ;
 
−
; Total virtual pins      ; 0                                            ;
 
−
; Total memory bits        ; 812,544 / 3,317,184 ( 24 % )                  ;
 
−
; DSP block 9-bit elements ; 10 / 96 ( 10 % )                              ;
 
−
; Total PLLs              ; 2 / 6 ( 33 % )                                ;
 
−
; Total DLLs              ; 0 / 2 ( 0 % )                                ;
 
−
+--------------------------+-----------------------------------------------+
 
−
 
−
* '''Timing Analyzer Summary''' (clk_card.tan.rpt):
 
−
+-----------------------------------------------------------------------------------------------------------
 
−
; Timing Analyzer Summary                                                                                 
 
−
+----------------------------------------------------------------------------------------------+-----------+
 
−
; Type                                                                                        ; Slack    ;
 
−
+----------------------------------------------------------------------------------------------+-----------+
 
−
; Worst-case tsu                                                                              ; N/A      ;
 
−
; Worst-case tco                                                                              ; N/A      ;
 
−
; Worst-case tpd                                                                              ; N/A      ;
 
−
; Worst-case th                                                                                ; N/A      ;
 
−
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk0' ; 1.646 ns  ;
 
−
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk1' ; 2.167 ns  ;
 
−
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk2' ; 2.919 ns  ;
 
−
; Clock Setup: 'fibre_rx_clkr'                                                                ; 14.506 ns ;
 
−
; Clock Setup: 'manch_pll:manch_pll_block|altpll:altpll_component|_clk0'                      ; 19.104 ns ;
 
−
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk3' ; 35.811 ns ;
 
−
; Clock Hold: 'fibre_rx_clkr'                                                                  ; 0.445 ns  ;
 
−
; Clock Hold: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk0'  ; 0.528 ns  ;
 
−
; Clock Hold: 'manch_pll:manch_pll_block|altpll:altpll_component|_clk0'                        ; 0.539 ns  ;
 
−
; Clock Hold: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk2'  ; 0.542 ns  ;
 
−
; Clock Hold: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk3'  ; 0.544 ns  ;
 
−
; Clock Hold: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk1'  ; 2.989 ns  ;
 
−
; Total number of failed paths                                                                ;          ;
 
−
+----------------------------------------------------------------------------------------------+-----------+
 
−
 
−
== Revision 4.0.b (Buggy) ==
 
−
* '''Filename:'''  cc_v0400000b_03jun2009.sof
 
−
 
−
* '''To Do:'''
 
−
** ---
 
−
 
−
* '''Features:'''
 
−
** Header Version 6
 
−
** Based on v4.0.a, with the necessary bug fixes to be as stable as v5.0.1 without implementing the dual-LVDS feature.
 
−
** STOP commands are meant to work in this revision.  The successful execution of STOP commands through the system depends also on the PCI card firmware, and PCI driver.  Modifications have been made to these, and their version numbers have been bumped to...
 
−
** This firmware is a hybrid version that implements a single LVDS line, but has STOP and On-The-Fly capabilities built in.  The purpose of this firmware is to give SCUBA-2 these features without forcing them to upgrade the firmware on all their other cards.
 
−
 
−
* '''Details:'''
 
−
** [[VHDL changes from v4.0.a and v4.0.b]]
 
−
 
−
* '''Bugs:'''
 
−
** There may be a problem with decoding sync numbers from the sync box.
 
−
 
−
* '''FPGA Resource Usage''' (clk_card.fit.rpt):
 
−
+---------------------------------------------------------------------+
 
−
; Fitter Summary                                                      ;
 
−
+--------------------------+------------------------------------------+
 
−
; Fitter Status            ; Successful - Wed Jun 03 15:35:18 2009    ;
 
−
; Quartus II Version      ; 8.1 Build 163 10/28/2008 SJ Full Version ;
 
−
; Revision Name            ; clk_card                                ;
 
−
; Top-level Entity Name    ; clk_card                                ;
 
−
; Family                  ; Stratix                                  ;
 
−
; Device                  ; EP1S30F780C5                            ;
 
−
; Timing Models            ; Final                                    ;
 
−
; Total logic elements    ; 15,023 / 32,470 ( 46 % )                ;
 
−
; Total pins              ; 254 / 598 ( 42 % )                      ;
 
−
; Total virtual pins      ; 0                                        ;
 
−
; Total memory bits        ; 812,544 / 3,317,184 ( 24 % )            ;
 
−
; DSP block 9-bit elements ; 10 / 96 ( 10 % )                        ;
 
−
; Total PLLs              ; 1 / 6 ( 17 % )                          ;
 
−
; Total DLLs              ; 0 / 2 ( 0 % )                            ;
 
−
+--------------------------+------------------------------------------+
 
−
 
−
* '''Timing Analyzer Summary''' (clk_card.tan.rpt):
 
−
+-----------------------------------------------------------------------------------------------------------
 
−
; Timing Analyzer Summary                                                                                 
 
−
+----------------------------------------------------------------------------------------------+-----------+
 
−
; Type                                                                                        ; Slack    ;
 
−
+----------------------------------------------------------------------------------------------+-----------+
 
−
; Worst-case tsu                                                                              ; N/A      ;
 
−
; Worst-case tco                                                                              ; N/A      ;
 
−
; Worst-case tpd                                                                              ; N/A      ;
 
−
; Worst-case th                                                                                ; N/A      ;
 
−
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk1' ; 1.328 ns  ;
 
−
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk0' ; 1.442 ns  ;
 
−
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk2' ; 3.383 ns  ;
 
−
; Clock Setup: 'fibre_rx_clkr'                                                                ; 11.093 ns ;
 
−
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk3' ; 36.700 ns ;
 
−
; Clock Hold: 'fibre_rx_clkr'                                                                  ; 0.445 ns  ;
 
−
; Clock Hold: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk0'  ; 0.532 ns  ;
 
−
; Clock Hold: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk3'  ; 0.542 ns  ;
 
−
; Clock Hold: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk2'  ; 0.556 ns  ;
 
−
; Clock Hold: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk1'  ; 2.989 ns  ;
 
−
; Total number of failed paths                                                                ;          ;
 
−
+----------------------------------------------------------------------------------------------+-----------+
 
−
 
−
== Revision 4.0.a (Not for Telescope Use) ==
 
−
* '''Filename:'''  cc_v0400000a_16oct2008
 
−
 
−
* '''To Do:'''
 
−
** Make sure that the errno word, and the cards to report word in the data frame header agree with cards_to_report
 
−
 
−
* '''Features:'''
 
−
** Header Version 6
 
−
** Based on 4.0.9
 
−
** Added stop_dly, rcs_to_report_data, and cards_to_report commands
 
−
** Added support for commands to the MCE during data acquisition
 
−
 
−
* '''Details:'''
 
−
** '''clk_card.vhd:'''  incremented the firmware version number, and added cards_to_report interface signals; added support for the stop_dly, rcs_to_report_data, and cards_to_report commands; Removed the Manchester PLL because the only way to ensure that packets are received without trouble is for the main PLL to be locked on the Manchester clock.  The Manchester PLL was a failed attempted around this.
 
−
** '''clock_card_pack.vhd:'''  added support for the stop_dly, rcs_to_report_data, and cards_to_report commands
 
−
** '''issue_reply.vhd:'''  added support for the stop_dly, rcs_to_report_data, and cards_to_report commands
 
−
** '''cmd_translator.vhd:'''  split up command registers so that it can handle WB/RB/RS commands while acquiring data based on a GO command.
 
−
** '''issue_reply_pack.vhd:'''  added indexing constants.
 
−
** '''reply_queue.vhd:'''  modified the logic for calculating the reply data size, in response to the addition of the rcs_to_report_data, and cards_to_report commands
 
−
** '''reply_queue_sequencer.vhd:'''  modified the logic for reading the data from the reply queues; modified the logic for determining when to stop readout from a card queue to ease timing constraints.  Changed to logic for multiplexing the data buses from the reply queues to combinatorial logic to ease timing constraints.
 
−
** '''reply_translator.vhd:''' added a stop_delay counter for delaying the replies to 'stop ret_dat' commands; added the QUICK_REPLY and QUICK_REPLY_PAUSE states to pause the return of replies to stop commands; added extra handling to the LD_STATUS state to avoid mixing stop replies, and replies to data or simple commands; added stop reply pause logic to DONE state
 
−
** '''ret_dat_wbs.vhd:'''  added the stop_delay_o, rcs_to_report_data, and cards_to_report_o interfaces; implemented a custom register from cards_to_report and stop_delay; removed the register for ret_dat_card_addr which was a special case of cards_to_report.
 
−
** '''ret_dat_wbs_pack:''' added the constant DEFAULT_CARDS_TO_REPORT
 
−
 
−
* '''Bugs:'''
 
−
** Reading back rcs_to_report_data returns zero (fixed)
 
−
** Can't issue simple commands during data taking
 
−
** Can't read from RC4 (fixed)
 
−
** There may be a problem with decoding sync numbers from the sync box.
 
−
 
−
* '''FPGA Resource Usage''' (clk_card.fit.rpt):
 
−
+--------------------------------------------------------------------------+
 
−
; Fitter Summary                                                          ;
 
−
+--------------------------+-----------------------------------------------+
 
−
; Fitter Status            ; Successful - Fri Nov 21 12:19:34 2008        ;
 
−
; Quartus II Version      ; 8.0 Build 231 07/10/2008 SP 1 SJ Full Version ;
 
−
; Revision Name            ; clk_card                                      ;
 
−
; Top-level Entity Name    ; clk_card                                      ;
 
−
; Family                  ; Stratix                                      ;
 
−
; Device                  ; EP1S30F780C5                                  ;
 
−
; Timing Models            ; Final                                        ;
 
−
; Total logic elements    ; 14,542 / 32,470 ( 45 % )                      ;
 
−
; Total pins              ; 254 / 598 ( 42 % )                            ;
 
−
; Total virtual pins      ; 0                                            ;
 
−
; Total memory bits        ; 812,544 / 3,317,184 ( 24 % )                  ;
 
−
; DSP block 9-bit elements ; 8 / 96 ( 8 % )                                ;
 
−
; Total PLLs              ; 1 / 6 ( 17 % )                                ;
 
−
; Total DLLs              ; 0 / 2 ( 0 % )                                ;
 
−
+--------------------------+-----------------------------------------------+
 
−
 
−
* '''Timing Analyzer Summary''' (clk_card.tan.rpt):
 
−
+---------------------------------------+-----------+
 
−
; Type                                  ; Slack    ;
 
−
+---------------------------------------+-----------+
 
−
; Worst-case tsu                        ; N/A      ;
 
−
; Worst-case tco                        ; N/A      ;
 
−
; Worst-case tpd                        ; N/A      ;
 
−
; Worst-case th                        ; N/A      ;
 
−
; Clock Setup: 'clk_switchover:t|_clk0' ; 1.712 ns  ;
 
−
; Clock Setup: 'clk_switchover:t|_clk1' ; 2.632 ns  ;
 
−
; Clock Setup: 'clk_switchover:t|_clk2' ; 3.884 ns  ;
 
−
; Clock Setup: 'fibre_rx_clkr'          ; 13.678 ns ;
 
−
; Clock Setup: 'clk_switchover:t|_clk3' ; 36.938 ns ;
 
−
; Clock Hold: 'fibre_rx_clkr'          ; 0.445 ns  ;
 
−
; Clock Hold: 'clk_switchover:c|_clk0'  ; 0.531 ns  ;
 
−
; Clock Hold: 'clk_switchover:c|_clk3'  ; 0.541 ns  ;
 
−
; Clock Hold: 'clk_switchover:c|_clk2'  ; 0.544 ns  ;
 
−
; Clock Hold: 'clk_switchover:c|_clk1'  ; 2.989 ns  ;
 
−
; Total number of failed paths          ;          ;
 
−
+---------------------------------------+-----------+
 
−
 
−
== Revision 4.0.9 ==
 
−
* '''Filename:'''  cc_v04000009
 
−
 
−
* '''Features:'''
 
−
** Header Version 6
 
−
** Integrated a bug fix for the sram_ctrl block
 
−
** Integrated new all_cards block of code which was causing a synthesis warning in ModelSim
 
−
** Two new commands added: card_type, scratch.
 
−
 
−
* '''Bugs:'''
 
−
** None to report so far
 
−
 
−
* '''FPGA Resource Usage''' (clk_card.fit.rpt):
 
−
+---------------------------------------------------------------------+
 
−
; Fitter Summary                                                      ;
 
−
+--------------------------+------------------------------------------+
 
−
; Fitter Status            ; Successful - Thu Feb 21 16:56:34 2008    ;
 
−
; Quartus II Version      ; 6.1 Build 201 11/27/2006 SJ Full Version ;
 
−
; Revision Name            ; clk_card                                ;
 
−
; Top-level Entity Name    ; clk_card                                ;
 
−
; Family                  ; Stratix                                  ;
 
−
; Device                  ; EP1S30F780C5                            ;
 
−
; Timing Models            ; Final                                    ;
 
−
; Total logic elements    ; 14,144 / 32,470 ( 44 % )                ;
 
−
; Total pins              ; 254 / 598 ( 42 % )                      ;
 
−
; Total virtual pins      ; 0                                        ;
 
−
; Total memory bits        ; 812,544 / 3,317,184 ( 24 % )            ;
 
−
; DSP block 9-bit elements ; 8 / 96 ( 8 % )                          ;
 
−
; Total PLLs              ; 2 / 6 ( 33 % )                          ;
 
−
; Total DLLs              ; 0 / 2 ( 0 % )                            ;
 
−
+--------------------------+------------------------------------------+
 
−
* '''Timing Analyzer Summary''' (clk_card.tan.rpt):
 
−
+-----------------------------------------------------------------------------------------------------------
 
−
; Timing Analyzer Summary                                                                                 
 
−
+----------------------------------------------------------------------------------------------+-----------+
 
−
; Type                                                                                        ; Slack    ;
 
−
+----------------------------------------------------------------------------------------------+-----------+
 
−
; Worst-case tsu                                                                              ; N/A      ;
 
−
; Worst-case tco                                                                              ; N/A      ;
 
−
; Worst-case tpd                                                                              ; N/A      ;
 
−
; Worst-case th                                                                                ; N/A      ;
 
−
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk1' ; 0.294 ns  ;
 
−
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk0' ; 2.091 ns  ;
 
−
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk2' ; 2.711 ns  ;
 
−
; Clock Setup: 'fibre_rx_clkr'                                                                ; 16.125 ns ;
 
−
; Clock Setup: 'manch_pll:manch_pll_block|altpll:altpll_component|_clk0'                      ; 18.658 ns ;
 
−
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk3' ; 35.366 ns ;
 
−
; Clock Hold: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk0'  ; 0.445 ns  ;
 
−
; Clock Hold: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk3'  ; 0.445 ns  ;
 
−
; Clock Hold: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk2'  ; 0.542 ns  ;
 
−
; Clock Hold: 'manch_pll:manch_pll_block|altpll:altpll_component|_clk0'                        ; 0.542 ns  ;
 
−
; Clock Hold: 'fibre_rx_clkr'                                                                  ; 0.543 ns  ;
 
−
; Clock Hold: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk1'  ; 2.989 ns  ;
 
−
; Total number of failed paths                                                                ;          ;
 
−
+----------------------------------------------------------------------------------------------+-----------+
 
−
 
−
= Firmware Links =
 
−
* [http://www.phas.ubc.ca/~mce/mcedocs/firmware/cc_fpga_programming_file_catalogue.pdf  Clock Card Firmware Catalog]
 
−
* [http://www.phas.ubc.ca/~mce/mcedocs/firmware/ Firmware Downloads]
 
  
−
= Wiki Links =
+
[[Category:Clock Card Firmware| ]]
−
* [http://e-mode.phas.ubc.ca/mcewiki/index.php/MCE_firmware  MCE Firmware Page]
 
−
* [http://e-mode.phas.ubc.ca/mcewiki/index.php/Main_Page  MCE Main Page]
 

Latest revision as of 14:52, 19 February 2018

Firmware links

Firmware Revision Listing

Revision 6.0.2

  • Filename: cc_v06000002_20160530.sof
  • Features: support of upper 32 word needs an additional wait cycle for ack_read
  • Features:fpga_clr and critical_error_rst commands added
  • Note: skip 6.0.1 due to losing track of all_cards
  • bug: When stop command is issued, two frames are sent with both last-frame-bit and stop-bit set. This is currently benign as mas ignores the extra frame, but needs to be fixed regardless.
  • bug: When data-timing-err bit is set, the last-frame-bit gets set but then the ret_dat counter doesn't not get reset, so when sync-dv starts coming in, clock card continues to send out frames again.

Revision 5.0.e (stable)

  • Filename: cc_v0500000e_15may2012.sof
  • Features: added pcb_rev interface to be able to read pcb revision starting RevC Clock Card.
  • bugfix: awg is now realigned with data-acquisition and the phase can be adjusted using ramp_step_phase.
  • bugfix: A time-delay is added between assertion of epc_sel and config_n to remedy the occasional failure of config_app and config_fac commands.
  • bug: When stop command is issued, two frames are sent with both last-frame-bit and stop-bit set. This is currently benign as mas ignores the extra frame, but needs to be fixed regardless.
  • bug: When data-timing-err bit is set, the last-frame-bit gets set but then the ret_dat counter doesn't not get reset, so when sync-dv starts coming in, clock card continues to send out frames again.

Revision 5.0.d (test)

  • Filename: cc_v0500000d_10may2012.sof
  • Features: Internal commands are issued at address-return-to-zero (ARZ) to provide more deterministic timing. This means the data_rate has to be at least 2, or internal commands will stop with a data_rate of 1. In previous versions, internal commands were being issued asynchronous to ARZ. The phase of the ramp or awg can be adjusted using ramp_step_phase.
  • bugfix: stop cmd works now and sets the stop-bit and last-frame-bit properly in the frame status word of the last frame.
  • bugfix: the ramp/awg value reported in the header is the one applied last. Previous versions reported what was going to be applied in the next iteration. If the command was not issued due to collision, then the value in the header was still being updated which was a bug.
  • bug: awg mode doesn't work properly.

Revision 5.0.c (test)

  • Filename: cc_v0500000c_26mar2012.sof
  • Features: frame header revision 7 with dv_pulse_fibre_i encoded as bit 9 of the frame-status word in the header.
    • Based on 5.0.a
  • Bugs: stop cmd may be broken?!It works but stop bit and last-frame bits are not set and a fakestop needs to be issued in mas.

Revision 5.0.b (test)

  • Filename: cc_v0500000b_06feb2012.sof
  • Features: based on 5.0.a, frame header revision 7 with dv_pulse_fibre_i encoded as bit 9 of the frame-status word in the header.
  • Bugs: stop cmd may be broken?!It works but stop bit is not set and a fakestop needs to be issued in mas.

Revision 5.0.a (test)

  • Filename: cc_v0500000a_06feb2012.sof
  • Features: Based on 5.0.9
  • Bugfix: last-frame-bit was not being set in 5.0.9 and it returns right number of frames!
  • Bugs: stop cmd may be broken. It works but stop bit is not set.

Revision 5.0.9 (test)

  • Filename: cc_v05000009_26jan2012.sof
  • Bugfix:
    • Internal housekeeping and internal ramp/awg commands can be run as tight as possible (data_rate=2 and ramp_step_period=2) alongside data acquisition without affecting data timing. Previous versions would hold the ramp-value refresh till data was collected first. In this version when there is a collision between ret_dat and ramp-command, the ramp value is still increased, so the next time it is due, it would apply the right value.
  • Bugs:
    • config_app command is broken, it works in 5.0.3, but not in this version. to be investigated.
    • command issue/reply translator blocks are overhauled, so watch out for bugs related to stop command. None discovered yet though.

Revision 5.0.8 (not issued)

  • Filename: cc_v05000008_12jul2011.sof
  • Features:
    • This tag was a place holder for the final version of Clock Cards with Ethernet support (CCwE). This tag currently references unfinished code in CVS. The Quartus project file in this tag is designed for the Altera Stratix I Development Board.
    • Header Version 6
    • Based on 5.0.7

Revision 5.0.7 (stable)

  • Filename: cc_v05000007_14may2010.sof
  • Features:
    • Header Version 6
    • Based on 5.0.6
    • Compatible with MCE Jam Player -- SVN revision 16 (~/jp_25/mce_jam/trunk)
    • Simulation compatible with firmware v5.0.0 for the other cards.
    • Fixed a bug that caused a Clock Card with version 5.x.x firmware installed to return stale data for cards that had version 4.x.x. firmware installed on them.
    • Fixed a bug that caused a Clock Card to return stale data if a card was not present, or not configured. Now the Clock Card returns 0x00000000.
  • Bugs:
    • internal_ramp and internal_awg only refresh on readout-frame rate (data_rate). So effective ramp_step_period is data_rate.
    • When both internal and data commands are scheduled to be issued on multiplexing frame N, then at ARZ, data command is issued first, followed by the internal command. This may cause problems when the internal command is not completed (too many words and row_len x num_rows not long enough) before next ARZ.
    • config_app command is broken (sometimes fails), it works in 5.0.3, but not in this version.
  • FPGA Resource Usage (clk_card.fit.rpt):
; Total logic elements     ; 18,745 / 32,470 ( 58 % )                      ;
; Total pins               ; 243 / 598 ( 41 % )                            ;
; Total virtual pins       ; 0                                             ;
; Total memory bits        ; 957,952 / 3,317,184 ( 29 % )                  ;
; DSP block 9-bit elements ; 10 / 96 ( 10 % )                              ;
; Total PLLs               ; 2 / 6 ( 33 % )                                ;
; Total DLLs               ; 0 / 2 ( 0 % )                                 ;
  • Timing Analyzer Summary (clk_card.tan.rpt):
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk1' ; 0.279 ns  ;
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk0' ; 0.437 ns  ;
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk2' ; 3.224 ns  ;

Revision 5.0.6 (buggy)

  • Filename: cc_v05000006_21apr2010.sof
  • Features:
    • Header Version 6
    • Based on 5.0.5
    • Fixed a bug that prevented the Clock Card from loading firmware from its Factory Configuration Device when sw1:p1 is set to open (to enable remote configuration).
    • This version of firmware works in conjunction with modified Jam Player code that was recently committed to SVN tag: ~/jp_25/mce_jam/trunk : revision 16.
  • Details:
    • To learn how to use remote configuration: Remote Firmware Update.
    • For .jam file conversions, see: MCE Programming File Conversions.
    • Removed crc_error functionality for now. It will get added back in when it is working. It was found to conflict with the Remote Configuration functionality by preventing the Clock Card from configuring from its Factory Configuration Device.
  • Bugs:
    • Has a bug that causes the Clock Card with version 5.x.x firmware installed to return stale data for cards that have version 4.x.x. firmware installed on them.
    • Has a bug that causes the Clock Card to return stale data if a card is not present, or not configured.
  • FPGA Resource Usage (clk_card.fit.rpt):
; Total logic elements     ; 18,652 / 32,470 ( 57 % )                      ;
; Total pins               ; 243 / 598 ( 41 % )                            ;
; Total virtual pins       ; 0                                             ;
; Total memory bits        ; 957,952 / 3,317,184 ( 29 % )                  ;
; DSP block 9-bit elements ; 10 / 96 ( 10 % )                              ;
; Total PLLs               ; 2 / 6 ( 33 % )                                ;
; Total DLLs               ; 0 / 2 ( 0 % )                                 ;
  • Timing Analyzer Summary (clk_card.tan.rpt):
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk0' ; 0.590 ns 
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk1' ; 1.683 ns  
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk2' ; 3.277 ns

Revision 5.0.5 (buggy)

  • Filename: cc_v05000005_05mar2010.sof
  • Features:
    • Header Version 6
    • Based on 5.0.4
    • Implemented unpacking logic for TMS and TDI signals, and inferring logic for TCK. This is the solution to the JTAG packing problem.
    • This version of firmware works in conjunction with modified Jam Player code that was recently committed to SVN tag: ~/jp_25/mce_jam/trunk : revision 8.
  • Details:
    • Added the following commands: upload_fw, config_jtag, tdo_sample_dly, tck_half_period
    • This firmware solves the TMS and TDI packing problem such that a "wb cc upload_fw" command contains the following:
      • Word 0: total number of valid bits contained in words 1-n
      • Word 1-n: (tms,tdi) pairs starting from word 1 (bits 1,0), word 1 (bits 3,2), etc.
    • The TDO packing is done differently: the tdo bits are captured by a shift register, and shifted from LSB to MSB, up to a maximum of 16 TDO bits per 32-bit fibre word.
  • Bugs:
    • Does not configure from its Factory Configuration Device upon power-up
    • (non-critical) when a card does not return a valid reply, the clock card does not send an error reply back to the PC. Instead, it fills the data with whatever it had in its buffer from previous command and sends it to mas.
  • FPGA Resource Usage (clk_card.fit.rpt):
; Total logic elements     ; 18,699 / 32,470 ( 58 % )                      ;
; Total pins               ; 261 / 598 ( 44 % )                            ;
; Total virtual pins       ; 0                                             ;
; Total memory bits        ; 957,952 / 3,317,184 ( 29 % )                  ;
; DSP block 9-bit elements ; 10 / 96 ( 10 % )                              ;
; Total PLLs               ; 2 / 6 ( 33 % )                                ;
; Total DLLs               ; 0 / 2 ( 0 % )                                 ;
  • Timing Analyzer Summary (clk_card.tan.rpt):
    • Note that the clock slack on clk0 has diminished significantly over the past few revisions. However, on this version, it increased again to a reasonable level.
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk1' ; 1.164 ns  ; 
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk0' ; 1.276 ns  ; 
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk2' ; 3.299 ns  ;

Revision 5.0.4 (buggy)

  • Filename: cc_v05000004_26feb2010.sof
  • Features:
    • Header Version 6
    • Based on 5.0.3
    • Added JTAG control registers that emulated a parallel port to allow Jam Player software to write to the MCE from a MAS PC and configure devices via JTAG.
      • JTAG0 -- Output data
      • JTAG1 -- Input data
      • JTAG2 -- JTAG Chain control
  • Details:
    • This version of firmware is compatible with ported JAM Player software that has been temporarily committed to CVS under \\mce\cards\clk_card\config_fpga\source\unix_code.
  • Bugs:
    • Does not configure from its Factory Configuration Device upon power-up
    • (non-critical) when a card does not return a valid reply, the clock card does not send an error reply back to the PC. Instead, it fills the data with whatever it had in its buffer from previous command and sends it to mas.
  • FPGA Resource Usage (clk_card.fit.rpt):
; Total logic elements     ; 17,827 / 32,470 ( 55 % )                      ;
; Total pins               ; 261 / 598 ( 44 % )                            ;
; Total virtual pins       ; 0                                             ;
; Total memory bits        ; 949,760 / 3,317,184 ( 29 % )                  ;
; DSP block 9-bit elements ; 10 / 96 ( 10 % )                              ;
; Total PLLs               ; 2 / 6 ( 33 % )                                ;
; Total DLLs               ; 0 / 2 ( 0 % )                                 ;
; M512s                    ; 66 / 295 ( 22 % )          
; M4Ks                     ; 171 / 171 ( 100 % )        
; M-RAMs                   ; 3 / 4 ( 75 % )
  • Timing Analyzer Summary (clk_card.tan.rpt):
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk0' ; 0.771 ns  ;
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk1' ; 1.576 ns  ;
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk2' ; 2.859 ns  ;

Revision 5.0.3 (tested)

  • Filename: cc_v05000003_13jan2010.sof
  • Features:
    • Header Version 6
    • Based on 5.0.2
    • Added a Stratix I generic parameter for synthesis-time library selection.
    • Made a top-level modification that makes the interface compatible with the LM95235, while maintaining backwards compatibility.
    • Added the following commands for applying maximum-length sequences to MCE outputs: AWG_SEQUENCE_LEN, AWG_DATA, AWG_ADDR. See Arbitrary Waveform Generator .
  • Bugs:
    • (non-critical) when a card does not return a valid reply, the clock card does not send an error reply back to the PC. Instead, it fills the data with whatever it had in its buffer from previous command and sends it to mas.
  • FPGA Resource Usage (clk_card.fit.rpt):
; Total logic elements     ; 18,095 / 32,470 ( 56 % )                      ;
; Total pins               ; 255 / 598 ( 43 % )                            ;
; Total virtual pins       ; 0                                             ;
; Total memory bits        ; 949,760 / 3,317,184 ( 29 % )                  ;
; DSP block 9-bit elements ; 10 / 96 ( 10 % )                              ;
; Total PLLs               ; 2 / 6 ( 33 % )                                ;
; Total DLLs               ; 0 / 2 ( 0 % )                                 ;
  • Timing Analyzer Summary (clk_card.tan.rpt):
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk0' ; 1.547 ns  ;
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk2' ; 1.985 ns  ;
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk1' ; 2.067 ns  ;

Revision 5.0.2

  • Filename: cc_v05000002_test00_tagged.sof
  • Features:
    • Header Version 6
    • Based off of 5.0.1 and in parallel with 4.0.c (equivalent version)
    • The Sync Box PLL was re-instated to the top level and routed to dv_rx. It was mistakenly removed after v4.0.9, which means that the sync box sequence number decoding has not worked since then! When collecting data while triggering off the Sync Box DV, the Clock Card would also sporadically trigger in between data frames.
    • Fixed a bug in ret_dat_wbs that did not handle wb num_rows_reported and wb num_cols_reported commands correctly.
  • Bugs:
    • (non-critical) when a card does not return a valid reply, the clock card does not send an error reply back to the PC. Instead, it fills the data with whatever it had in its buffer from previous command and sends it to mas.
  • FPGA Resource Usage (clk_card.fit.rpt):
; Total logic elements     ; 17,598 / 32,470 ( 54 % )                      ;
; Total pins               ; 254 / 598 ( 42 % )                            ;
; Total virtual pins       ; 0                                             ;
; Total memory bits        ; 818,688 / 3,317,184 ( 25 % )                  ;
; DSP block 9-bit elements ; 10 / 96 ( 10 % )                              ;
; Total PLLs               ; 2 / 6 ( 33 % )                                ;
; Total DLLs               ; 0 / 2 ( 0 % )                                 ;
  • Timing Analyzer Summary (clk_card.tan.rpt):
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk0' ; 1.965 ns  ;
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk1' ; 2.041 ns  ;
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk2' ; 3.548 ns  ;

Revision 5.0.1 (buggy)

  • Filename: cc_v05000001_12may2009.sof
  • Features:
    • Based on 5.0.0 and in parallel with 4.0.b (equivalent version)
    • Header Version 6
    • STOP commands are meant to work in this revision. The successful execution of STOP commands through the system depends also on the PCI card firmware, and PCI driver. Modifications have been made to these, and their version numbers have been bumped to...
  • Bugs:
    • There may be a problem with decoding sync numbers from the sync box.
  • FPGA Resource Usage (clk_card.fit.rpt):
; Total logic elements     ; 18,286 / 32,470 ( 56 % )                 ;
; Total pins               ; 259 / 598 ( 43 % )                       ;
; Total virtual pins       ; 0                                        ;
; Total memory bits        ; 1,537,536 / 3,317,184 ( 46 % )           ;
; DSP block 9-bit elements ; 10 / 96 ( 10 % )                         ;
; Total PLLs               ; 1 / 6 ( 17 % )                           ;
; Total DLLs               ; 0 / 2 ( 0 % )                            ;
  • Timing Analyzer Summary (clk_card.tan.rpt):
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk0' ; 1.995 ns  ;
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk2' ; 3.585 ns  ;
; Clock Setup: 'altera_internal_jtag~TCKUTAP'                                                  ; 5.644 ns  ;

Revision 5.0.0 (buggy)

  • Filename: cc_v05000000_22dec2008.sof (tagged as sys_v05000000_22dec2008)
  • Features:
    • Header Version 6
    • IMPORTANT: Must be used in conjunction with firmware v05000000 of all other cards!!!
    • This version is based on 4.0.a. That is, it includes all of the features that were under development in 4.0.a, even though 4.0.a was not released for telescope use.
    • Added the ability to read out a single column of data continuously from one Readout Card
    • New commands include: readout_col_index, readout_priority, num_cols_reported
    • To allow enough data bandwidth, the spare LVDS line from each card to the Clock Card is now used
  • Details:
  • Bugs:
    • There may be a problem with decoding sync numbers from the sync box.
  • FPGA Resource Usage (clk_card.fit.rpt):
; Total logic elements     ; 26,607 / 41,250 ( 65 % )                 ;
; Total pins               ; 358 / 616 ( 58 % )                       ;
; Total virtual pins       ; 0                                        ;
; Total memory bits        ; 406,016 / 3,423,744 ( 12 % )             ;
; DSP block 9-bit elements ; 76 / 112 ( 68 % )                        ;
; Total PLLs               ; 1 / 6 ( 17 % )                           ;
; Total DLLs               ; 0 / 2 ( 0 % )                            ;
  • Timing Analyzer Summary (clk_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.558 ns  ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.892 ns  ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.987 ns ;
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