Difference between revisions of "Readout Card firmware"

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−
= Recommended Firmware Revisions =
+
{{Related|Readout Card Firmware}}
−
* 5.5.0 for normal operation (http://www.phas.ubc.ca/~mce/mcedocs/firmware/)
+
An overview of the firmware implemented in Readout card is described here: [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/tech_description/SC2_ELE_S582_501_readout_card_description.pdf PDF]]
−
* 4.3.7 for 50MHz data acquisition (14 bit)
+
* Synthesis Reminders (for firmware developers)
−
* 4.2.7 for 50MHz data acquisition (8 bit)
+
** Remember that readout_card/fsfb_clac/source/rtl/ram_40x64.vhd must be initialized with the ram_40x64.hex file in the same directory.
 +
= Revision 6.0.3 =
 +
* '''Filename:'''
 +
** [http://e-mode.phas.ubc.ca/mce/firmware/rc_stratix3_v06000003_20160601.sof rc_stratix3_v06000003_20160601.sof]
 +
* ''' Features:'''
 +
** 6.0.2 was built based on a version that had an unsuccessful attempt to fix the filter dynamic-range issue. This version reverts back to 5.2.1 for fsfb_calc implementation.
 +
* '''bugs'''
 +
** per-pixel servo reset doesn't also reset the filter
 +
** resetting any pixel with per-pixel reset also resets all the pixels in the last row (as specified by {{param|sys|num_rows}}, ignoring {{param|ac|row_order}})
  
−
= Complete Firmware Revision Listing =
+
= Revision 6.0.2 (TEST!) =
 +
* '''Filename:''' 
 +
** [http://e-mode.phas.ubc.ca/mce/firmware/rc_stratix3_v06000002_20160509.sof rc_stratix3_v06000002_20160509.sof]
 +
** [http://e-mode.phas.ubc.ca/mce/firmware/rc_stratix3_v06000002_20160509.jic rc_stratix3_v06000002_20160509.jic]
  
−
== Revision 5.0.0 (Latest Release) ==
+
* '''Features'''
−
* '''Filename:'''  rc_v05000000_22dec2008.sof
+
**built based on 5.2.2
 +
**added support of upper 32 word needs an additional wait cycle for ack_read
 +
** delay wishbone readback by one clock cycle for reading back flx_quanta and adc_offset,
 +
** there seem to be a filter gain of factor of 2 added
 +
 
 +
* '''bugs'''
 +
** per-pixel servo reset doesn't also reset the filter
 +
** resetting any pixel with per-pixel reset also resets all the pixels in the last row (as specified by {{param|sys|num_rows}}, ignoring {{param|ac|row_order}})
 +
** it seems to have a different filter gain
 +
 
 +
= Revision 5.2.2 (TEST!) =
 +
* '''Filename:''' 
 +
** [http://e-mode.phas.ubc.ca/mce/firmware/rc_stratix3_v050200002_17oct2014.sof rc_stratix3_v050200002_17oct2014.sof]
 +
 
 +
* '''bugfix or enhancement?''' 
 +
** fixes a dynamic-range issue with the filter by applying a 20-bit window to the output of stage 1 filter (with lsb being configurable) before passing it on the next stage.
 +
* '''bugs'''
 +
** per-pixel servo reset doesn't also reset the filter
 +
** resetting any pixel with per-pixel reset also resets all the pixels in the last row (as specified by {{param|sys|num_rows}}, ignoring {{param|ac|row_order}})
 +
 
 +
= Revision 5.2.1 (recommended!) =
 +
* '''Filename:''' 
 +
** rc_stratixIII_v05020001_05jun2014.sof
 +
 
 +
* '''bugfix''' 
 +
** {{param|rc|servo_rst_col0|servo_rst_col''#''}} now works for all columns! (bug reported in 5.2.0)
 +
* '''bugs'''
 +
** per-pixel servo reset doesn't also reset the filter
 +
** resetting any pixel with per-pixel reset also resets all the pixels in the last row (as specified by {{param|sys|num_rows}}, ignoring {{param|ac|row_order}})
 +
 
 +
= Revision 5.2.0 =
 +
* '''Filename:'''   
 +
** rc_stratixIII_v05020000_28may2013.sof  
  
 
* '''Features:'''   
 
* '''Features:'''   
−
** IMPORTANT: Must be used in conjunction with firmware v05000000 of all other cards!!!
+
** added the ability to reset the flux-loop servo on per-detector basis by adding {{param|rc|servo_rst_arm}} and {{param|rc|servo_rst_col0|servo_rst_col''#''}} parameters. This will reset the integral_term, the integral_clamp, anf flux-jump counter.
−
** Adds the ability to read out one column of data continuously from readout cards
+
 
 +
* '''bug:''' 
 +
** {{param|rc|servo_rst_col0|servo_rst_col''#''}} works for col 0 and 1, but not for col2 to 7! This is fixed in 5.2.1
 +
** per-pixel servo reset doesn't also reset the filter
 +
** resetting any pixel with per-pixel reset also resets all the pixels in the last row (as specified by {{param|sys|num_rows}}, ignoring {{param|ac|row_order}})
 +
 
 +
= Revision 5.1.d =
 +
* '''Filename:''' 
 +
** rc_stratixIII_v0501000d_30oct2012.sof
 +
 
 +
* '''Features:''' 
 +
** flux-jump routine is revamped to minimize the additional delay for applying sq1fb when flux-jump is enabled. In this version sq1fb DAC is refreshed at clock cycle 10 of each row visit when flux-jump is enabled and at clock cycle 7 when flux-jump is disabled.
 +
** extended dynamic range of the filter by increasing the width of filter-delay terms from 29 to 32 bits
 +
** lower power consumption (maybe?)
 +
 
 +
* '''Details'''
 +
** DDR2 module not instantiated (chips not installed) and on-chip termination resistors not in effect which can potentially save power.
 +
 
 +
=== Revision 5.1.c (Test) ===
 +
* '''Filename:''' 
 +
** rc_stratixIII_v0501000c_31aug2012.sof
 +
 
 +
* '''Features:''' 
 +
** extended dynamic range of the filter by increasing the width of filter-delay terms from 29 to 32 bits
 +
** based on 5.1.a
 +
** lower power consumption (maybe?)
 +
** {{param|rc|data_mode}}=4 reports fb(29 downto 12) instead of fb(31) & fb(28 downto 12)! no sticky bit.
 +
 
 +
* '''Details'''
 +
** DDR2 module not instantiated (chips not installed) and on-chip termination resistors not in effect which can potentially save power.
 +
 
 +
= Revision 5.1.b (Stable '''Rev.B''' Cards) =
 +
* '''Filename:''' 
 +
** rc_v0501000b_23mar2012.sof (Rev. B cards)
 +
 
 +
* '''Features:''' 
 +
** based on 5.1.8 (used Q11SP1)
 +
** added intergral_term fix from 5.1.9
 +
 
 +
* '''Details'''
 +
** qterm (or filtered-p) implementation is not included, because the design doesn't fit on the FPGA on Rev. B cards anymore.
 +
 
 +
= Revision 5.1.a (Stable) =
 +
* '''Filename:''' 
 +
** rc_stratix3_v0501000a_24jan2012.sof (Rev. E cards)
 +
 
 +
* '''Features:''' 
 +
** based on 5.1.9 (used Q10SP1)
 +
** {{param|rc|pterm_decay_bits}} (par_id = 0x64) is now '''programmable''' and is initially set to 0 to have pure p-term and be compatible with older firmware. (p-term implemented as q(n) = er(n) + b*q(n-1) where b=(1-1/2^k)with k={{param|rc|pterm_decay_bits}})
 +
** see bugfix in 5.1.9
 +
 
 +
== Revision 5.1.9 (test) ==
 +
* '''Filename:''' 
 +
** rc_stratix3_v05010009_23jan2012.sof (for Rev. E cards)
 +
 
 +
* '''Features:''' 
 +
** based on 5.1.8 (used Q10SP1)
 +
** first implementation of decayed-p-term in sq1fb calculation. The p-term is now implemented as q(n) = er(n) + b*q(n-1) where b=(1-1/2^k) and '''k=3 hardcoded'''.
 +
** added {{param|rc|pterm_decay_bits}} (par_id=0x64) as a register set to 3, but not tied to k in pterm calculation yet.
 +
 
 +
* ''' Bugfix:'''
 +
** This version fixes the bug introduced starting 5.0.e, the integral-term used to calculate sq1fb was calculated based on coadded value of (sample_num-1) samples and then the integral term stored for next round included sample_num-2. This is almost like having a p-term..
 +
 
 +
== Revision 5.1.8 (s1fb_dly=7) ==
 +
* '''Filename:''' 
 +
** rc_stratix3_v05010008_11jan2012.sof (for Rev. E cards)
 +
 
 +
* '''Features:''' 
 +
** based on 5.1.7 (used Q10SP1)
 +
** reverts back to applying S1fb after 7 clock cycles when flux-jump is off, and after 18 clock cycles when flux-jump is on.
 +
 
 +
== Revision 5.1.7 (rectangle-mode bugfix) ==
 +
[[File:RC516 vs RC517 hash.jpeg|thumb|Reduction in high-frequency noise due to rectangle-mode bugfix]]
 +
* '''Filename:''' 
 +
** rc_stratix3_v05010007_17nov2011.sof (for Rev. E cards)
 +
 
 +
* '''Features:''' 
 +
** based on 5.1.6 (used Q10SP1)
 +
 
 +
* ''' Bugfix:'''
 +
** In all RC firmware prior to 5.1.7, the read pointer in the rectangle-mode data was being refreshed at ARZ even if it was in the middle of a long readout (large frame readout). This resulted in seeing '''duplicate data in high-data-rate rectangle-mode readout''' only when the following condition was _NOT_ true: (230 + 2*{{param|cc|num_rows_reported|cc&nbsp;num_rows_reported}}*{{param|cc|num_cols_reported|cc&nbsp;num_cols_reported}}) < ({{param|sys|num_rows}}*{{param|sys|row_len}}). This is fixed in 5.1.7.
 +
 
 +
= Revision 5.1.6 (Stable) =
 +
* '''Filename:''' 
 +
** rc_stratix3_v05010006_27oct2011.sof (for Rev. E cards)
 +
 
 +
* '''Features:''' 
 +
** based on 5.1.5 (used Q10SP1)
 +
** coadd window and feedback-calculation blocks are adjusted for ADC latency of readout card Rev. E
 +
 
 +
* ''' Bugfix:'''
 +
** {{param|rc|sample_dly}} + {{param|rc|sample_num}} = {{param|sys|row_len}} should work now.
 +
 
 +
== Revision 5.1.5 (test)==
 +
* '''Filename:''' 
 +
** rc_stratix3_v05010005_15sep2011.sof (for Rev. E cards)
 +
 
 +
* '''Features:''' 
 +
** based on 5.1.2
 +
** reverts back to applying SQ1FB after 18 clock cycles whether flux-jumping is on or off
 +
 
 +
* ''' Bugfix:'''
 +
** All stratixiii firmware revisions prior to this version adjusted the co-add window for an ADC latency of 4 instead of 11. (Rev. E RC has serial ADC installed with 11 clock cycle latency.) The coadd window is now adjusted properly.
 +
 
 +
*'''Bug:'''
 +
** The last row samples can not be used in {{param|rc|servo_mode}}=3. For proper operation: {{param|rc|sample_dly}} + {{param|rc|sample_num}} needs to be < {{param|sys|row_len}} - 7 (I think). Although, the coadd window was adjusted in this version, but the calculation block latches data before coadd is done (coadd_done_o signal).
 +
 
 +
== Revision 5.1.4 (Scuba2) ==
 +
 
 +
* '''Filename:''' 
 +
** rc_v05010004_01jun2011.sof (for Rev. B cards)
 +
 
 +
* '''Features:''' 
 +
** based on 5.1.3
 +
** sq1_fb applied after 7 clock cycles when flux-jump off, and after 18 when flux-jump is on.
 +
* ''' bugfix:'''
 +
** fixed bug with fsfb_corr when reverting back to applying sq1fb after 7 clk cycles when fj is off
 +
 
 +
== Revision 5.1.3 (Scuba2) ==
 +
* '''Filename:''' 
 +
** rc_v05010003_01jun2011.sof (for Rev. B cards)
 +
 
 +
* '''Features:''' 
 +
** based on 5.1.2
 +
** reverts back to applying SQ1FB after 7 clock cyclces when flux-jumping is off, and after 18 clock cycles when flux-jumping is on.
 +
** k1 of filter params is now limited to k1<8. After generating coeffs for many filters, it is certain that this range is more than what we ever need.
 +
 
 +
= Revision 5.1.2 (Stable)=
 +
* '''Filename:''' 
 +
** rc_stratix3_v05010002_18jan2011.sof (for Rev. E cards)
 +
** rc_stratix3_v05010002_18jan2011.jic (for Rev. E cards)
 +
** rc_v05010002_03feb2011.sof (for Rev. B cards)
 +
** rc_v05010002_03feb2011.pof (for Rev. B cards)
 +
 
 +
* '''Features:''' 
 +
** based on 5.1.1 with k1 and k2 (filter params) limited to k1<16 and k2<32 in order to resolve the timing when compiling for smaller Stratix FPGA on RC Rev. B.
 +
 
 +
* '''Bug fix:'''
 +
** the 2-rows-off filtered data readout introduced with configurable filter in rev. 5.1.0 and 5.1.1 is fixed now.
 +
 +
* '''Bugs:'''
 +
** none so far.
 +
 
 +
* '''FPGA Resource Usage''' (readout_card.fit.rpt, rev. B)
 +
; Total logic elements      ; 33,285 / 41,250 ( 81 % )                      ;
 +
; Total pins                ; 358 / 616 ( 58 % )                            ;
 +
; Total memory bits        ; 1,405,440 / 3,423,744 ( 41 % )                ;
 +
 
 +
* '''FPGA Timing Analysis''' (readout_card.tan.rpt, rev. B)
 +
; Fast Model Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 6.591 ns 
 +
; Fast Model Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 7.206 ns 
 +
; Fast Model Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 18.299 ns
 +
 
 +
== Revision 5.1.1 (test only) ==
 +
* '''Filename:''' 
 +
** rc_v05010001_01dec2010.sof (for Rev. B cards)
 +
 
 +
* '''Features:''' 
 +
** based on 5.1.0, but k1 and k2 (filter params) are now limited to k1<16 and k2<32 in order to resolve the timing failures of compiling 5.1.0 for smaller Stratix FPGA on RC Rev. B.
 +
 
 +
* '''Bugs:'''
 +
** filter mode data is off by 2 rows.
 +
 
 +
== Revision 5.1.0 (test only) ==
 +
* '''Filename:''' 
 +
** rc_stratix3_v05010000_01nov2010.sof  (for Rev. E cards)
 +
** rc_v05010000_01nov2010.sof (for Rev. B cards) has timing failures '''do not use!!!'''
 +
 
 +
* '''Features:''' 
 +
** added configurable filter parameters specified by {{param|rc|fltr_coeff}}, default is the f<sub>cutoff</sub>/f<sub>sampl</sub>=122Hz/15kHz. see [[ Digital 4-pole Butterworth Low-pass filter ]].
 +
** {{param|rc|fltr_type}} is set to 255 to indicate configurable filter parameters.
 +
* '''Details'''
 +
** It is built on Quartus10.1.
 +
** tcl files had to be updated as cmp syntax is not supported in Q10 anymore.
 +
** Rev. E cards now can be identified by reading back pcb_rev as part of card_type, therefore both stratix I and III sof/pof/jic are generated from the same source.
 +
 
 +
* '''Bugs:'''
 +
** rc_v05010000_01nov2010.sof has timing failures that were overlooked, do not use this firmware for Rev.B cards.
 +
** '''filter mode data is off by 2 rows.'''
 +
 
 +
* '''FPGA Resource Usage and Timing Report''' (readout_card.fit.rpt and readout_card.tan.rpt): logic usage is upto 85% from 66% in 5.0.d/e/f
 +
 
 +
= Revision 5.0.f (Stable) =
 +
* '''Filename:''' 
 +
** rc_v0500000f_22oct2010.sof (for Rev. B cards)
 +
** rc_stratix3_v0500000f_22oct2010.sof  (for Rev. E cards)
 +
 
 +
* '''Features:''' 
 +
**  Bugfix: integral clamp should work now. only positive integral_clamp values are valid!
  
−
* '''Details:'''
+
* '''Details:''':
−
** ---
+
** SQ1FB is applied 18 clock cycles after start of a row visit (SQ1_Bias being applied) regardless of flux-jump being enabled or not. In pre-5.0.b firmware SQ1FB was being applied after 7 clock cycles when flux-jump was disabled and after 18 clock cycles when flux-jump was enabled.
 +
** available for both Rev. E and Rev. B cards, the upper byte of card_type parameter now reports the pcb revision.
 +
** development note: It is built on Quartus10.1.
  
 
* '''Bugs:'''
 
* '''Bugs:'''
−
** None so far.
+
**none yet!
 +
 
 +
* '''FPGA Resource Usage''' (readout_card.fit.rpt):
 +
; Total logic elements      ; 27,377 / 41,250 ( 66 % )                          ;
 +
; Total pins                ; 358 / 616 ( 58 % )                                ;
 +
; Total memory bits        ; 1,405,440 / 3,423,744 ( 41 % )                    ;
  
−
* '''Synthesis Notes:'''
+
* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
−
** The quartus.ini file was not present in the synth directory during synthesis.
+
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.652 ns
 +
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.385 ns
 +
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.860 ns
  
−
* '''FPGA Resource Usage''' (readout_card.fit.rpt):
+
== Revision 5.0.e (test only) ==
−
  +---------------------------------------------------------------------+
+
* '''Filename:'''   
−
; Fitter Summary                                                      ;
+
** rc_v0500000e_06oct2010.sof
−
+--------------------------+------------------------------------------+
 
−
; Fitter Status            ; Successful - Thu Jan 15 17:18:34 2009    ;
 
−
; Quartus II Version      ; 8.1 Build 163 10/28/2008 SJ Full Version ;
 
−
; Revision Name            ; readout_card                            ;
 
−
; Top-level Entity Name    ; readout_card                            ;
 
−
; Family                  ; Stratix                                  ;
 
−
; Device                  ; EP1S40F780C6                            ;
 
−
; Timing Models            ; Final                                    ;
 
−
; Total logic elements    ; 26,607 / 41,250 ( 65 % )                ;
 
−
; Total pins              ; 358 / 616 ( 58 % )                      ;
 
−
; Total virtual pins      ; 0                                        ;
 
−
; Total memory bits        ; 406,016 / 3,423,744 ( 12 % )            ;
 
−
; DSP block 9-bit elements ; 76 / 112 ( 68 % )                        ;
 
−
; Total PLLs              ; 1 / 6 ( 17 % )                          ;
 
−
; Total DLLs              ; 0 / 2 ( 0 % )                            ;
 
−
+--------------------------+------------------------------------------+
 
  
−
* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
+
* '''Details:'''   
−
+---------------------------------------------------------------------------
+
** an unsuccessful attempt to fix {{param|rc|integral_clamp}}, but changed the functionality so that it clamps at the value, but it doesn't hold the clamp. i.e., if the calculated sq1fb becomes less than the specified clamp value, the sq1fb is not clamped anymore. This is not a desired functionality!
−
; Timing Analyzer Summary                                                 
 
−
+--------------------------------------------------------------+-----------+
 
−
; Type                                                        ; Slack    ;
 
−
+--------------------------------------------------------------+-----------+
 
−
; Worst-case tsu                                              ; N/A      ;
 
−
; Worst-case tco                                              ; N/A      ;
 
−
; Worst-case th                                                ; N/A      ;
 
−
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.558 ns  ;
 
−
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.892 ns ;
 
−
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.987 ns ;
 
−
; Clock Hold: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0'  ; 0.741 ns  ;
 
−
; Clock Hold: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2'  ; 0.762 ns  ;
 
−
; Clock Hold: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3'  ; 0.763 ns  ;
 
−
; Total number of failed paths                                ;          ;
 
−
+--------------------------------------------------------------+-----------+
 
  
−
== Revision 4.4.1 ==
+
== Revision 5.0.d (test only) ==
−
* '''Filename:'''  rc_v04040001_21nov2008
+
[[Image:Clamp_unstable.png|thumb|right|Scope snapshot]]
 +
* '''Filename:'''   
 +
** rc_v0500000d_04aug2010.sof
  
 
* '''Features:'''   
 
* '''Features:'''   
−
** Fixes a bug that froze up the firmware if any of the following commands were issued:  CARD_ID_ADDR, CARD_TEMP_ADDR, FPGA_TEMP_ADDR in 4.4.0 only.
+
** Bugfix: To fix the bug associated with negative flux-jumps, reverted to signed multiplier and hence, incremented the width of the flux-quanta multiplier input by 1.
  
−
* '''Details:'''
+
* '''Details:''':
−
** The bug fix include adding more logic to the wishbone ack path (readout_card.vhd), which subsequently decreased the minimum clock setup time to 1.588ns. The new logic will catch errors that the old logic wouldn't have, and is now consistent with the firmware on all the other cards.  However, if timing becomes an issue, the logic may have to revert back to that which was in version 4.0.c.
+
** SQ1FB is applied 18 clock cycles after start of a row visit (SQ1_Bias being applied) regardless of flux-jump being enabled or not. In pre-5.0.b firmware SQ1FB was being applied after 7 clock cycles when flux-jump was disabled and after 18 clock cycles when flux-jump was enabled.
  
 
* '''Bugs:'''
 
* '''Bugs:'''
−
** None so far.
+
** '''{{param|rc|integral_clamp}} is broken'''. To test the clamping, a servo-locked ramp was initiated on the sq1fb and then flux-jumping was turned on and observed by attaching a scope to the SQ1FB output. With {{param|rc|integral_clamp}}=80000000, {{param|rc|flx_quanta0|flux_quanta}}=8000, {{param|rc|gaini0|gaini}}=1, flux-jump enabled, we see scope snapshot used slow_fb_ramp.py script for testing.
 +
 
 +
* '''FPGA Resource Usage and Timing Report''' (readout_card.fit.rpt and readout_card.tan.rpt): no change compared to 5.0.a/b/c
 +
 
 +
== Revision 5.0.c (test only) ==
 +
* '''Filename:''' 
 +
** rc_v0500000c_16jun2010.sof
 +
 
 +
* '''Features:''' 
 +
** Based on rev. 5.0.b
 +
** Re-introduced flux-jump counter clamping to maintain continuity in behavior from past versions of firmware in the field.
 +
** '''Important''': SQ1FB is applied 18 clock cycles after start of a row visit (SQ1_Bias being applied) regardless of flux-jump being enabled or not. In pre-5.0.b firmware SQ1FB was being applied after 7 clock cycles when flux-jump was disabled and after 18 clock cycles when flux-jump was enabled.
  
−
* '''Synthesis Notes:'''
+
* '''Details:'''
−
** The quartus.ini file was not present in the synth directory during synthesis.
+
* '''Bugs:'''
 +
** '''flux-jump is broken'''. flux-jumping block misbehaves at the first jump in the negative range.
  
 
* '''FPGA Resource Usage''' (readout_card.fit.rpt):
 
* '''FPGA Resource Usage''' (readout_card.fit.rpt):
−
+--------------------------------------------------------------------------+
+
  ; Total logic elements    ; 26,800 / 41,250 ( 65 % )                      ;
−
; Fitter Summary                                                          ;
 
−
+--------------------------+-----------------------------------------------+
 
−
; Fitter Status            ; Successful - Wed Nov 19 16:20:55 2008        ;
 
−
; Quartus II Version      ; 8.0 Build 231 07/10/2008 SP 1 SJ Full Version ;
 
−
; Revision Name            ; readout_card                                  ;
 
−
; Top-level Entity Name    ; readout_card                                  ;
 
−
; Family                  ; Stratix                                      ;
 
−
; Device                  ; EP1S40F780C6                                  ;
 
−
; Timing Models            ; Final                                        ;
 
−
  ; Total logic elements    ; 27,241 / 41,250 ( 66 % )                      ;
 
 
  ; Total pins              ; 358 / 616 ( 58 % )                            ;
 
  ; Total pins              ; 358 / 616 ( 58 % )                            ;
 
  ; Total virtual pins      ; 0                                            ;
 
  ; Total virtual pins      ; 0                                            ;
−
  ; Total memory bits        ; 405,504 / 3,423,744 ( 12 % )                 ;
+
  ; Total memory bits        ; 1,405,440 / 3,423,744 ( 41 % )               ;
 
  ; DSP block 9-bit elements ; 76 / 112 ( 68 % )                            ;
 
  ; DSP block 9-bit elements ; 76 / 112 ( 68 % )                            ;
 
  ; Total PLLs              ; 1 / 6 ( 17 % )                                ;
 
  ; Total PLLs              ; 1 / 6 ( 17 % )                                ;
 
  ; Total DLLs              ; 0 / 2 ( 0 % )                                ;
 
  ; Total DLLs              ; 0 / 2 ( 0 % )                                ;
−
+--------------------------+-----------------------------------------------+
 
  
 
* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
 
* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
−
+---------------------------------------------------------------------------
+
  ; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.964 ns  ;
−
; Timing Analyzer Summary                                                 
+
  ; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 4.382 ns  ;
−
+--------------------------------------------------------------+-----------+
+
  ; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 15.924 ns ;
−
; Type                                                        ; Slack    ;
+
 
−
+--------------------------------------------------------------+-----------+
+
== Revision 5.0.b (test only) ==
−
; Worst-case tsu                                              ; N/A      ;
+
* '''Filename:'''   
−
; Worst-case tco                                              ; N/A      ;
+
** rc_v0500000b_03jun2010.sof
−
; Worst-case th                                                ; N/A      ;
 
−
  ; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.588 ns  ;
 
−
  ; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.585 ns  ;
 
−
  ; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 17.057 ns ;
 
−
; Clock Hold: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0'  ; 0.741 ns  ;
 
−
; Clock Hold: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 0.755 ns  ;
 
−
; Clock Hold: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2'  ; 0.770 ns  ;
 
−
; Total number of failed paths                                ;          ;
 
−
+--------------------------------------------------------------+-----------+
 
  
−
== Revision 4.4.0 (buggy!) ==
 
−
* '''Filename:'''  rc_v04040000_02oct2008
 
 
* '''Features:'''   
 
* '''Features:'''   
−
** Reinstated the data modes in wbs_frame_data.vhd that were removed in 4.0.c.  This firmware has the following modes: '''0, 1, 2, 4, 5, 7, 10'''.  The modes that are not present are: '''3''' (raw data), '''6''' (replaced by data_mode = 7), '''8''' (replaced by data_mode = 10), '''9''' (replaced by data_mode = 10).  For more information on data modes, see [[Data mode]].
+
** Based on rev. 5.0.a
−
** Re-integrated the id_thermo and fpga_thermo block in the readout_card.vhd top level that was removed in 4.0.c.
+
** A bug that caused jumps in first-stage feedback, and detected as spikes in the raw data of pixels that were in servo_mode=0,1,2 was fixed.  The jumps in FSFB were due to flux-jumping being enabled on live pixels with non-zero {{param|rc|flx_quanta0|flx_quanta}}, and being disabled on the fly on dead pixels with {{param|rc|flx_quanta0|flx_quanta}}=0.  Flux-jumping is now disabled on a column-by-column basis if a column is in servo_mode = 0,1,2.
−
** Removed the sticky bit in fsfb_corr.vhd, which was enabled when flux-jumping was turned on.  Because the feedback is signed, the sticky bit would usually reflect the value of the 14th bit, except in situations when the number of flux quanta to jump was greater than 1 (i.e. cosmic rays, IV-curves, etc).  Flux jumps are made at a maximum rate of one per frame period, so that if the First-Stage Feedback increased past the 13th bit, it would not be reflected in the feedback applied.  Now it is.
+
** Ineffective clamping was removed from the flux-jumping block (as per 5.0.9), as it is now replaced by the clamping that was perfected in rev. 5.0.10
 +
** A sticky bit that only affected servo_mode=0,1,2 was also removed from the flux-jumping block.
 +
** {{param|rc|flx_lp_init}} commands now also clear the flux-jumping block as well.
 +
** The 11-clock-cycle delay (in applying SQ1_FB) that in previous firmware only occurred when flux-jumping was enabled, now (in this version) is in effect all the time. Due to the bug-fix above, flux-jumping can be disabled on a column-by-column basis by setting servo_mode=0,1,2 when {{param|rc|en_fb_jump}}=1.  Before the change, this meant that constant values could be applied with or without the 11-cycle delay if {{param|rc|en_fb_jump}}=1 or 0.  To make the delay consistent, it is now always 11 cycles.  As background, the flux-jumping block is pipelined, meaning that it does calculations for all 8 channels serially. The serialization is because of DSP-block limitations in the Readout Card FPGA that prevent us from doing all 8 channels in parallel.  The reason that it takes 11 cycles to complete the flux-jumping calculations is because the values are computed for the eight channels in three ALU stages:  8 + 3 = 11 cycles.  Adding 11 cycles to the 7 cycles of latency from other stages in the system results in: 11 + 7 = 18 cycles of latency from the start of a row dwell period before the first-stage feedback is applied.  In rc_v5.0.c, I enforce the 18-cycle delay even when flux-jumping is not enabled to maintain uniformity across all eight channels, because flux-jumping is enabled/disabled on a per-channel basis. In other words, if I hadn't enforced the 18-cycle delay, some channels could have their feedback applied after 7 cycles, while others could have it applied after 18 cycles.  I wasn't a fan of this non-uniformity.  I realize that 18 cycles is a long time.  In fact, so is 7.  In the last few months, we have been discussing how to reduce these times to 1 cycle, because every experiment out there wants to multiplex as fast as possible, and the 7/18-delay is a rate limiting step.
 +
** The flux-jumping code was re-arranged in the flux-jumping block to reflect the flow of data through the pipeline and make it easier to understand.
 +
 
 
* '''Details:'''
 
* '''Details:'''
−
** Simplified the FSM logic in wbs_frame_data.vhd that determines when to transition from IDLE to WSS1.  This was done to lower the number of gates in that path, and ease the timing.
+
 
−
** Removed the z_dat_i port in fsfb_processor.vhd and fsfb_calc_pack.vhd to the fsfb_proc_pidz block, in an effort to make it clearer within that block that the z-term is always = 0.
 
−
** Removed the z-term sign extension in fsfb_proc_pidz.vhd, and the [d-term + z-term] adder to free up DSP resources since the z-term is always = 0.
 
−
** Adjusted the indentation in fsfb_io_controller.vhd to make the file more readable.
 
−
** Moved the tga_o signal out of the dispatch_wishbone.vhd FSM, and made it a continuous assignment.  This signal had one of the highest fan-out counts in the RTL design, and actually was impossible to route in Stratix III chips in its previous configuration because of the number of gates on the fan-out.  As a consequence of making it a continuous assignment, the Stratix III fitter was able to succeed, and the Stratix I timing characteristics were greatly improved.  This is the most significant change in this revision.  This change single-handedly increased the minimum slack from 1.282 ns in v0400000c to 2.372 ns (or 56.7 MHz max) in this revision.
 
 
* '''Bugs:'''
 
* '''Bugs:'''
−
** The following commands lock up the Readout Card firmware:  CARD_ID_ADDR, CARD_TEMP_ADDR, FPGA_TEMP_ADDR.
+
** flux-jump does not work when jumping to negative values.
−
* '''Synthesis Notes:'''
+
 
−
** The quartus.ini file was not present in the synth directory during synthesis.
 
 
* '''FPGA Resource Usage''' (readout_card.fit.rpt):
 
* '''FPGA Resource Usage''' (readout_card.fit.rpt):
−
+--------------------------------------------------------------------------+
+
  ; Total logic elements    ; 26,745 / 41,250 ( 65 % )                      ;
−
; Fitter Summary                                                          ;
 
−
+--------------------------+-----------------------------------------------+
 
−
; Fitter Status            ; Successful - Mon Sep 29 16:29:56 2008        ;
 
−
; Quartus II Version      ; 8.0 Build 231 07/10/2008 SP 1 SJ Full Version ;
 
−
; Revision Name            ; readout_card                                  ;
 
−
; Top-level Entity Name    ; readout_card                                  ;
 
−
; Family                  ; Stratix                                      ;
 
−
; Device                  ; EP1S40F780C6                                  ;
 
−
; Timing Models            ; Final                                        ;
 
−
  ; Total logic elements    ; 27,099 / 41,250 ( 66 % )                      ;
 
 
  ; Total pins              ; 358 / 616 ( 58 % )                            ;
 
  ; Total pins              ; 358 / 616 ( 58 % )                            ;
 
  ; Total virtual pins      ; 0                                            ;
 
  ; Total virtual pins      ; 0                                            ;
−
  ; Total memory bits        ; 406,016 / 3,423,744 ( 12 % )                 ;
+
  ; Total memory bits        ; 1,405,440 / 3,423,744 ( 41 % )               ;
 
  ; DSP block 9-bit elements ; 76 / 112 ( 68 % )                            ;
 
  ; DSP block 9-bit elements ; 76 / 112 ( 68 % )                            ;
 
  ; Total PLLs              ; 1 / 6 ( 17 % )                                ;
 
  ; Total PLLs              ; 1 / 6 ( 17 % )                                ;
 
  ; Total DLLs              ; 0 / 2 ( 0 % )                                ;
 
  ; Total DLLs              ; 0 / 2 ( 0 % )                                ;
−
+--------------------------+-----------------------------------------------+
 
 
* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
 
* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
−
  --------------------------------------------------------------------------
+
  ; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.459 ns   
−
Timing Analyzer Summary                                                 
+
  ; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.895 ns   
−
-------------------------------------------------------------+-----------+
+
  ; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 15.956 ns
−
Type                                                        ; Slack    ;
+
 
−
-------------------------------------------------------------+-----------+
+
== Revision 5.0.a (test only) ==
−
Worst-case tsu                                              ; N/A      ;
+
* '''Filename:''' 
−
Worst-case tco                                              ; N/A      ;
+
** rc_v0500000a_12mar2010.sof
−
Worst-case th                                                ; N/A      ;
+
 
−
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.372 ns  ;
+
* '''Features:''' 
−
  Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 4.052 ns  ;
+
** Based on the merger of rev. 5.0.8 and 5.0.9.
−
  Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.066 ns ;
+
** {{param|rc|integral_clamp}} command is added where a clamp value is set for the integral term and once the integral term hits that value, the integral-term is clamped to that value and p-term and d-term are clamped to zero. When integral_term=0 then no clamping is in effect, similar to previous releases of firmware.
−
  Clock Hold: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 0.741 ns  ;
+
** The low pass filter has 20-bit input and f_3dB/f_samp = 122Hz/15kHz .
−
  Clock Hold: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 0.761 ns  ;
+
** The flux-jump clamping that was removed in 5.0.9 is included once again here, as we decided this is safer for now.
−
  Clock Hold: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 0.788 ns ;
+
 
−
  Total number of failed paths                                ;          ;
+
* '''Details:'''
−
-------------------------------------------------------------+-----------+
+
** "lock_dat_left" parameter that was removed in 5.0.9 is now implemented as "lock_dat_lsb"
 +
 
 +
* '''Bugs:'''
 +
** {{param|rc|flx_lp_init}} does not reinitialize the flux-jump block
 +
 
 +
* '''Synthesis Notes:'''
 +
** The quartus.ini file '''was''' present in the synth directory during synthesis
 +
** tag name: rc_v0500000a_12mar2009! years were mixed up!
 +
 
 +
* '''FPGA Resource Usage''' (readout_card.fit.rpt):
 +
* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
 +
 
 +
== Revision 5.0.9 (buggy) ==
 +
* '''Filename:''' 
 +
** rc_v05000009_13nov2009.sof
 +
 
 +
* '''Features:''' 
 +
** Based on rev. 5.0.4
 +
** Removes a sticky bit in pid calculation result storage -- in fsfb_processor.
 +
** Adds a command to clamp the growth of the I-term to prevent wrapping and track down the source of Caltech's FSFB jumps.
 +
** Removed the unused lock_dat_left parameter.  The ability to shift left was moved to the fsfb_corr block some time ago.
 +
** Fixed a sign extension bug acting on the flux quanta, which limited the value to 8191.  Changed the extension from signed to unsigned.
 +
** Removed ineffective clamping in the flux-jump calculation block.
 +
** IMPORTANT: Must be used in conjunction with firmware rev. 5.0.0+ of all other cards.
 +
 
 +
* '''Details:'''
 +
 
 +
* '''Bugs:'''
 +
** {{param|rc|integral_clamp}} read/write command does not work.
 +
 
 +
* '''Synthesis Notes:'''
 +
** The quartus.ini file '''was''' present in the synth directory during synthesis
 +
 
 +
* '''FPGA Resource Usage''' (readout_card.fit.rpt):
 +
; Total logic elements    ; 27,960 / 41,250 ( 68 % )                      ;
 +
  ; Total memory bits        ; 1,405,440 / 3,423,744 ( 41 % )                ;
 +
 
 +
* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
 +
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.825 ns  ;
 +
  ; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.878 ns  ;
 +
  ; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 14.397 ns ;
 +
 
 +
== Revision 5.0.8 (UBC only) ==
 +
* '''Filename:'''  
 +
** rc_v05000008_09oct2009.sof
 +
 
 +
* '''Features:'''
 +
** Based on rev. 5.0.4
 +
** type 1 low-pass filter: f<sub>3dB</sub>=122Hz for f<sub>sample</sub>=15kHz
 +
** Filter-input-width changed from 18b to 20b with no sticky bits!
 +
** removed sticky bits in internal arithmetic of the filter.
 +
 
 +
= Revision 5.0.7 (type-2 filter) =
 +
* '''Filename:''' 
 +
** rc_v05000007_09oct2009.sof
  
−
== Revision 4.0.c ==
 
−
* '''Filename:'''  rc_v0400000c_15aug2008.sof
 
 
* '''Features:'''
 
* '''Features:'''
−
** Only has data modes 0, 1, 4, and 10.
+
** Based on rev. 5.0.4
−
** Fixed the bug that exists in 4.0.b, 4.0.a, and 4.0.9 that prevented the fb_const value from being applied to channel zero (wbs_fb_data.vhd).
+
** type-2 low-pass-filter: f<sub>3dB</sub>=75Hz for f<sub>sample</sub>=30000.
 +
** Filter-input-width changed from 18b to 20b with no sticky bits!
 +
** inter-biquad-gain-scaling for the filter is 2^14
 +
** filter results are scaled down by 2^3 in the output of the filter.
 +
** removed sticky bits in internal arithmetics
 +
** _correction_ disabled in fsfb_proc_pidz
 +
 
 +
* '''Details:'''
 +
** quartus.ini file was '''not''' present in synth directory.
 +
 
 +
* '''Bugs:'''
 +
** none to report
 +
 
 +
* '''FPGA Resource Usage''' (readout_card.fit.rpt):
 +
* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
 +
== Revision 5.0.6  (UBC only) ==
 +
* '''Filename:''' 
 +
** rc_stratix3_v05000006_15sep2009.sof
 +
 
 +
* '''Features:''' 
 +
** Only Valid for Rev. C/D Cards
 +
** Based on rev. 5.0.3
 +
** tcl file updated for Rev. D and aligned with top-level and qsf (project file).
 +
** flux loop commented, just to try sampling the ADC.
 +
** compiled with Q9.1
 +
 
 +
== Revision 5.0.5 (UBC only) ==
 +
* '''Filename:''' 
 +
** rc_v05000005_04sep2009.sof
 +
 
 +
* '''Features:''' 
 +
** Based on rev. 5.0.2
 +
** changed the low-pass-filter to f(3db)=75Hz for f(sample)=30000.
 +
 
 
* '''Details:'''
 
* '''Details:'''
−
** Changed a counter in the dispatch block to ease timing constraints in synthesis (dispatch_wishbone.vhd)
+
** quartus.ini file was '''not''' present in synth directory.
−
** Updated the tagged versions of dispatch.vhd , dispatch_cmd_receive.vhd, and dispatch_reply_transmit.vhd to the version that is used by all the other cards.
+
 
−
** Removed the fpga_termo (command:  fpga_temp) and id_thermo (commands: card_temp, card_id) to ease timing constraints in synthesis (readout_card.vhd)
 
−
** Updated the tagged version of fpga_termo.vhd to include the new 'stale bit' feature
 
−
** Updated the tagged version of frame_timing_core.vhd to include the new 'err_o' interface
 
 
* '''Bugs:'''
 
* '''Bugs:'''
−
** None reported yet
+
** negative inputs to the filter cause filter to have a non-flat pass-band region. may have to do with sign-handling...
 +
 
 +
* '''FPGA Resource Usage''' (readout_card.fit.rpt):
 +
* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
 +
 
 +
= Revision 5.0.4 (Stable) =
 +
* '''Filename:''' 
 +
** rc_v05000004_28aug2009.sof
 +
 
 +
* '''Features:''' 
 +
** Based on rev. 5.0.2
 +
** BUG Fix: handles 14-bit flux quanta (changed the multiplier to unsigned)
 +
** BUG Fix: changed standard logic vector extension from signed to unsigned in flux-jumping slave.
 +
** IMPORTANT: Must be used in conjunction with firmware rev. 5.0.0+ of all other cards.
 +
 
 +
* '''Details:'''
 +
 
 +
* '''Bugs:'''
 +
** None so far.
 +
 
 
* '''Synthesis Notes:'''
 
* '''Synthesis Notes:'''
−
** The quartus.ini file was not present in the synth directory during synthesis.
+
** The quartus.ini file '''was''' present in the synth directory during synthesis
−
* '''FPGA Resource Usage:'''
+
 
−
Fitter Status : Successful - Thu Aug 14 17:55:33 2008
+
* '''FPGA Resource Usage''' (readout_card.fit.rpt):
−
Quartus II Version : 8.0 Build 215 05/29/2008 SJ Full Version
+
  ; Total logic elements     ; 26,170 / 41,250 ( 63 % )                     ;
−
Revision Name : readout_card
+
  ; Total memory bits       ; 1,405,440 / 3,423,744 ( 41 % )               ;
−
Top-level Entity Name : readout_card
+
 
−
Family : Stratix
+
* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
−
Device : EP1S40F780C6
+
  ; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.541 ns  ;
−
Timing Models : Final
+
  ; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.612 ns  ;
−
  Total logic elements : 25,058 / 41,250 ( 61 % )
+
  ; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 15.398 ns ;
−
  Total pins : 358 / 616 ( 58 % )
+
 
−
Total virtual pins : 0
+
= Revision 5.0.3 =
−
Total memory bits : 400,896 / 3,423,744 ( 12 % )
+
* '''Filename:'''   
−
DSP block 9-bit elements : 76 / 112 ( 68 % )
+
** rc_stratix3_v05000003_21aug2009.sof
−
Total PLLs : 1 / 6 ( 17 % )
+
 
−
Total DLLs : 0 / 2 ( 0 % )
+
* '''Features:'''   
−
* '''Timing Analysis''' (readout_card.tan.rpt):
+
** ONLY valid REV C/D RC Cards
−
  --------------------------------------------------------------------------
+
** Based on rev. 5.0.2
−
Timing Analyzer Summary                                                 
+
** flux loop commented, just to try sampling the ADC.
−
-------------------------------------------------------------+-----------+
+
** updated tcl file, but still need to rely on project file as well as qsf file.
−
Type                                                        ; Slack    ;
+
** changed default level of adc_sclk to '1'
−
-------------------------------------------------------------+-----------+
+
** dac_clr_n was changed from an output to an input.
−
Worst-case tsu                                              ; N/A      ;
+
** added 'locked' interface to rc_pll_stratix_iii
−
Worst-case tco                                              ; N/A      ;
+
** renamed the adc_pll clock signals to more explanitory names
−
Worst-case th                                                ; N/A      ;
+
** added the FPGA_DEVICE_FAMILY generic to the dispatch interace for synthesis of the dc_fifo in lvds_rx
−
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.282 ns  ;
+
** uncommented DDR interface to force the syntesizer to use correct left and right PLLs (in conjunction with ADC and DDR PLLs)
−
  Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.736 ns  ;
+
** added test signals to test_status to see clocks on the scope.
−
  Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.665 ns ;
+
== Revision 5.0.2 (buggy) ==
−
  Clock Hold: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0'  ; 0.741 ns  ;
+
* '''Filename:'''  
−
Clock Hold: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3'  ; 0.752 ns  ;
+
** rc_v05000002_test00_tagged.sof
−
Clock Hold: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 0.811 ns  ;
 
−
  Total number of failed paths                                ;          ;
 
−
-------------------------------------------------------------+-----------+
 
  
−
== Revision 4.0.b (buggy!) ==
+
* '''Features:'''
−
Note: This revision is on a watch list, after the bug detected 15 July 2008.  See the bug section for more details.
+
** Based on rev. 5.0.1
−
* '''Filename''' : rc_v0400000b_04aug2008.sof
+
** Fixed a bug in wbs_frame_data that stored data incorrectly if reporting 1 or 2 pixels only.
−
* '''Features'''
+
** IMPORTANT: Must be used in conjunction with firmware rev. 5.0.0+ of all other cards.
−
** data_mode 10 is added to provide more filtfb bits (compared to data mode 9) for planet observations. filtered_dat(27 downto 3) & flux_cnt_dat(6 downto 0)
 
  
−
* '''Bugs'''
+
* '''Details:'''
−
** An unexplained bug that appeared in 4.0.a and may still be present in 4.0.b is a problem with the readout of channels being clipped out of data reporting. [[Bug 1 Notes]]
 
  
−
* ''' Synthesis note '''
+
* '''Bugs:'''
−
** Quartus.ini removed.
+
** None so far.
  
−
== Revision 4.0.a (buggy!) ==
+
* '''Synthesis Notes:'''
−
Note: This revision is on a watch list, after the bug detected 15 July 2008.  See the bug section for more details.
+
** The quartus.ini file '''was''' present in the synth directory during synthesis.
−
* '''Filename''' : rc_v0400000a_07jul2008.sof
 
−
* '''Bug Fix'''
 
−
** mce_status and adc_offset/flx_quanta commands do not fail after power up.
 
−
* ''' Synthesis note '''
 
−
** Quartus.ini removed.
 
  
−
* '''Bugs'''
+
* '''FPGA Resource Usage''' (readout_card.fit.rpt):
−
** Seems to clip out channel 0 from data reporting.
+
; Total logic elements    ; 26,186 / 41,250 ( 63 % )                      ;
 +
; Total memory bits        ; 1,405,440 / 3,423,744 ( 41 % )                ;
  
−
== Revision 4.0.9 (buggy!) ==
+
* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
−
* '''Filename''' : rc_v04000009_26jun2008.sof
+
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.755 ns  ;
−
* '''Features'''  
+
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.979 ns ;
−
** sa_bias and offset DACs only refreshed when new values are written. (in previous versions, DACs were refreshed every frame)
+
  ; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.067 ns ;
−
* '''Bugs'''
 
−
** fb_const0 commands to channel 0 do not work.  The value is stored in the register, but not applied to the DAC. Thus, read-back returns the correct value, but the DAC does not.
 
−
** reading flx_quanta and adc_offset right after power up hangs the reply datapath to CC. resetmce clears this error as temporary solution. the problem is caused by first read ack of the wishbone slave.
 
  
−
== Revision 4.0.8 ==
+
== Revision 5.0.1 (buggy) (Filter + Raw + Rectangle, 2 LVDS) ==
−
* '''Filename''' : rc_v04000008_26jun2008.sof
+
* '''Filename:'''
−
* '''Features'''  
+
** rc_v05000001_26may2009.sof
−
** The gaini, gainp, gaind resolution increased to 12-bit, i.e. -2048 to 2047 (formerly 10-bit).
 
  
−
* '''Bug fix'''
+
* '''Features:'''
−
** the bug associated with gainpid read before mce_reset is fixed.
+
** Combines features in rev. 5.0.0 (2 LVDS Lines) and rev. 4.0.e (Filtered + Raw), with the NEW rectangle mode.
 +
** IMPORTANT: Must be used in conjunction with firmware rev. 5.0.0+ of all other cards.
  
−
* ''' Synthesis note '''
+
* '''Bugs:'''
−
** Quartus.ini removed.
+
** Has a bug in wbs_frame_data that stored data incorrectly if reporting 1 or 2 pixels only.
  
−
== Revision 4.3.7 ==
+
* '''Synthesis Notes:'''
−
* '''Filename''' : rc_v04030007_26may2008_raw.sof
+
** The quartus.ini file '''was''' present in the synth directory during synthesis.
−
* '''Features'''  
 
−
** 14-bit raw mode enabled to buffer a snapshot of 50MHz samples for 2 frames of row_len * num_rows samples.
 
−
** In order to extend the raw-mode to 14-bit, an assumption is made that the raw buffer is not written to while being read. Therefore, make sure there is at least 2*row_len*num_rows*20ns between issuing captr_raw command and reading back the raw data.
 
−
** In order to save RAM for raw mode, two memory-intensive features are disabled:
 
−
*** low-pass filter disabled ( mixed filtfb data modes 6, 7, 9 are also disabled)
 
−
*** PID (gainp0, gaini0, gaind0) readback disabled. one can still set PID values and run servo, but can not read back the values.
 
  
−
== Revision 4.2.7 ==
+
* '''FPGA Resource Usage''' (readout_card.fit.rpt):
−
* '''Filename''' : rc_v04020007_24may2008_raw.sof
+
; Total logic elements    ; 26,565 / 41,250 ( 64 % )                 ;
−
* '''Features'''
+
; Total memory bits        ; 1,405,440 / 3,423,744 ( 41 % )           ;
−
** raw mode enabled to buffer a snapshot of 50MHz samples for 2 frames of row_len * num_rows samples.
 
−
** In order to save RAM for raw mode, two memory-intensive features are disabled:
 
−
*** low-pass filter disabled ( mixed filtfb data modes 6, 7, 9 are also disabled)
 
−
*** PID (gainp0, gaini0, gaind0) readback disabled. one can still set PID values and run servo, but can not read back the values.
 
−
* '''Bug fix'''
 
−
** the bug associated with reading from raw-buffer is fixed.
 
  
−
== Revision 4.1.7 ==
+
* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
−
* '''Filename''' : rc_v04010007_25apr2008_raw.sof
+
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.656 ns  ;
−
* '''Features'''
+
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.861 ns  ;
−
** raw mode enabled to buffer a snapshot of 50MHz samples for 2 frames of row_len * num_rows samples.
+
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 14.167 ns ;
−
** In order to save RAM for raw mode, two memory-intensive features are disabled:
 
−
*** low-pass filter disabled ( mixed filtfb data modes 6, 7, 9 are also disabled)
 
−
*** PID (gainp0, gaini0, gaind0) readback disabled. one can still set PID values and run servo, but can not read back the values.
 
−
* '''Bugs'''
 
−
** after each readout frame, raw-buffer readout counter falls behind by 3 and this causes skipping 3 50MHz samples in the data stream and column-data being messed up in subsequent frames. Data can be rearranged by post processing.
 
  
−
== Revision 4.0.6 (buggy!) ==
+
== Revision 5.0.0 (Filter Only, 2 LVDS) ==
−
* '''Filename''' : rc_v04000006_15feb2008.sof or .pof     
+
* '''Filename:'''
−
* '''Features'''  
+
** rc_v05000000_22dec2008.sof (tagged as sys_v05000000_22dec2008)
−
** '''bugfix''': unreliable reset due to unsafe and incomplete state machines is fixed.
 
−
** '''bugfix''': flux_jump sign problem fixed, so far proved in const_mode, to be tested in servo_mode with cold setup.
 
−
** servo_mode=2 or ramp previously only went from 0 to ramp_amp, but now goes from -8192 to -8192+ramp_amp
 
−
** new commands are added: ''scratch'' and ''card_type''. Scratch takes 8 values and can be used by software to detect reset.
 
−
** slot_id and fw_rev are now integrated as part of all_cards.vhd
 
−
** lvds_tx_b=0, This will allow Clock Card to use the secondary backplane lvds line and check whether RC is plugged in.
 
−
** filter_coeff in misc_banks_admin commented as it is not implemented and causes timing problems.
 
  
−
* '''Bugs'''
+
* '''Features:'''
−
** reading gainp/gaini/gaind right after power up hangs the reply datapath to CC. resetmce clears this error as temporary solution. the problem is caused by first read ack of pid_ram_admin.
+
** IMPORTANT: Must be used in conjunction with firmware v05000000+ of all other cards!!!
−
** slot_id is only set after a resetmce is issued. (using the latest all_cards in the next revision will fix this)
+
** Adds the ability to read out one column of data continuously from readout cards
−
** has spurious spikes on channel 7 data, which max out the integral, and cause the detectors to come unlocked. This firmware officially meets timing requirements, but the bug could be due to marginal timing on the longest data paths, i.e. ~0.1 ns in some cases.
+
** Adds data mode 11, which is an engineering mode.  Data points are 32-bits, and bits [9..3]=row_index, [2..0]=column_index. This mode is useful for determining which pixels one is reading out in the array, in column mode for example.
  
−
== Revision 4.0.5 ==
+
* '''Details:'''
−
* '''Filename''' : rc_v04000005_01nov2007.sof or .pof     
+
** [[CVS Diff Between rc_v0400000c and sys_v05000000]]
−
* '''Features'''  
 
−
** data mode 9 (mixed filt + flux jump) with windowing readjusted compared to data mode 8
 
  
−
* '''Bugs'''
+
* '''Bugs:'''
−
** unreliable resetmce. Sometimes, firmware waked up non-responsive on lvds lines.
+
** None so far.
−
** In data mode 5 and 9, flux-jump counter is not reported properly due to a sign error. However, flux jumping works fine.
 
  
−
== Revision 3.0.19 ==
+
* '''Synthesis Notes:'''
−
* '''Filename''' : rc_v03000019_16feb2007_raw.sof (no pof as one is not likely to run with this as regular firmware)
+
** The quartus.ini file was not present in the synth directory during synthesis.
−
* '''Features'''  
 
−
** data mode 3 is enabled.
 
−
** filter is disabled as a compromise to fit the raw-mode buffer.
 
  
−
* '''Bugs'''
+
* '''FPGA Resource Usage''' (readout_card.fit.rpt):
−
** unreliable resetmce. Sometimes, firmware waked up non-responsive on lvds lines.
+
; Total logic elements    ; 26,607 / 41,250 ( 65 % )                ;
 +
; Total memory bits        ; 406,016 / 3,423,744 ( 12 % )            ;
  
−
== Old Firmware Revisions ==
+
* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
−
* '''4.0.4''':  rc_v04000004_11oct2007.sof  data mode 8 added (mixed filt + flux jump)
+
  ; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.558 ns ;
−
* '''4.0.3''':  rc_v04000003_19sep2007.sof  data mode 7 bit split readjusted to 10b error being bit 4 to 14
+
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.892 ns ;
−
* '''4.0.2''':  rc_v04000002_11sep2007.sof pid resolution increased to 10b, data mode 7 added
+
  ; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.987 ns ;
−
* '''4.0.1''': rc_v04000001_06sep2007.sof  
 
−
* '''4.0.0''':  rc_v04000000_29aug2007.sof  supports readout_row_index * [[ bugs ]]
 
  
 
= To-Do List =
 
= To-Do List =
−
* continuous readout mode where one column is read at frame rate, this means the output frame is regular size, but all entries relate to one column (high).
+
* the starting point for the servo is currently zero and it would be nice to have it programmable.
−
* reject single out-of-range adc sample based on (er<sub>n</sub>-er<sub>n-1</sub> > 2*er<sub>n-1</sub>)
 
−
* reduce co-add storage from 32b wide to 24b (14b adc + 10b (for coadding up to sample_num=1024 samples)).  This frees up resources generally on the RC.  (High)
 
−
* reduce the width for pid calculations.  This might relieve resource needs on the RC. (High, but maybe risky.)
 
−
* By using the MRAMs to a greater depth, we may be able to increase the number of raw data points stored.
 
  
 
= RC Synthesis Notes =
 
= RC Synthesis Notes =
−
# Quartus.ini file had to exist in synth directory up to revision 4.0.a due to a bug that started in Quartus 6.1 and would synthesize away arbitrary parts of readout card. We contacted Altera at the time and they provided us the ini file.  We have stopped using this file starting with rc_v04000008, although v04000009 does use it.  This file needs to be used when Quartus synthesizes out blocks of firmware.  If this occurs, the utilization drops well below 66%.  If posssible, avoid using this file, because it causes timing violations.
+
# The following note applies when using Quartus versions earlier than Q7: Quartus.ini file had to exist in synth directory up to revision 4.0.a due to a bug that started in Quartus 6.1 and would synthesize away arbitrary parts of readout card. We contacted Altera at the time and they provided us the ini file.  
 
# Timing: There is no "lock region" defined for readout card. Timing on readout card is tight and since version 3 or so any new feature would initially fail timing till some synthesis options were tweaked. One path that remains to be consistently marginal is from addr_gen counter (i.e. tga_o counter) in dispatch_wishbone.vhd to wishbone slaves particularly misc_banks_admin.vhd. Modules that are rewritten to address timing concerns are fsfb_corr, all_cards, misc_banks_admin, and finally instantiating an lpm counter instead of a counter from components library. Surprisingly, the lpm counter reduced 87 failures to 37, although looking at the technology map viewer, it seemed that they were both synthesized the same.
 
# Timing: There is no "lock region" defined for readout card. Timing on readout card is tight and since version 3 or so any new feature would initially fail timing till some synthesis options were tweaked. One path that remains to be consistently marginal is from addr_gen counter (i.e. tga_o counter) in dispatch_wishbone.vhd to wishbone slaves particularly misc_banks_admin.vhd. Modules that are rewritten to address timing concerns are fsfb_corr, all_cards, misc_banks_admin, and finally instantiating an lpm counter instead of a counter from components library. Surprisingly, the lpm counter reduced 87 failures to 37, although looking at the technology map viewer, it seemed that they were both synthesized the same.
 
# Compile time: This was at some point 4.5 hours, after going to dual core PC, this was reduced to 35 minutes. After extending pid gains to 12b and fixing offset/sa_bias update code, the compile time increased to 1.5hr again with utilization up to ~70%.
 
# Compile time: This was at some point 4.5 hours, after going to dual core PC, this was reduced to 35 minutes. After extending pid gains to 12b and fixing offset/sa_bias update code, the compile time increased to 1.5hr again with utilization up to ~70%.
Line 341: Line 585:
 
  lpm_file => "C:/scuba2_repository/cards/readout_card/fsfb_calc/source/rtl/ram_40x64.hex", and
 
  lpm_file => "C:/scuba2_repository/cards/readout_card/fsfb_calc/source/rtl/ram_40x64.hex", and
 
  lpm_file    : STRING;
 
  lpm_file    : STRING;
−
 
+
#Starting Q10.0 use TimeQuest timing analyzer as oppose to the classic one. The classic one is being phased out by Altera. In order to use TimeQuest, you need to have an sdc file present in your project directory.
−
= Approximate RC FPGA Utilization =
+
* [[Pre-v5 firmware#Readout Card|Pre-v5 firmware]]
−
* Normal-operation firmware:
+
[[Category:Readout Card Firmware| ]]
−
Fitter Status : Successful - Mon Jul 07 17:50:07 2008
 
−
Quartus II Version : 7.2 Build 151 09/26/2007 SJ Full Version
 
−
Device : EP1S40F780C6
 
−
Timing Models : Final
 
−
Total logic elements : 27,213 / 41,250 ( 66 % )
 
−
Total pins : 358 / 616 ( 58 % )
 
−
Total memory bits : 405,504 / 3,423,744 ( 12 % )
 
−
* M512s                                      ; 86 / 384 ( 22 % )                                                                           
 
−
* M4Ks                                        ; 183 / 183 ( 100 % )                                                                       
 
−
* M-RAMs                                      ; 0 / 4 ( 0 % )                                                                             
 
−
DSP block 9-bit elements : 76 / 112 ( 68 % )
 
−
Total PLLs : 1 / 6 ( 17 % )
 
−
Total DLLs : 0 / 2 ( 0 % )
 
−
 
 
−
*Raw-mode firmware
 
−
Total memory bits : 1,242,112 / 3,423,744 ( 36 % )                                                    ;
 
−
* M512s                                      ; 292 / 384 ( 76 % )                                                               
 
−
* M4Ks                                        ; 183 / 183 ( 100 % )                                                               
 
−
* M-RAMs                                      ; 4 / 4 ( 100 % )                                                                   
 
−
 
 
−
 
 
−
 
 
−
----
 
−
[http://e-mode.phas.ubc.ca/mcewiki/index.php/Main_Page  MCE Main Page]
 

Latest revision as of 11:32, 11 October 2022

An overview of the firmware implemented in Readout card is described here: [PDF]

  • Synthesis Reminders (for firmware developers)
    • Remember that readout_card/fsfb_clac/source/rtl/ram_40x64.vhd must be initialized with the ram_40x64.hex file in the same directory.

Revision 6.0.3

  • Filename:
  • Features:
    • 6.0.2 was built based on a version that had an unsuccessful attempt to fix the filter dynamic-range issue. This version reverts back to 5.2.1 for fsfb_calc implementation.
  • bugs
    • per-pixel servo reset doesn't also reset the filter
    • resetting any pixel with per-pixel reset also resets all the pixels in the last row (as specified by num_rows, ignoring row_order)

Revision 6.0.2 (TEST!)

  • Features
    • built based on 5.2.2
    • added support of upper 32 word needs an additional wait cycle for ack_read
    • delay wishbone readback by one clock cycle for reading back flx_quanta and adc_offset,
    • there seem to be a filter gain of factor of 2 added
  • bugs
    • per-pixel servo reset doesn't also reset the filter
    • resetting any pixel with per-pixel reset also resets all the pixels in the last row (as specified by num_rows, ignoring row_order)
    • it seems to have a different filter gain

Revision 5.2.2 (TEST!)

  • bugfix or enhancement?
    • fixes a dynamic-range issue with the filter by applying a 20-bit window to the output of stage 1 filter (with lsb being configurable) before passing it on the next stage.
  • bugs
    • per-pixel servo reset doesn't also reset the filter
    • resetting any pixel with per-pixel reset also resets all the pixels in the last row (as specified by num_rows, ignoring row_order)

Revision 5.2.1 (recommended!)

  • Filename:
    • rc_stratixIII_v05020001_05jun2014.sof
  • bugfix
  • bugs
    • per-pixel servo reset doesn't also reset the filter
    • resetting any pixel with per-pixel reset also resets all the pixels in the last row (as specified by num_rows, ignoring row_order)

Revision 5.2.0

  • Filename:
    • rc_stratixIII_v05020000_28may2013.sof
  • Features:
    • added the ability to reset the flux-loop servo on per-detector basis by adding servo_rst_arm and servo_rst_col# parameters. This will reset the integral_term, the integral_clamp, anf flux-jump counter.
  • bug:
    • servo_rst_col# works for col 0 and 1, but not for col2 to 7! This is fixed in 5.2.1
    • per-pixel servo reset doesn't also reset the filter
    • resetting any pixel with per-pixel reset also resets all the pixels in the last row (as specified by num_rows, ignoring row_order)

Revision 5.1.d

  • Filename:
    • rc_stratixIII_v0501000d_30oct2012.sof
  • Features:
    • flux-jump routine is revamped to minimize the additional delay for applying sq1fb when flux-jump is enabled. In this version sq1fb DAC is refreshed at clock cycle 10 of each row visit when flux-jump is enabled and at clock cycle 7 when flux-jump is disabled.
    • extended dynamic range of the filter by increasing the width of filter-delay terms from 29 to 32 bits
    • lower power consumption (maybe?)
  • Details
    • DDR2 module not instantiated (chips not installed) and on-chip termination resistors not in effect which can potentially save power.

Revision 5.1.c (Test)

  • Filename:
    • rc_stratixIII_v0501000c_31aug2012.sof
  • Features:
    • extended dynamic range of the filter by increasing the width of filter-delay terms from 29 to 32 bits
    • based on 5.1.a
    • lower power consumption (maybe?)
    • data_mode=4 reports fb(29 downto 12) instead of fb(31) & fb(28 downto 12)! no sticky bit.
  • Details
    • DDR2 module not instantiated (chips not installed) and on-chip termination resistors not in effect which can potentially save power.

Revision 5.1.b (Stable Rev.B Cards)

  • Filename:
    • rc_v0501000b_23mar2012.sof (Rev. B cards)
  • Features:
    • based on 5.1.8 (used Q11SP1)
    • added intergral_term fix from 5.1.9
  • Details
    • qterm (or filtered-p) implementation is not included, because the design doesn't fit on the FPGA on Rev. B cards anymore.

Revision 5.1.a (Stable)

  • Filename:
    • rc_stratix3_v0501000a_24jan2012.sof (Rev. E cards)
  • Features:
    • based on 5.1.9 (used Q10SP1)
    • pterm_decay_bits (par_id = 0x64) is now programmable and is initially set to 0 to have pure p-term and be compatible with older firmware. (p-term implemented as q(n) = er(n) + b*q(n-1) where b=(1-1/2^k)with k=pterm_decay_bits)
    • see bugfix in 5.1.9

Revision 5.1.9 (test)

  • Filename:
    • rc_stratix3_v05010009_23jan2012.sof (for Rev. E cards)
  • Features:
    • based on 5.1.8 (used Q10SP1)
    • first implementation of decayed-p-term in sq1fb calculation. The p-term is now implemented as q(n) = er(n) + b*q(n-1) where b=(1-1/2^k) and k=3 hardcoded.
    • added pterm_decay_bits (par_id=0x64) as a register set to 3, but not tied to k in pterm calculation yet.
  • Bugfix:
    • This version fixes the bug introduced starting 5.0.e, the integral-term used to calculate sq1fb was calculated based on coadded value of (sample_num-1) samples and then the integral term stored for next round included sample_num-2. This is almost like having a p-term..

Revision 5.1.8 (s1fb_dly=7)

  • Filename:
    • rc_stratix3_v05010008_11jan2012.sof (for Rev. E cards)
  • Features:
    • based on 5.1.7 (used Q10SP1)
    • reverts back to applying S1fb after 7 clock cycles when flux-jump is off, and after 18 clock cycles when flux-jump is on.

Revision 5.1.7 (rectangle-mode bugfix)

Reduction in high-frequency noise due to rectangle-mode bugfix
  • Filename:
    • rc_stratix3_v05010007_17nov2011.sof (for Rev. E cards)
  • Features:
    • based on 5.1.6 (used Q10SP1)
  • Bugfix:
    • In all RC firmware prior to 5.1.7, the read pointer in the rectangle-mode data was being refreshed at ARZ even if it was in the middle of a long readout (large frame readout). This resulted in seeing duplicate data in high-data-rate rectangle-mode readout only when the following condition was _NOT_ true: (230 + 2*cc num_rows_reported*cc num_cols_reported) < (num_rows*row_len). This is fixed in 5.1.7.

Revision 5.1.6 (Stable)

  • Filename:
    • rc_stratix3_v05010006_27oct2011.sof (for Rev. E cards)
  • Features:
    • based on 5.1.5 (used Q10SP1)
    • coadd window and feedback-calculation blocks are adjusted for ADC latency of readout card Rev. E

Revision 5.1.5 (test)

  • Filename:
    • rc_stratix3_v05010005_15sep2011.sof (for Rev. E cards)
  • Features:
    • based on 5.1.2
    • reverts back to applying SQ1FB after 18 clock cycles whether flux-jumping is on or off
  • Bugfix:
    • All stratixiii firmware revisions prior to this version adjusted the co-add window for an ADC latency of 4 instead of 11. (Rev. E RC has serial ADC installed with 11 clock cycle latency.) The coadd window is now adjusted properly.
  • Bug:
    • The last row samples can not be used in servo_mode=3. For proper operation: sample_dly + sample_num needs to be < row_len - 7 (I think). Although, the coadd window was adjusted in this version, but the calculation block latches data before coadd is done (coadd_done_o signal).

Revision 5.1.4 (Scuba2)

  • Filename:
    • rc_v05010004_01jun2011.sof (for Rev. B cards)
  • Features:
    • based on 5.1.3
    • sq1_fb applied after 7 clock cycles when flux-jump off, and after 18 when flux-jump is on.
  • bugfix:
    • fixed bug with fsfb_corr when reverting back to applying sq1fb after 7 clk cycles when fj is off

Revision 5.1.3 (Scuba2)

  • Filename:
    • rc_v05010003_01jun2011.sof (for Rev. B cards)
  • Features:
    • based on 5.1.2
    • reverts back to applying SQ1FB after 7 clock cyclces when flux-jumping is off, and after 18 clock cycles when flux-jumping is on.
    • k1 of filter params is now limited to k1<8. After generating coeffs for many filters, it is certain that this range is more than what we ever need.

Revision 5.1.2 (Stable)

  • Filename:
    • rc_stratix3_v05010002_18jan2011.sof (for Rev. E cards)
    • rc_stratix3_v05010002_18jan2011.jic (for Rev. E cards)
    • rc_v05010002_03feb2011.sof (for Rev. B cards)
    • rc_v05010002_03feb2011.pof (for Rev. B cards)
  • Features:
    • based on 5.1.1 with k1 and k2 (filter params) limited to k1<16 and k2<32 in order to resolve the timing when compiling for smaller Stratix FPGA on RC Rev. B.
  • Bug fix:
    • the 2-rows-off filtered data readout introduced with configurable filter in rev. 5.1.0 and 5.1.1 is fixed now.
  • Bugs:
    • none so far.
  • FPGA Resource Usage (readout_card.fit.rpt, rev. B)
; Total logic elements      ; 33,285 / 41,250 ( 81 % )                       ;
; Total pins                ; 358 / 616 ( 58 % )                             ;
; Total memory bits         ; 1,405,440 / 3,423,744 ( 41 % )                 ;
  • FPGA Timing Analysis (readout_card.tan.rpt, rev. B)
; Fast Model Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 6.591 ns  
; Fast Model Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 7.206 ns  
; Fast Model Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 18.299 ns

Revision 5.1.1 (test only)

  • Filename:
    • rc_v05010001_01dec2010.sof (for Rev. B cards)
  • Features:
    • based on 5.1.0, but k1 and k2 (filter params) are now limited to k1<16 and k2<32 in order to resolve the timing failures of compiling 5.1.0 for smaller Stratix FPGA on RC Rev. B.
  • Bugs:
    • filter mode data is off by 2 rows.

Revision 5.1.0 (test only)

  • Filename:
    • rc_stratix3_v05010000_01nov2010.sof (for Rev. E cards)
    • rc_v05010000_01nov2010.sof (for Rev. B cards) has timing failures do not use!!!
  • Features:
  • Details
    • It is built on Quartus10.1.
    • tcl files had to be updated as cmp syntax is not supported in Q10 anymore.
    • Rev. E cards now can be identified by reading back pcb_rev as part of card_type, therefore both stratix I and III sof/pof/jic are generated from the same source.
  • Bugs:
    • rc_v05010000_01nov2010.sof has timing failures that were overlooked, do not use this firmware for Rev.B cards.
    • filter mode data is off by 2 rows.
  • FPGA Resource Usage and Timing Report (readout_card.fit.rpt and readout_card.tan.rpt): logic usage is upto 85% from 66% in 5.0.d/e/f

Revision 5.0.f (Stable)

  • Filename:
    • rc_v0500000f_22oct2010.sof (for Rev. B cards)
    • rc_stratix3_v0500000f_22oct2010.sof (for Rev. E cards)
  • Features:
    • Bugfix: integral clamp should work now. only positive integral_clamp values are valid!
  • Details::
    • SQ1FB is applied 18 clock cycles after start of a row visit (SQ1_Bias being applied) regardless of flux-jump being enabled or not. In pre-5.0.b firmware SQ1FB was being applied after 7 clock cycles when flux-jump was disabled and after 18 clock cycles when flux-jump was enabled.
    • available for both Rev. E and Rev. B cards, the upper byte of card_type parameter now reports the pcb revision.
    • development note: It is built on Quartus10.1.
  • Bugs:
    • none yet!
  • FPGA Resource Usage (readout_card.fit.rpt):
; Total logic elements      ; 27,377 / 41,250 ( 66 % )                           ;
; Total pins                ; 358 / 616 ( 58 % )                                 ;
; Total memory bits         ; 1,405,440 / 3,423,744 ( 41 % )                     ;
  • FPGA Timing Analysis (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.652 ns 
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.385 ns 
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.860 ns

Revision 5.0.e (test only)

  • Filename:
    • rc_v0500000e_06oct2010.sof
  • Details:
    • an unsuccessful attempt to fix integral_clamp, but changed the functionality so that it clamps at the value, but it doesn't hold the clamp. i.e., if the calculated sq1fb becomes less than the specified clamp value, the sq1fb is not clamped anymore. This is not a desired functionality!

Revision 5.0.d (test only)

Scope snapshot
  • Filename:
    • rc_v0500000d_04aug2010.sof
  • Features:
    • Bugfix: To fix the bug associated with negative flux-jumps, reverted to signed multiplier and hence, incremented the width of the flux-quanta multiplier input by 1.
  • Details::
    • SQ1FB is applied 18 clock cycles after start of a row visit (SQ1_Bias being applied) regardless of flux-jump being enabled or not. In pre-5.0.b firmware SQ1FB was being applied after 7 clock cycles when flux-jump was disabled and after 18 clock cycles when flux-jump was enabled.
  • Bugs:
    • integral_clamp is broken. To test the clamping, a servo-locked ramp was initiated on the sq1fb and then flux-jumping was turned on and observed by attaching a scope to the SQ1FB output. With integral_clamp=80000000, flux_quanta=8000, gaini=1, flux-jump enabled, we see scope snapshot used slow_fb_ramp.py script for testing.
  • FPGA Resource Usage and Timing Report (readout_card.fit.rpt and readout_card.tan.rpt): no change compared to 5.0.a/b/c

Revision 5.0.c (test only)

  • Filename:
    • rc_v0500000c_16jun2010.sof
  • Features:
    • Based on rev. 5.0.b
    • Re-introduced flux-jump counter clamping to maintain continuity in behavior from past versions of firmware in the field.
    • Important: SQ1FB is applied 18 clock cycles after start of a row visit (SQ1_Bias being applied) regardless of flux-jump being enabled or not. In pre-5.0.b firmware SQ1FB was being applied after 7 clock cycles when flux-jump was disabled and after 18 clock cycles when flux-jump was enabled.
  • Details:
  • Bugs:
    • flux-jump is broken. flux-jumping block misbehaves at the first jump in the negative range.
  • FPGA Resource Usage (readout_card.fit.rpt):
; Total logic elements     ; 26,800 / 41,250 ( 65 % )                      ;
; Total pins               ; 358 / 616 ( 58 % )                            ;
; Total virtual pins       ; 0                                             ;
; Total memory bits        ; 1,405,440 / 3,423,744 ( 41 % )                ;
; DSP block 9-bit elements ; 76 / 112 ( 68 % )                             ;
; Total PLLs               ; 1 / 6 ( 17 % )                                ;
; Total DLLs               ; 0 / 2 ( 0 % )                                 ;
  • FPGA Timing Analysis (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.964 ns  ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 4.382 ns  ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 15.924 ns ;

Revision 5.0.b (test only)

  • Filename:
    • rc_v0500000b_03jun2010.sof
  • Features:
    • Based on rev. 5.0.a
    • A bug that caused jumps in first-stage feedback, and detected as spikes in the raw data of pixels that were in servo_mode=0,1,2 was fixed. The jumps in FSFB were due to flux-jumping being enabled on live pixels with non-zero flx_quanta, and being disabled on the fly on dead pixels with flx_quanta=0. Flux-jumping is now disabled on a column-by-column basis if a column is in servo_mode = 0,1,2.
    • Ineffective clamping was removed from the flux-jumping block (as per 5.0.9), as it is now replaced by the clamping that was perfected in rev. 5.0.10
    • A sticky bit that only affected servo_mode=0,1,2 was also removed from the flux-jumping block.
    • flx_lp_init commands now also clear the flux-jumping block as well.
    • The 11-clock-cycle delay (in applying SQ1_FB) that in previous firmware only occurred when flux-jumping was enabled, now (in this version) is in effect all the time. Due to the bug-fix above, flux-jumping can be disabled on a column-by-column basis by setting servo_mode=0,1,2 when en_fb_jump=1. Before the change, this meant that constant values could be applied with or without the 11-cycle delay if en_fb_jump=1 or 0. To make the delay consistent, it is now always 11 cycles. As background, the flux-jumping block is pipelined, meaning that it does calculations for all 8 channels serially. The serialization is because of DSP-block limitations in the Readout Card FPGA that prevent us from doing all 8 channels in parallel. The reason that it takes 11 cycles to complete the flux-jumping calculations is because the values are computed for the eight channels in three ALU stages: 8 + 3 = 11 cycles. Adding 11 cycles to the 7 cycles of latency from other stages in the system results in: 11 + 7 = 18 cycles of latency from the start of a row dwell period before the first-stage feedback is applied. In rc_v5.0.c, I enforce the 18-cycle delay even when flux-jumping is not enabled to maintain uniformity across all eight channels, because flux-jumping is enabled/disabled on a per-channel basis. In other words, if I hadn't enforced the 18-cycle delay, some channels could have their feedback applied after 7 cycles, while others could have it applied after 18 cycles. I wasn't a fan of this non-uniformity. I realize that 18 cycles is a long time. In fact, so is 7. In the last few months, we have been discussing how to reduce these times to 1 cycle, because every experiment out there wants to multiplex as fast as possible, and the 7/18-delay is a rate limiting step.
    • The flux-jumping code was re-arranged in the flux-jumping block to reflect the flow of data through the pipeline and make it easier to understand.
  • Details:
  • Bugs:
    • flux-jump does not work when jumping to negative values.
  • FPGA Resource Usage (readout_card.fit.rpt):
; Total logic elements     ; 26,745 / 41,250 ( 65 % )                      ;
; Total pins               ; 358 / 616 ( 58 % )                            ;
; Total virtual pins       ; 0                                             ;
; Total memory bits        ; 1,405,440 / 3,423,744 ( 41 % )                ;
; DSP block 9-bit elements ; 76 / 112 ( 68 % )                             ;
; Total PLLs               ; 1 / 6 ( 17 % )                                ;
; Total DLLs               ; 0 / 2 ( 0 % )                                 ;
  • FPGA Timing Analysis (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.459 ns  
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.895 ns  
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 15.956 ns

Revision 5.0.a (test only)

  • Filename:
    • rc_v0500000a_12mar2010.sof
  • Features:
    • Based on the merger of rev. 5.0.8 and 5.0.9.
    • integral_clamp command is added where a clamp value is set for the integral term and once the integral term hits that value, the integral-term is clamped to that value and p-term and d-term are clamped to zero. When integral_term=0 then no clamping is in effect, similar to previous releases of firmware.
    • The low pass filter has 20-bit input and f_3dB/f_samp = 122Hz/15kHz .
    • The flux-jump clamping that was removed in 5.0.9 is included once again here, as we decided this is safer for now.
  • Details:
    • "lock_dat_left" parameter that was removed in 5.0.9 is now implemented as "lock_dat_lsb"
  • Bugs:
  • Synthesis Notes:
    • The quartus.ini file was present in the synth directory during synthesis
    • tag name: rc_v0500000a_12mar2009! years were mixed up!
  • FPGA Resource Usage (readout_card.fit.rpt):
  • FPGA Timing Analysis (readout_card.tan.rpt):

Revision 5.0.9 (buggy)

  • Filename:
    • rc_v05000009_13nov2009.sof
  • Features:
    • Based on rev. 5.0.4
    • Removes a sticky bit in pid calculation result storage -- in fsfb_processor.
    • Adds a command to clamp the growth of the I-term to prevent wrapping and track down the source of Caltech's FSFB jumps.
    • Removed the unused lock_dat_left parameter. The ability to shift left was moved to the fsfb_corr block some time ago.
    • Fixed a sign extension bug acting on the flux quanta, which limited the value to 8191. Changed the extension from signed to unsigned.
    • Removed ineffective clamping in the flux-jump calculation block.
    • IMPORTANT: Must be used in conjunction with firmware rev. 5.0.0+ of all other cards.
  • Details:
  • Synthesis Notes:
    • The quartus.ini file was present in the synth directory during synthesis
  • FPGA Resource Usage (readout_card.fit.rpt):
; Total logic elements     ; 27,960 / 41,250 ( 68 % )                      ;
; Total memory bits        ; 1,405,440 / 3,423,744 ( 41 % )                ;
  • FPGA Timing Analysis (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.825 ns  ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.878 ns  ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 14.397 ns ;

Revision 5.0.8 (UBC only)

  • Filename:
    • rc_v05000008_09oct2009.sof
  • Features:
    • Based on rev. 5.0.4
    • type 1 low-pass filter: f3dB=122Hz for fsample=15kHz
    • Filter-input-width changed from 18b to 20b with no sticky bits!
    • removed sticky bits in internal arithmetic of the filter.

Revision 5.0.7 (type-2 filter)

  • Filename:
    • rc_v05000007_09oct2009.sof
  • Features:
    • Based on rev. 5.0.4
    • type-2 low-pass-filter: f3dB=75Hz for fsample=30000.
    • Filter-input-width changed from 18b to 20b with no sticky bits!
    • inter-biquad-gain-scaling for the filter is 2^14
    • filter results are scaled down by 2^3 in the output of the filter.
    • removed sticky bits in internal arithmetics
    • _correction_ disabled in fsfb_proc_pidz
  • Details:
    • quartus.ini file was not present in synth directory.
  • Bugs:
    • none to report
  • FPGA Resource Usage (readout_card.fit.rpt):
  • FPGA Timing Analysis (readout_card.tan.rpt):

Revision 5.0.6 (UBC only)

  • Filename:
    • rc_stratix3_v05000006_15sep2009.sof
  • Features:
    • Only Valid for Rev. C/D Cards
    • Based on rev. 5.0.3
    • tcl file updated for Rev. D and aligned with top-level and qsf (project file).
    • flux loop commented, just to try sampling the ADC.
    • compiled with Q9.1

Revision 5.0.5 (UBC only)

  • Filename:
    • rc_v05000005_04sep2009.sof
  • Features:
    • Based on rev. 5.0.2
    • changed the low-pass-filter to f(3db)=75Hz for f(sample)=30000.
  • Details:
    • quartus.ini file was not present in synth directory.
  • Bugs:
    • negative inputs to the filter cause filter to have a non-flat pass-band region. may have to do with sign-handling...
  • FPGA Resource Usage (readout_card.fit.rpt):
  • FPGA Timing Analysis (readout_card.tan.rpt):

Revision 5.0.4 (Stable)

  • Filename:
    • rc_v05000004_28aug2009.sof
  • Features:
    • Based on rev. 5.0.2
    • BUG Fix: handles 14-bit flux quanta (changed the multiplier to unsigned)
    • BUG Fix: changed standard logic vector extension from signed to unsigned in flux-jumping slave.
    • IMPORTANT: Must be used in conjunction with firmware rev. 5.0.0+ of all other cards.
  • Details:
  • Bugs:
    • None so far.
  • Synthesis Notes:
    • The quartus.ini file was present in the synth directory during synthesis
  • FPGA Resource Usage (readout_card.fit.rpt):
; Total logic elements     ; 26,170 / 41,250 ( 63 % )                      ;
; Total memory bits        ; 1,405,440 / 3,423,744 ( 41 % )                ;
  • FPGA Timing Analysis (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.541 ns  ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.612 ns  ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 15.398 ns ;

Revision 5.0.3

  • Filename:
    • rc_stratix3_v05000003_21aug2009.sof
  • Features:
    • ONLY valid REV C/D RC Cards
    • Based on rev. 5.0.2
    • flux loop commented, just to try sampling the ADC.
    • updated tcl file, but still need to rely on project file as well as qsf file.
    • changed default level of adc_sclk to '1'
    • dac_clr_n was changed from an output to an input.
    • added 'locked' interface to rc_pll_stratix_iii
    • renamed the adc_pll clock signals to more explanitory names
    • added the FPGA_DEVICE_FAMILY generic to the dispatch interace for synthesis of the dc_fifo in lvds_rx
    • uncommented DDR interface to force the syntesizer to use correct left and right PLLs (in conjunction with ADC and DDR PLLs)
    • added test signals to test_status to see clocks on the scope.

Revision 5.0.2 (buggy)

  • Filename:
    • rc_v05000002_test00_tagged.sof
  • Features:
    • Based on rev. 5.0.1
    • Fixed a bug in wbs_frame_data that stored data incorrectly if reporting 1 or 2 pixels only.
    • IMPORTANT: Must be used in conjunction with firmware rev. 5.0.0+ of all other cards.
  • Details:
  • Bugs:
    • None so far.
  • Synthesis Notes:
    • The quartus.ini file was present in the synth directory during synthesis.
  • FPGA Resource Usage (readout_card.fit.rpt):
; Total logic elements     ; 26,186 / 41,250 ( 63 % )                      ;
; Total memory bits        ; 1,405,440 / 3,423,744 ( 41 % )                ;
  • FPGA Timing Analysis (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.755 ns  ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.979 ns  ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.067 ns ;

Revision 5.0.1 (buggy) (Filter + Raw + Rectangle, 2 LVDS)

  • Filename:
    • rc_v05000001_26may2009.sof
  • Features:
    • Combines features in rev. 5.0.0 (2 LVDS Lines) and rev. 4.0.e (Filtered + Raw), with the NEW rectangle mode.
    • IMPORTANT: Must be used in conjunction with firmware rev. 5.0.0+ of all other cards.
  • Bugs:
    • Has a bug in wbs_frame_data that stored data incorrectly if reporting 1 or 2 pixels only.
  • Synthesis Notes:
    • The quartus.ini file was present in the synth directory during synthesis.
  • FPGA Resource Usage (readout_card.fit.rpt):
; Total logic elements     ; 26,565 / 41,250 ( 64 % )                 ;
; Total memory bits        ; 1,405,440 / 3,423,744 ( 41 % )           ;
  • FPGA Timing Analysis (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.656 ns  ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.861 ns  ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 14.167 ns ;

Revision 5.0.0 (Filter Only, 2 LVDS)

  • Filename:
    • rc_v05000000_22dec2008.sof (tagged as sys_v05000000_22dec2008)
  • Features:
    • IMPORTANT: Must be used in conjunction with firmware v05000000+ of all other cards!!!
    • Adds the ability to read out one column of data continuously from readout cards
    • Adds data mode 11, which is an engineering mode. Data points are 32-bits, and bits [9..3]=row_index, [2..0]=column_index. This mode is useful for determining which pixels one is reading out in the array, in column mode for example.
  • Bugs:
    • None so far.
  • Synthesis Notes:
    • The quartus.ini file was not present in the synth directory during synthesis.
  • FPGA Resource Usage (readout_card.fit.rpt):
; Total logic elements     ; 26,607 / 41,250 ( 65 % )                 ;
; Total memory bits        ; 406,016 / 3,423,744 ( 12 % )             ;
  • FPGA Timing Analysis (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.558 ns  ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.892 ns  ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.987 ns ;

To-Do List

  • the starting point for the servo is currently zero and it would be nice to have it programmable.

RC Synthesis Notes

  1. The following note applies when using Quartus versions earlier than Q7: Quartus.ini file had to exist in synth directory up to revision 4.0.a due to a bug that started in Quartus 6.1 and would synthesize away arbitrary parts of readout card. We contacted Altera at the time and they provided us the ini file.
  2. Timing: There is no "lock region" defined for readout card. Timing on readout card is tight and since version 3 or so any new feature would initially fail timing till some synthesis options were tweaked. One path that remains to be consistently marginal is from addr_gen counter (i.e. tga_o counter) in dispatch_wishbone.vhd to wishbone slaves particularly misc_banks_admin.vhd. Modules that are rewritten to address timing concerns are fsfb_corr, all_cards, misc_banks_admin, and finally instantiating an lpm counter instead of a counter from components library. Surprisingly, the lpm counter reduced 87 failures to 37, although looking at the technology map viewer, it seemed that they were both synthesized the same.
  3. Compile time: This was at some point 4.5 hours, after going to dual core PC, this was reduced to 35 minutes. After extending pid gains to 12b and fixing offset/sa_bias update code, the compile time increased to 1.5hr again with utilization up to ~70%.
  4. wbs_fb_storage, ram_8x64, pid_ram had to be regenerated using latest (Q7.2) MegaWizard to get rid of the bug associated with failure to read after power up until a reset was issued.
  5. During simulations, the initialization of RAM block with .hex files needs to be disabled. This is done by commenting out the following lines from the MegaWizard generated Megafunction files (remember to un-comment them before synthesizing the code):
lpm_file => "C:/scuba2_repository/cards/readout_card/fsfb_calc/source/rtl/ram_40x64.hex", and
lpm_file    : STRING;
  1. Starting Q10.0 use TimeQuest timing analyzer as oppose to the classic one. The classic one is being phased out by Altera. In order to use TimeQuest, you need to have an sdc file present in your project directory.
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