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Firmware Programming Files

Revision 6.0.2

Filename: bc_v06000002_20160519.sof
Features: support for upper 32 words; introduced flux_fb_dly so flux_fb DACs are asserted after flux_fb_dly. New data is pre-loaded right after flux_fb_dly.

Revision 5.3.5 (test)

Filename: bc_v05030005_18dec2014.sof
Features: based on 5.3.4, introduced num_rows_idle

Revision 5.3.4 (recommended)

Filename: bc_v05030004_20dec2012.sof
Features: based on 5.3.2
Bugfix: enbl_flux_fb_mod and enbl_bias_mod can be asserted for any combination of columns
Bug: with row_len=90, changing ln_bias_0 parameter also changes ln_bias_1!

Revision 5.3.2 (Rev E cards only!)

Filename: bc_v05030002_21aug2012.sof
Features: based on 5.3.1, compiled with RevE pin assignment.
Bug: enbl_flux_fb_mod only works for channel 0.; enbl_bias_mod has an offset of 1.

Revision 5.3.1 (Stable)

Filename: bc_v05030001_12apr2012.sof
Features: mod_val is now a single value instead of 32 distinct values.
Bug: enbl_flux_fb_mod only works for channel 0.; enbl_bias_mod has an offset of 1.

Revision 5.3.0 (Test)

Filename: bc_v05030000_26mar2012.sof
Features: added mod_val, enbl_flux_fb_mod, enbl_bias_mod parameters. Once the modulation is enabled, values specified by mod_val are going to be added to flux_fb or bias. This can be used to run an internal ramp on mod_val values and having ramps with different offsets being run on individual bias lines.

Revision 5.2.0 (Stable)

Filename: bc_v05020000_28nov2011.sof
Features: ln_bias lines wake up to 0V and an 'rb bias' command returns the content of the RAM block used to refresh DACs from. This RAM is initilized to 0. Note that Rev. F cards have bipolar DACs and 0V corresponds to 32768 (mid range) as oppose to 0. Therefore, an initial readback from RAM does not return valid values!!! I claim that this is not confusing!

critical_err_rst and fpga_clr commands are supported now. critical_err_rst only works if JP2 jumper inserted.

Details: When installed on Rev. D file, tes_mapping has to have offset =11 in mce.cfg, heater has to have offset=10 in mce.cfg.

Revision 5.1.0 (Stable)

Filename: bc_v05010000_25oct2011.sof
Features: In multiplex mode: DACs are clocked early in the row-visit, chip-select is always low and only strobed high at clock-cycle 1 during row-visit.; In non-multiplex mode: flux_fb values are all loaded at the start of the frame. (Previous versions updated DACs row-aligned as oppose to frame-aligned and this had the undesired effect of refreshing some DACs on one row and rest of the DACs on the following row depending on which clock cycle the command was received. This only matters when running internal ramp on bias-card parameters.); ln_bias lines are only refreshed once and frame-aligned! a bugfix!

Bugs: ln_bias lines are set to code 0 or -5V at power up and need to be cleared to 0V by issuing an exclusive command upon startup.

Details: When installed on Rev. D file, tes_mapping has to have offset =11 in mce.cfg.

Revision 5.0.a (lab use)

Filename: bc_v0500000a_24oct2011.sof
Features: based on 5.0.9, with fixing the incomplete ifelse in spi_dac module. Was this causing the improper chip-select?

Details: When installed on Rev. D file, tes_mapping has to have offset =11 in mce.cfg.

Revision 5.0.9 (lab use)

Filename: bc_v05000009_05oct2011.sof
Features: based on 5.0.5, but instead of loading a new DAC value at the start of the row, it is now 32 clock cycles after row switch.(or clocking starts at row-switch)

Details: When installed on Rev. D board, tes_mapping has to have offset =11 in mce.cfg.

Revision 5.0.8 (test)

Filename: bc_v05000008_04oct2011.sof
Features: based on 5.0.5, but instead of loading a new DAC value at the start of the row, it is now 20 clock cycles after row switch.

Details: When installed on Rev. D board, tes_mapping has to have offset =11 in mce.cfg.

Revision 5.0.7 (recommended)

Filename: bc_v05000007_22jun2011.sof
Features: based on 5.0.5, but instead of loading a new DAC value at the start of the row, it is now 10 clock cycles after row switch.

Details: When installed on Rev. D board, tes_mapping has to have offset =11 in mce.cfg.

Revision 5.0.6 (test)

Filename: bc_v05000006_11may2011.sof

To Do:
Features:
- Changes the timing of loading the fb_col# values from 32 clock cycles before the start of a new frame, to the start of a new frame. This firmware was generated to find the reason for the downturns in raw data at the end of rows, as seen by Jeffrey Filippini:
- See details here: http://spiderwiki.princeton.edu/spider/AnalysisLogbook/TestCryostat/20110427_muxing/index.html

FPGA Resource Usage (bias_card.fit.rpt):

; Total logic elements     ; 6,278 / 10,570 ( 59 % )                       ;
; Total pins               ; 209 / 427 ( 49 % )                            ;
; Total virtual pins       ; 0                                             ;
; Total memory bits        ; 133,120 / 920,448 ( 14 % )                    ;
; DSP block 9-bit elements ; 8 / 48 ( 17 % )                               ;

Timing Analyzer Summary (bias_card.tan.rpt):

; Fast Model Clock Setup: 'bc_pll:pll0|altpll:altpll_component|_clk0' ; 6.930 ns  
; Fast Model Clock Setup: 'bc_pll:pll0|altpll:altpll_component|_clk1' ; 6.980 ns  
; Fast Model Clock Setup: 'bc_pll:pll0|altpll:altpll_component|_clk3' ; 16.383 ns

Revision 5.0.5 (recommended)

Filename: bc_v05000005_20jul2010.sof
Features: based on 5.0.4, but updated for Rev. F/D hardware pinout.; card_type parameter now includes the pcb-revision information as well as the card_type. card_type is specified as 0x01 as the lower byte (same as before). Reading back card_type parameter returns: 0x0F01 in Rev. D cards, and 0x0601 in Rev. F cards. (Previously, reading back card_type parameter only returned 0x01).

Details: When using tes_bias lines, make sure the count is 12 for bias parameter in mce.cfg file.; When installed on Rev. D file, tes_mapping has to have offset =11 in mce.cfg.

To do: none
Bugs: none
FPGA Resource Usage

: Total logic elements     ; 60%
: M512s                    ; 49%
: M4Ks                     ; 100%
: M-RAMs                   ; 100%

Revision 5.0.4 (lab use)

Filename: bc_v05000004_20may2010.sof
Features: build based on 5.0.3 for Rev. E cards; Biases are refreshed 1 clock cycles after the start of a new row, regardless of whether they are running in multiplex mode or not and whether it is a regular bias line or low-noise bias line.
Details: NOTE If this firmware is loaded on a Rev. D card, it's harmless. The only functionality loss is that the bias command will not work as unfortunately DAC CS and CLK pins are swapped for the bias DAC between the two revisions of the card.
To do: none
Bugs: none
FPGA Resource Usage: Total logic elements ; 60%; M512s ; 49%; M4Ks ; 100%; M-RAMs ; 100%

Revision 5.0.3 (Rev. E cards)

Filename: bc_v05000003_12may2010.sof
Features: build based on 5.0.2 for Rev. E cards; added fb_col0 to fb_col31 and enbl_mux commands to accommodate row-based sq2fb switching. When enbl_mux is asserted for a column, then the DAC is refreshed on every row visit with the value specified by fb_col# command.
Details: The original Bias Card design has a buffer after the DAC that is too slow followed by kHz range RC filters, so in order to enable the multiplexing feature, one has to make sure that the BC hardware is modified as per ECO-xxx (to be added here).; card_type returns 5 (indicating a Rev. E); If this firmware is loaded on a Rev. D card, it's harmless. The only functionality loss is that the bias command will not work as unfortunately DAC CS and CLK pins are swapped for the bias DAC between the two revisions of the card.; combinational loops present in previous versions are removed now; There is 9+16*2=41 clock cycle (820ns) delay for the bias to be applied after the start of a new row. This combined with another 400ns delay due to inherent DAC delay is about 60 clock-cycle delay.
To do: The excessive 41 clock cycle delay to apply a new bias has to be reduced. It is conceivable to preload the DACs and reduce this delay to 1 to 2 clock cycles.
Bugs: none
FPGA Resource Usage: Total logic elements ; 6,140 / 10,570 ( 58 % ) ;; Total memory bits ; 133,120 / 920,448 ( 14 % ) ;; M512s ; 48 / 94 ( 51 % ) ;; M4Ks ; 60 / 60 ( 100 % ) ;; M-RAMs ; 0 / 1 ( 0 % ) ;

Revision 5.0.2 (lab use)

Filename: bc_v05000002_xxjan2010.sof
Features: build based on 5.0.1 for Rev. E cards; Independent control for ln_bias lines 0 to 11
Details: If this firmware is loaded on a Rev. D card, it's harmless. The only functionality loss is that the bias command will not work as unfortunately DAC CS and CLK pins are swapped for the bias DAC between the two revisions of the card.
To do: fix combinational loops on read-ram register

Bugs

Revision 5.0.1 (lab use)

Filename: bc_v05000001_19jan2010.sof
Features: supports the new low-noise bias lines (total of 12) introduced in Bias Card Rev. E; card_type parameter is set to 5 (bias-card Rev. E); All DACs are loaded at once as oppose to previous revisions that loaded them one after next.; DAC clock is now 25MHz and generated by PLL, previous firmware had 12.5MHz clock generated by dividing down.
Details: If this firmware is loaded on a Rev. D card, it's harmless. The only functionality loss is that the bias command will not work as unfortunately DAC CS and CLK pins are swapped for the bias DAC between the two revisions of the card.
To do: All ln_bias lines are controlled at once and this should be modified to independent control.
Bugs

ln_bias_0 doesn't work, because the data line for ln_bias_0 is not connected in firmware.

Revision 5.0.0

Filename: bc_v05000000_22dec2008.sof (tagged as sys_v05000000_22dec2008)

To Do:
Features:
- IMPORTANT: Must be used in conjunction with firmware v05000000 of all other cards!!!
- To allow enough data bandwidth, the spare LVDS line from each card to the Clock Card is now used

Details:

Bugs:
- None yet reported

FPGA Resource Usage (bias_card.fit.rpt):

; Fitter Status            ; Successful - Wed Jan 14 11:19:37 2009    ;
; Quartus II Version       ; 8.1 Build 163 10/28/2008 SJ Full Version ;
; Device                   ; EP1S10F780C5                             ;
; Total logic elements     ; 3,356 / 10,570 ( 32 % )                  ;
; Total pins               ; 187 / 427 ( 44 % )                       ;
; Total memory bits        ; 70,144 / 920,448 ( 8 % )                 ;

Timing Analyzer Summary (bias_card.tan.rpt):

; Fast Model Clock Setup: 'bc_pll:pll0|altpll:altpll_component|_clk1' ; 7.060 ns  ;
; Fast Model Clock Setup: 'bc_pll:pll0|altpll:altpll_component|_clk0' ; 7.125 ns  ;
; Fast Model Clock Hold: 'bc_pll:pll0|altpll:altpll_component|_clk0'  ; 0.383 ns  ;
; Fast Model Clock Hold: 'bc_pll:pll0|altpll:altpll_component|_clk1'  ; 0.384 ns  ;
; Fast Model Recovery: 'bc_pll:pll0|altpll:altpll_component|_clk0'    ; 16.037 ns ;
; Fast Model Removal: 'bc_pll:pll0|altpll:altpll_component|_clk0'     ; 0.575 ns  ;
; Total number of failed paths                                        ;           ;

Firmware repository

http://e-mode.phas.ubc.ca/mce_firmware/

Bias Card firmware

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