Difference between revisions of "Bus Backplane"

From MCEWiki
Line 1: Line 1:
{{Hierarchy header}}
+
{{Related|Backplanes}}
 
The bus backplane distributes power to MCE cards and also provides the data bus which allows inter-card communication. The data bus consist of a multi-drop 'command' line from the master slot (clock card) to all slave cards (readout, address, bias cards) and two point-to-point 'reply' lines from each slave card to the clock card. All JTAG signals are routed on the backplane to form a single JTAG chain that can be used to program all the cards in the MCE. Bypass buffers on the JTAG signals allow programming a partially populated MCE.
 
The bus backplane distributes power to MCE cards and also provides the data bus which allows inter-card communication. The data bus consist of a multi-drop 'command' line from the master slot (clock card) to all slave cards (readout, address, bias cards) and two point-to-point 'reply' lines from each slave card to the clock card. All JTAG signals are routed on the backplane to form a single JTAG chain that can be used to program all the cards in the MCE. Bypass buffers on the JTAG signals allow programming a partially populated MCE.
  

Revision as of 18:00, 31 August 2016

The bus backplane distributes power to MCE cards and also provides the data bus which allows inter-card communication. The data bus consist of a multi-drop 'command' line from the master slot (clock card) to all slave cards (readout, address, bias cards) and two point-to-point 'reply' lines from each slave card to the clock card. All JTAG signals are routed on the backplane to form a single JTAG chain that can be used to program all the cards in the MCE. Bypass buffers on the JTAG signals allow programming a partially populated MCE.

Schematics

  • MCEv2 5-MDM D0 (C586-201) [PDF]
  • MCEv2 3-MDM A (C586-101) [PDF]