Testing Bus Backplane
This page describes the procedure to test the Bus Backplane unit of an MCE.
Test Setup
(This page is excerpts from the following document: BB PWB Test (SC2_TST_S586_801) 2009-10-22-MA.doc)
This test needs to be performed when the unit under test is installed in an MCE sub-rack and wired up to the 34-pin Winchester connector. The subrack is initially empty. The back panel of the subrack should not be mounted.
Make sure the serial number for this subrack and the unit under test are recorded in: MCE subrack index
Then enter test results in CBB-0xx on the internal MCE wiki where CBB-0xx is the serial number of the unit-under test.
Test results prior to May 2011 can be found on: Z:\public_html\sc2mce\system\bus_bp\test-results
Power-rail test
- Insert a proven Power Supply Assembly (PSA) into its slot (or use a Winchester cable) and make sure it mates well with the 34-pin Winchester connector
- Connect the PSA to an external ACDCCU
- Power up the otherwise empty sub-rack
- Measure the voltages at the far end of the power lines (rails) and check if all the measured values fall within 20% of the acceptable values as follows:
Vah = 10V -Va = -6.2V +Va = 6.2V Vcore = 3V Vlvd = 4.8V Note: This test only verifies that the power distribution of the Bus Back-plane is correct. All other functionality will be tested during the pre-shipment system test.
JTAG Test
Populate the subrack with all cards. Plug in a USB Blaster to the the JTAG connector on the front panel of the clock card. Run Quartus and perform an Auto Detect. If auto-detect is successful, then the test has passed.
Repeat test with only the Clock Card installed to test the JTAG chain buffers on the backplane.
LVDS receive/transmit Test
Tested during system test.
ID Test
Record the silicon id: Issue the following command and record the result:
mce_cmd -x rb cc box_id
