Difference between revisions of "Bus Backplane"
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== Schematics == | == Schematics == | ||
| − | * MCEv2 5-MDM E0 (C586-201) [[ | + | * MCEv2 5-MDM E0 (C586-201) [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/schematics/mceV2_BusBackplane_RevE/ELE-C586-201E_Bus_BP_Schematics.PDF PDF]] (Double MCEs) |
* MCEv2 5-MDM D0 (C586-201) [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/schematics/mceV2_BusBackplane_RevD/ELE-C586-201_RevD0_BusBp_Schematics.pdf PDF]] | * MCEv2 5-MDM D0 (C586-201) [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/schematics/mceV2_BusBackplane_RevD/ELE-C586-201_RevD0_BusBp_Schematics.pdf PDF]] | ||
* MCEv2 3-MDM A (C586-101) [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/schematics/mceV2_BusBackplane_RevD/ELE-C586-101_BusBP_Schematic%20Prints.pdf PDF]] | * MCEv2 3-MDM A (C586-101) [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/schematics/mceV2_BusBackplane_RevD/ELE-C586-101_BusBP_Schematic%20Prints.pdf PDF]] | ||
[[Category:Backplanes]] | [[Category:Backplanes]] | ||
Latest revision as of 16:50, 31 January 2022
Related topics:
► Subrack
The bus backplane distributes power to MCE cards and also provides the data bus which allows inter-card communication. The data bus consist of a multi-drop 'command' line from the master slot (clock card) to all slave cards (readout, address, bias cards) and two point-to-point 'reply' lines from each slave card to the clock card. All JTAG signals are routed on the backplane to form a single JTAG chain that can be used to program all the cards in the MCE. Bypass buffers on the JTAG signals allow programming a partially populated MCE.
