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| − | = Using Remote Configuration =
| + | {{Related|Development Tools}} |
| − | * Load Clock Card v5.0.6+ Firmware in the Clock Card Factory Configuration Device (.pof file). Clock Card firmware descriptions are available [http://e-mode.phas.ubc.ca/mcewiki/index.php/Clock_Card_(CC) here].
| + | The procedure to update the [[MCE firmware]] over the fibre interface using a [[MAS]] PC, also known as "Remote Firmware Update", is described here. |
| − | * Flip the SW1p1 "BB_EN" Dip Switch on the Clock Card to 'OPEN'.
| |
| − | * Get the version of JAM Player software from SVN that is compatible with the version of Clock Card firmware you just loaded in the Factory Configuration Device:
| |
| − | ~/jp_25/mce_jam/trunk : SVN revision 16 is compatible with cc_v0500006.
| |
| − | * Compile the SVN software with the following commands:
| |
| − | make clean
| |
| − | make
| |
| − | * Use the following commands on a MAS PC to program the MCE:
| |
| − | sudo ./jam -u -v -f8000000 -aread_idcode read_idcode.jam // For Querying ID Codes
| |
| − | sudo ./jam -u -v -f800000 -aprogram -dDO_VERIFY=0 cc_xfpga_rc_pof.jam // For Programming EPC16's
| |
| − | sudo ./jam -u -v -f8000000 -aconfigure cc_xfpga_rc_sof.jam // For Configuring FPGA's
| |
| − | sudo ./jam -u -v -f8000000 -aconfigure cc_rcd_jic.jam // For Programming EPCS64's (Step 1 of 2)
| |
| − | sudo ./jam -u -v -f100000 -aprogram -dDO_VERIFY=0 cc_rcd_jic.jam // For Programming EPCS64's (Step 2 of 2)
| |
| − | * The read_idcode.jam file is included in SVN as a test script to help you determine whether you have set up the system correctly. If you can run it, then you are ready to re-configure FPGA's, EPC16's and EPCS64's. For these devices, you will need to generate .jam files that are specifically suited to your system. You will need Quartus II software to do this. Instructions on generating .jam files are [http://e-mode.phas.ubc.ca/mcewiki/index.php/MCE_Programming_File_Conversions here]. If you do not have access to this software, send the output of the read_idcode.jam script to UBC, and configuration .jam files will be generated for you.
| |
| | | | |
| − | = System Snapshot Prior to Implementation = | + | = Introduction = |
| − | * Note that to enable remote configuration, SW1p1 must be switched to "OPEN."
| |
| − | * Make sure that any scope probes on the JTAG lines are set to 1MOhm input resistance.
| |
| | | | |
| − | == MCE Hardware ==
| + | Each of the Address Card, Bias Cards, and Readout Cards of the MCE has an Altera Stratix FPGA along with a configuration device ([[MCE FPGA Types | See here]]). The Clock Card, however, has one FPGA with two configuration devices. FPGAs are RAM-based devices while configuration devices are Flash-based devices. Upon power up, each FPGA is loaded from its respective configuration device. The Clock Card FPGA is loaded from its factory configuration device upon power up, but then later, the firmware in the application configuration device can be loaded into the FPGA by issuing a command, i.e.: |
| − | Card Schematics:
| |
| − | * [http://www.phas.ubc.ca/~mce/mcedocs/hardware/schematics/Clock%20Card%20RevB/SC2-ELE-S581-101_RevB5_CC_Schematics.pdf Clock Card Rev. B]
| |
| − | * [http://www.phas.ubc.ca/~mce/mcedocs/hardware/schematics/Readout%20Card%20RevB/RO_S582_101BIss9_Schematic.pdf Readout Card Rev. B]
| |
| − | * [http://www.phas.ubc.ca/~mce/mcedocs/hardware/schematics/Readout%20Card%20RevD/RC_C582_101D0_Schematic.pdf Readout Card Rev. D]
| |
| − | * [http://www.phas.ubc.ca/~mce/mcedocs/hardware/schematics/Address%20Card%20RevC/AC_S584_101CIss4_Schematics.pdf Address Card Rev. C]
| |
| − | * [http://www.phas.ubc.ca/~mce/mcedocs/hardware/schematics/Bias%20Card%20RevE/BC_ELE_C583_101E0_Schematic.pdf Bias Card Rev. E]
| |
| | | | |
| − | == Clock Card Firmware ==
| + | mce_cmd -x rs cc {{param|cc|config_app}} |
| − | *Bug:
| |
| − | ** There is a problem with the Clock Card firmware. With the .tcl assignment '''# cmp add_assignment $top_name "" jtag_sel LOCATION "Pin_B19"''' and the pin driven by logic, the Clock Card firmware does not configure upon power up.
| |
| − | ** With the .tck assignments removed for jtag_sel and crc_error, the Clock Card reconfigures.
| |
| − | ** With the jtag_sel pin reassigned in the .tcl file, but driven by the assignment '''jtag_sel <= '0';''', the Clock Card reconfigures fine.
| |
| − | ** With the jtag_sel functionality re-instated, things seem to work fine.. What?? Did the problem have to do with crc_error?
| |
| | | | |
| | + | All these programmable parts, with the exception of the factory configuration device, are on a continuous JTAG chain that can be controlled via the MCE front-panel connector with an attached USB-Blaster, ''or'' via the Clock Card FPGA, provided it is running the right firmware, and is driven through the fibre interface. |
| | | | |
| − | * Rev. 5.0.3 FPGA Resource Usage (clk_card.fit.rpt):
| + | The factory configuration device, however, is not on the same JTAG chain. It is only accessible through an on-board JTAG connector and can only be programmed with a USB-Blaster attached and Quartus Programmer. |
| − | +--------------------------------------------------------------------------+
| |
| − | ; Fitter Summary ;
| |
| − | +--------------------------+-----------------------------------------------+
| |
| − | ; Fitter Status ; Successful - Mon Jan 25 20:10:18 2010 ;
| |
| − | ; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Full Version ;
| |
| − | ; Revision Name ; clk_card ;
| |
| − | ; Top-level Entity Name ; clk_card ;
| |
| − | ; Family ; Stratix ;
| |
| − | ; Device ; EP1S30F780C5 ;
| |
| − | ; Timing Models ; Final ;
| |
| − | ; Total logic elements ; 18,095 / 32,470 ( 56 % ) ;
| |
| − | ; Total pins ; 255 / 598 ( 43 % ) ;
| |
| − | ; Total virtual pins ; 0 ;
| |
| − | ; Total memory bits ; 949,760 / 3,317,184 ( 29 % ) ;
| |
| − | ; DSP block 9-bit elements ; 10 / 96 ( 10 % ) ;
| |
| − | ; Total PLLs ; 2 / 6 ( 33 % ) ;
| |
| − | ; Total DLLs ; 0 / 2 ( 0 % ) ;
| |
| − | +--------------------------+-----------------------------------------------+
| |
| | | | |
| − | == MAS Software ==
| + | In order to load temporary firmware, an sof file can be loaded into the FPGA. This firmware will be lost upon power cycle. To load permanent firmware, a pof file (or a jic file depending on EPC16 or EPCS64) can be loaded. |
| − | * MAS is now capable of sustained command rates of 3 kHz.
| |
| − | * The data block of a command packet can span words 6 trough 63. This is a total of 63 - 6 + 1 = 58 words per packet.
| |
| − | * Thus total sustained bandwidth of packet data with MAS is
| |
| − | MAS Bandwidth = [3000 packets/s] * [58 words/packet] * [32 bits/word] = 5.568 Mbps
| |
| − | * If this rate is faster than the timeout rate of the JTAG chain, it may be possible to program the MCE without first storing the programming files on the MCE.
| |
| − | * According to the [http://en.wikipedia.org/wiki/Joint_Test_Action_Group JTAG Wiki entry], "the operating frequency of TCK varies depending on all chips in the chain (lowest speed must be used), but it is typically 10-100 MHz (100-10 ns per bit)." This indicates that MAS' bandwidth is about half of the typical lowest speed for TCK.
| |
| − | * However, according to [http://www.altera.com/support/kdb/solutions/rd03112009_879.html this support posting], the nominal frequency of TCK from the USB Blaster is 6 MHz.
| |
| − | * There is probably no lower limit on the frequency of TCK, as the USB Blaster seems to operated at the lowest common frequency in the chain. However, the flash chip inside the configuration devices, or the JAM player may have timeout constraints.
| |
| | | | |
| − | == Altera Programming Software == | + | = Remote Update: step by step = |
| − | * [https://www.altera.com/support/software/download/programming/quartus2/dnl-quartus2_programmer.jsp Quartus II Programmer]. Program and verify Altera devices. Now includes SignalTap® II embedded logic analyzer viewer.
| + | This can be done in 3 steps: |
| − | * [https://www.altera.com/support/software/download/programming/asap2/dnl-asap2.jsp Altera Stand-Alone Programmer (ASAP2) (version 10.23)]. Program and verify Altera devices.
| + | # Scan JTAG chain |
| − | * [http://www.altera.com/support/software/drivers/dri-index.html Driver Installation Instructions]. Set up drivers for programming cables and hardware.
| + | # Generate JAM file |
| − | * [https://www.altera.com/support/software/download/programming/jam/jam-index.jsp Jam™ STAPL Programs]. Provides source code and utilities for Jam programming.
| + | # Update Firmware |
| − | * [https://www.altera.com/support/software/download/programming/jrunner/dnl-jrunner.html JRunner Software]. Provides source code for embedded JTAG programming.
| + | == Scan JTAG Chain == |
| − | * [https://www.altera.com/support/software/download/programming/srunner/dnl-srunner.html SRunner Software]. Provides source code for Serial Configuration Device programming.
| |
| − | * [https://www.altera.com/support/software/download/programming/microblaster/dnl-microblaster.html MicroBlaster™ Software]. Provides source code for embedded programming.
| |
| | | | |
| − | == Mandana's Remote Firmware Sandbox ==
| + | Run '''mce_auto_detect''': |
| − | This was handed off to Ernie in 2009:
| + | user@ubuntu:~$ mce_auto_detect |
| − | * http://www.phas.ubc.ca/~scuba2/sc2mce/system/sys_design/fpga_config
| + | mce_scan version 1 |
| | + | card_scan |
| | + | # card card_id card_type pcb_rev slot_id |
| | + | 2 0x124fb77 3 0 8 |
| | + | 3 0x19c74de 2 0 4 |
| | + | 4 0x1256aa5 2 0 5 |
| | + | 7 0x19c0a93 1 6 1 |
| | + | 8 0x19c3071 1 6 2 |
| | + | 9 0x19c1455 1 6 3 |
| | + | 10 0x19c6305 0 0 0 |
| | + | jtag_scan |
| | + | # id device |
| | + | 1 EPC4/EPC8/EPC16 |
| | + | 2 EP1S40 |
| | + | 3 EPC4/EPC8/EPC16 |
| | + | 4 EP1S40 |
| | + | 5 EPC4/EPC8/EPC16 |
| | + | 6 EP1S10 |
| | + | 7 EPC4/EPC8/EPC16 |
| | + | 8 EP1S10 |
| | + | 9 EPC4/EPC8/EPC16 |
| | + | 10 EP1S10 |
| | + | 11 EPC4/EPC8/EPC16 |
| | + | 12 EP1S10 |
| | + | 13 EPC4/EPC8/EPC16 |
| | | | |
| − | = Configuration Tests =
| + | Note that the order of devices are cc (#1), rc2 (device #2, #3), rc1(#4, #5), bc3 (#6, #7), bc2(#8, #9), bc1(#10, #11), ac(#12, #13). |
| | | | |
| | + | Device #1 refers to the Application configuration device on Clock Card. |
| | | | |
| − | == Programming File Formats Supported by Altera ==
| + | If there are no devices listed below "jtag_scan", you probably have to flip a jumper on your clock card. See the section below on [[ #Hardware Requirements ]]. |
| − | {| border="1"
| |
| − | |-
| |
| − | ! File Type !! Notes !! Created From !! Target Devices !! Quartus II 9.1 <br/> (no source) <br/> JTAG !! jp_25.exe <br/> (+ source) <br/> JTAG !! JRunner <br/> (+ source) <br/> embedded !! uProc <br/> (+ source) <br/> embedded !! MicroBlaster <br/> (+ source) <br/> embedded !! Quartus JLI <br/> (no source) <br/> JTAG !! jbi_22.exe <br/> (+ source) <br/> JTAG !! jp_25.exe <br/> (+ source) <br/> Fibre!
| |
| − | |-
| |
| − | | .sof || SRAM Object File <br/> (For FPGAs) || synthesis (automatic)
| |
| − | || FPGA
| |
| − | || Eth-B (3.0 Mb, 0.1 min)
| |
| − | || No
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| − | || No
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| − | || No
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| − | || No
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| − | || No
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| − | || No
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| − | || No
| |
| − | |-
| |
| − | | .pof || Programmer Object File <br/> (For FPP Flash devices or CPLDs) || synthesis, .sof
| |
| − | || EPC16 <br/> EPM3128
| |
| − | || Eth-B (2.1 Mb, 3 min) <br/> Eth-B (0.01 Mb, 1 min)
| |
| − | || No <br/> No
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| − | || No <br/> No
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| − | || No <br/> No
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| − | || No <br/> No
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| − | || No <br/> No
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| − | || No <br/> No
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| − | || No <br/> No
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| − | |-
| |
| − | | .jic || JTAG Indirect Configuration File <br/> (For Serial Flash devices) <br/> '''Must be generated by Quartus II 9.1+''' || .sof+SFL
| |
| − | || EPCS64
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| − | || Eth-B (8.2 Mb, 2 min)
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| − | || No
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| − | || No
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| − | || No
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| − | || No
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| − | || No
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| − | || No
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| − | || No
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| − | |-
| |
| − | | .jbc || Jam Byte-Code 2.0 File <br/> (Compiled Jam files) <br/> '''Must be generated by Quartus II 9.1+''' || synthesis, .sof +/.pof +/.jic, <br/> .jam (jam_24.exe)
| |
| − | || FPGA <br/> EPCS64 <br/> EPC16
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| − | || Eth-B (1.1 Mb, 0.7 min) <br/> Eth-B (2.7 Mb, 12 min) <br/> Eth-B (0.8 Mb, 6 min)
| |
| − | || No <br/> No <br/> No
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| − | || No <br/> No <br/> No
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| − | || JTAG <br/> JTAG <br/> JTAG
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| − | || No <br/> No <br/> No
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| − | || Byte-B (0.7 Mb, 1 min) <br/> Byte-B<br/> Byte-B (1.6 Mb, 6 min)
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| − | || Byte-B? <br/> Byte-B? <br/> Byte-B?
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| − | || No <br/> No <br/> No
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| − | |-
| |
| − | | .jam || Jam File (for JTAG) <br/> (JESD-71A specification) <br/> '''Must be generated by Quartus II 9.1+''' || synthesis, .sof +/.pof +/.jic
| |
| − | || FPGA <br/> EPCS64 <br/> EPC16
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| − | || Eth-B (1.5 Mb, 1 min) <br/> Eth-B (3.8 Mb, 12 min) <br/> Eth-B (2.2 Mb, 26 min)
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| − | || Byte-B (0.9 Mb, 1 min) <br/> Byte-B (3.8 Mb, 7 min)* <br/> Byte-B (2.2 Mb, 6 min)
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| − | || No <br/> No <br/> No
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| − | || JTAG <br/> JTAG <br/> JTAG
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| − | || No <br/> No <br/> No
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| − | || Byte-B (0.9 Mb, 1 min) <br/> Byte-B <br/> Byte-B (2.2 Mb, 7 min)
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| − | || No <br/> No <br/> No
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| − | || Fibre (1.2 Mb, 0.1 min) <br/> Fibre (3.8 Mb, 10.0 min) <br/> Fibre (2.7 Mb, 3.8 min)
| |
| − | |-
| |
| − | | .rbf || Raw Binary File || synthesis, .sof
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| − | || FPGA
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| − | || No
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| − | || No
| |
| − | || Yes* (+.cdf)
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| − | || PS,FPP,PPS,PPA
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| − | || FPP
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| − | || No
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| − | || No
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| − | || No
| |
| − | |-
| |
| − | | .hexout || Hexadecimal (Intel-Format) File || synthesis, .sof or .pof
| |
| − | || EPCS64 <br/> EPC16
| |
| − | || No <br/> No
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| − | || No <br/> No
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| − | || No <br/> No
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| − | || AS <br/> PS,FPP,PPS,PPA
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| − | || No <br/> No
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| − | || No <br/> No
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| − | || No <br/> No
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| − | || No <br/> No
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| − | |-
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| − | | .svf (obsolete) || Serial Vector File (for testing) || synthesis, .jic
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| − | || CPLD
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| − | || No
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| − | || No
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| − | || No
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| − | || ?
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| − | || No
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| − | || No
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| − | || No
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| − | || No
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| − | |-
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| − | | .rpd || Raw Programming Data File || .pof
| |
| − | || FPGA
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| − | || No
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| − | || No
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| − | || No
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| − | || AS
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| − | || No
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| − | || No
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| − | || No
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| − | || No
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| − | |-
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| − | | .ttf || Tabular Text Format || synthesis, .sof+uProc routines
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| − | || FPGA
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| − | || No
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| − | || No
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| − | || No
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| − | || PS,FPP,PPS,PPA
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| − | || No
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| − | || No
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| − | || No
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| − | || No
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| − | |-
| |
| − | | .ekp || Encryption Key Programming <br/> (For locking & encryption) || ??
| |
| − | || ?
| |
| − | || Yes
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| − | || No
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| − | || No
| |
| − | || ?
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| − | || No
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| − | || No
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| − | || No
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| − | || No
| |
| − | |-
| |
| − | | .isc || In System Configuration <br/> '''Must be generated by Quartus II 9.1+''' || .jic (Quartus), .svf (svf2isc)
| |
| − | || FPGA (not EP3SE50!) <br/> EPCS64? <br/> EPC16?
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| − | || No <br/> No <br/> No
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| − | || No <br/> No <br/> No
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| − | || No <br/> No <br/> No
| |
| − | || ? <br/> ? <br/> ?
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| − | || No <br/> No <br/> No
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| − | || No <br/> No <br/> No
| |
| − | || No <br/> No <br/> No
| |
| − | || No <br/> No <br/> No
| |
| − | |}
| |
| − | * Fibre test were conducted with cc_v05000004_26feb2010 tagged firmware. The jam files must not include the Clock Card FPGA because it drives the JTAG chain.
| |
| − | * The minimum time in which MAS can configure an EP1S30 if JTAG information is fully compressed into 58-word chunks over the fibre is:
| |
| − | min_time_ep1s30 = 69 min * [3 bits/write]/[58 words/write * 32 bits/word] = 0.11 min
| |
| − | * jam_25 released in 2004. jbi_22 released in 2001. jamstub.c and jbistub.c are very similar. The main difference are associated with changing function names from the "jam" prefix to the "jbi" prefix. Not much of the logic has changed, and where it has, it is easy to reconcile. Thus, if we need the capability to program .jbc files as well as .jam, we can almost certainly do this.
| |
| − | * When probing the TCK line during configuration, I notice that the Ethernet Blaster drives TCK in a two-state cycle (on-off-on-off..) but jp_25.exe drives TCK in a three-state cycle (on-off-off-on-off-off..)
| |
| − | * Configuration files that target AS configuration devices (i.e. EPCS64) must be generated by Quartus II 9.1+. Previous versions of Quartus generate files that don't work.
| |
| − | * uProc can be fed configuration data from configuration devices or some other storage device.
| |
| − | * Time and file-size figures above are for programming a single device in a full 9-card subrack. As much as possible, the largest file-size was used. For example, .sof files for readout card rev.D were used above, etc. Bear in mind that for programming all devices, file-sizes and times will be larger because there are:
| |
| − | ** 9 FPGA's
| |
| − | ** 10 EPC16's/ 4 EPCS16's
| |
| − | ** 1 CPLD
| |
| − | * Because serial configuration devices do not support the JTAG interface, the conventional method to program them is via the active serial (AS) programming interface. With the AS programming interface, the configuration data used to program serial configuration devices is downloaded via programming hardware.
| |
| − | * The Quartus "Convert Programming File" software cannot generate .rbf files for Active Serial devices.
| |
| − | * The Quartus Programmer cannot configure FPGAs/Configuration Devices with .rbf files. However, microprocessors can -- but I'm not sure if both FPGAs and Configuration Devices can accept these files.
| |
| − | * [http://e-mode.phas.ubc.ca/intmcewiki/index.php/Stratix_III_Development_Board#Test_12 Readout Card Programming Bug]: .jic files do not configure the Readout Cards correctly, unless the Clock Card is fully configured during a configuration process.
| |
| − | * .pof files are all the same size (no compression for flashing smaller FPGAs) therefore files generated from a .pof are also the same size as each other.
| |
| − | * .isc files cannot be generated for more than one programming file at a time (i.e. not a chain description, and does not contain programs for multiple devices), which implies that they consist of raw programming information that gets flashed directly into a single device.
| |
| − | * Devices that speak natively to the JTAG Chain are Altera Programmers (ByteBlaster, USB Blaster, Ethernet Blaster), with any of the following software: Quartus II, JAM player, JLI.
| |
| − | * .jam files describe an entire JTAG chain, but do not need configuration data for all/any of the devices in the chain. Thus, the Quartus "Creation" tool can generate .jam files from .sof and/or .pof and/or .jic files for any subset of devices in the chain. When generating a .jam file for a client, ensure that the topology of their chain is correctly specified in the programmer window that is generating the .jbc/.jam/.svf/.isc file -- otherwise it will not work at the client's site.
| |
| | | | |
| − | == Byte Blaster Commands == | + | == Generate Jam File == |
| − | * JRunner commanding:
| + | You need to update firmware on one device type at a time, i.e., EPC only, or FPGA only, or EPCS64 only. |
| − | > ?
| |
| | | | |
| − | * quartus_jli commanding:
| + | '''If you have access to internet:''' |
| − | // To see programming options
| + | # Go to MCE Firmware Canning Party webpage: http://e-mode.phas.ubc.ca/mcefcp/ |
| − | > C:\altera\91\quartus\bin>quartus_jli jli_scripts/x.jbc -i
| + | # copy and paste the result of mce_auto_detect on that webpage. |
| − |
| + | # Choose the target device(s) you want to program and a drop down menu of available firmware revisions will appear. |
| − | // To configure FPGA's
| + | # Choose the firmware revision and click generate (find out which is the appropriate firmware version here: https://e-mode.phas.ubc.ca/mcewiki/index.php/MCE_firmware and download the firmware from here: https://e-mode.phas.ubc.ca/mce/firmware/). |
| − | > C:\altera\91\quartus\bin>quartus_jli jli_scripts/x.jbc -a CONFIGURE
| + | # Save the generated file somewhere on your mas PC. |
| − | > C:\altera\91\quartus\bin>quartus_jli jli_scripts/x.jam -a CONFIGURE
| |
| − |
| |
| − | // To program EPC16's
| |
| − | > C:\altera\91\quartus\bin>quartus_jli jli_scripts/x.jbc -a PROGRAM
| |
| − | > C:\altera\91\quartus\bin>quartus_jli jli_scripts/x.jam -a PROGRAM
| |
| − |
| |
| − | // To program EPCS64's
| |
| − | .. unsupported.
| |
| | | | |
| − | * '''Sample Byte Blaster JTAG Commands From Ubuntu Command Line on MAS PC:'''
| + | '''If you do NOT have access to internet:''' |
| − | sudo ./jam -p0x378 -v -aprogram scripts/cc_pof_rca.jam // For Programming EPC16's
| + | # Install Quartus II Web Edition on Linux [[Quartus II Installation | See Instructions here]] |
| − | sudo ./jam -p0x378 -v -aconfigure scripts/cc_sof_rca.jam // For Configuring FPGA's
| + | # make a cdf file from the output of mce_auto_detect. Here is a sample cdf file [http://www.phas.ubc.ca/~mce/mcedocs/software/sample.cdf CDF] |
| − | sudo ./jam -p0x378 -v -aread_idcode read_idcode.jam // For Querying ID Codes
| + | # generate a jam file by typing: |
| − | sudo ./jam -p0x378 -v -aconfigure scripts/cc_rcd_jic.jam // For Programming EPCS64's (Step 1 of 2)
| + | quartus_cpf -c <cdf_file_name> <jamfilename> |
| − | sudo ./jam -p0x378 -v -aprogram scripts/cc_rcd_jic.jam // For Programming EPCS64's (Step 2 of 2)
| |
| | | | |
| − | == Byte Blaster Configuration Tests == | + | == Update Firmware== |
| − | * JAM Player commanding (Linux):
| |
| − | Parallel Port BIOS Settings: Output Only, 0x378, IRQ=7
| |
| − |
| |
| − | > mce@mce-ubc-1:/etc/mce$ ln -s v5/mce_v1.cfg mce.cfg
| |
| − |
| |
| − | // The latest version of code is here:
| |
| − | > cd /home/mce/jp_25/mce_jam/trunk
| |
| − |
| |
| − | // To compile:
| |
| − | > rm *.o
| |
| − | > rm *.exe
| |
| − | > make
| |
| − |
| |
| − | // To get ID codes via parallel port:
| |
| − | > sudo ./jam -p0x378 -v -aread_idcode read_idcode.jam
| |
| − |
| |
| − | // To get ID codes via serial port:
| |
| − | > sudo ./jam -u -v -aread_idcode read_idcode.jam
| |
| − |
| |
| − | // To get the CPU frequency:
| |
| − | > cat /proc/cpuinfo
| |
| − |
| |
| − | // To get command line options:
| |
| − | > sudo ./jam
| |
| − |
| |
| − | // For FPGAs:
| |
| − | > sudo ./jam -aconfigure scripts/cc_sof_rca.jam
| |
| − |
| |
| − | // For EPC16s:
| |
| − | > sudo ./jam -aprogram scripts/cc_pof_rca.jam
| |
| − |
| |
| − | // For EPCS64s (2 steps):
| |
| − | > sudo ./jam -p0x378 -v -aconfigure scripts/cc_rcd_jic.jam
| |
| − | > sudo ./jam -p0x378 -v -aprogram scripts/cc_rcd_jic.jam
| |
| | | | |
| − | * Conclusions:
| + | Run '''mce_fw_update''': |
| − | ** .jam file size is additive
| + | Usage: /usr/mce/mce_script/script/mce_fw_update <device> <jamfilename> |
| − | ** .jam file programming time is not additive
| + | device one of: |
| − | ** Parallel Port (jr_25.exe):
| + | FPGA: for temporary firmware (sof) |
| − | *** Max Frequency: 223 kHz
| + | EPC16: for permanent firmware on any card other than RC Rev. E (pof) |
| − | *** the nominal frequecy of the parallel port is 150 kBytes/s = 150 kbits/s*pin, but we get up to 223 kbits/s*pin. There is a linear regime below tck = 10000 where the change in tck is linear. Above this, it seems like other effects, like processing, CPU loading, and IRQ play a role in the speed of TCK.
| + | EPCS64: for permanent firmware on RC Rev. E (jic) |
| − | *** 1 sof => .jam, tck = 100 = 0.12kHz = XXs.png
| + | jamfilename either an absolute pathname, or a file in $MCE_JAM_DIR |
| − | *** 1 sof => .jam, tck = 1000 = 1.3kHz = XXs.png
| |
| − | *** 1 sof => .jam, tck = 10000 = 13kHz = 823s.png
| |
| − | *** 1 sof => .jam, tck = 100000 = 80kHz = 132s.png
| |
| − | *** 1 sof => .jam, tck = 1000000 = 200kHz = 55s.png
| |
| − | *** 1 sof => .jam, tck = 10000000 = 223kHz = 48s.png
| |
| − | *** 1 sof => .jam, tck = 100000000 = 223kHz = 51s.png
| |
| − | ** Ethernet Blaster
| |
| − | *** Max Frequency: 8348 kHz
| |
| − | ** USB Blaster
| |
| − | *** Max Frequency: 6000 kHz
| |
| | | | |
| − | * Quartus Programmer: full subrack .sof's and .pof's 4-RC subrack (CC + RC4 + RC3 + RC2 + RC1 [rev. D] + BC3 + BC2 + BC1 + AC).
| + | If you are programming FPGA parts (temporary firmware), this step takes seconds. However, it takes minutes to program permanent firmware into EPC16 or EPCS64 devices, e.g. '''13 minutes''' to program 2 rev F. Readout Cards. |
| − | Info: Started Programmer operation at Wed Jan 27 17:07:22 2010
| |
| − | Info: Configuring device index 2
| |
| − | Info: Device 2 contains JTAG ID code 0x020010DD
| |
| − | Info: Configuring device index 4
| |
| − | Info: Device 4 contains JTAG ID code 0x020010DD --EP1S10
| |
| − | Info: Configuring device index 6
| |
| − | Info: Device 6 contains JTAG ID code 0x020010DD --EP1S10
| |
| − | Info: Configuring device index 8
| |
| − | Info: Device 8 contains JTAG ID code 0x020010DD --EP1S10
| |
| − | Info: Configuring device index 9
| |
| − | Info: Device 9 contains JTAG ID code 0x021060DD --EP3SE50
| |
| − | Info: Configuring device index 11
| |
| − | Info: Device 11 contains JTAG ID code 0x020050DD --EP1S40
| |
| − | Info: Configuring device index 13
| |
| − | Info: Device 13 contains JTAG ID code 0x020050DD --EP1S40
| |
| − | Info: Configuring device index 15
| |
| − | Info: Device 15 contains JTAG ID code 0x020050DD --EP1S40
| |
| − | Info: Configuring device index 17
| |
| − | Info: Device 17 contains JTAG ID code 0x020040DD --EP1S30
| |
| − | Info: Device 1 contains JTAG ID code 0x0100A0DD --EPC4/EPC8/EPC16
| |
| − | Info: Device 3 contains JTAG ID code 0x0100A0DD --EPC4/EPC8/EPC16
| |
| − | Info: Device 5 contains JTAG ID code 0x0100A0DD --EPC4/EPC8/EPC16
| |
| − | Info: Device 7 contains JTAG ID code 0x0100A0DD --EPC4/EPC8/EPC16
| |
| − | Info: Device 10 contains JTAG ID code 0x0100A0DD --EPC4/EPC8/EPC16
| |
| − | Info: Device 12 contains JTAG ID code 0x0100A0DD --EPC4/EPC8/EPC16
| |
| − | Info: Device 14 contains JTAG ID code 0x0100A0DD --EPC4/EPC8/EPC16
| |
| − | Info: Device 16 contains JTAG ID code 0x0100A0DD --EPC4/EPC8/EPC16
| |
| − | Info: Device 1 silicon ID is 0xB0E9 --Sharp-Flash EPC16
| |
| − | Info: Device 3 silicon ID is 0xB0E9 --Sharp-Flash EPC16
| |
| − | Info: Device 5 silicon ID is 0x8991 --***Intel-Flash EPC16***
| |
| − | Info: Device 7 silicon ID is 0xB0E9 --Sharp-Flash EPC16
| |
| − | Info: Device 10 silicon ID is 0xB0E9 --Sharp-Flash EPC16
| |
| − | Info: Device 12 silicon ID is 0xB0E9 --Sharp-Flash EPC16
| |
| − | Info: Device 14 silicon ID is 0xB0E9 --Sharp-Flash EPC16
| |
| − | Info: Device 16 silicon ID is 0xB0E9 --Sharp-Flash EPC16
| |
| − | Info: Erasing EPC4/8/16 configuration device(s)
| |
| − | Info: Programming device(s)
| |
| | | | |
| − | * Quartus Programmer: 1x.jam file, full subrack .sof's and .pof's and .jic (CC + RC4 + RC3 + RC2 + RC1[revD] + BC3 + BC2 + BC1 + AC)
| + | If the programming fails, you might need to mess with the programming frequencies. These are passed to mce_jam via the -f flag, as frequencies in Hz. See the mce_fw_update script, and try decreasing the frequency by a factor of 10. |
| − | Info: Started Programmer operation at Fri Jan 29 12:43:16 2010
| |
| − | Info: Ended Programmer operation at Fri Jan 29 14:39:06 2010
| |
| − | Time = 1h 55m 50s
| |
| − | File size = 22,529 kb | |
| − | One device failed -> Configuration of RC Rev. D firmware with Serial Flash Loader.
| |
| | | | |
| − | * Quartus Programmer: 1x.jam generated from .sofs for AC/BC/BC/BC/RC[revD]/RC/RC/CC (full subrack)
| + | Note that when programming permanent firmware, the fw_rev will not immediately be updated. The new firmware will not be loaded until the card is power cycled. |
| − | Info: Started Programmer operation at Tue Feb 02 13:25:15 2010
| |
| − | Info: Ended Programmer operation at Tue Feb 02 13:27:22 2010
| |
| − | Time = 0h 2m 7s
| |
| − | File Size = 6.8 Mb | |
| | | | |
| − | * Quartus Programmer: 1x.jbc generated from .sofs for AC/BC/BC/BC/RC[revD]/RC/RC/CC (full subrack) | + | = Troubleshooting Remote Update = |
| − | Info: Started Programmer operation at Tue Feb 02 13:43:15 2010
| + | == Software Requirements == |
| − | Info: Ended Programmer operation at Tue Feb 02 13:45:22 2010
| + | Make sure the following are installed. |
| − | Time = 0h 2m 7s
| + | From the MAS repository: |
| − | File Size = 5.0 Mb
| + | * mce_jam : This will be installed under /usr/mce/bin/. |
| | + | From the MCE script repository (trunk): |
| | + | * read_idcode.jam : This should be in $MAS_TEMPLATE directory. |
| | + | * $MCE_JAM_DIR is set : This is set through mas_env.bash. |
| | + | * mce_auto_detect (in mce_script directory) |
| | + | * mce_fw_update (in mce_script directory) |
| | + | == Firmware Requirements == |
| | + | The Clock Card FPGA has to run firmware revision 5.0.7 or later. Considering that Clock Card FPGA can be loaded through either the Factory or Application configuration devices, at least one of these need to have 5.0.7+ firmware. If you are running Clock Card firmware prior to 5.0.7, which means your factory configuration device is loaded with firmware prior to 5.0.7, then attach USB-Blaster to the MCE front-panel connector. Run Quaruts Programmer, click on auto-detect, and program the second part from the bottom of the list, EPC16, with Clock Card firmware 5.0.7+.pof. |
| | | | |
| − | The following two test were done to demonstrate the differences in programming time when the frequency of TCK is modified, and to demonstrate that a TCK=1MHz is feasible.
| + | Then issue the following command: |
| − | * Ported JAM Player with BB (mce-ubc-1): 1x.jam generated from .pof for CC (CC + RC[revA])
| + | mce_cmd -x rs cc {{param|cc|config_app}} |
| − | mce@mce-ubc-1:~/jp_25/source$ sudo ./jam.exe -p0x378 -v -f1000 -aprogram scripts/cc_pof_rca.jam | + | to switch to the new firmware. (Read back the firmware revision to make sure the new firmware is now active.) |
| − | Jam STAPL Player Version 2.5 (20040526) | |
| − | >> calibrate_delay: one_ms_delay = 430500
| |
| − | >> jam_set_frequency: TCK frequency = 1000 kHz
| |
| − | >> initialize_jtag_hardware: Checking parallel port permissions..
| |
| − | >> initialize_jtag_hardware: Parallel port 0x378 is open.
| |
| − | Device #3 Silicon ID is 0xB0E9
| |
| − | erasing EPC4/8/16 device(s)...
| |
| − | programming EPC4/8/16 device(s)...
| |
| − | verifying EPC4/8/16 device(s)...
| |
| − | DONE
| |
| − | Exit code = 0... Success
| |
| − | Elapsed time = 09:41:11
| |
| | | | |
| − | * Ported JAM Player with BB (mce-ubc-1): 1x.jam generated from .pof for CC (CC + RC[revA])
| + | == Hardware Requirements == |
| − | mce@mce-ubc-1:~/jp_25/source$ sudo ./jam.exe -p0x378 -v -f10000 -aprogram scripts/cc_pof_rca.jam
| + | The buffer that controls whether the FPGA can drive the JTAG chain or not is controlled by BB_EN or SW1 dip switch setting on the Clock Card. Clock Cards shipped earlier than Dec. 2010, do not have the right settings. To check this setting on your Clock Card, turn off the MCE power and unplug the Clock Card. The SW1.P1 labeled as "BB_EN" DIP should be on OPEN position. |
| − | Jam STAPL Player Version 2.5 (20040526)
| |
| − | >> calibrate_delay: one_ms_delay = 358000
| |
| − | >> jam_set_frequency: TCK frequency = 10000 kHz
| |
| − | >> initialize_jtag_hardware: Checking parallel port permissions..
| |
| − | >> initialize_jtag_hardware: Parallel port 0x378 is open.
| |
| − | Device #3 Silicon ID is 0xB0E9
| |
| − | erasing EPC4/8/16 device(s)...
| |
| − | programming EPC4/8/16 device(s)...
| |
| − | verifying EPC4/8/16 device(s)...
| |
| − | DONE
| |
| − | Exit code = 0... Success
| |
| − | Elapsed time = 00:54:11
| |
| | | | |
| − | * Ported JAM Player with BB (mce-ubc-1): 1x.jam generated from .pof for CC (CC + RC[revA]) | + | * Note that with DIP switch SW1.P1 set to OPEN, you can not program the FPGA(sof) from the front panel connector (USB_Blaster) anymore. |
| − | mce@mce-ubc-1:~/jp_25/source$ sudo ./jam.exe -p0x378 -v -f100000 -aprogram scripts/cc_pof_rca.jam
| + | * With DIP switch set to OPEN, if CC firmware is pre-5.0.7, you can not access the JTAG chain from the front panel connector (USB_Blaster) anymore. Assuming you have 5.0.7+ in your configuration device, you need to issue: <code>mce_cmd -x rs cc config_app 1</code> to be able to access front-panel JTAG. |
| − | ------------------------------------------
| |
| − | Jam STAPL Player Version 2.5 (20040526)
| |
| − | Copyright (C) 1997-2004 Altera Corporation
| |
| − | ------------------------------------------
| |
| − | >> calibrate_delay: one_ms_delay = 374000
| |
| − | >> jam_set_frequency: TCK frequency = 100000 kHz
| |
| − | >> initialize_jtag_hardware: Checking parallel port 0x378 permissions..
| |
| − | >> initialize_jtag_hardware: Parallel port 0x378 is open.
| |
| − | Device #3 Silicon ID is 0xB0E9
| |
| − | erasing EPC4/8/16 device(s)...
| |
| − | programming EPC4/8/16 device(s)...
| |
| − | verifying EPC4/8/16 device(s)...
| |
| − | DONE
| |
| − | Exit code = 0... Success
| |
| − | Elapsed time = 00:11:22
| |
| − | >> close_jtag_hardware: Closing port 0x378..
| |
| − | >> close_jtag_hardware: Parallel port 0x378 is closed.
| |
| | | | |
| − | == Fibre Commands == | + | = Footnotes = |
| − | * Commands for the Programmer
| + | == Porting Remote Configuration Sofware to DAS == |
| − | sudo ./jam -u -v -f800000 -aprogram -dDO_VERIFY=0 cc_xfpga_rc_pof.jam // For Programming EPC16's
| + | The following C-code will need to be ported to DAS to enable Remote Configuration. You will need to convert the MCE WB and RB commands in the code to use DAS libraries and compile the code with the included Makefile: |
| − | sudo ./jam -u -v -f8000000 -aconfigure cc_xfpga_rc_sof.jam // For Configuring FPGA's
| + | *[http://www.phas.ubc.ca/~mce/mcedocs/software/mce_jam/ MCE Jam Player -- SVN revision 16 (~/jp_25/mce_jam/trunk)]. |
| − | sudo ./jam -u -v -f8000000 -aread_idcode read_idcode.jam // For Querying ID Codes
| + | ** '''jam_mce.c''': contains low-level MCE routines used during programming |
| − | sudo ./jam -u -v -f8000000 -aconfigure cc_rcd_jic.jam // For Programming EPCS64's (Step 1 of 2)
| + | ** all other files should be fine. |
| − | sudo ./jam -u -v -f100000 -aprogram -dDO_VERIFY=0 cc_rcd_jic.jam // For Programming EPCS64's (Step 2 of 2)
| |
| | | | |
| − | == Fibre Configuration Tests == | + | == Development Notes == |
| − | * Ported JAM Player over Fibre!!! (mce-ubc-1): 1x.jam generated from .sof for RC (CC + RC[revA]) | + | * [[intmce:Remote Firmware Update]] |
| − | mce@mce-ubc-1:~/jp_25/source$ sudo ./jam.exe -f10000000 -p0x100 -aconfigure scripts/cc_xfpga_rca_sof.jam -v
| |
| − | [sudo] password for mce:
| |
| − | ------------------------------------------
| |
| − | Jam STAPL Player Version 2.5 (20040526)
| |
| − | Copyright (C) 1997-2004 Altera Corporation
| |
| − | ------------------------------------------
| |
| − | >> calibrate_delay: one_ms_delay = 340200
| |
| − | >> jam_set_frequency: TCK frequency = 10000000 kHz
| |
| − | CRC matched: CRC value = 8436
| |
| − | Export: key = "JAM_STATEMENT_BUFFER_SIZE", value = 3088
| |
| − | NOTE "CREATOR" = "QUARTUS II JAM COMPOSER 9.1"
| |
| − | NOTE "DATE" = "2010/02/25"
| |
| − | NOTE "DEVICE" = "EPC16, EP1S30, EPC16"
| |
| − | NOTE "FILE" = "-, rc_ep1s30_v03000100_17jul2006.sof, -"
| |
| − | NOTE "TARGET" = "2"
| |
| − | NOTE "IDCODE" = "0100A0DD, 020040DD, 0100A0DD"
| |
| − | NOTE "USERCODE" = "-, FFFFFFFF, -"
| |
| − | NOTE "CHECKSUM" = "-, 01965C6C, -"
| |
| − | NOTE "SAVE_DATA" = "DEVICE_DATA"
| |
| − | NOTE "SAVE_DATA_VARIABLES" = "V0, A12, A13, A25, A42, A93, A43, A92, A94, A95, A105, A109, A111"
| |
| − | NOTE "STAPL_VERSION" = "JESD71"
| |
| − | NOTE "JAM_VERSION" = "2.0"
| |
| − | NOTE "ALG_VERSION" = "51"
| |
| − | >> rb cc fw_rev = 83886084 (0x5000004)
| |
| − | >> initialize_jtag_hardware: Checking parallel port 0x100 permissions..
| |
| − | >> initialize_jtag_hardware: Parallel port 0x100 is open.
| |
| − | >> initialize_jtag_hardware: JTAG chain enabled = 0x2.
| |
| − | Device #3 IDCODE is 0100A0DD
| |
| − | Device #2 IDCODE is 020040DD
| |
| − | Device #1 IDCODE is 0100A0DD
| |
| − | configuring SRAM device(s)...
| |
| − | DONE
| |
| − | Exit code = 0... Success
| |
| − | Elapsed time = 01:09:04
| |
| − | >> close_jtag_hardware: JTAG chain disabled = 0.
| |
| − | >> close_jtag_hardware: Closing port 0x100..
| |
| − | >> close_jtag_hardware: Parallel port 0x100 is closed.
| |
| | | | |
| − | * Quartus Programing and Verification = 12 minutes
| + | [[Category:Firmware]] |
| − | Info: Started Programmer operation at Tue Apr 13 13:00:22 2010
| + | [[Category:MAS]] |
| − | Info: Device 1 contains JTAG ID code 0x0100A0DD
| + | [[Category:MCE Script]] |
| − | Info: Device 1 silicon ID is 0xB0E9
| + | [[Category:Development Tools]] |
| − | Info: Erasing EPC4/8/16 configuration device(s)
| |
| − | Info: Programming device(s)
| |
| − | Info: Performing verification on device(s)
| |
| − | Info: Successfully performed operation(s)
| |
| − | Info: Ended Programmer operation at Tue Apr 13 13:12:07 2010
| |
| − | | |
| − | * SOF Programming (via Fibre)
| |
| − | ** TCK = 200 kHz: 1:08
| |
| − | ** TCK = 500 kHz: 0:31
| |
| − | ** TCK = 800 kHz: 0:22
| |
| − | ** TCK = 900 kHz: 0:20
| |
| − | ** TCK = 1000 kHz: 0:18
| |
| − | ** TCK = 5000 kHz: 0:08
| |
| − | | |
| − | * POF Programming (via Fibre)
| |
| − | ** TCK = 200 kHz: 4:35 (-dDO_VERIFY=0)
| |
| − | ** TCK = 500 kHz: 3:53 (-dDO_VERIFY=0)
| |
| − | ** TCK = 800 kHz: 4:02 (-dDO_VERIFY=0)
| |
| − | ** TCK = 900 kHz: FAIL
| |
| − | ** TCK = 1000 kHz: FAIL
| |
| − | ** TCK = 5000 kHz: FAIL
| |
| − | ------------------------------------------
| |
| − | >> close_mce(): compression statistics:
| |
| − | 1 bits: 47391 packets.
| |
| − | 8 bits: 1892 packets.
| |
| − | 46 bits: 42 packets.
| |
| − | 49 bits: 40 packets.
| |
| − | 50 bits: 3 packets.
| |
| − | 87 bits: 39 packets.
| |
| − | 88 bits: 1 packets.
| |
| − | 92 bits: 1 packets.
| |
| − | 199 bits: 1 packets.
| |
| − | 896 bits: 24384 packets.
| |
| − | ------------------------------------------
| |
| − | | |
| − | * POF Programming (via Fibre with verification)
| |
| − | ** TCK = 200 kHz: 1:30:35 (-dDO_VERIFY=1)
| |
| − | ------------------------------------------
| |
| − | >> close_mce(): compression statistics:
| |
| − | 1 bits: 14868399 packets.
| |
| − | 8 bits: 781989 packets.
| |
| − | 46 bits: 43 packets.
| |
| − | 49 bits: 40 packets.
| |
| − | 50 bits: 5 packets.
| |
| − | 87 bits: 39 packets.
| |
| − | 88 bits: 1 packets.
| |
| − | 92 bits: 1 packets.
| |
| − | 115 bits: 1 packets.
| |
| − | 120 bits: 1 packets.
| |
| − | 199 bits: 1 packets.
| |
| − | 896 bits: 24384 packets.
| |
| − | ------------------------------------------
| |
| − | | |
| − | == Timing Information ==
| |
| − | t<sub>pprog</sub> = t<sub>ppulse</sub> + Sigma(Cycle<sub>Ptck</sub> / f<sub>tck</sub>) of all devices
| |
| − | | |
| − | where t<sub>pprog</sub> = Programming time
| |
| − | t<sub>ppulse</sub> = Sum of the fixed times to rease, program and verify the EEPROM cells for ony the largest device
| |
| − | Cycle<sub>Ptck</sub> = Number of tck cycles to program each device
| |
| − | f<sub>tck</sub> = tck frequency
| |
| − | | |
| − | * There are a variety of timing parameters associated with the JTAG chain. One of the most important is the delay between the falling edge of TCK and the assertion of valid TDO data:
| |
| − | ** EP1S10/ 30/ 40 ([http://www.altera.com.cn/literature/an/an122.pdf AN122: Timing Information])
| |
| − | *** t<sub>JPZX</sub>: 25ns
| |
| − | *** t<sub>JPCO</sub>: 25ns
| |
| − | *** t<sub>JPXZ</sub>: 25ns
| |
| − | ** EP3Sxx ([http://www.altera.com/literature/hb/stx3/stratix3_handbook.pdf Stratix III Device Handbook, p.397])
| |
| − | *** t<sub>JPZX</sub>: unlisted
| |
| − | *** t<sub>JPCO</sub>: unlisted
| |
| − | *** t<sub>JPXZ</sub>: unlisted
| |
| − | ** EPC16 ([http://www.altera.co.jp/literature/hb/cfg/cfg_cf52001.pdf Enhanced Configuration Devices])
| |
| − | *** t<sub>JPZX</sub>: 25ns
| |
| − | *** t<sub>JPCO</sub>: 25ns
| |
| − | *** t<sub>JPXZ</sub>: 25ns
| |
| − | ** EPCS64
| |
| − | *** t<sub>JPZX</sub>: N/A
| |
| − | *** t<sub>JPCO</sub>: N/A
| |
| − | *** t<sub>JPXZ</sub>: N/A
| |
| − | | |
| − | == Investigations ==
| |
| − | * Changing the TCK frequency. What is the slowest frequency allowable? There is no documented minimum. Tests show that tck = 1000 = 1.3kHz works for read_idcode.jam, cc_pof_rca.jam, and cc_sof_rca.jam
| |
| − | * Generating .pof's with only the correct page programmed. Does this reduce configuration times?
| |
| − | * How fast do the Ethernet Blaster, and USB Blaster clock the TCK line? Ethernet Blaster = 8.3MHz (.sof, .pof, .jam) -- the timing differences between these files are associated gaps of differing sizes between the JTAG data packets. USB Blaster = 5.0MHz.
| |
| − | * Does loading the CPU with a loop with "while /bin/true; do /bin/true; done" affect the programming time? Yes, it extended the execution time of the following command from 55s to 63s:
| |
| − | sudo ./jam.exe -p0x378 -v -f1000000 -aconfigure scripts/cc_sof_rca.jam
| |
| − | * What is the maximum TCK frequency that we can achieve over the parallel port?
| |
| − | * Is there a JAM spec for our devices? See the timing section above.
| |
| − | * What is the minimum/ maximum delay between a falling edge of TCK and when TDO can be sampled? According to numbers quoted above, the minimum delay is 25ns for some devices. However, hardware tests show that a delay of 1 cycle (20ns) works. A delay of 0 cycles (0ns) does not work, and neither does a delay of 100000 cycles (2ms).
| |
| − | wb cc tdo_sample_dly 1 //1 cycle = 20ns
| |
| − | | |
| − | = Possible Solutions =
| |
| − | == Option 1a: Ethernet Blaster ==
| |
| − | Ethernet Blaster hooked up permanently to each MCE.
| |
| − | | |
| − | * Pros:
| |
| − | ** Off-the-shelf solution
| |
| − | ** Standard Ethernet interface to each Blaster
| |
| − | ** Can configure all devices (FPGA/CPLD/EPC16/EPCS64) with a wide range of file types (.sof/.pof/.jic/.jbc/.jam)
| |
| − | ** DAS/MAS software independent.
| |
| − | | |
| − | * Cons:
| |
| − | ** Requires an Ethernet connection for every MCE
| |
| − | ** Ethernet Blasters are not in production anymore. Requires building our own.
| |
| − | ** Electrical connections to MCE's can cause ground loops.
| |
| − | | |
| − | * To investigate:
| |
| − | ** Is Altera planning to release a new version of the Ethernet Blaster?
| |
| − | | |
| − | == Option 1b: USB Blaster ==
| |
| − | USB Blaster hooked up permanently to each MCE.
| |
| − | | |
| − | * Pros:
| |
| − | ** Off-the-shelf solution
| |
| − | ** Standard USB interface to each Blaster.
| |
| − | ** Can configure all devices (FPGA/CPLD/EPC16/EPCS64) with a wide range of file types (.sof/.pof/.jic/.jbc/.jam)
| |
| − | ** USB Blasters are widely available.
| |
| − | ** Multiple USB connections are easily made with USB replicators
| |
| − | ** DAS/MAS software independent.
| |
| − | | |
| − | * Cons:
| |
| − | ** Requires a PC nearby that runs Windows or Linux for Altera's Standalone programmer.
| |
| − | ** Electrical connections to MCE's can cause ground loops.
| |
| − | | |
| − | * To investigate:
| |
| − | ** Are there optically isolated USB replicators available?
| |
| − | ** How close are PC's to MCE's at all times that reconfiguration is required?
| |
| − | | |
| − | == Option 1c: Custom 'UBC' Blaster ==
| |
| − | Custom hardware that acts as a USB Blaster and is optically isolated from the MCE.
| |
| − | | |
| − | * Pros:
| |
| − | ** Customizable computer interface to each Blaster (probably USB).
| |
| − | ** Can configure all devices (FPGA/CPLD/EPC16/EPCS64) with a wide range of file types (.sof/.pof/.jic/.jbc/.jam)
| |
| − | ** UBC controls the IP, therefore these devices can be produced and supported indefinitely.
| |
| − | ** Multiple USB connections are easily made with USB replicators
| |
| − | ** Can be designed so that it is maintains the MCE's electrical isolation.
| |
| − | ** DAS/MAS software independent.
| |
| − | | |
| − | * Cons:
| |
| − | ** Requires hardware development.
| |
| − | ** Requires a PC nearby that runs Windows or Linux for Altera's Standalone programmer.
| |
| − | | |
| − | * To investigate:
| |
| − | ** Are there optically isolated USB replicators available? If so, they would make this a worse solution than USB Blasters.
| |
| − | ** How close are PC's to MCE's at all times that reconfiguration is required?
| |
| − | | |
| − | == Option 2: JRunner on CC ==
| |
| − | NIOS processor on the Clock Card that runs ported JRunner code and configures devices via JTAG interface. Requires loading a .cdf (chain description file), and a .rbf (raw binary file).
| |
| − | | |
| − | * Pros:
| |
| − | ** Uses existing fiber-optic connections to the MCE's.
| |
| − | ** MCE's remain electrically isolated.
| |
| − | ** Implementation is purely firmware/ software, thus no hardware design & support issues.
| |
| − | ** No supply issues, because there is no reliance on third-party hardware.
| |
| − | ** Does not require additional peripheral hardware in the form of Blasters or PCs.
| |
| − | ** JRunner code is open-source, ANSI C.
| |
| − | ** DAS/MAS software independent.
| |
| − | | |
| − | * Cons:
| |
| − | ** Requires porting existing JRunner code for use in NIOS processor.
| |
| − | ** JRunner code will require significant Clock Card resources, and may not fit in the existing firmware design. In this case, specialized firmware would be implemented as a 'Factory' configuration, which we would switch over to for configuring other devices.
| |
| − | ** Can only configure from JRunner with .cdf+.rbf file formats, so new file formats must be created for this configuration method.
| |
| − | ** Can only configure FPGA's (SRAM devices) with .rbf files. The Quartus "Convert Programming File" software cannot generate .rbf files for EPC16's or EPCS64's.
| |
| − | | |
| − | * To investigate:
| |
| − | ** Check the FPGA resources available on the Clock Card, and compare to estimated resource requirements.
| |
| − | ** How developed are Altera's resources for NIOS implementation?
| |
| − | ** What file formats can be converted to .rbf? This has implications on what devices can be configured via this method.
| |
| − | ** Long configuration times
| |
| − | | |
| − | Links:
| |
| − | * JRunner Source: http://www.altera.com/literature/an/an414.pdf
| |
| − | | |
| − | == Option 3: MicroBlaster on All FPGAs ==
| |
| − | A NIOS processor on every card that runs ported MicroBlaster code and configures devices via FPP interfaces. Requires .rbf files.
| |
| − | * Pros:
| |
| − | ** Uses existing fiber-optic connections to the MCE's.
| |
| − | ** MCE's remain electrically isolated.
| |
| − | ** Implementation is purely firmware/ software, thus no hardware design & support issues.
| |
| − | ** No supply issues, because there is no reliance on third-party hardware.
| |
| − | ** Does not require additional peripheral hardware in the form of Blasters or PCs.
| |
| − | ** MicroBlaster code is open-source, ANSI C.
| |
| − | ** DAS/MAS software independent.
| |
| − | ** Does not require .cdf file
| |
| − | | |
| − | * Cons:
| |
| − | ** Requires porting existing MicroBlaster code for use in NIOS processor. If it is simple, perhaps a NIOS processor is not necessary?
| |
| − | ** MicroBlaster code may require significant resources, and may not fit in existing firmware designs. Factory configuration is only available on the Clock Card.
| |
| − | ** Can only configure from MicroBlaster with .rbf file format, so new file formats must be created for this configuration method.
| |
| − | ** The Quartus "Convert Programming File" software cannot generate .rbf files for Active Serial devices, i.e. Readout Card Rev. D.
| |
| − | ** This method can only configure devices via the FPP interface, which may not be connected.
| |
| − | ** FPP configuration only allows the reconfiguration of FPP flash devices (i.e. EPC16's -- but not FPGA's or EPCS64's)
| |
| − | ** Long configuration times
| |
| − | | |
| − | * To investigate:
| |
| − | ** Check the FPGA resources available on all cards, and compare to estimated resource requirements.
| |
| − | ** How developed are Altera's resources for NIOS implementation?
| |
| − | ** What file formats can be converted to .rbf? This has implications on what devices can be configured via this method.
| |
| − | ** Are the FPP interfaces connected on very card?
| |
| − | | |
| − | == Option 4: JRunner in MAS ==
| |
| − | Embed JRunner software in MAS, and implement a simple switch in Clock Card firmware for piping configuration data into the JTAG interface.
| |
| − | * Pros:
| |
| − | ** Uses existing fiber-optic connections to the MCE's.
| |
| − | ** MCE's remain electrically isolated.
| |
| − | ** Implementation is purely firmware/ software, thus no hardware design & support issues.
| |
| − | ** No supply issues, because there is no reliance on third-party hardware.
| |
| − | ** Does not require additional peripheral hardware in the form of Blasters or PCs.
| |
| − | ** JRunner code is open-source, ANSI C.
| |
| − | ** Does not tax existing FPGA resources with either a NIOS processor or code storage.
| |
| − | | |
| − | * Cons:
| |
| − | ** Requires porting existing JRunner code for use in MAS.
| |
| − | ** Can only configure from JRunner with .cdf+.rbf file format, so new file formats must be created for this configuration method.
| |
| − | ** Can only configure FPGA's (SRAM devices) with .rbf files. The Quartus "Convert Programming File" software cannot generate .rbf files for EPC16's or EPCS64's.
| |
| − | ** DAS/MAS software '''dependent.''' Requires additional features to both.
| |
| − | ** Long configuration times
| |
| − | | |
| − | * To investigate:
| |
| − | ** What file formats can be converted to .rbf? This has implications on what devices can be configured via this method.
| |
| − | ** Do we want to move SCUBA-2 over to MAS? If not, will Gao implement the features that are required in DAS?
| |
| − | ** Does the current fiber bandwidth allow this method?
| |
| − | ** What is the back-end interface that must convert from the output of the JRunner to fiber to JTAG?
| |
| − | | |
| − | == Option 5: Jam STAPL Player in MAS ==
| |
| − | * Pros:
| |
| − | ** Uses existing fiber-optic connections to the MCE's.
| |
| − | ** MCE's remain electrically isolated.
| |
| − | ** Implementation is purely firmware/ software, thus no hardware design & support issues.
| |
| − | ** No supply issues, because there is no reliance on third-party hardware.
| |
| − | ** Does not require additional peripheral hardware in the form of Blasters or PCs.
| |
| − | ** Jam Player code is open-source, ANSI C.
| |
| − | ** Does not tax existing FPGA resources with either a NIOS processor or code storage.
| |
| − | ** Can configure all devices: FPGA's/ EPC16's/ EPCS64's.
| |
| − | | |
| − | * Cons:
| |
| − | ** Requires porting existing Jam Player code for use in MAS.
| |
| − | ** Can only configure using .jam or .jbc file formats, so new file formats must be created for this configuration method.
| |
| − | ** DAS/MAS software '''dependent.''' Requires additional features to both.
| |
| − | ** Long configuration times
| |
| − | | |
| − | * To investigate:
| |
| − | ** Do we want to move SCUBA-2 over to MAS? If not, will Gao implement the features that are required in DAS?
| |
| − | ** Does the current fiber bandwidth allow this method?
| |
| − | ** What is the back-end interface that must convert from the output of the Jam Player to fiber to JTAG?
| |
| − | | |
| − | = Altera Documentation =
| |
| − | * [http://www.xilinx.com/products/design_resources/config_sol/isp_standards_specs.htm#1149.1 Xilinx Spec].
| |
| − | * AN039: [http://www.altera.com/literature/an/an039.pdf IEEE 1149.1 (JTAG) Boundary-Scan Testing in Altera Devices]
| |
| − | | |
| − | * AN425: [http://www.altera.com/literature/an/AN425.pdf JAM-P vs JLI]
| |
| − | | |
| − | * [http://www.altera.com/support/kdb/solutions/rd06092003_387.html SVF file information]
| |
| − | | |
| − | * Altera recommends using Jam STAPL Byte-Code files in embedded applications because they use minimal memory
| |
| − | | |
| − | * The Jam STAPL Player is an interpreter program that reads and executes a STAPL file. A single STAPL file can perform several functions, such as programming, configuring, verifying, erasing, and blank-checking a programmable device. The Jam STAPL Player has access to the IEEE 1149.1 signals that are used for all instructions based on the IEEE 1149.1 interface. In addition, the Jam STAPL Player is capable of processing the user-specified actions and procedures in a STAPL file.
| |
| − | | |
| − | * The quartus_jli command-line executable has the same functionality as the Jam STAPL Player plus two additional capabilities. It provides command-line control of the Quartus II software from the UNIX or DOS prompt and supports all programming hardware available in the Quartus II software version 6.0 or later.
| |
| − | | |
| − | * AN122: [http://www.altera.com.cn/literature/an/an122.pdf Using Jam STAPL for ISP & ICR via an Embedded Processor] (Altera JTAG Device Timing Parameters: starting p.15)
| |
| − | | |
| − | * [http://groups.google.com/group/alt.sources/browse_thread/thread/8761df1865c088f4 JAM Player Ported to USB]
| |
| − | | |
| − | * [http://www.altera.com/products/devices/stratix-fpgas/stratix/stratix/features/stx-remote_config.html Remote System Upgrades with Stratix Series FPGAs].
| |
| − | | |
| − | * [http://www.altera.com/literature/hb/cfg/config_handbook.pdf Configuration Handbook].
| |
| − | ** [http://www.altera.com/literature/hb/cfg/cfg_cf52007.pdf?GSA_pos=5&WT.oss_r=1&WT.oss=rbf%20configure Configuration File Formats].
| |
| − | ** [http://quartushelp.altera.com/9.1/mergedProjects/program/pgm/pgm_view_convert.htm File Format Help]. (F1)
| |
| − | | |
| − | * [http://www1.cs.columbia.edu/~sedwards/classes/2007/4840/lab3.pdf NIOS Lab Tutorial]
| |
| − | | |
| − | * [http://www.altera.com/literature/wp/wp_epc_flash.pdf The change from Sharp to Intel flash in EPC16 devices].
| |
| − | ** "This white paper documents the differences between the Micron or Sharp flash memory against the Intel flash memory. This document helps designers to perform the migration from current Micron-based EPC4 device or Sharp-based EPC8 and EPC16 devices to the new Intel flash memory-based EPC4, EPC8, and EPC16 devices."
| |
| − | | |
| − | * AN370: [http://www.altera.com/literature/an/an370.pdf AN 370: Using the Serial FlashLoader with the Quartus II Software]
| |
| − | ** In version 9.0 and onwards of the Quartus II software, the enhanced mode of the SFL solution is introduced. This allows faster EPCS programming time with the following advantages:
| |
| − | ** Enhanced SFL solution correctly interprets extra padding bits introduced by third programmer tool to ensure successful EPCS programming with SFL solution.
| |
| − | ** Enhanced SFL allows conversion from JTAG Indirect Configuration (.jic) to Jam™ STAPL (.jam), JAM Byte-Code File (.jbc) or Serial Vector Format File (.svf) for multiple devices in JTAG chain in which only one device uses the SFL solution.
| |
| − | ** Enhanced SFL allows conversion from .jic to .jam, .jbc, or .svf file for multiple devices in JTAG chain in which two or more devices uses the SFL solution.
| |
| − | | |
| − | * [http://www.altera.com/literature/hb/max2/max2_mii51015.pdf Using Jam STAPL for ISP via an Embedded Processor]
| |
| − | * [http://www.altera.com/support/kdb/solutions/rd06092003_387.html Differences between the SVF and Jam® /STAPL players and interpreters].
| |
| − | ** STAPL (Standard Test and Programming Language) is a high level language designed specifically for CPLD ISP programming. STAPL is the JEDEC standardized version of the original Jam Language created by Altera. Jam/STAPL supports branching - which means faster programming times.
| |
| − | | |
| − | * Serial Configuration Devices: There is a megafunction in the Altera Megawizard Library called altremote_update. This megafunction allows the reconfiguration of a device.
| |
| − | ** Design example: http://www.altera.com/support/examples/quartus/alt_remote_update.html
| |
| − | ** User's guide: http://www.altera.com/literature/ug/ug_altremote.pdf
| |
| − | ** User's guide index: http://www.altera.com/literature/lit-ug.jsp?GSA_pos=1&WT.oss_r=1&WT.oss=user%27s%20guide
| |
| − | ** Stratix I handbook: http://www.altera.com/literature/hb/stx/ch_15_vol_2.pdf
| |
| − | ** Stratix III handbook: http://www.altera.com/literature/hb/stx3/stx3_siii51012.pdf
| |
| − | ** EPC datasheet: http://www.altera.com/literature/hb/cfg/cfg_cf52001.pdf
| |
