Difference between revisions of "Bias Card"
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* Technical description [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/tech_description/SC2_ELE_S583_501_bias_card_description.pdf PDF]] (obsolete) | * Technical description [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/tech_description/SC2_ELE_S583_501_bias_card_description.pdf PDF]] (obsolete) | ||
| − | + | == Other documentation == | |
* [[Bias Card firmware]] | * [[Bias Card firmware]] | ||
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* [[Bias Card RevD to RevF changes]] | * [[Bias Card RevD to RevF changes]] | ||
* [[Bias Card Rev F2 to Rev F4 changes]] (lowering 1/f noise on signle-ended bias lines) | * [[Bias Card Rev F2 to Rev F4 changes]] (lowering 1/f noise on signle-ended bias lines) | ||
| + | * [[Testing Bias Cards]] | ||
== Schematics == | == Schematics == | ||
Revision as of 14:36, 13 December 2012
Functional Description
Every bias card (BC) in the MCE can provide 32 programmable single-ended voltages and a small number of other differential bias voltages. What these voltages are used for is determined by which slot of the MCE the Bias Card has been inserted into. The signal routing and load resistors which determine the function and current are located on the Instrument Bus (IB) backplane. In SCUBA2, three BCs are required per 32x41 pixel sub-array, which is a quadrant of the full single passband array. The main part of the digital control logic is encapsulated in a 780-pin Altera EP1S10 Stratix FPGA.
Each output is generated by a serial-input, voltage-output, 16-bit DAC (Max5443) with a high-stability (1 ppm/C), low-noise, +2.5 V voltage reference. Upon reset or power up, all the DACs are set to 0.
- Technical description [PDF] (obsolete)
Other documentation
- Bias Card firmware
- Noise Analysis of LN_BIAS lines in Bias Card
- Noise Calculations
- Bias Card RevD to RevE changes
- Bias Card RevD to RevF changes
- Bias Card Rev F2 to Rev F4 changes (lowering 1/f noise on signle-ended bias lines)
- Testing Bias Cards
Schematics
- Block diagram [PDF] (obsolete)
- Rev.D6 schematic [PDF] (Original design)
- Rev.D7/8 schematic [PDF] (High-current det_bias)
- Rev.D11 schematic [PDF] (High-current det_bias/no heater)
- Rev.E0 schematic [PDF] (Multiple det_bias lines)
- Rev.F0 schematic [PDF] (Multi det_bias & MHz-response bias lines; Low-noise bias lines turned off)
- Rev.F1 schematic [PDF] (Power turned off on ln_bias)
- Rev.F2 schematic [PDF] (Minor change in ln_bias circuit)
- Rev.F3 schematic [PDF] (low 1/f-noise opamp for channel 0-15)
- Rev.F4 schematic [PDF] (low 1/f-noise opamp for channel 15-31)
