2-slot Backplane
A 2-slot backplane is designed to accomodate a Clock Card and a test card and is used to test MCE cards. The test card slot can mate with an Address Card, Readout Card or Bias Card. When the Clock Card and test card are “plugged in” to the two slot board, one can orient the apparatus to make all necessary measurements.See Schematics here
Power Connections
Here is the pinout for P14 Power Connector on 2-slot Backplane:
| Signal | Voltage | P14.Pin |
|---|---|---|
| -Va | -6.2V | 1, 4 |
| DGND | 2, 5, 8 | |
| +Vah | +10V | 3 |
| Vlvd | +4.5V | 6 |
| +Va | +6.2V | 7, 10 |
| Vcore | +3V | 9 |
| AGND | 11, 12 |
Switches and Buttons
- Clock-Card ID (SW1)
- set the Clock Card ID , should be set to 0111
- Test-Card ID (SW3)
- set the Test card ID
- The ID for AC, BC1, BC2, BC3, RC1, RC2, RC3, RC4 is 0xF, oxE, 0xD, 0xC, 0xB, 0xA, 0x9, 0x8, respectively.
- In order for the Test Card to communicate with the Clock Card and hence be controlled through the fibre, this switch needs to be set properly.
- Array ID (SW2)
- is used to set the array ID. For the array ID a 6 pin header gives access to the array ID, digital ground and +5V. SW3 or Card ID Switch is used to set the test card ID. For all switches, when the switch is closed the line will be a “low”.
- Reset button (SW4)
- A BRST threshold potentiometer provides easy level setting of the BRST signal.
Headers
P13 is an extra header which allows access to the CMD, TX Spare, SYNC and CLK LVDS lines. This header minimizes the trace distance from the test card. For example, if you make a measurement on P13, this measurement should reflect the actual signal in the test card. A Mictor header (P3) is supplied which allows access to JTAG, spare TTL, power supply, converted LVDS and array signal lines. Headers P9, P11, P12, P18 and P4 will give you access to the same signals as the Mictor header respectively. P6 and P7 provide access to the analog lines of the test card. Each analog line has its own return line.
Please note: On the PCB, the silkscreen for analog rows B and D (on P7) have been switched. Row B is actually row D and row D is actually row B.
1 to 10 LVDS Signal Distributor
The two slot board contains two 1 to 10 LVDS signal distributors. These distributors take LVDS signals from the test card (P3) and distribute more LVDS lines to the Clock Card. This was done so testing the integrity of the LVDS lines can be performed.
When the operational firmware is loaded, commands received by clock card through the fiber interface are distributed to the test card over the CMD line. In an MCE subrack, the CMD line is a multi drop line, but each card has its dedicated LVDS line to send replies back to the clock card. The LVDS signal distributor on the 2-slot backplane tries to immitate this functionality. In order for Clock Card to receive the replies properly, SW1 and SW3 have to be set properly.
