MCE Sync Buffer
“MCE Sync Buffer” (MSB) is a daughter-board for TS7800 single-board computer designed for asynchronous reading of SyncBox status sequence.
It has RS-485 receiver for accepting data from a SyncBox and a parallel interface for communicating with TS7800 DIO.
MSB may be in 2 states “Busy” and “Not Busy” which is determined by a flip-flop (U6A, U6B).
When it's in “Not Busy” state and TS7800 (PC) enables communication with SyncBox (pc_enable=1) data signal transition received by U1 would trigger flip-flop to a “Busy” state. In this stated data will go to cascaded shift-registers (U7-U14) until 64th bit is received (note that pc_clock = 1 is assumed for normal operation). On receiving the 64th bit a counter (U5) will issue “overflow” (RCO) signal that would trigger flip-flop to “Not Busy” state. This would also stop shift-registers clocking (with help of U2C) and reset the counter (S0 = busy). As a result the shift registers would contain 64 bit of data received from a SyncBox (until next transition in data).
After that, PC can block MSB input (pc_enable = 0) and clock-in the data from shift-registers with pc_clock. Data is accessed by 8-bit slices so it take 7 clock circles to get it into PC.
Note that TS7800 DIOs have 3.3V logic. Therefore some voltage dividers were added to the design. To minimize number of the dividers the shift registers will also have 3.3V power.
Thus basic PC algorithm can be as follows. (initial state: pc_enable = 1; pc_clock = 1)
- PC watches busy_PC signal, and waits for high-to-low transition;
- PC blocks MSB inputs ( pc_enable = 0) and goes to data-reading loop (accessing DIO 0..7 and clocking pc_clock)
- PC enables MSB inputs ( pc_enable = 1) and waits till next data sequence.
