Difference between revisions of "Address Card firmware"

From MCEWiki
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= Firmware Revision Listing =
 
= Firmware Revision Listing =
 +
== Revision 5.0.1 ==
 +
* '''Filename:'''  ac_v05000001_14sep2009.sof
 +
 +
* '''To Do:'''
 +
** ---
 +
 +
* '''Features:'''
 +
** IMPORTANT:  Must be used in conjunction with firmware v05000000+ of all other cards.
 +
** To increase data bandwidth, the spare LVDS line from each card to the Clock Card is now used
 +
 +
* '''Details:'''
 +
** ---
 +
 +
* '''Bugs:'''
 +
** None yet reported
 +
 +
* '''FPGA Resource Usage''' (clk_card.fit.rpt):
 +
 +
* '''Timing Analyzer Summary''' (clk_card.tan.rpt):
 +
 
== Revision 5.0.0 ==
 
== Revision 5.0.0 ==
 
* '''Filename:'''  ac_v05000000_22dec2008.sof
 
* '''Filename:'''  ac_v05000000_22dec2008.sof
Line 54: Line 74:
 
  ; Total number of failed paths                            ;          ;
 
  ; Total number of failed paths                            ;          ;
 
  +----------------------------------------------------------+----------+
 
  +----------------------------------------------------------+----------+
 +
 +
== Revision 2.0.8 ==
 +
* '''Filename:'''  ac_v02000008_xxsep2009.sof
 +
 +
* '''To Do:'''
 +
** ---
 +
 +
* '''Features:'''
 +
** --
 +
 +
* '''Details:'''
 +
** ---
 +
 +
* '''Bugs:'''
 +
** None yet reported
 +
 +
* '''FPGA Resource Usage''' (clk_card.fit.rpt):
 +
 +
* '''Timing Analyzer Summary''' (clk_card.tan.rpt):
 +
  
 
== Revision 2.0.7 ==
 
== Revision 2.0.7 ==

Revision as of 14:42, 14 September 2009

Recommended Firmware Revisions

Firmware Revision Listing

Revision 5.0.1

  • Filename: ac_v05000001_14sep2009.sof
  • To Do:
    • ---
  • Features:
    • IMPORTANT: Must be used in conjunction with firmware v05000000+ of all other cards.
    • To increase data bandwidth, the spare LVDS line from each card to the Clock Card is now used
  • Details:
    • ---
  • Bugs:
    • None yet reported
  • FPGA Resource Usage (clk_card.fit.rpt):
  • Timing Analyzer Summary (clk_card.tan.rpt):

Revision 5.0.0

  • Filename: ac_v05000000_22dec2008.sof
  • To Do:
    • ---
  • Features:
    • IMPORTANT: Must be used in conjunction with firmware v05000000 of all other cards!!!
    • To increase data bandwidth, the spare LVDS line from each card to the Clock Card is now used
  • Details:
    • ---
  • Bugs:
    • None yet reported
  • FPGA Resource Usage (clk_card.fit.rpt):
+---------------------------------------------------------------------+
; Fitter Summary                                                      ;
+--------------------------+------------------------------------------+
; Fitter Status            ; Successful - Tue Jan 13 16:19:16 2009    ;
; Quartus II Version       ; 8.1 Build 163 10/28/2008 SJ Full Version ;
; Revision Name            ; addr_card                                ;
; Top-level Entity Name    ; addr_card                                ;
; Family                   ; Stratix                                  ;
; Device                   ; EP1S10F780C5                             ;
; Timing Models            ; Final                                    ;
; Total logic elements     ; 9,383 / 10,570 ( 89 % )                  ;
; Total pins               ; 279 / 427 ( 65 % )                       ;
; Total virtual pins       ; 0                                        ;
; Total memory bits        ; 196,096 / 920,448 ( 21 % )               ;
; DSP block 9-bit elements ; 8 / 48 ( 17 % )                          ;
; Total PLLs               ; 1 / 6 ( 17 % )                           ;
; Total DLLs               ; 0 / 2 ( 0 % )                            ;
+--------------------------+------------------------------------------+
  • Timing Analyzer Summary (clk_card.tan.rpt):
+----------------------------------------------------------------------
; Timing Analyzer Summary                                              
+----------------------------------------------------------+----------+
; Type                                                     ; Slack    ;
+----------------------------------------------------------+----------+
; Worst-case tsu                                           ; N/A      ;
; Worst-case tco                                           ; N/A      ;
; Worst-case th                                            ; N/A      ;
; Clock Setup: 'ac_pll:pll0|altpll:altpll_component|_clk0' ; 2.617 ns ;
; Clock Setup: 'ac_pll:pll0|altpll:altpll_component|_clk2' ; 4.588 ns ;
; Clock Hold: 'ac_pll:pll0|altpll:altpll_component|_clk0'  ; 0.539 ns ;
; Clock Hold: 'ac_pll:pll0|altpll:altpll_component|_clk2'  ; 0.658 ns ;
; Total number of failed paths                             ;          ;
+----------------------------------------------------------+----------+

Revision 2.0.8

  • Filename: ac_v02000008_xxsep2009.sof
  • To Do:
    • ---
  • Features:
    • --
  • Details:
    • ---
  • Bugs:
    • None yet reported
  • FPGA Resource Usage (clk_card.fit.rpt):
  • Timing Analyzer Summary (clk_card.tan.rpt):


Revision 2.0.7

Features:

  • Added the const_val39 command to support internal TES Bias ramping

Bugs:

  • None so far

Firmware Links

Wiki Links

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