Difference between revisions of "Address Card firmware"
From MCEWiki
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* [http://www.phas.ubc.ca/~mce/mcedocs/firmware/ac_fpga_programming_file_catalogue.pdf Address Card Firmware Catalog] | * [http://www.phas.ubc.ca/~mce/mcedocs/firmware/ac_fpga_programming_file_catalogue.pdf Address Card Firmware Catalog] | ||
* [http://www.phas.ubc.ca/~mce/mcedocs/firmware/ Firmware Downloads] | * [http://www.phas.ubc.ca/~mce/mcedocs/firmware/ Firmware Downloads] | ||
| + | |||
| + | == FPGA Utilization == | ||
| + | +-----------------------------------------------------------------------------------------------------+ | ||
| + | ; Fitter Resource Usage Summary ; | ||
| + | +---------------------------------------------+-------------------------------------------------------+ | ||
| + | ; Resource ; Usage ; | ||
| + | +---------------------------------------------+-------------------------------------------------------+ | ||
| + | ; Total logic elements ; 8,982 / 10,570 ( 85 % ) ; | ||
| + | ; -- Combinational with no register ; 4414 ; | ||
| + | ; -- Register only ; 1227 ; | ||
| + | ; -- Combinational with a register ; 3341 ; | ||
| + | ; ; ; | ||
| + | ; Logic element usage by number of LUT inputs ; ; | ||
| + | ; -- 4 input functions ; 6383 ; | ||
| + | ; -- 3 input functions ; 730 ; | ||
| + | ; -- 2 input functions ; 619 ; | ||
| + | ; -- 1 input functions ; 565 ; | ||
| + | ; -- 0 input functions ; 685 ; | ||
| + | ; ; ; | ||
| + | ; Logic elements by mode ; ; | ||
| + | ; -- normal mode ; 8563 ; | ||
| + | ; -- arithmetic mode ; 419 ; | ||
| + | ; -- qfbk mode ; 2006 ; | ||
| + | ; -- register cascade mode ; 0 ; | ||
| + | ; -- synchronous clear/load mode ; 3018 ; | ||
| + | ; -- asynchronous clear/load mode ; 4460 ; | ||
| + | ; ; ; | ||
| + | ; Total registers ; 4,568 / 13,052 ( 35 % ) ; | ||
| + | ; Total LABs ; 991 / 1,057 ( 94 % ) ; | ||
| + | ; Logic elements in carry chains ; 450 ; | ||
| + | ; User inserted logic elements ; 0 ; | ||
| + | ; Virtual pins ; 0 ; | ||
| + | ; I/O pins ; 279 / 427 ( 65 % ) ; | ||
| + | ; -- Clock pins ; 1 / 16 ( 6 % ) ; | ||
| + | ; Global signals ; 4 ; | ||
| + | ; M512s ; 91 / 94 ( 97 % ) ; | ||
| + | ; M4Ks ; 60 / 60 ( 100 % ) ; | ||
| + | ; M-RAMs ; 0 / 1 ( 0 % ) ; | ||
| + | ; Total memory bits ; 195,584 / 920,448 ( 21 % ) ; | ||
| + | ; Total RAM block bits ; 328,896 / 920,448 ( 36 % ) ; | ||
| + | ; DSP block 9-bit elements ; 8 / 48 ( 17 % ) ; | ||
| + | ; PLLs ; 1 / 6 ( 17 % ) ; | ||
| + | ; Global clocks ; 4 / 16 ( 25 % ) ; | ||
| + | ; Regional clocks ; 0 / 16 ( 0 % ) ; | ||
| + | ; Fast regional clocks ; 0 / 8 ( 0 % ) ; | ||
| + | ; SERDES transmitters ; 0 / 44 ( 0 % ) ; | ||
| + | ; SERDES receivers ; 0 / 44 ( 0 % ) ; | ||
| + | ; Average interconnect usage ; 31% ; | ||
| + | ; Peak interconnect usage ; 43% ; | ||
| + | ; Maximum fan-out node ; ac_pll:pll0|altpll:altpll_component|_clk0 ; | ||
| + | ; Maximum fan-out ; 4760 ; | ||
| + | ; Highest non-global fan-out signal ; dispatch:cmd0|dispatch_wishbone:wishbone|tga_o[3]~190 ; | ||
| + | ; Highest non-global fan-out ; 913 ; | ||
| + | ; Total fan-out ; 47230 ; | ||
| + | ; Average fan-out ; 5.01 ; | ||
| + | +---------------------------------------------+-------------------------------------------------------+ | ||
== Wiki Links == | == Wiki Links == | ||
* [http://e-mode.phas.ubc.ca/mcewiki/index.php/MCE_firmware MCE Firmware Page] | * [http://e-mode.phas.ubc.ca/mcewiki/index.php/MCE_firmware MCE Firmware Page] | ||
* [http://e-mode.phas.ubc.ca/mcewiki/index.php/Main_Page MCE Main Page] | * [http://e-mode.phas.ubc.ca/mcewiki/index.php/Main_Page MCE Main Page] | ||
Revision as of 16:16, 14 July 2008
Latest Stable Release
v 2.0.7 (ac_v02000007)
Features:
- Added the const_val39 command to support internal TES Bias ramping
Bugs:
- None so far
Firmware Links
FPGA Utilization
+-----------------------------------------------------------------------------------------------------+ ; Fitter Resource Usage Summary ; +---------------------------------------------+-------------------------------------------------------+ ; Resource ; Usage ; +---------------------------------------------+-------------------------------------------------------+ ; Total logic elements ; 8,982 / 10,570 ( 85 % ) ; ; -- Combinational with no register ; 4414 ; ; -- Register only ; 1227 ; ; -- Combinational with a register ; 3341 ; ; ; ; ; Logic element usage by number of LUT inputs ; ; ; -- 4 input functions ; 6383 ; ; -- 3 input functions ; 730 ; ; -- 2 input functions ; 619 ; ; -- 1 input functions ; 565 ; ; -- 0 input functions ; 685 ; ; ; ; ; Logic elements by mode ; ; ; -- normal mode ; 8563 ; ; -- arithmetic mode ; 419 ; ; -- qfbk mode ; 2006 ; ; -- register cascade mode ; 0 ; ; -- synchronous clear/load mode ; 3018 ; ; -- asynchronous clear/load mode ; 4460 ; ; ; ; ; Total registers ; 4,568 / 13,052 ( 35 % ) ; ; Total LABs ; 991 / 1,057 ( 94 % ) ; ; Logic elements in carry chains ; 450 ; ; User inserted logic elements ; 0 ; ; Virtual pins ; 0 ; ; I/O pins ; 279 / 427 ( 65 % ) ; ; -- Clock pins ; 1 / 16 ( 6 % ) ; ; Global signals ; 4 ; ; M512s ; 91 / 94 ( 97 % ) ; ; M4Ks ; 60 / 60 ( 100 % ) ; ; M-RAMs ; 0 / 1 ( 0 % ) ; ; Total memory bits ; 195,584 / 920,448 ( 21 % ) ; ; Total RAM block bits ; 328,896 / 920,448 ( 36 % ) ; ; DSP block 9-bit elements ; 8 / 48 ( 17 % ) ; ; PLLs ; 1 / 6 ( 17 % ) ; ; Global clocks ; 4 / 16 ( 25 % ) ; ; Regional clocks ; 0 / 16 ( 0 % ) ; ; Fast regional clocks ; 0 / 8 ( 0 % ) ; ; SERDES transmitters ; 0 / 44 ( 0 % ) ; ; SERDES receivers ; 0 / 44 ( 0 % ) ; ; Average interconnect usage ; 31% ; ; Peak interconnect usage ; 43% ; ; Maximum fan-out node ; ac_pll:pll0|altpll:altpll_component|_clk0 ; ; Maximum fan-out ; 4760 ; ; Highest non-global fan-out signal ; dispatch:cmd0|dispatch_wishbone:wishbone|tga_o[3]~190 ; ; Highest non-global fan-out ; 913 ; ; Total fan-out ; 47230 ; ; Average fan-out ; 5.01 ; +---------------------------------------------+-------------------------------------------------------+
