MCE Timing Diagram

The following timing diagram is generated by simulating MCE firmware using Modelsim^TM. Parameters used for this simulation:

row_len	100
num_rows	33
sample_dly	40
sample_num	10
servo_mode	3
Address Card enbl_mux	1
Bias Card enbl_mux	1
RC firmware rev.	5.1.2
BC firmware rev.	5.0.6
AC firmware rev.	5.0.3
CC firmware rev.	5.0.7

Note that Bias Card DACs (MAX5443) latch on CS’s low-to-high transition. Address Card DACs are clocked on the negative edge of the main clock.

Under Address Card section, both DAC_clk(0) and DAC_clk(32) are shown. This indicates that first, the previous row's DAC (32 in this case) is turned off and then the new DAC (0 in this case) is turned on. All Address-Card DACs are off for 2 clock cycles.

The coadd window takes the 4 clock cycles of ADC latency into account, i.e., When the coadd window is asserted at clock cycle 40 in the diagram above, the samples are stored starting clock cycle 44.