Bias Card firmware
From MCEWiki
- Recommended Firmware Revisions
- Please see the recommend firmware revisions page.
Contents
Firmware Revision Listing
Revision 5.0.4 (lab use)
- Filename
- bc_v05000004_20may2010.sof
- Features
- build based on 5.0.3 for Rev. E cards
- Biases are refreshed 1 clock cycles after the start of a new row, regardless of whether they are running in multiplex mode or not and whether it is a regular bias line or low-noise bias line.
- Details
- NOTE If this firmware is loaded on a Rev. D card, it's harmless. The only functionality loss is that the bias command will not work as unfortunately DAC CS and CLK pins are swapped for the bias DAC between the two revisions of the card.
- To do
- none
- Bugs
- none
- FPGA Resource Usage
- Total logic elements ; 60%
- M512s ; 49%
- M4Ks ; 100%
- M-RAMs ; 100%
Revision 5.0.3 (lab use)
- Filename
- bc_v05000003_12may2010.sof
- Features
- build based on 5.0.2 for Rev. E cards
- added fb_col0 to fb_col31 and enbl_mux commands to accommodate row-based sq2fb switching. When enbl_mux is asserted for a column, then the DAC is refreshed on every row visit with the value specified by fb_col command.
- Details
- The original Bias Card design has a buffer after the DAC that is too slow followed by kHz range RC filters, so in order to enable the multiplexing feature, one has to make sure that the BC hardware is modified as per ECO-xxx (to be added here).
- card_type returns 5 (indicating a Rev. E)
- If this firmware is loaded on a Rev. D card, it's harmless. The only functionality loss is that the bias command will not work as unfortunately DAC CS and CLK pins are swapped for the bias DAC between the two revisions of the card.
- combinational loops present in previous versions are removed now
- There is 9+16*2=41 clock cycle (820ns) delay for the bias to be applied after the start of a new row. This combined with another 400ns delay due to inherent DAC delay is about 60 clock-cycle delay.
- To do
- The excessive 41 clock cycle delay to apply a new bias has to be reduced. It is conceivable to preload the DACs and reduce this delay to 1 to 2 clock cycles.
- Bugs
- none
- FPGA Resource Usage
- Total logic elements ; 6,140 / 10,570 ( 58 % ) ;
- Total memory bits ; 133,120 / 920,448 ( 14 % ) ;
- M512s ; 48 / 94 ( 51 % ) ;
- M4Ks ; 60 / 60 ( 100 % ) ;
- M-RAMs ; 0 / 1 ( 0 % ) ;
Revision 5.0.2 (lab use)
- Filename
- bc_v05000002_xxjan2010.sof
- Features
- build based on 5.0.1 for Rev. E cards
- Independent control for ln_bias lines 0 to 11
- Details
- If this firmware is loaded on a Rev. D card, it's harmless. The only functionality loss is that the bias command will not work as unfortunately DAC CS and CLK pins are swapped for the bias DAC between the two revisions of the card.
- To do
- fix combinational loops on read-ram register
- Bugs
Revision 5.0.1 (lab use)
- Filename
- bc_v05000001_19jan2010.sof
- Features
- supports the new low-noise bias lines (total of 12) introduced in Bias Card Rev. E
- card_type parameter is set to 5 (bias-card Rev. E)
- All DACs are loaded at once as oppose to previous revisions that loaded them one after next.
- DAC clock is now 25MHz and generated by PLL, previous firmware had 12.5MHz clock generated by dividing down.
- Details
- If this firmware is loaded on a Rev. D card, it's harmless. The only functionality loss is that the bias command will not work as unfortunately DAC CS and CLK pins are swapped for the bias DAC between the two revisions of the card.
- To do
- All ln_bias lines are controlled at once and this should be modified to independent control.
- Bugs
ln_bias_0 doesn't work, because the data line for ln_bias_0 is not connected in firmware.
Revision 5.0.0
- Filename: bc_v05000000_22dec2008.sof (tagged as sys_v05000000_22dec2008)
- To Do:
- Features:
- IMPORTANT: Must be used in conjunction with firmware v05000000 of all other cards!!!
- To allow enough data bandwidth, the spare LVDS line from each card to the Clock Card is now used
- Details:
- Bugs:
- None yet reported
- FPGA Resource Usage (bias_card.fit.rpt):
; Fitter Status ; Successful - Wed Jan 14 11:19:37 2009 ; ; Quartus II Version ; 8.1 Build 163 10/28/2008 SJ Full Version ; ; Device ; EP1S10F780C5 ; ; Total logic elements ; 3,356 / 10,570 ( 32 % ) ; ; Total pins ; 187 / 427 ( 44 % ) ; ; Total memory bits ; 70,144 / 920,448 ( 8 % ) ;
- Timing Analyzer Summary (bias_card.tan.rpt):
; Fast Model Clock Setup: 'bc_pll:pll0|altpll:altpll_component|_clk1' ; 7.060 ns ; ; Fast Model Clock Setup: 'bc_pll:pll0|altpll:altpll_component|_clk0' ; 7.125 ns ; ; Fast Model Clock Hold: 'bc_pll:pll0|altpll:altpll_component|_clk0' ; 0.383 ns ; ; Fast Model Clock Hold: 'bc_pll:pll0|altpll:altpll_component|_clk1' ; 0.384 ns ; ; Fast Model Recovery: 'bc_pll:pll0|altpll:altpll_component|_clk0' ; 16.037 ns ; ; Fast Model Removal: 'bc_pll:pll0|altpll:altpll_component|_clk0' ; 0.575 ns ; ; Total number of failed paths ; ;
Revision 1.4.2
- bc_v01040002_15jul2008.sof
Features:
- Added the tga_i signal to the sensitivity list for the bc_dac_ctrl FSM
- potential bug may have been introduced with resetting the DAC counter due to inadvertently using the wrong bc_dac_ctrl_core.vhd version.
Revision 1.4.1
- bc_v01040001_25jan2008.sof
Features:
- Added card_type and scratch commands
- Integrated fw_rev and slot_id as part of all_cards
- Added provisions for safe state machines to fix the reset problem.
- Added lvds_tx = 0 so clock-card can check whether the card is plugged in using this spare lvds line.
Bugs: None so far
