Bias Card firmware
From MCEWiki
Contents
Recommended Firmware Revisions
- Please see the recommend firmware revisions page.
Firmware Revision Listing
Revision 5.0.0
- Filename: bc_v05000000_22dec2008.sof (tagged as sys_v05000000_22dec2008)
- To Do:
- ---
- Features:
- IMPORTANT: Must be used in conjunction with firmware v05000000 of all other cards!!!
- To allow enough data bandwidth, the spare LVDS line from each card to the Clock Card is now used
- Details:
- ---
- Bugs:
- None yet reported
- FPGA Resource Usage (bias_card.fit.rpt):
+---------------------------------------------------------------------+ ; Fitter Summary ; +--------------------------+------------------------------------------+ ; Fitter Status ; Successful - Wed Jan 14 11:19:37 2009 ; ; Quartus II Version ; 8.1 Build 163 10/28/2008 SJ Full Version ; ; Revision Name ; bias_card ; ; Top-level Entity Name ; bias_card ; ; Family ; Stratix ; ; Device ; EP1S10F780C5 ; ; Timing Models ; Final ; ; Total logic elements ; 3,356 / 10,570 ( 32 % ) ; ; Total pins ; 187 / 427 ( 44 % ) ; ; Total virtual pins ; 0 ; ; Total memory bits ; 70,144 / 920,448 ( 8 % ) ; ; DSP block 9-bit elements ; 0 / 48 ( 0 % ) ; ; Total PLLs ; 1 / 6 ( 17 % ) ; ; Total DLLs ; 0 / 2 ( 0 % ) ; +--------------------------+------------------------------------------+
- Timing Analyzer Summary (bias_card.tan.rpt):
+---------------------------------------------------------------------------------- ; Fast Model Timing Analyzer Summary +---------------------------------------------------------------------+-----------+ ; Type ; Slack ; +---------------------------------------------------------------------+-----------+ ; Worst-case tsu ; N/A ; ; Worst-case tco ; N/A ; ; Worst-case tpd ; N/A ; ; Worst-case th ; N/A ; ; Worst-case Minimum tco ; N/A ; ; Worst-case Minimum tpd ; N/A ; ; Fast Model Clock Setup: 'bc_pll:pll0|altpll:altpll_component|_clk1' ; 7.060 ns ; ; Fast Model Clock Setup: 'bc_pll:pll0|altpll:altpll_component|_clk0' ; 7.125 ns ; ; Fast Model Clock Hold: 'bc_pll:pll0|altpll:altpll_component|_clk0' ; 0.383 ns ; ; Fast Model Clock Hold: 'bc_pll:pll0|altpll:altpll_component|_clk1' ; 0.384 ns ; ; Fast Model Recovery: 'bc_pll:pll0|altpll:altpll_component|_clk0' ; 16.037 ns ; ; Fast Model Removal: 'bc_pll:pll0|altpll:altpll_component|_clk0' ; 0.575 ns ; ; Total number of failed paths ; ; +---------------------------------------------------------------------+-----------+
Revision 1.4.2
There is no information on this.
Revision 1.4.1
- bc_v01040001_25jan2008.sof
Features:
- Added card_type and scratch commands
- Integrated fw_rev and slot_id as part of all_cards
- Added provisions for safe state machines to fix the reset problem.
- Added lvds_tx = 0 so clock-card can check whether the card is plugged in using this spare lvds line.
Bugs: None so far
