Address Card firmware

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Revision as of 13:39, 16 September 2009 by 142.103.235.238 (talk)

Recommended Firmware Revisions

Firmware Revision Listing

Revision 5.0.1

  • Filename: ac_v05000001_14sep2009.sof
  • To Do:
    • ---
  • Features:
    • The resource usage on the AC has now reached a level where there isn't enough left to implement Signal Tap. To enable SignalTap, comment out the largest usage of RAM/LE's: "ram : tpram_32bit_x_64" in ac_dac_ctrl.vhd. Remember to uncomment this when running the final synthesis before committal.
    • Based on ac_v5.0.0.
    • Implements the bias_start command for different bias heating across rows on SCUBA2 arrays.
    • IMPORTANT: Must be used in conjunction with firmware v05000000+ of all other cards.
  • Details:
    • Differences between ac_v5.0.0 and ac_v5.0.1
U system/test/source/tb/tb_cc_rcs_bcs_ac.vhd
U addr_card/ac_dac_ctrl/source/rtl/ac_dac_ctrl.vhd
U addr_card/ac_dac_ctrl/source/rtl/ac_dac_ctrl_pack.vhd
U addr_card/addr_card/source/rtl/addr_card.vhd
U addr_card/addr_card/source/rtl/addr_card_self_test.vhd
U addr_card/addr_card/synth/addr_card.fit.rpt
U addr_card/addr_card/synth/addr_card.fit.summary
U addr_card/addr_card/synth/addr_card.map.rpt
U addr_card/addr_card/synth/addr_card.qsf
U addr_card/addr_card/synth/addr_card.sof
U addr_card/addr_card/synth/addr_card.tan.rpt
U addr_card/addr_card/synth/addr_card.tan.summary
U all_cards/all_cards/source/rtl/all_cards_pack.vhd
U all_cards/async/source/rtl/async_pack.vhd
U all_cards/async/source/rtl/lvds_rx.vhd
U all_cards/dispatch/source/rtl/dispatch.vhd
U all_cards/dispatch/source/rtl/dispatch_cmd_receive.vhd
U all_cards/frame_timing/source/rtl/frame_timing.vhd
U all_cards/frame_timing/source/rtl/frame_timing_core.vhd
U all_cards/frame_timing/source/rtl/frame_timing_pack.vhd
U library/sys_param/source/rtl/data_types_pack.vhd
U library/sys_param/source/rtl/wishbone_pack.vhd
  • Bugs:
    • None yet reported
  • FPGA Resource Usage (addr_card.fit.rpt):
+--------------------------------------------------------------------------+
; Fitter Summary                                                           ;
+--------------------------+-----------------------------------------------+
; Fitter Status            ; Successful - Mon Sep 14 13:46:41 2009         ;
; Quartus II Version       ; 9.0 Build 235 06/17/2009 SP 2 SJ Full Version ;
; Revision Name            ; addr_card                                     ;
; Top-level Entity Name    ; addr_card                                     ;
; Family                   ; Stratix                                       ;
; Device                   ; EP1S10F780C5                                  ;
; Timing Models            ; Final                                         ;
; Total logic elements     ; 9,370 / 10,570 ( 89 % )                       ;
; Total pins               ; 279 / 427 ( 65 % )                            ;
; Total virtual pins       ; 0                                             ;
; Total memory bits        ; 199,168 / 920,448 ( 22 % )                    ;
; DSP block 9-bit elements ; 8 / 48 ( 17 % )                               ;
; Total PLLs               ; 1 / 6 ( 17 % )                                ;
; Total DLLs               ; 0 / 2 ( 0 % )                                 ;
+--------------------------+-----------------------------------------------+
  • Timing Analyzer Summary (addr_card.tan.rpt):
+----------------------------------------------------------------------
; Timing Analyzer Summary                                              
+----------------------------------------------------------+----------+
; Type                                                     ; Slack    ;
+----------------------------------------------------------+----------+
; Worst-case tsu                                           ; N/A      ;
; Worst-case tco                                           ; N/A      ;
; Worst-case th                                            ; N/A      ;
; Clock Setup: 'ac_pll:pll0|altpll:altpll_component|_clk0' ; 3.361 ns ;
; Clock Setup: 'ac_pll:pll0|altpll:altpll_component|_clk2' ; 4.142 ns ;
; Clock Hold: 'ac_pll:pll0|altpll:altpll_component|_clk0'  ; 0.528 ns ;
; Clock Hold: 'ac_pll:pll0|altpll:altpll_component|_clk2'  ; 0.562 ns ;
; Total number of failed paths                             ;          ; 
+----------------------------------------------------------+----------+

Revision 5.0.0

  • Filename: ac_v05000000_22dec2008.sof
  • To Do:
    • ---
  • Features:
    • IMPORTANT: Must be used in conjunction with firmware v05000000+ of all other cards.
    • To increase data bandwidth, the spare LVDS line from each card to the Clock Card is now used
  • Details:
    • ---
  • Bugs:
    • None yet reported
  • FPGA Resource Usage (addr_card.fit.rpt):
+---------------------------------------------------------------------+
; Fitter Summary                                                      ;
+--------------------------+------------------------------------------+
; Fitter Status            ; Successful - Tue Jan 13 16:19:16 2009    ;
; Quartus II Version       ; 8.1 Build 163 10/28/2008 SJ Full Version ;
; Revision Name            ; addr_card                                ;
; Top-level Entity Name    ; addr_card                                ;
; Family                   ; Stratix                                  ;
; Device                   ; EP1S10F780C5                             ;
; Timing Models            ; Final                                    ;
; Total logic elements     ; 9,383 / 10,570 ( 89 % )                  ;
; Total pins               ; 279 / 427 ( 65 % )                       ;
; Total virtual pins       ; 0                                        ;
; Total memory bits        ; 196,096 / 920,448 ( 21 % )               ;
; DSP block 9-bit elements ; 8 / 48 ( 17 % )                          ;
; Total PLLs               ; 1 / 6 ( 17 % )                           ;
; Total DLLs               ; 0 / 2 ( 0 % )                            ;
+--------------------------+------------------------------------------+
  • Timing Analyzer Summary (addr_card.tan.rpt):
+----------------------------------------------------------------------
; Timing Analyzer Summary                                              
+----------------------------------------------------------+----------+
; Type                                                     ; Slack    ;
+----------------------------------------------------------+----------+
; Worst-case tsu                                           ; N/A      ;
; Worst-case tco                                           ; N/A      ;
; Worst-case th                                            ; N/A      ;
; Clock Setup: 'ac_pll:pll0|altpll:altpll_component|_clk0' ; 2.617 ns ;
; Clock Setup: 'ac_pll:pll0|altpll:altpll_component|_clk2' ; 4.588 ns ;
; Clock Hold: 'ac_pll:pll0|altpll:altpll_component|_clk0'  ; 0.539 ns ;
; Clock Hold: 'ac_pll:pll0|altpll:altpll_component|_clk2'  ; 0.658 ns ;
; Total number of failed paths                             ;          ;
+----------------------------------------------------------+----------+

Revision 2.0.8

  • Filename: ac_v02000008_xxsep2009.sof
  • To Do:
    • ---
  • Features:
    • Based on ac_v2.0.7
    • Implements the bias_start command for different bias heating across rows on SCUBA2 arrays.
  • Details:
    • Differences between ac_v2.0.7 and ac_v2.0.8
U system/test/source/tb/tb_cc_rcs_bcs_ac.vhd
U addr_card/ac_dac_ctrl/source/rtl/ac_dac_ctrl.vhd
U addr_card/ac_dac_ctrl/source/rtl/ac_dac_ctrl_pack.vhd
U addr_card/addr_card/source/rtl/addr_card.vhd
U addr_card/addr_card/source/rtl/addr_card_self_test.vhd
U addr_card/addr_card/synth/addr_card.fit.rpt
U addr_card/addr_card/synth/addr_card.fit.summary
U addr_card/addr_card/synth/addr_card.map.rpt
C addr_card/addr_card/synth/addr_card.qws
U addr_card/addr_card/synth/addr_card.qsf
U addr_card/addr_card/synth/addr_card.sof
U addr_card/addr_card/synth/addr_card.tan.rpt
U addr_card/addr_card/synth/addr_card.tan.summary
U all_cards/all_cards/source/rtl/all_cards.vhd
U all_cards/all_cards/source/rtl/all_cards_pack.vhd
U all_cards/frame_timing/source/rtl/frame_timing.vhd
U all_cards/frame_timing/source/rtl/frame_timing_core.vhd
U all_cards/frame_timing/source/rtl/frame_timing_pack.vhd
U all_cards/frame_timing/source/rtl/frame_timing_wbs.vhd
U library/components/source/rtl/parallel_crc.vhd
U library/sys_param/source/rtl/data_types_pack.vhd
U library/sys_param/source/rtl/wishbone_pack.vhd
  • Bugs:
    • None yet reported
  • FPGA Resource Usage (addr_card.fit.rpt):
+---------------------------------------------------------------------+
; Fitter Summary                                                      ;
+--------------------------+------------------------------------------+
; Fitter Status            ; Successful - Wed Sep 16 13:03:57 2009    ;
; Quartus II Version       ; 8.1 Build 163 10/28/2008 SJ Full Version ;
; Revision Name            ; addr_card                                ;
; Top-level Entity Name    ; addr_card                                ;
; Family                   ; Stratix                                  ;
; Device                   ; EP1S10F780C5                             ;
; Timing Models            ; Final                                    ;
; Total logic elements     ; 9,141 / 10,570 ( 86 % )                  ;
; Total pins               ; 279 / 427 ( 65 % )                       ;
; Total virtual pins       ; 0                                        ;
; Total memory bits        ; 198,656 / 920,448 ( 22 % )               ;
; DSP block 9-bit elements ; 8 / 48 ( 17 % )                          ;
; Total PLLs               ; 1 / 6 ( 17 % )                           ;
; Total DLLs               ; 0 / 2 ( 0 % )                            ;
+--------------------------+------------------------------------------+
  • Timing Analyzer Summary (addr_card.tan.rpt):
+----------------------------------------------------------------------
; Timing Analyzer Summary                                              
+----------------------------------------------------------+----------+
; Type                                                     ; Slack    ;
+----------------------------------------------------------+----------+
; Worst-case tsu                                           ; N/A      ;
; Worst-case tco                                           ; N/A      ;
; Worst-case th                                            ; N/A      ;
; Clock Setup: 'ac_pll:pll0|altpll:altpll_component|_clk0' ; 1.971 ns ;
; Clock Setup: 'ac_pll:pll0|altpll:altpll_component|_clk2' ; 4.506 ns ;
; Clock Hold: 'ac_pll:pll0|altpll:altpll_component|_clk0'  ; 0.539 ns ;
; Clock Hold: 'ac_pll:pll0|altpll:altpll_component|_clk2'  ; 0.549 ns ;
; Total number of failed paths                             ;          ;
+----------------------------------------------------------+----------+

Revision 2.0.7

Features:

  • Added the const_val39 command to support internal TES Bias ramping

Bugs:

  • None so far

Firmware Links

Wiki Links

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