Difference between revisions of "Sync Box AC-in Rack Mount I/O"

Revision as of 13:16, 13 April 2010

ACDCU(0-7): 8 TTL outputs. Carries a high/low signal that enables/disables the MCE AC/DC converter.
MCE(0-7): 8 Fibre outputs. Carries a 50 MHz Manchester-encoded signal containing data packets, which include incremented sequence numbers. Programmable as two sets of 4 outputs with differently spaced data packets on each.
RTS-DV: TTL input. Detects falling edges from a Real-Time Sequencer (implemented by SCUBA2) which tells the Sync box when to tell the MCE's to collect data.
OPTO-TTL: TTL input, spare input to the command processor. ***Not currently used, and open for suggestions.
RS232 RxTx: TTL input and output, used to command the Sync Box from a PC.
DV Spare 1: TTL output. Carries a 5 MHz clock signal that is synchronous with DV Spare 2.
DV Spare 2: TTL output. Carries a 5 MHz data signal that is synchronized with DV Spare 1, and contains the same sequence numbers as the MCE(0-7) outputs. NOTE: This output only contains the DV info stream, but not the occurrences of Addr_Zero between DVs.
Polarimeter: TTL output. Carries a 5 MHz TTL signal that contains the same sequence numbers as the MCE(0-7) outputs.
FTS: TTL output. Carries a 5 MHz TTL signal that contains the same sequence numbers as the MCE(0-7) outputs.
TTL-IN: SMB TTL input, spare input to the FPGA. ***Not currently used, and open for suggestions.
TTL-OUT: SMB TTL output. Carries a 50 MHz clock signal.
Power: AC

@@ Line 23: / Line 23: @@
 ; Power
 : AC
+= =
+[http://www.phas.ubc.ca/~mce/mcedocs/hardware/schematics/SyncBox/S589-102_SyncBox_Wiring_Diagram.pdf Connector Pinout]
+[http://www.phas.ubc.ca/~mce/mcedocs/hardware/board_block_diagram/S589-001_Syncbox_Block_Diagram.pdf Block Diagram]
 = =
 [http://cmbr.phas.ubc.ca/mcewiki/index.php/Sync_Box#User.27s_Guide back to Sync Box ]