Difference between revisions of "Sync Box AC-in Rack Mount I/O"

From MCEWiki
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: 8 Fibre outputs. Carries a 50 MHz Manchester-encoded signal containing data packets, which include incremented sequence numbers. Programmable as two sets of 4 outputs with differently spaced data packets on each.
 
: 8 Fibre outputs. Carries a 50 MHz Manchester-encoded signal containing data packets, which include incremented sequence numbers. Programmable as two sets of 4 outputs with differently spaced data packets on each.
 
;RTS-DV
 
;RTS-DV
: TTL input. Detects falling edges from a Real-Time Sequencer (implemented by SCUBA2) which tells the Sync box when to tell the MCE's to collect data.
+
: differential RS485 input. Detects falling edges from a Real-Time Sequencer (implemented by SCUBA2) which tells the Sync box when to tell the MCE's to collect data.
 
;OPTO-TTL
 
;OPTO-TTL
 
: TTL input, spare input to the command processor. ***Not currently used, and open for suggestions.
 
: TTL input, spare input to the command processor. ***Not currently used, and open for suggestions.
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: TTL input and output, used to command the Sync Box from a PC.
 
: TTL input and output, used to command the Sync Box from a PC.
 
; DV Spare 1
 
; DV Spare 1
: TTL output. Carries a 5 MHz clock signal that is synchronous with DV Spare 2.
+
: differential RS485 output. Carries a 5 MHz clock signal that is synchronous with DV Spare 2.
 
; DV Spare 2
 
; DV Spare 2
: TTL output. Carries a 5 MHz data signal that is synchronized with DV Spare 1, and contains the same sequence numbers as the MCE(0-7) outputs. NOTE: This output only contains the DV info stream, but not the occurrences of Addr_Zero between DVs.
+
: differential RS485 output. Carries a 5 MHz data signal that is synchronized with DV Spare 1, and contains the same sequence numbers as the MCE(0-7) outputs. NOTE: This output only contains the DV info stream, but not the occurrences of Addr_Zero between DVs.
 
; Polarimeter
 
; Polarimeter
: TTL output. asserted for 1us on an Address-Return-to-Zero(ARZ) if a DV pulse is detected since the last ARZ.
+
: output, available both as TTL and differential RS485, asserted for 1us on an Address-Return-to-Zero(ARZ) if a DV pulse is detected since the last ARZ.
 
; FTS
 
; FTS
: TTL output. asserted for 1us on an Address-Return-to-Zero(ARZ) if a DV pulse is detected since the last ARZ.
+
: output, available both as TTL and differential RS485, asserted for 1us on an Address-Return-to-Zero(ARZ) if a DV pulse is detected since the last ARZ.
 
; TTL-IN
 
; TTL-IN
 
: SMB TTL input, spare input to the FPGA. ***Not currently used, and open for suggestions.
 
: SMB TTL input, spare input to the FPGA. ***Not currently used, and open for suggestions.

Revision as of 14:16, 17 January 2012

Back to Sync Box Guide
ACDCU(0-7)
8 TTL outputs. Carries a high/low signal that enables/disables the MCE AC/DC converter.
MCE(0-7)
8 Fibre outputs. Carries a 50 MHz Manchester-encoded signal containing data packets, which include incremented sequence numbers. Programmable as two sets of 4 outputs with differently spaced data packets on each.
RTS-DV
differential RS485 input. Detects falling edges from a Real-Time Sequencer (implemented by SCUBA2) which tells the Sync box when to tell the MCE's to collect data.
OPTO-TTL
TTL input, spare input to the command processor. ***Not currently used, and open for suggestions.
RS232 RxTx
TTL input and output, used to command the Sync Box from a PC.
DV Spare 1
differential RS485 output. Carries a 5 MHz clock signal that is synchronous with DV Spare 2.
DV Spare 2
differential RS485 output. Carries a 5 MHz data signal that is synchronized with DV Spare 1, and contains the same sequence numbers as the MCE(0-7) outputs. NOTE: This output only contains the DV info stream, but not the occurrences of Addr_Zero between DVs.
Polarimeter
output, available both as TTL and differential RS485, asserted for 1us on an Address-Return-to-Zero(ARZ) if a DV pulse is detected since the last ARZ.
FTS
output, available both as TTL and differential RS485, asserted for 1us on an Address-Return-to-Zero(ARZ) if a DV pulse is detected since the last ARZ.
TTL-IN
SMB TTL input, spare input to the FPGA. ***Not currently used, and open for suggestions.
TTL-OUT
SMB TTL output. Carries a 50 MHz clock signal.
Power
AC

Schematics