Difference between revisions of "Sync Box AC-in Rack Mount I/O"
From MCEWiki
| Line 1: | Line 1: | ||
| + | :''[[Sync_Box#User.27s_Guide|Back to Sync Box Guide]]'' | ||
| + | |||
;ACDCU(0-7) | ;ACDCU(0-7) | ||
: 8 TTL outputs. Carries a high/low signal that enables/disables the MCE AC/DC converter. | : 8 TTL outputs. Carries a high/low signal that enables/disables the MCE AC/DC converter. | ||
| Line 14: | Line 16: | ||
: TTL output. Carries a 5 MHz data signal that is synchronized with DV Spare 1, and contains the same sequence numbers as the MCE(0-7) outputs. NOTE: This output only contains the DV info stream, but not the occurrences of Addr_Zero between DVs. | : TTL output. Carries a 5 MHz data signal that is synchronized with DV Spare 1, and contains the same sequence numbers as the MCE(0-7) outputs. NOTE: This output only contains the DV info stream, but not the occurrences of Addr_Zero between DVs. | ||
; Polarimeter | ; Polarimeter | ||
| − | : TTL output. | + | : TTL output. asserted for 1us on an Address-Return-to-Zero(ARZ) if a DV pulse is detected since the last ARZ. |
; FTS | ; FTS | ||
| − | :TTL output. | + | : TTL output. asserted for 1us on an Address-Return-to-Zero(ARZ) if a DV pulse is detected since the last ARZ. |
; TTL-IN | ; TTL-IN | ||
: SMB TTL input, spare input to the FPGA. ***Not currently used, and open for suggestions. | : SMB TTL input, spare input to the FPGA. ***Not currently used, and open for suggestions. | ||
| Line 23: | Line 25: | ||
; Power | ; Power | ||
: AC | : AC | ||
| − | = = | + | == Schematics == |
| − | |||
| − | |||
| − | |||
| − | |||
| − | + | * [http://www.phas.ubc.ca/~mce/mcedocs/hardware/schematics/SyncBox/S589-102_SyncBox_Wiring_Diagram.pdf Connector Pinout] | |
| − | [http:// | + | * [http://www.phas.ubc.ca/~mce/mcedocs/hardware/board_block_diagram/S589-001_Syncbox_Block_Diagram.pdf Block Diagram] |
Revision as of 17:06, 7 October 2010
- ACDCU(0-7)
- 8 TTL outputs. Carries a high/low signal that enables/disables the MCE AC/DC converter.
- MCE(0-7)
- 8 Fibre outputs. Carries a 50 MHz Manchester-encoded signal containing data packets, which include incremented sequence numbers. Programmable as two sets of 4 outputs with differently spaced data packets on each.
- RTS-DV
- TTL input. Detects falling edges from a Real-Time Sequencer (implemented by SCUBA2) which tells the Sync box when to tell the MCE's to collect data.
- OPTO-TTL
- TTL input, spare input to the command processor. ***Not currently used, and open for suggestions.
- RS232 RxTx
- TTL input and output, used to command the Sync Box from a PC.
- DV Spare 1
- TTL output. Carries a 5 MHz clock signal that is synchronous with DV Spare 2.
- DV Spare 2
- TTL output. Carries a 5 MHz data signal that is synchronized with DV Spare 1, and contains the same sequence numbers as the MCE(0-7) outputs. NOTE: This output only contains the DV info stream, but not the occurrences of Addr_Zero between DVs.
- Polarimeter
- TTL output. asserted for 1us on an Address-Return-to-Zero(ARZ) if a DV pulse is detected since the last ARZ.
- FTS
- TTL output. asserted for 1us on an Address-Return-to-Zero(ARZ) if a DV pulse is detected since the last ARZ.
- TTL-IN
- SMB TTL input, spare input to the FPGA. ***Not currently used, and open for suggestions.
- TTL-OUT
- SMB TTL output. Carries a 50 MHz clock signal.
- Power
- AC
