Difference between revisions of "MCE hardware"

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== MCEv2 5-MDM Instrument Backplane design notes ==
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{{Related|Hardware}}
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Here is the schematic posted for review:
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== General information ==
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[[http://www.phas.ubc.ca/~mce/projects/spider-spud-bicep2/system/MCEv2_Inst_Backplane/design/elec/C587-201_A_5MDM_IB/C587-201_INST_BP.pdf | IB schematics]]
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* [http://www.phas.ubc.ca/~mce/mcedocs/overview/functional_desc.pdf Functional Description of the Multi-Channel Electronics (PDF)] (Sep. 27, 2003)
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* [http://www.phas.ubc.ca/~mce/mcedocs/overview/SC2_ELE_S580_520_mce_getting_started_manual.pdf MCE Getting-Started Manual : Cryostat installation, troubleshooting, firmware upgrade (PDF)]
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* [[ MCE Accessories ]]
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* [[ Ordering MCE Hardware ]]
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* [[ MCE Power Requirements ]]
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* [http://www.phas.ubc.ca/~mce/mcedocs/hardware/Characteristics/MUX_drive_ubc_actual_values_Rev1.7.xls Output Drive Calculations (XLS)]
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* [[Noise Calculations]]
  
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For the record, here are some of the design decisions, currently not too late to change them:
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== Subrack interface and mounting ==
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* [[Subrack|MCE Subrack]] (volume, mass, configuration)
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* [http://www.phas.ubc.ca/~mce/mcedocs/overview/SC2_ELE_S580_005_Rev4.0_mce_interfaces.pdf Hardware Interface Block Diagram(PDF)]
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* '''Proposed''' MCE signal assignment scheme: [http://www.phas.ubc.ca/~mce/mcedocs/system/mce_mdm_signal_names_and_pinouts.pdf [PDF]] [http://www.phas.ubc.ca/~mce/mcedocs/system/mce_mdm_signal_names_and_pinouts.xls [XLS]]
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* MCE-Cryostat Diagram - cartoons of squid chain setup, servo loop calculations, and word-sizes [[http://www.phas.ubc.ca/~mce/mcedocs/system/Cryo_MCE%20Block%20Diagram.pdf PDF]]
  
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* '''implementation of configurable jumpers '''
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== Hardware documents ==
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In previous backplane designs, jumpers were implemented either as PCB traces or solder jumpers. The former had the problem of not being configurable as we had to cut traces. The latter had the problem that the assembler wouldn't put the solder jumpers on and since they are not on the BOM, it became hard to track whether they were done or not. Therefore, we settled on the following solution for the new design:
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'''Caveat lector:''' some of the documents in the following tables are obsolete, and have not been updated recently.  They may contain incorrect or outdated information.  Read with caution.
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** Jumpers for signal pairs have reference designators of JPn and JNn (eg. JP1 and JN1 are signal pair jumpers)
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{{MCE hardware table}}<!-- to edit this table, go here: http://e-mode.phas.ubc.ca/mcewiki/index.php/Template:MCE_hardware_table -->
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** These jumpers are called out on the BOM as zero ohm resistors or DNP (do not populate) parts
 
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** Zero ohm resistors will not be used for connect ground planes, copper traces will be used
 
  
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* ''' MDM routing of low-noise bias lines '''
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=== Other component details ===
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How to divide up the Low Noise Bias Signals between the new Bias Cards.
 
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** We need to maintain compatibility with existing Bias Cards which should ground these new backplane signal lines.
 
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** Maximizing the number of Low Noise Bias Signals we could get 10 on each of BC1-BC3 for a total of 30.
 
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** How we route them to the MDM connectors is limited but we have a few options, what seems to be best to me is
 
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*** P2 gets LN_BIAS_00 to 08
 
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*** P3 gets LN_BIAS_09 to 15 (P3 also has DET_BIAS_ORG and PXL_HTR)
 
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*** P4 gets LN_BIAS_16 to 23 with 1 spare signal (pair)
 
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*** P5 gets LN_BIAS_24 to 29 with 3 spare signal (pair)
 
  
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* '''Mechanical and Cosmetic Changes '''
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* [[MCE FPGA Types]]
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** Include provisions for clamping Hirose connectors
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* [[ MCE CARD Serial-Number Lookup ]]
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** Reorder Resistor Reference Designators so they are in order on the PCB
 
  
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* '''Design Concerns '''
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== Production testing ==
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** A considerable number of signal lines now have 0805 zero ohm jumpers which may be difficult to layout in the space available
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* [[ Test plans ]]
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[[Category:Hardware| ]]

Latest revision as of 18:34, 6 December 2021

Related topics:
▼ Hardware‎ (8 C, 4 P)
► Accessories‎ (1 C, 10 P)
► Address Card‎ (1 C, 6 P)
► Bias Card‎ (1 C, 15 P)
► Clock Card‎ (1 C, 8 P)
► Computing Hardware‎ (1 C, 3 P)
► Power‎ (10 P)
► Readout Card‎ (1 C, 10 P)
► Subrack‎ (1 C, 7 P)
  MCE hardware
  Cryocable Impedance
  MCE usage
  Ordering MCE Hardware

General information

Subrack interface and mounting

Hardware documents

Caveat lector: some of the documents in the following tables are obsolete, and have not been updated recently. They may contain incorrect or outdated information. Read with caution.

Component Type Doc. Id Technical
Description† 		Block
Diagram† 		Schematics Rev. Notes
Clock Card S581 [PDF] [PDF] [PDF] B5
Readout Card S582 [PDF] [PDF] [PDF] B9
[PDF] E0 Low-power RC
Bias Card S583 [PDF] [PDF] [PDF] D6 Original design
[PDF] D7/8 High-current det_bias
[PDF] D11 High-current det_bias/no heater
[PDF] E0 Multiple det_bias lines
[PDF] F0 Multi det_bias & MHz-response bias lines; Low-noise bias lines turned off
[PDF] F1 Power turned off on ln_bias
[PDF] F2 Minor change in ln_bias circuit
[PDF] F3 low 1/f-noise opamp for channel 0-15
[PDF] F4 low 1/f-noise opamp for channel 15-31
Address Card S584 [PDF] [PDF] [PDF] C4
[PDF] D0
Instrument Backplane 5MDM C587-201 [PDF] — [PDF] A
3MDM C587-101 [PDF] [PDF] B
[PDF] C1
[PDF] C2
Bus Backplane 3MDM C586-101 [PDF] — [PDF] A
5MDM C586-201 [PDF] D
Filter Board 3MDM C587-111 — — [PDF] A
5MDM C587-210 [PDF] A

†: Not updated since early design stages.

External Hardware and Accessories

Component Part Doc. Id Technical
Description† 		Block
Diagram 		Schematics Rev. Notes
MDM Breakout Board S58H — — [XLS] B
Linear Feed Card C585-104 — — [PDF] B
Vicor Power Assembly PCB C585-401 — — [PDF] C2
Wiring Harness C584-402 — [PDF] A
Sync Box PCB S589-101 [PDF] — [PDF] A2 Used in both Sync Box enclosures
AC-in: Internal Wiring S589-102 [PDF] [PDF] A2
AC-in: Cable Wiring S589-103 [PDF]
DC-in: Internal Wiring C589-102 [PDF] [PDF] A
PCI fibre card — — — [PDF] 5A
Extender Card S565-008 [PDF] — [PDF]
IB Tester S58E-502 [PDF] — [PDF] C
2-slot Backplane S58G — — [PDF] A
— — [PDF] B

†: Not updated since early design stages.

Other component details

Production testing

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