Difference between revisions of "Sync Box AC-in Rack Mount I/O"
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| − | + | {{Related|Sync Box}} | |
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;ACDCU(0-7) | ;ACDCU(0-7) | ||
: 8 TTL outputs. Carries a high/low signal that enables/disables the MCE AC/DC converter. | : 8 TTL outputs. Carries a high/low signal that enables/disables the MCE AC/DC converter. | ||
| Line 12: | Line 11: | ||
: TTL input and output, used to command the Sync Box from a PC. | : TTL input and output, used to command the Sync Box from a PC. | ||
; DV Spare 1 | ; DV Spare 1 | ||
| − | : differential RS485 output. Carries a 5 MHz clock signal that is synchronous with DV Spare 2. | + | : differential RS485 output. Carries a 5 MHz clock signal that is synchronous with DV Spare 2. Now called Data Sync 2 |
; DV Spare 2 | ; DV Spare 2 | ||
| − | : differential RS485 output. Carries a 5 MHz data signal that is synchronized with DV Spare 1, and contains the same sequence numbers as the MCE(0-7) outputs. NOTE: This output only contains the DV info stream, but not the occurrences of Addr_Zero between DVs. | + | : differential RS485 output. Carries a 5 MHz data signal that is synchronized with DV Spare 1, and contains the same sequence numbers as the MCE(0-7) outputs. NOTE: This output only contains the DV info stream, but not the occurrences of Addr_Zero between DVs. Now called Data Sync 1 |
; Polarimeter | ; Polarimeter | ||
| − | : output, available both as TTL and differential RS485, asserted for 1us on an Address-Return-to-Zero(ARZ) if a DV pulse is detected since the last ARZ. | + | : output, available both as TTL and differential RS485, asserted for 1us on an Address-Return-to-Zero(ARZ) if a DV pulse is detected since the last ARZ. Now called Data Sync 4 and in firmware Rev 21, this output is duplicate of DV_Spare2 or 5MHz clock. |
; FTS | ; FTS | ||
| − | : output, available both as TTL and differential RS485, asserted for 1us on an Address-Return-to-Zero(ARZ) if a DV pulse is detected since the last ARZ. | + | : output, available both as TTL and differential RS485, asserted for 1us on an Address-Return-to-Zero(ARZ) if a DV pulse is detected since the last ARZ. Now called Data Sync 3 and in firmware Rev 21, this output is duplicate of DV_Spare1 or 5MHz data-stream. |
; TTL-IN | ; TTL-IN | ||
| − | : SMB TTL input, spare input to the FPGA | + | : SMB TTL input, spare input to the FPGA. |
; TTL-OUT | ; TTL-OUT | ||
: SMB TTL output. Carries a 50 MHz clock signal. | : SMB TTL output. Carries a 50 MHz clock signal. | ||
; Power | ; Power | ||
| − | : AC | + | : 47–440Hz, 85–265VAC mains power over a 3-pin HP-style power connector. |
| + | |||
| + | == Signal Translation table between Rack-mount and DC-in versions of Sync Box == | ||
| + | {| class="wikitable" | ||
| + | ! AC-in !! DC-in | ||
| + | |- | ||
| + | | DV_Spare1 || data_sync1 | ||
| + | |- | ||
| + | | DV_Spare2 || data_sync2 | ||
| + | |- | ||
| + | | DV_OUT_FTS || data_sync4 | ||
| + | |- | ||
| + | | DV_OUT_POL || data_sync3 | ||
| + | |} | ||
| + | WARNING: signal polarity may be swapped on data_sync1 and data_sync2. | ||
| + | |||
== Schematics == | == Schematics == | ||
* [http://www.phas.ubc.ca/~mce/mcedocs/hardware/schematics/SyncBox/S589-102_SyncBox_Wiring_Diagram.pdf Connector Pinout] | * [http://www.phas.ubc.ca/~mce/mcedocs/hardware/schematics/SyncBox/S589-102_SyncBox_Wiring_Diagram.pdf Connector Pinout] | ||
* [http://www.phas.ubc.ca/~mce/mcedocs/hardware/board_block_diagram/S589-001_Syncbox_Block_Diagram.pdf Block Diagram] | * [http://www.phas.ubc.ca/~mce/mcedocs/hardware/board_block_diagram/S589-001_Syncbox_Block_Diagram.pdf Block Diagram] | ||
| + | |||
| + | [[Category:Sync Box]] | ||
Latest revision as of 17:27, 31 July 2018
Related topics:
- ACDCU(0-7)
- 8 TTL outputs. Carries a high/low signal that enables/disables the MCE AC/DC converter.
- MCE(0-7)
- 8 Fibre outputs. Carries a 50 MHz Manchester-encoded signal containing data packets, which include incremented sequence numbers. Programmable as two sets of 4 outputs with differently spaced data packets on each.
- RTS-DV
- differential RS485 input. Detects falling edges from a Real-Time Sequencer (implemented by SCUBA2) which tells the Sync box when to tell the MCE's to collect data.
- OPTO-TTL
- TTL input, spare input to the command processor. ***Not currently used, and open for suggestions.
- RS232 RxTx
- TTL input and output, used to command the Sync Box from a PC.
- DV Spare 1
- differential RS485 output. Carries a 5 MHz clock signal that is synchronous with DV Spare 2. Now called Data Sync 2
- DV Spare 2
- differential RS485 output. Carries a 5 MHz data signal that is synchronized with DV Spare 1, and contains the same sequence numbers as the MCE(0-7) outputs. NOTE: This output only contains the DV info stream, but not the occurrences of Addr_Zero between DVs. Now called Data Sync 1
- Polarimeter
- output, available both as TTL and differential RS485, asserted for 1us on an Address-Return-to-Zero(ARZ) if a DV pulse is detected since the last ARZ. Now called Data Sync 4 and in firmware Rev 21, this output is duplicate of DV_Spare2 or 5MHz clock.
- FTS
- output, available both as TTL and differential RS485, asserted for 1us on an Address-Return-to-Zero(ARZ) if a DV pulse is detected since the last ARZ. Now called Data Sync 3 and in firmware Rev 21, this output is duplicate of DV_Spare1 or 5MHz data-stream.
- TTL-IN
- SMB TTL input, spare input to the FPGA.
- TTL-OUT
- SMB TTL output. Carries a 50 MHz clock signal.
- Power
- 47–440Hz, 85–265VAC mains power over a 3-pin HP-style power connector.
Signal Translation table between Rack-mount and DC-in versions of Sync Box
| AC-in | DC-in |
|---|---|
| DV_Spare1 | data_sync1 |
| DV_Spare2 | data_sync2 |
| DV_OUT_FTS | data_sync4 |
| DV_OUT_POL | data_sync3 |
WARNING: signal polarity may be swapped on data_sync1 and data_sync2.
