Difference between revisions of "Bias Card firmware"
From MCEWiki
(→Revision 5.0.0) |
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== Revision 5.0.0 == | == Revision 5.0.0 == | ||
| − | * '''Filename:''' | + | * '''Filename:''' bc_v05000000_22dec2008.sof |
* '''To Do:''' | * '''To Do:''' | ||
| Line 20: | Line 20: | ||
** None yet reported | ** None yet reported | ||
| − | * '''FPGA Resource Usage''' ( | + | * '''FPGA Resource Usage''' (bias_card.fit.rpt): |
+---------------------------------------------------------------------+ | +---------------------------------------------------------------------+ | ||
; Fitter Summary ; | ; Fitter Summary ; | ||
| Line 40: | Line 40: | ||
+--------------------------+------------------------------------------+ | +--------------------------+------------------------------------------+ | ||
| − | * '''Timing Analyzer Summary''' ( | + | * '''Timing Analyzer Summary''' (bias_card.tan.rpt): |
+---------------------------------------------------------------------- | +---------------------------------------------------------------------- | ||
; Timing Analyzer Summary | ; Timing Analyzer Summary | ||
Revision as of 15:33, 17 September 2009
Contents
Recommended Firmware Revisions
- Please see the recommend firmware revisions page.
Firmware Revision Listing
Revision 5.0.0
- Filename: bc_v05000000_22dec2008.sof
- To Do:
- ---
- Features:
- IMPORTANT: Must be used in conjunction with firmware v05000000 of all other cards!!!
- To allow enough data bandwidth, the spare LVDS line from each card to the Clock Card is now used
- Details:
- ---
- Bugs:
- None yet reported
- FPGA Resource Usage (bias_card.fit.rpt):
+---------------------------------------------------------------------+ ; Fitter Summary ; +--------------------------+------------------------------------------+ ; Fitter Status ; Successful - Tue Jan 13 16:19:16 2009 ; ; Quartus II Version ; 8.1 Build 163 10/28/2008 SJ Full Version ; ; Revision Name ; addr_card ; ; Top-level Entity Name ; addr_card ; ; Family ; Stratix ; ; Device ; EP1S10F780C5 ; ; Timing Models ; Final ; ; Total logic elements ; 9,383 / 10,570 ( 89 % ) ; ; Total pins ; 279 / 427 ( 65 % ) ; ; Total virtual pins ; 0 ; ; Total memory bits ; 196,096 / 920,448 ( 21 % ) ; ; DSP block 9-bit elements ; 8 / 48 ( 17 % ) ; ; Total PLLs ; 1 / 6 ( 17 % ) ; ; Total DLLs ; 0 / 2 ( 0 % ) ; +--------------------------+------------------------------------------+
- Timing Analyzer Summary (bias_card.tan.rpt):
+---------------------------------------------------------------------- ; Timing Analyzer Summary +----------------------------------------------------------+----------+ ; Type ; Slack ; +----------------------------------------------------------+----------+ ; Worst-case tsu ; N/A ; ; Worst-case tco ; N/A ; ; Worst-case th ; N/A ; ; Clock Setup: 'ac_pll:pll0|altpll:altpll_component|_clk0' ; 2.617 ns ; ; Clock Setup: 'ac_pll:pll0|altpll:altpll_component|_clk2' ; 4.588 ns ; ; Clock Hold: 'ac_pll:pll0|altpll:altpll_component|_clk0' ; 0.539 ns ; ; Clock Hold: 'ac_pll:pll0|altpll:altpll_component|_clk2' ; 0.658 ns ; ; Total number of failed paths ; ; +----------------------------------------------------------+----------+
Revision 1.4.2
There is no information on this.
Revision 1.4.1
- bc_v01040001_25jan2008.sof
Features:
- Added card_type and scratch commands
- Integrated fw_rev and slot_id as part of all_cards
- Added provisions for safe state machines to fix the reset problem.
- Added lvds_tx = 0 so clock-card can check whether the card is plugged in using this spare lvds line.
Bugs: None so far
