Difference between revisions of "Bias Card firmware"
From MCEWiki
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| − | == Latest | + | = Firmware Revision Listing = |
| − | ''' | + | |
| + | == Revision 5.0.0 (Latest Release) == | ||
| + | * '''Filename:''' ac_v05000000_22dec2008.sof | ||
| + | |||
| + | * '''To Do:''' | ||
| + | ** --- | ||
| + | |||
| + | * '''Features:''' | ||
| + | ** IMPORTANT: Must be used in conjunction with firmware v05000000 of all other cards!!! | ||
| + | ** To allow enough data bandwidth, the spare LVDS line from each card to the Clock Card is now used | ||
| + | |||
| + | * '''Details:''' | ||
| + | ** --- | ||
| + | |||
| + | * '''Bugs:''' | ||
| + | ** None yet reported | ||
| + | |||
| + | * '''FPGA Resource Usage''' (clk_card.fit.rpt): | ||
| + | +---------------------------------------------------------------------+ | ||
| + | ; Fitter Summary ; | ||
| + | +--------------------------+------------------------------------------+ | ||
| + | ; Fitter Status ; Successful - Tue Jan 13 16:19:16 2009 ; | ||
| + | ; Quartus II Version ; 8.1 Build 163 10/28/2008 SJ Full Version ; | ||
| + | ; Revision Name ; addr_card ; | ||
| + | ; Top-level Entity Name ; addr_card ; | ||
| + | ; Family ; Stratix ; | ||
| + | ; Device ; EP1S10F780C5 ; | ||
| + | ; Timing Models ; Final ; | ||
| + | ; Total logic elements ; 9,383 / 10,570 ( 89 % ) ; | ||
| + | ; Total pins ; 279 / 427 ( 65 % ) ; | ||
| + | ; Total virtual pins ; 0 ; | ||
| + | ; Total memory bits ; 196,096 / 920,448 ( 21 % ) ; | ||
| + | ; DSP block 9-bit elements ; 8 / 48 ( 17 % ) ; | ||
| + | ; Total PLLs ; 1 / 6 ( 17 % ) ; | ||
| + | ; Total DLLs ; 0 / 2 ( 0 % ) ; | ||
| + | +--------------------------+------------------------------------------+ | ||
| + | |||
| + | * '''Timing Analyzer Summary''' (clk_card.tan.rpt): | ||
| + | +---------------------------------------------------------------------- | ||
| + | ; Timing Analyzer Summary | ||
| + | +----------------------------------------------------------+----------+ | ||
| + | ; Type ; Slack ; | ||
| + | +----------------------------------------------------------+----------+ | ||
| + | ; Worst-case tsu ; N/A ; | ||
| + | ; Worst-case tco ; N/A ; | ||
| + | ; Worst-case th ; N/A ; | ||
| + | ; Clock Setup: 'ac_pll:pll0|altpll:altpll_component|_clk0' ; 2.617 ns ; | ||
| + | ; Clock Setup: 'ac_pll:pll0|altpll:altpll_component|_clk2' ; 4.588 ns ; | ||
| + | ; Clock Hold: 'ac_pll:pll0|altpll:altpll_component|_clk0' ; 0.539 ns ; | ||
| + | ; Clock Hold: 'ac_pll:pll0|altpll:altpll_component|_clk2' ; 0.658 ns ; | ||
| + | ; Total number of failed paths ; ; | ||
| + | +----------------------------------------------------------+----------+ | ||
| + | |||
| + | == Revision 1.4.1 == | ||
| + | * bc_v01040001_25jan2008.sof | ||
Features: | Features: | ||
| Line 9: | Line 63: | ||
Bugs: None so far | Bugs: None so far | ||
| − | + | = Firmware Links = | |
* [http://www.phas.ubc.ca/~mce/mcedocs/firmware/bc_fpga_programming_file_catalogue.pdf Bias Card Firmware Catalog] | * [http://www.phas.ubc.ca/~mce/mcedocs/firmware/bc_fpga_programming_file_catalogue.pdf Bias Card Firmware Catalog] | ||
* [http://www.phas.ubc.ca/~mce/mcedocs/firmware/ Firmware .sof & .pof Downloads] | * [http://www.phas.ubc.ca/~mce/mcedocs/firmware/ Firmware .sof & .pof Downloads] | ||
| − | + | = Wiki Links = | |
* [http://e-mode.phas.ubc.ca/mcewiki/index.php/MCE_firmware MCE Firmware Page] | * [http://e-mode.phas.ubc.ca/mcewiki/index.php/MCE_firmware MCE Firmware Page] | ||
* [http://e-mode.phas.ubc.ca/mcewiki/index.php/Main_Page MCE Main Page] | * [http://e-mode.phas.ubc.ca/mcewiki/index.php/Main_Page MCE Main Page] | ||
Revision as of 18:10, 19 January 2009
Contents
Firmware Revision Listing
Revision 5.0.0 (Latest Release)
- Filename: ac_v05000000_22dec2008.sof
- To Do:
- ---
- Features:
- IMPORTANT: Must be used in conjunction with firmware v05000000 of all other cards!!!
- To allow enough data bandwidth, the spare LVDS line from each card to the Clock Card is now used
- Details:
- ---
- Bugs:
- None yet reported
- FPGA Resource Usage (clk_card.fit.rpt):
+---------------------------------------------------------------------+ ; Fitter Summary ; +--------------------------+------------------------------------------+ ; Fitter Status ; Successful - Tue Jan 13 16:19:16 2009 ; ; Quartus II Version ; 8.1 Build 163 10/28/2008 SJ Full Version ; ; Revision Name ; addr_card ; ; Top-level Entity Name ; addr_card ; ; Family ; Stratix ; ; Device ; EP1S10F780C5 ; ; Timing Models ; Final ; ; Total logic elements ; 9,383 / 10,570 ( 89 % ) ; ; Total pins ; 279 / 427 ( 65 % ) ; ; Total virtual pins ; 0 ; ; Total memory bits ; 196,096 / 920,448 ( 21 % ) ; ; DSP block 9-bit elements ; 8 / 48 ( 17 % ) ; ; Total PLLs ; 1 / 6 ( 17 % ) ; ; Total DLLs ; 0 / 2 ( 0 % ) ; +--------------------------+------------------------------------------+
- Timing Analyzer Summary (clk_card.tan.rpt):
+----------------------------------------------------------------------
- Timing Analyzer Summary
+----------------------------------------------------------+----------+
- Type ; Slack ;
+----------------------------------------------------------+----------+
- Worst-case tsu ; N/A ;
- Worst-case tco ; N/A ;
- Worst-case th ; N/A ;
- Clock Setup
- 'ac_pll:pll0|altpll:altpll_component|_clk0' ; 2.617 ns ;
- Clock Setup
- 'ac_pll:pll0|altpll:altpll_component|_clk2' ; 4.588 ns ;
- Clock Hold
- 'ac_pll:pll0|altpll:altpll_component|_clk0' ; 0.539 ns ;
- Clock Hold
- 'ac_pll:pll0|altpll:altpll_component|_clk2' ; 0.658 ns ;
- Total number of failed paths ; ;
+----------------------------------------------------------+----------+
Revision 1.4.1
- bc_v01040001_25jan2008.sof
Features:
- Added card_type and scratch commands
- Integrated fw_rev and slot_id as part of all_cards
- Added provisions for safe state machines to fix the reset problem.
- Added lvds_tx = 0 so clock-card can check whether the card is plugged in using this spare lvds line.
Bugs: None so far
