Difference between revisions of "Readout Card firmware"
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** The quartus.ini file was not present in the synth directory during synthesis. | ** The quartus.ini file was not present in the synth directory during synthesis. | ||
* '''FPGA Resource Usage''' (readout_card.fit.rpt): | * '''FPGA Resource Usage''' (readout_card.fit.rpt): | ||
| − | + | +--------------------------------------------------------------------------+ | |
| − | Fitter | + | ; Fitter Summary ; |
| − | + | +--------------------------+-----------------------------------------------+ | |
| − | + | ; Fitter Status ; Successful - Mon Sep 29 16:29:56 2008 ; | |
| − | + | ; Quartus II Version ; 8.0 Build 231 07/10/2008 SP 1 SJ Full Version ; | |
| − | + | ; Revision Name ; readout_card ; | |
| − | + | ; Top-level Entity Name ; readout_card ; | |
| − | + | ; Family ; Stratix ; | |
| − | + | ; Device ; EP1S40F780C6 ; | |
| − | + | ; Timing Models ; Final ; | |
| − | + | ; Total logic elements ; 27,099 / 41,250 ( 66 % ) ; | |
| − | + | ; Total pins ; 358 / 616 ( 58 % ) ; | |
| − | + | ; Total virtual pins ; 0 ; | |
| − | + | ; Total memory bits ; 406,016 / 3,423,744 ( 12 % ) ; | |
| − | + | ; DSP block 9-bit elements ; 76 / 112 ( 68 % ) ; | |
| − | + | ; Total PLLs ; 1 / 6 ( 17 % ) ; | |
| − | + | ; Total DLLs ; 0 / 2 ( 0 % ) ; | |
| − | + | +--------------------------+-----------------------------------------------+ | |
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* '''FPGA Timing Analysis''' (readout_card.tan.rpt): | * '''FPGA Timing Analysis''' (readout_card.tan.rpt): | ||
-------------------------------------------------------------------------- | -------------------------------------------------------------------------- | ||
Revision as of 16:02, 28 October 2008
Contents
- 1 Recommended Firmware Revisions
- 2 Complete Firmware Revision Listing
- 2.1 Revision 4.4.0 (in testing phase)
- 2.2 Revision 4.0.c (latest release)
- 2.3 Revision 4.0.b (buggy!)
- 2.4 Revision 4.0.a (buggy!)
- 2.5 Revision 4.0.9 (buggy!)
- 2.6 Revision 4.0.8
- 2.7 Revision 4.3.7
- 2.8 Revision 4.2.7
- 2.9 Revision 4.1.7
- 2.10 Revision 4.0.6 (buggy!)
- 2.11 Revision 4.0.5
- 2.12 Revision 3.0.19
- 2.13 Old Firmware Revisions
- 3 To-Do List
- 4 RC Synthesis Notes
- 5 RC FPGA Utilization
Recommended Firmware Revisions
- 4.0.c for normal operation (http://www.phas.ubc.ca/~mce/mcedocs/firmware/rc_v0400000c_15aug2008.sof)
- 4.3.7 for 50MHz data acquisition (14 bit) (http://www.phas.ubc.ca/~mce/mcedocs/firmware/rc_v04030007_26may2008_raw.sof)
- 4.2.7 for 50MHz data acquisition (8 bit)
Complete Firmware Revision Listing
Revision 4.4.0 (in testing phase)
- Filename: rc_v04040000_02oct2008
- Features:
- Reinstated the data modes in wbs_frame_data.vhd that were removed in 4.0.c. This firmware has the following modes: 0, 1, 2, 4, 5, 7, 10. The modes that are not present are: 3 (raw data), 6 (replaced by data_mode = 7), 8 (replaced by data_mode = 10), 9 (replaced by data_mode = 10). For more information on data modes, see Data mode.
- Simplified the FSM logic in wbs_frame_data.vhd that determines when to transition from IDLE to WSS1. This was done to lower the number of gates in that path, and ease the timing.
- Re-integrated the id_thermo and fpga_thermo block in the readout_card.vhd top level that was removed in 4.0.c.
- Removed the sticky bit in fsfb_corr.vhd, which was enabled when flux-jumping was turned on. Because the feedback is signed, the sticky bit would usually reflect the value of the 14th bit, except in situations when the number of flux quanta to jump was greater than 1 (i.e. cosmic rays, IV-curves, etc). Flux jumps are made at a maximum rate of one per frame period, so that if the First-Stage Feedback increased past the 13th bit, it would not be reflected in the feedback applied. Now it is.
- Removed the z_dat_i port in fsfb_processor.vhd and fsfb_calc_pack.vhd to the fsfb_proc_pidz block, in an effort to make it clearer within that block that the z-term is always = 0.
- Removed the z-term sign extension in fsfb_proc_pidz.vhd, and the [d-term + z-term] adder to free up DSP resources since the z-term is always = 0.
- Adjusted the indentation in fsfb_io_controller.vhd to make the file more readable.
- Moved the tga_o signal out of the dispatch_wishbone.vhd FSM, and made it a continuous assignment. This signal had one of the highest fan-out counts in the RTL design, and actually was impossible to route in Stratix III chips in its previous configuration because of the number of gates on the fan-out. As a consequence of making it a continuous assignment, the Stratix III fitter was able to succeed, and the Stratix I timing characteristics were greatly improved. This is the most significant change in this revision. This change single-handedly increased the minimum slack from 1.282 ns in v0400000c to 2.372 ns (or 56.7 MHz max) in this revision.
- Bugs:
- None reported yet
- Synthesis Notes:
- The quartus.ini file was not present in the synth directory during synthesis.
- FPGA Resource Usage (readout_card.fit.rpt):
+--------------------------------------------------------------------------+ ; Fitter Summary ; +--------------------------+-----------------------------------------------+ ; Fitter Status ; Successful - Mon Sep 29 16:29:56 2008 ; ; Quartus II Version ; 8.0 Build 231 07/10/2008 SP 1 SJ Full Version ; ; Revision Name ; readout_card ; ; Top-level Entity Name ; readout_card ; ; Family ; Stratix ; ; Device ; EP1S40F780C6 ; ; Timing Models ; Final ; ; Total logic elements ; 27,099 / 41,250 ( 66 % ) ; ; Total pins ; 358 / 616 ( 58 % ) ; ; Total virtual pins ; 0 ; ; Total memory bits ; 406,016 / 3,423,744 ( 12 % ) ; ; DSP block 9-bit elements ; 76 / 112 ( 68 % ) ; ; Total PLLs ; 1 / 6 ( 17 % ) ; ; Total DLLs ; 0 / 2 ( 0 % ) ; +--------------------------+-----------------------------------------------+
- FPGA Timing Analysis (readout_card.tan.rpt):
-------------------------------------------------------------------------- Timing Analyzer Summary -------------------------------------------------------------+-----------+ Type ; Slack ; -------------------------------------------------------------+-----------+ Worst-case tsu ; N/A ; Worst-case tco ; N/A ; Worst-case th ; N/A ; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.372 ns ; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 4.052 ns ; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.066 ns ; Clock Hold: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 0.741 ns ; Clock Hold: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 0.761 ns ; Clock Hold: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 0.788 ns ; Total number of failed paths ; ; -------------------------------------------------------------+-----------+
Revision 4.0.c (latest release)
- Filename: rc_v0400000c_15aug2008.sof
- Features:
- Only has data modes 0, 1, 4, and 10.
- Fixed the bug that exists in 4.0.b, 4.0.a, and 4.0.9 that prevented the fb_const value from being applied to channel zero (wbs_fb_data.vhd).
- Changed a counter in the dispatch block to ease timing constraints in synthesis (dispatch_wishbone.vhd)
- Updated the tagged versions of dispatch.vhd , dispatch_cmd_receive.vhd, and dispatch_reply_transmit.vhd to the version that is used by all the other cards.
- Removed the fpga_termo (command: fpga_temp) and id_thermo (commands: card_temp, card_id) to ease timing constraints in synthesis (readout_card.vhd)
- Updated the tagged version of fpga_termo.vhd to include the new 'stale bit' feature
- Updated the tagged version of frame_timing_core.vhd to include the new 'err_o' interface
- Bugs:
- None reported yet
- Synthesis Notes:
- The quartus.ini file was not present in the synth directory during synthesis.
- FPGA Resource Usage:
Fitter Status : Successful - Thu Aug 14 17:55:33 2008 Quartus II Version : 8.0 Build 215 05/29/2008 SJ Full Version Revision Name : readout_card Top-level Entity Name : readout_card Family : Stratix Device : EP1S40F780C6 Timing Models : Final Total logic elements : 25,058 / 41,250 ( 61 % ) Total pins : 358 / 616 ( 58 % ) Total virtual pins : 0 Total memory bits : 400,896 / 3,423,744 ( 12 % ) DSP block 9-bit elements : 76 / 112 ( 68 % ) Total PLLs : 1 / 6 ( 17 % ) Total DLLs : 0 / 2 ( 0 % )
- Timing Analysis (readout_card.tan.rpt):
-------------------------------------------------------------------------- Timing Analyzer Summary -------------------------------------------------------------+-----------+ Type ; Slack ; -------------------------------------------------------------+-----------+ Worst-case tsu ; N/A ; Worst-case tco ; N/A ; Worst-case th ; N/A ; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.282 ns ; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.736 ns ; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.665 ns ; Clock Hold: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 0.741 ns ; Clock Hold: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 0.752 ns ; Clock Hold: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 0.811 ns ; Total number of failed paths ; ; -------------------------------------------------------------+-----------+
Revision 4.0.b (buggy!)
Note: This revision is on a watch list, after the bug detected 15 July 2008. See the bug section for more details.
- Filename : rc_v0400000b_04aug2008.sof
- Features
- data_mode 10 is added to provide more filtfb bits (compared to data mode 9) for planet observations. filtered_dat(27 downto 3) & flux_cnt_dat(6 downto 0)
- Bugs
- An unexplained bug that appeared in 4.0.a and may still be present in 4.0.b is a problem with the readout of channels being clipped out of data reporting. Bug 1 Notes
- Synthesis note
- Quartus.ini removed.
Revision 4.0.a (buggy!)
Note: This revision is on a watch list, after the bug detected 15 July 2008. See the bug section for more details.
- Filename : rc_v0400000a_07jul2008.sof
- Bug Fix
- mce_status and adc_offset/flx_quanta commands do not fail after power up.
- Synthesis note
- Quartus.ini removed.
- Bugs
- Seems to clip out channel 0 from data reporting.
Revision 4.0.9 (buggy!)
- Filename : rc_v04000009_26jun2008.sof
- Features
- sa_bias and offset DACs only refreshed when new values are written. (in previous versions, DACs were refreshed every frame)
- Bugs
- fb_const0 commands to channel 0 do not work. The value is stored in the register, but not applied to the DAC. Thus, read-back returns the correct value, but the DAC does not.
- reading flx_quanta and adc_offset right after power up hangs the reply datapath to CC. resetmce clears this error as temporary solution. the problem is caused by first read ack of the wishbone slave.
Revision 4.0.8
- Filename : rc_v04000008_26jun2008.sof
- Features
- The gaini, gainp, gaind resolution increased to 12-bit, i.e. -2048 to 2047 (formerly 10-bit).
- Bug fix
- the bug associated with gainpid read before mce_reset is fixed.
- Synthesis note
- Quartus.ini removed.
Revision 4.3.7
- Filename : rc_v04030007_26may2008_raw.sof
- Features
- 14-bit raw mode enabled to buffer a snapshot of 50MHz samples for 2 frames of row_len * num_rows samples.
- In order to extend the raw-mode to 14-bit, an assumption is made that the raw buffer is not written to while being read. Therefore, make sure there is at least 2*row_len*num_rows*20ns between issuing captr_raw command and reading back the raw data.
- In order to save RAM for raw mode, two memory-intensive features are disabled:
- low-pass filter disabled ( mixed filtfb data modes 6, 7, 9 are also disabled)
- PID (gainp0, gaini0, gaind0) readback disabled. one can still set PID values and run servo, but can not read back the values.
Revision 4.2.7
- Filename : rc_v04020007_24may2008_raw.sof
- Features
- raw mode enabled to buffer a snapshot of 50MHz samples for 2 frames of row_len * num_rows samples.
- In order to save RAM for raw mode, two memory-intensive features are disabled:
- low-pass filter disabled ( mixed filtfb data modes 6, 7, 9 are also disabled)
- PID (gainp0, gaini0, gaind0) readback disabled. one can still set PID values and run servo, but can not read back the values.
- Bug fix
- the bug associated with reading from raw-buffer is fixed.
Revision 4.1.7
- Filename : rc_v04010007_25apr2008_raw.sof
- Features
- raw mode enabled to buffer a snapshot of 50MHz samples for 2 frames of row_len * num_rows samples.
- In order to save RAM for raw mode, two memory-intensive features are disabled:
- low-pass filter disabled ( mixed filtfb data modes 6, 7, 9 are also disabled)
- PID (gainp0, gaini0, gaind0) readback disabled. one can still set PID values and run servo, but can not read back the values.
- Bugs
- after each readout frame, raw-buffer readout counter falls behind by 3 and this causes skipping 3 50MHz samples in the data stream and column-data being messed up in subsequent frames. Data can be rearranged by post processing.
Revision 4.0.6 (buggy!)
- Filename : rc_v04000006_15feb2008.sof or .pof
- Features
- bugfix: unreliable reset due to unsafe and incomplete state machines is fixed.
- bugfix: flux_jump sign problem fixed, so far proved in const_mode, to be tested in servo_mode with cold setup.
- servo_mode=2 or ramp previously only went from 0 to ramp_amp, but now goes from -8192 to -8192+ramp_amp
- new commands are added: scratch and card_type. Scratch takes 8 values and can be used by software to detect reset.
- slot_id and fw_rev are now integrated as part of all_cards.vhd
- lvds_tx_b=0, This will allow Clock Card to use the secondary backplane lvds line and check whether RC is plugged in.
- filter_coeff in misc_banks_admin commented as it is not implemented and causes timing problems.
- Bugs
- reading gainp/gaini/gaind right after power up hangs the reply datapath to CC. resetmce clears this error as temporary solution. the problem is caused by first read ack of pid_ram_admin.
- slot_id is only set after a resetmce is issued. (using the latest all_cards in the next revision will fix this)
- has spurious spikes on channel 7 data, which max out the integral, and cause the detectors to come unlocked. This firmware officially meets timing requirements, but the bug could be due to marginal timing on the longest data paths, i.e. ~0.1 ns in some cases.
Revision 4.0.5
- Filename : rc_v04000005_01nov2007.sof or .pof
- Features
- data mode 9 (mixed filt + flux jump) with windowing readjusted compared to data mode 8
- Bugs
- unreliable resetmce. Sometimes, firmware waked up non-responsive on lvds lines.
- In data mode 5 and 9, flux-jump counter is not reported properly due to a sign error. However, flux jumping works fine.
Revision 3.0.19
- Filename : rc_v03000019_16feb2007_raw.sof (no pof as one is not likely to run with this as regular firmware)
- Features
- data mode 3 is enabled.
- filter is disabled as a compromise to fit the raw-mode buffer.
- Bugs
- unreliable resetmce. Sometimes, firmware waked up non-responsive on lvds lines.
Old Firmware Revisions
- 4.0.4: rc_v04000004_11oct2007.sof data mode 8 added (mixed filt + flux jump)
- 4.0.3: rc_v04000003_19sep2007.sof data mode 7 bit split readjusted to 10b error being bit 4 to 14
- 4.0.2: rc_v04000002_11sep2007.sof pid resolution increased to 10b, data mode 7 added
- 4.0.1: rc_v04000001_06sep2007.sof
- 4.0.0: rc_v04000000_29aug2007.sof supports readout_row_index * bugs
To-Do List
- continuous readout mode where one column is read at frame rate, this means the output frame is regular size, but all entries relate to one column (high).
- reject single out-of-range adc sample based on (ern-ern-1 > 2*ern-1)
- reduce co-add storage from 32b wide to 24b (14b adc + 10b (for coadding up to sample_num=1024 samples)). This frees up resources generally on the RC. (High)
- reduce the width for pid calculations. This might relieve resource needs on the RC. (High, but maybe risky.)
- By using the MRAMs to a greater depth, we may be able to increase the number of raw data points stored.
RC Synthesis Notes
- Quartus.ini file had to exist in synth directory up to revision 4.0.a due to a bug that started in Quartus 6.1 and would synthesize away arbitrary parts of readout card. We contacted Altera at the time and they provided us the ini file. We have stopped using this file starting with rc_v04000008, although v04000009 does use it. This file needs to be used when Quartus synthesizes out blocks of firmware. If this occurs, the utilization drops well below 66%. If posssible, avoid using this file, because it causes timing violations.
- Timing: There is no "lock region" defined for readout card. Timing on readout card is tight and since version 3 or so any new feature would initially fail timing till some synthesis options were tweaked. One path that remains to be consistently marginal is from addr_gen counter (i.e. tga_o counter) in dispatch_wishbone.vhd to wishbone slaves particularly misc_banks_admin.vhd. Modules that are rewritten to address timing concerns are fsfb_corr, all_cards, misc_banks_admin, and finally instantiating an lpm counter instead of a counter from components library. Surprisingly, the lpm counter reduced 87 failures to 37, although looking at the technology map viewer, it seemed that they were both synthesized the same.
- Compile time: This was at some point 4.5 hours, after going to dual core PC, this was reduced to 35 minutes. After extending pid gains to 12b and fixing offset/sa_bias update code, the compile time increased to 1.5hr again with utilization up to ~70%.
- wbs_fb_storage, ram_8x64, pid_ram had to be regenerated using latest (Q7.2) MegaWizard to get rid of the bug associated with failure to read after power up until a reset was issued.
- During simulations, the initialization of RAM block with .hex files needs to be disabled. This is done by commenting out the following lines from the MegaWizard generated Megafunction files (remember to un-comment them before synthesizing the code):
lpm_file => "C:/scuba2_repository/cards/readout_card/fsfb_calc/source/rtl/ram_40x64.hex", and lpm_file : STRING;
RC FPGA Utilization
- Normal-operation firmware:
Fitter Status : Successful - Mon Jul 07 17:50:07 2008 Quartus II Version : 7.2 Build 151 09/26/2007 SJ Full Version Device : EP1S40F780C6 Timing Models : Final Total logic elements : 27,213 / 41,250 ( 66 % ) Total pins : 358 / 616 ( 58 % ) Total memory bits : 405,504 / 3,423,744 ( 12 % ) * M512s ; 86 / 384 ( 22 % ) * M4Ks ; 183 / 183 ( 100 % ) * M-RAMs ; 0 / 4 ( 0 % ) DSP block 9-bit elements : 76 / 112 ( 68 % ) Total PLLs : 1 / 6 ( 17 % ) Total DLLs : 0 / 2 ( 0 % )
- Raw-mode firmware
Total memory bits : 1,242,112 / 3,423,744 ( 36 % ) ; * M512s ; 292 / 384 ( 76 % ) * M4Ks ; 183 / 183 ( 100 % ) * M-RAMs ; 4 / 4 ( 100 % )
