Difference between revisions of "Testing Clock Cards"

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(Created page with "== Setup == The following equipments are needed: * mas PC: An ubuntu-based PC with ARC-64 PCI card installed an running mas software. * 2-slot backplane with Clock Card plugged i…")
 
(lvds rx/tx or command/reply lines)
 
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The following equipments are needed:
 
The following equipments are needed:
 
* mas PC: An ubuntu-based PC with ARC-64 PCI card installed an running mas software.
 
* mas PC: An ubuntu-based PC with ARC-64 PCI card installed an running mas software.
* 2-slot backplane with Clock Card plugged in: Device under test (DUT) is plugged into this backplane during testing.
+
* A fully populated 5-MDM MCE subrack with Device under test (DUT) plugged into this backplane during testing.
 
* fibre-optic cable: connects mas-PC to Clock Card.
 
* fibre-optic cable: connects mas-PC to Clock Card.
 
* set of Linear supplies to power up the cards. (3V, 4.5V, 6.2V, -6.2V)
 
* set of Linear supplies to power up the cards. (3V, 4.5V, 6.2V, -6.2V)
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If you have all the above and '''if your DUT has already been smoke tested''', you are ready to start:
 
If you have all the above and '''if your DUT has already been smoke tested''', you are ready to start:
 +
# Connect all the cables.
 +
#unplug all cards from Subrack except Clock card unit under test, (just pull out, so they are not inserted)
 +
# Power on the MCE and if the clock card is not progammed, the red led should be on.
 +
 
== Configuring Clock Card ==
 
== Configuring Clock Card ==
 
The FPGA on clock card (U7) can be configured from one of the two on-board configuration devices (EPC16): A factory configuration device (U18) and an application configuration device (U17). The factory configuration is loaded upon power up and hard reset. The application configuration is loaded by issuing a command on the mas PC: wb cc config_app 1.
 
The FPGA on clock card (U7) can be configured from one of the two on-board configuration devices (EPC16): A factory configuration device (U18) and an application configuration device (U17). The factory configuration is loaded upon power up and hard reset. The application configuration is loaded by issuing a command on the mas PC: wb cc config_app 1.
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The FPGA and the application configuration device can be programmed through the front-panel JTAG port while the factory configuration device can be programmed from the on-board connector.  
 
The FPGA and the application configuration device can be programmed through the front-panel JTAG port while the factory configuration device can be programmed from the on-board connector.  
  
 
+
=== Programming via Front-panel JTAG connector===
# connect them up an power up the 2-slot backplane.
+
# Load FPGA firmware using Quartus. Firmware is located at http://e-mode.phas.ubc.ca/mce_firmware/. Run auto-detect and you should see list of devices. The part at the bottom of the list corresponts to Clock card FPGA and the part above it in the list is EPC16 or the "application configuration device". Right click on the row and choose a file to program. Load following firmware from the above directory: CC firmware 5.0.e, '''cc_v0500000e_15may2012.sof''' for FPGA and '''cc_v0500000e_15may2012.pof''' for EPC16. Then checkmark the program button for both devices and press start programming. The green LED should come up when programming is done.
# Load FPGA firmware using Quartus. Firmware is located at http://e-mode.phas.ubc.ca/mce_firmware/. Run auto-detect and you should see 4 devices. The part at the bottom of the list corresponts to Clock card FPGA. Load following firmware from the above directory: '''CC firmware 5.0.7''', '''BC firmware bc_v05030001_12apr2012.sof'''
+
# If the tx/rx fibers are connected right, the red LED is off and the green LED is on. If the Sync Box fiber is connected and Sync Box is on, then the amber LED is also off.
# On the 2-slot backplane there are two sets of dip switches. You need to set the one on the Bias card side to '''1110 (0xe)''', otherwise bc1 replies do not come back, because the card is not identified properly.
+
# Now make sure that the card communicates with the PC.  
# Now make sure both cards communicate with the PC. ssh to the PC running mas and connected to the 2-slot backplane trhough fibre cables and run the following command:
 
 
   mce_cmd -x rb cc fw_rev
 
   mce_cmd -x rb cc fw_rev
  
 
and you will see:
 
and you will see:
   Line  0 : ok : 0x5000007
+
   Line  0 : ok : 0x500000e
 +
 
 +
So far, '''you confirmed that FPGA is programmed successfully and the fiber interface is working.'''
 +
 
 +
Now, proceed to programming the factory-configuration device.
 +
 
 +
=== Programming via on-board P2 JTAG connector===
 +
#Now turn off the MCE,
 +
#unplug the Clock Card and move the JTAG programming cable from the front-panel to the on-board P2 connector. plug the card back in and let the cable slide through the slot.
 +
# Power on the MCE.
 +
# In Quartus, press on auto-detect and you should only see two devices listed. Choose the same pof file for EPC16.
 +
'''cc_v0500000e_15may2012.pof'''
 +
# Turn off the MCE, unplug the card and remove the JTAG cable. Then re-insert the card and power on the MCE.
 +
# The green LED should come on. Ths confirms that '''factory configuraiton is loaded successfully upon power up'''.
 +
 
 +
# Verify that the application configuration can be loaded successfuly:
 +
mce_cmd -x wb cc config_app 1
 +
The Green LED should momentarily go off, the red LED should momentarily turn on and then when firmware is loaded, green LED would be on and red is off.
 +
This shows that '''application configuration is loaded successfully'''.
  
and then type:
+
*'''Note 1''': Sometimes the reconfiguration time exceeds the timeout period and you get an "MCE timeout" message. Issue another command like rb cc fw_rev to verify that the FPGA was reconfigured successfully.
  mce_cmd -x rb bc1 fw_rev
+
*'''Note 2''': Sometimes when you switch between external and internal clock, you get an "'''Unexpected interface (DSP) error'''" caused by an accidental character transmit on the fiber during configuration switch over, if this happens, you need to reset the PCI card by issuing: mce_cmd -x dsp_reset.
and you will see
 
  Line  0 : ok : 0x5000005
 
  
 
== Testing General Features (card_all_test)==
 
== Testing General Features (card_all_test)==
We run a scrip on the mas PC to issue commands over the fibre to test the Readout Card unit under test. In this script, the following circuits are tested: LEDs, silicon ID chip, slot-id and pcb-revision identification pins, FPGA and board temperature sense circuitry, LVDS communication pairs.
+
The following script is used to test features that are common to all MCE cards: LED, silicon id, card_type, PCB revision, LEDs, dip switches, etc.
  
On mas PC, type: '''card_all_test'''
+
On mas PC, type:  
 +
card_all_test -c cc SCC-NNN
  
 
The output should look like:
 
The output should look like:
 
   ****** Check to make sure the LEDs on the target card switched status! ****
 
   ****** Check to make sure the LEDs on the target card switched status! ****
   Unit Under Test  :  rc1
+
   Unit Under Test  :  CC
   Serial Number    :  SRC-216
+
   Serial Number    :  SCC-069
   Firmware Revision:  -0xfffa
+
   Firmware Revision:  5.0.e
 
   card_id          :  0x20be502
 
   card_id          :  0x20be502
   slot_id          :  [4]
+
   slot_id          :  [8]
   card_type        :  [2]
+
   card_type        :  3
   card_rev        :  0
+
   card_rev        :  D
 
   fpga_temp        :  34 C pass
 
   fpga_temp        :  34 C pass
 
   card_temp        :  28 C pass
 
   card_temp        :  28 C pass
   results are in  :  /data/cryo/current_data/SRC-216_1285959943_all_test
+
   results are in  :  /data/cryo/current_data/SCC-069_1285959943_all_test
  
 
copy the results into the test logfile and record the card_id on [[MCE CARD Serial-Number Lookup]]
 
copy the results into the test logfile and record the card_id on [[MCE CARD Serial-Number Lookup]]
  
== Testing DACS ==
+
== testing communication with backplane silicon_id chip==
In this stage, we test the 16-bit serial DACs: 32 single-ended bias lines and 12 differential bias lines (ln_bias). For serial DACs, the script only tries loading 3 values: 0, midrange, full-range.
+
issue following commands to make sure clock card can read the silicon_id and temperature from the id chip on the backplane:
 +
mce_cmd -x rb cc box_id
 +
mce_cmd -x rb cc box_temp
 +
 
 +
record the results in logfile
 +
== lvds rx/tx or command/reply lines==
  
To run the test, on mas PC, connect the multiplexer board via USB,  HP 34401A multimeter via RS-232, and run the '''bc_ate.py''' script by typing '''python bc_ate.py SBC-nnn'''  where nnn is the card number.  This will create a CSV file named SBC-nnn.csv with the test results.
+
run mce_status -s|grep fw_rev
 +
and you should see all cards listed, make sure there are 9 replies.
 +
cc fw_rev : 0x500000e
 +
rc1 fw_rev : 0x5010005
 +
rc2 fw_rev : 0x5010005
 +
rc3 fw_rev : 0x5010005
 +
rc4 fw_rev : 0x5010005
 +
bc1 fw_rev : 0x5000000
 +
bc2 fw_rev : 0x5000000
 +
bc3 fw_rev : 0x5000000
 +
ac fw_rev : 0x5000004
  
When the '''bc_ate.py''' script is run, DACs are loaded with a set of fixed values that are measured by the RS232-connected multimeter and recorded in the CSV file.  Follow the instructions given by the python script and flip the switches on the multiplexer when prompted.
+
If any of the replies is ERROR and the card is present, then check you need to debug the corresponding lvds_rx on Clock Card.
  
After the fixed value tests are completed, a ramp is applied to the DACs and outputs need to be probed in all cases.
+
Record the result in logfile.
  
Here is a PASS criteria for the serial DACs. Verify that the numbers are within this range and save the generated CSV file in the same directory as the test log.
+
== Sync Box communication and clock circuitry ==
 +
Check the amber LED and it should be on if the Sync input is not connected or if the Sync Box is off. Check to see the LED go off when the Sync Box is turned on and the fiber cable is connected to the Sync input. Now on mas PC, issue the following commands:
 +
wb cc select_clk 1
 +
wb cc use_dv 2
 +
wb cc use_sync 2
 +
rb cc select_clk
  
{| border="1" class="Serial DACs codes"
+
The last command should return 1 which means the Clock Card is still running from the Sync Box clk.
|-
 
! Output
 
! 0x0000
 
! 0x8000
 
! 0xffff
 
! 0-2.5V Ramp
 
|-
 
| D00
 
| +-100mV
 
| 1.25V +-10mV
 
| 2.5V +-10mV
 
| OK
 
|-
 
| LN0 (in Rev D)
 
| +-100mV
 
| 1.25V +-10mV
 
| 2.5V +-10mV
 
| OK
 
|-
 
| LN0 (in Rev F)
 
| -2.5V +-10mV
 
| +-100mV
 
| 2.5V +-10mV
 
| OK
 
|}
 
  
== Testing Serial Configuration device and FPGA reconfiguration ==
+
'''Note''': ''Sometimes when you switch between external and internal clock, you get an "'''Unexpected interface (DSP) error'''" caused by an accidental character transmit on the fiber, if this happens, you need to reset the PCI card by issuing'': mce_cmd -x dsp_reset.
Load firmware into the configuration device as oppose to the FPGA now. The parallel configuration device, EPC16, is programmed through the JTAG port on the Clock-Card front panel. Here are the steps:
 
* Run Quartus programmer and click on auto-detect. You should see 4 devices in the list.
 
* Select EPC16 device on top and click on change file to choose ''' bc_v05030001_12apr2012.pof''' (found in http://e-mode.phas.ubc.ca/mce_firmware/ )
 
* Now select the device and click on program.
 
* When programming is done, turn off the power and turn it back on. If the Green Light is on, it means that you have successfully programmed the configuration device.
 
* on mas prompt, type:''' mce_cmd -x rb bc1 fw_rev''' and you should see the firmware revision of the firmware you loaded. This is usually noted in the filename of the file you chose.
 
  
Record the result in logfile.
+
Take some data to verify that the manchester decoder is working:
 +
mce_run test_data_xxxx 100 1
 +
 
 +
check to see whether the file exist and has some data.
 +
Then unplug the Sync input and issue:
 +
wb cc led 7
 +
 
 +
no reply should come back. Now issue
 +
rb cc select_clk
 +
and the result should be 0 which means the clock has fallen back on the internal clock on clock card.
 +
 
 +
== reset switch and brst line ==
 +
 
 +
Press the switch on the front panel and you should see the green LED go off and red LED go on indicating configuration file reloaded. After few seconds, the red one should go off and green one come back on indicating that the reset switch works properly.
 +
 
 +
To make sure brst line on Clock Card is working, toggle the LEDs from their default state and then issue a reset command and make sure the LEDs go to their default state (only Green on) which would mean the reset worked.  
 +
wb rc1 led 7
 +
(red and amber LED go on, green goes off)
 +
mce_cmd -x mce_reset
  
 
log results
 
log results
 +
 +
[[Category:Clock Card]]
 +
[[Category:MCE Script]]
 +
[[Category:Testing]]

Latest revision as of 10:21, 1 August 2018

Setup

The following equipments are needed:

  • mas PC: An ubuntu-based PC with ARC-64 PCI card installed an running mas software.
  • A fully populated 5-MDM MCE subrack with Device under test (DUT) plugged into this backplane during testing.
  • fibre-optic cable: connects mas-PC to Clock Card.
  • set of Linear supplies to power up the cards. (3V, 4.5V, 6.2V, -6.2V)
  • Altera USB programmer: attached to the JTAG connector in Clock card front panel.
  • PC with Quartus installed: used to program FPGA and configuration devices on Readout Card.
  • Sync Box with a fiber-optic cable connecting a fiber output to the sync input of the Clock Card.

If you have all the above and if your DUT has already been smoke tested, you are ready to start:

  1. Connect all the cables.
  2. unplug all cards from Subrack except Clock card unit under test, (just pull out, so they are not inserted)
  3. Power on the MCE and if the clock card is not progammed, the red led should be on.

Configuring Clock Card

The FPGA on clock card (U7) can be configured from one of the two on-board configuration devices (EPC16): A factory configuration device (U18) and an application configuration device (U17). The factory configuration is loaded upon power up and hard reset. The application configuration is loaded by issuing a command on the mas PC: wb cc config_app 1.

The FPGA and the application configuration device can be programmed through the front-panel JTAG port while the factory configuration device can be programmed from the on-board connector.

Programming via Front-panel JTAG connector

  1. Load FPGA firmware using Quartus. Firmware is located at http://e-mode.phas.ubc.ca/mce_firmware/. Run auto-detect and you should see list of devices. The part at the bottom of the list corresponts to Clock card FPGA and the part above it in the list is EPC16 or the "application configuration device". Right click on the row and choose a file to program. Load following firmware from the above directory: CC firmware 5.0.e, cc_v0500000e_15may2012.sof for FPGA and cc_v0500000e_15may2012.pof for EPC16. Then checkmark the program button for both devices and press start programming. The green LED should come up when programming is done.
  2. If the tx/rx fibers are connected right, the red LED is off and the green LED is on. If the Sync Box fiber is connected and Sync Box is on, then the amber LED is also off.
  3. Now make sure that the card communicates with the PC.
 mce_cmd -x rb cc fw_rev

and you will see:

 Line   0 : ok : 0x500000e

So far, you confirmed that FPGA is programmed successfully and the fiber interface is working.

Now, proceed to programming the factory-configuration device.

Programming via on-board P2 JTAG connector

  1. Now turn off the MCE,
  2. unplug the Clock Card and move the JTAG programming cable from the front-panel to the on-board P2 connector. plug the card back in and let the cable slide through the slot.
  3. Power on the MCE.
  4. In Quartus, press on auto-detect and you should only see two devices listed. Choose the same pof file for EPC16.

cc_v0500000e_15may2012.pof

  1. Turn off the MCE, unplug the card and remove the JTAG cable. Then re-insert the card and power on the MCE.
  2. The green LED should come on. Ths confirms that factory configuraiton is loaded successfully upon power up.
  1. Verify that the application configuration can be loaded successfuly:
mce_cmd -x wb cc config_app 1

The Green LED should momentarily go off, the red LED should momentarily turn on and then when firmware is loaded, green LED would be on and red is off. This shows that application configuration is loaded successfully.

  • Note 1: Sometimes the reconfiguration time exceeds the timeout period and you get an "MCE timeout" message. Issue another command like rb cc fw_rev to verify that the FPGA was reconfigured successfully.
  • Note 2: Sometimes when you switch between external and internal clock, you get an "Unexpected interface (DSP) error" caused by an accidental character transmit on the fiber during configuration switch over, if this happens, you need to reset the PCI card by issuing: mce_cmd -x dsp_reset.

Testing General Features (card_all_test)

The following script is used to test features that are common to all MCE cards: LED, silicon id, card_type, PCB revision, LEDs, dip switches, etc.

On mas PC, type:

card_all_test -c cc SCC-NNN

The output should look like:

 ****** Check to make sure the LEDs on the target card switched status! ****
 Unit Under Test  :  CC
 Serial Number    :  SCC-069
 Firmware Revision:  5.0.e
 card_id          :  0x20be502
 slot_id          :  [8]
 card_type        :  3
 card_rev         :  D
 fpga_temp        :  34 C pass
 card_temp        :  28 C pass
 results are in   :  /data/cryo/current_data/SCC-069_1285959943_all_test

copy the results into the test logfile and record the card_id on MCE CARD Serial-Number Lookup

testing communication with backplane silicon_id chip

issue following commands to make sure clock card can read the silicon_id and temperature from the id chip on the backplane:

mce_cmd -x rb cc box_id
mce_cmd -x rb cc box_temp

record the results in logfile

lvds rx/tx or command/reply lines

run mce_status -s|grep fw_rev and you should see all cards listed, make sure there are 9 replies. cc fw_rev : 0x500000e rc1 fw_rev : 0x5010005 rc2 fw_rev : 0x5010005 rc3 fw_rev : 0x5010005 rc4 fw_rev : 0x5010005 bc1 fw_rev : 0x5000000 bc2 fw_rev : 0x5000000 bc3 fw_rev : 0x5000000 ac fw_rev : 0x5000004

If any of the replies is ERROR and the card is present, then check you need to debug the corresponding lvds_rx on Clock Card.

Record the result in logfile.

Sync Box communication and clock circuitry

Check the amber LED and it should be on if the Sync input is not connected or if the Sync Box is off. Check to see the LED go off when the Sync Box is turned on and the fiber cable is connected to the Sync input. Now on mas PC, issue the following commands:

wb cc select_clk 1
wb cc use_dv 2
wb cc use_sync 2
rb cc select_clk 

The last command should return 1 which means the Clock Card is still running from the Sync Box clk.

Note: Sometimes when you switch between external and internal clock, you get an "Unexpected interface (DSP) error" caused by an accidental character transmit on the fiber, if this happens, you need to reset the PCI card by issuing: mce_cmd -x dsp_reset.

Take some data to verify that the manchester decoder is working:

mce_run test_data_xxxx 100 1

check to see whether the file exist and has some data. Then unplug the Sync input and issue:

wb cc led 7

no reply should come back. Now issue

rb cc select_clk 

and the result should be 0 which means the clock has fallen back on the internal clock on clock card.

reset switch and brst line

Press the switch on the front panel and you should see the green LED go off and red LED go on indicating configuration file reloaded. After few seconds, the red one should go off and green one come back on indicating that the reset switch works properly.

To make sure brst line on Clock Card is working, toggle the LEDs from their default state and then issue a reset command and make sure the LEDs go to their default state (only Green on) which would mean the reset worked.

wb rc1 led 7 

(red and amber LED go on, green goes off)

mce_cmd -x mce_reset

log results