Sync Box firmware

Template:Hierarchy header There is an Altera CPLD (EPM570T144C3) and an Atmel micro-controller (AT89C51) on the Sync board.

• SyncBox CPLD Firmware Description [PDF] (SC2-ELE-S589-201)
• SyncBox Microcontroller Software Description [PDF] (SC2-ELE-S589-202)

Consequently, there are two sets of firmware:

• firmware for the CPLD part (*.pof file)
• firmware for the microcontroller (*.hex file)

Firmware Upgrade Instructions

To upgrade the Sync Box firmware,most times both the microcontroller and the CPLD firmware need to be reprogrammed.

The CPLD firmware can be loaded using the Altera USB-Blaster that connects to the on-board P23 JTAG header, and Quartus Programmer software. A *.pof file needs to be loaded.

The micro-controller firmware can be loaded using a USB cable that connects to the on-board J1 connector, and Flip Programmer software available from Atmel website. A *.hex file needs to be loaded. Alternately, see if you can use free software dfu-programmer on linux: Sync Box Firmware Upgrade using dfu-programmer.

For more details, see section 9 in: Sync Box User's Guide

Note: I had to install Flip on 3 computers before I could get the USB driver to work!

Firmware .hex & .pof Downloads

Revisions

Firmware set Rev. 31

Filename

sync_box_v31_21Jun2016.hex

sync_box_v31_21Jun2016.pof

Features

The two banks of Manchester outputs can now be configured independently. This permits up to 4 MCEs to share one timing configuration, while up to 4 other MCEs share a second timing configuration.

The microprocessor's on-board EEPROM can be used to load and save configurations. A preferred configuration can be loaded "on startup", so there is no need for per-experiment defaults.

Notes

The firmware version is not reported by the serial interface. Subsequent versions will report the version, so if you see the "eeprom" menu but no version number then you're probably looking at v31!

Firmware set Rev. 30

Features

The microprocessor code has been ported to the sdcc compiler. There are no changes in behaviour. This code should continue to work with CPLD code from version 1f.

Firmware set Rev. 22

Filename

sync_box_v22_26sep2014.hex

no change to cpld code

Features

Sync Box default values are set for ACT values: fr=38, num_rows=33, row_len=50

Firmware set Rev. 21

Filename

sync_box_v21_02sep2014.pof

no change to microcontroller code or *.hex file

Features

DV_FTS and DV_POL are now duplicate copies of DV_SPARE1 and DV_SPARE2, respectively. See IO for rackmount AC-in Sync Box

Firmware set Rev. 20

Filename

sync_box_v20_22aug2013.hex

Features

hard-coded Spider values of fr=120, num_rows=33, row_len=53 (which translates to row_len=106 on mce front)

firmware revision on rs232 interface now shows 20

Firmware set Rev. 1f

Filename

sync_box_v1f_25feb2010.pof

sync_box_v1f_25feb2010.hex

Features

adds a ckd command to the rs232 interface to adjust the frequency of DV_Spare1 and DV_Spare2 by setting a 50MHz divisor through the command.

when you turn on the sync box, the firmware revision 1f appears on the rs232 terminal

Firmware set Rev. 1e (6e?)

Filename

sync_box_v6e_11aug2008.pof

sync_box_v1c_17nov2006.hex

Features

added a 50MHz clock on SMA output of the Sync box

Note

Since the microcontroller code is still 1c and that is what is reported in rs232 terminal, there is no way to identify this set from a 1c set.

Firmware set Rev. 1c

Filename

sync_box_v6c_19oct2006.pof

sync_box_v1c_17nov2006.hex

Features

original firmware

Source code

The sync box source (both CPLD and Atmel code) is available in the sync_box project in the UBC SVN repository. So, something like this might work:

svn checkout --username=mceanon svn://e-mode.phas.ubc.ca/sync_box/trunk sync_box