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| − | :''[[Sync_Box#User.27s_Guide|Back to Sync Box Guide]]''
| + | #REDIRECT[[Sync Box#External connectors and I/O]] |
| − | | |
| − | ; MCE0 to MCE7
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| − | : 8 Fibre outputs. Carries a 50 MHz Manchester-encoded signal containing data packets, which include incremented sequence numbers. Programmable as two sets of 4 outputs with differently spaced data packets on each.
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| − | ; RS232 Command IO
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| − | : DB9 connector (CJ2), TTL input and output, used to command the Sync Box from a PC using a regular RS232 cable.
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| − | ; TTL-IN
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| − | : BNC connector (CJ5), TTL input, spare input to the FPGA. ***Not currently used, and open for suggestions.
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| − | ; TTL-OUT
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| − | : BNC connector (CJ6), TTL output. Carries a 50 MHz clock signal.
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| − | ; Power
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| − | : Circular connector (CP1), 5V input.
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| − | | |
| − | == '''Interface Connector: CJ3''' ==
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| − | A DB25 connector that provides the following auxiliary input/outputs:
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| − | ; DATA_VALID
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| − | : Differential RS485 input. Detects falling edges from a Real-Time Sequencer (implemented by SCUBA2) which tells the Sync box when to tell the MCE's to collect data.
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| − | ; DATA_SYNC1 (formerly DV_SPARE1)
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| − | : differential RS485 output. Carries a 5 MHz clock signal that is synchronous with DATA_SYNC2. (WARNING: signal polarity may be swapped)
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| − | ; DATA_SYNC2 (formerly DV_SPARE2)
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| − | : differential RS485 output. Carries a 5 MHz data signal that is synchronized with DATA_SYNC1, and contains the same frame sequence numbers as the MCE(0-7) outputs. NOTE: This output only contains the DV info stream (40-bit), but not the occurrences of Addr_Return-to-Zero between DVs. (WARNING: signal polarity may be swapped)
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| − | ; DATA_SYNC3
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| − | : output, available both as TTL '''and''' differential RS485, asserted for 1us on an Address-Return-to-Zero(ARZ) if a DV pulse is detected since the last ARZ.
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| − | ; DATA_SYNC4
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| − | : output, available both as TTL '''and''' differential RS485, asserted for 1us on an Address-Return-to-Zero(ARZ) if a DV pulse is detected since the last ARZ.
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| − | | |
| − | === Pinout ===
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| − | {|
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| − | |-
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| − | ! Pin !! Signal !! Pin !! Signal
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| − | |-
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| − | | '''1''' || Data_Valid+ || '''14''' || GND
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| − | |-
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| − | | '''2''' || Data_Valid- || '''15''' || Data_Sync1+
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| − | |-
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| − | | '''3''' || GND || '''16''' || Data_Sync1-
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| − | |-
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| − | | '''4''' || Data_Sync2+ || '''17''' || GND
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| − | |-
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| − | | '''5''' || Data_Sync2- || '''18''' || Data_Sync3+
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| − | |-
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| − | | '''6''' || GND || '''19''' || Data_Sync3-
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| − | |-
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| − | | '''7''' || Data_Sync3_TTL || '''20''' || GND
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| − | |-
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| − | | '''8''' || GND || '''21''' || Data_Sync4+
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| − | |-
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| − | | '''9''' || Data_Sync4_TTL || '''22''' || Data_Sync4-
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| − | |-
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| − | | '''10''' || ''N/C'' || '''23''' || GND
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| − | |-
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| − | | '''11''' || ''N/C'' || '''24''' || ''N/C''
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| − | |-
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| − | | '''12''' || ''N/C'' || '''25''' || ''N/C''
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| − | |-
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| − | | '''13''' || ''N/C''
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| − | |}
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| − | | |
| − | == Schematics ==
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| − | | |
| − | * [http://www.phas.ubc.ca/~mce/mcedocs/hardware/schematics/SyncBox/ELE-C589-102_Sync_Box_Connector_Pinouts_Rev2.pdf Connector Pinout]
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| − | * [http://www.phas.ubc.ca/~mce/mcedocs/hardware/board_block_diagram/ELE-C589-101B_DC-In_Sync_Blk_Diagram.pdf Block Diagram]
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| − | * [http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/schematics/SyncBox/SC2-ELE-S589-101_RevA2_SyncGen_Schematics.pdf Sync Board Schematics]
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| − | | |
| − | == Notes ==
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| − | Here are examples of RS485 driver/receiver chips:
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| − | | |
| − | *[http://www.ti.com/lit/ds/symlink/sn75lbc173.pdf Quad Differential Receiver SN75LBC173D]
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| − | *[http://www.ti.com/lit/ds/symlink/sn75179b.pdf Differential Driver/Receiver pair SN75179B]
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| − | | |
| − | [[Category:Hardware]]
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