Difference between revisions of "Sync Box DC-in io"

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('''Interface Connector''')
('''Interface Connector''')
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: TTL input, spare input to the command processor. ***Not currently used, and open for suggestions.
 
: TTL input, spare input to the command processor. ***Not currently used, and open for suggestions.
 
; DATA_SYNC1 (formerly DV_SPARE1)
 
; DATA_SYNC1 (formerly DV_SPARE1)
: TTL output. Carries a 5 MHz clock signal that is synchronous with DV Spare 2. (WARNING: signal polarity may be swapped)
+
: TTL output. Carries a 5 MHz clock signal that is synchronous with DATA_SYNC2. (WARNING: signal polarity may be swapped)
 
; DATA_SYNC2 (formerly DV_SPARE2)
 
; DATA_SYNC2 (formerly DV_SPARE2)
: TTL output. Carries a 5 MHz data signal that is synchronized with DV Spare 1, and contains the same sequence numbers as the MCE(0-7) outputs. NOTE: This output only contains the DV info stream, but not the occurrences of Addr_Zero between DVs. (WARNING: signal polarity may be swapped)
+
: TTL output. Carries a 5 MHz data signal that is synchronized with DATA_SYNC1, and contains the same frame sequence numbers as the MCE(0-7) outputs. NOTE: This output only contains the DV info stream (40-bit), but not the occurrences of Addr_Return-to-Zero between DVs. (WARNING: signal polarity may be swapped)
 
; DATA_SYNC3
 
; DATA_SYNC3
: TTL output. Carries a 5 MHz TTL signal that contains the same sequence numbers as the MCE(0-7) outputs.
+
: TTL output. asserted for 1us on an Address-Return-to-Zero(ARZ) if a DV pulse is detected since the last ARZ.
 
; DATA_SYNC4
 
; DATA_SYNC4
:TTL output. Carries a 5 MHz TTL signal that contains the same sequence numbers as the MCE(0-7) outputs.
+
:TTL output. asserted for 1us on an Address-Return-to-Zero(ARZ) if a DV pulse is detected since the last ARZ.
  
 
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= =

Revision as of 16:39, 7 October 2010

MCE0 to MCE7
8 Fibre outputs. Carries a 50 MHz Manchester-encoded signal containing data packets, which include incremented sequence numbers. Programmable as two sets of 4 outputs with differently spaced data packets on each.
RS232 Command IO
DB9 connector, TTL input and output, used to command the Sync Box from a PC using a regular RS232 cable.
TTL-IN
BNC connector, TTL input, spare input to the FPGA. ***Not currently used, and open for suggestions.
TTL-OUT
BNC connector, TTL output. Carries a 50 MHz clock signal.

Interface Connector

A DB25 connector that provides the following auxiliary input/outputs:
Data Valid
TTL input. Detects falling edges from a Real-Time Sequencer (implemented by SCUBA2) which tells the Sync box when to tell the MCE's to collect data.
OPTO-TTL
TTL input, spare input to the command processor. ***Not currently used, and open for suggestions.
DATA_SYNC1 (formerly DV_SPARE1)
TTL output. Carries a 5 MHz clock signal that is synchronous with DATA_SYNC2. (WARNING: signal polarity may be swapped)
DATA_SYNC2 (formerly DV_SPARE2)
TTL output. Carries a 5 MHz data signal that is synchronized with DATA_SYNC1, and contains the same frame sequence numbers as the MCE(0-7) outputs. NOTE: This output only contains the DV info stream (40-bit), but not the occurrences of Addr_Return-to-Zero between DVs. (WARNING: signal polarity may be swapped)
DATA_SYNC3
TTL output. asserted for 1us on an Address-Return-to-Zero(ARZ) if a DV pulse is detected since the last ARZ.
DATA_SYNC4
TTL output. asserted for 1us on an Address-Return-to-Zero(ARZ) if a DV pulse is detected since the last ARZ.

Connector Pinout

Block Diagram

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