Readout Card RevB to RevE changes

Lower power

Rev. E cards consume about 13.4W while Rev. B cards consume about 25W. The power saving is mainly due to using a serial 8-channel serial ADC along with a Stratix III FPGA that is configured using a serial device.

Preamp chain

The noise bandwidth of the preamp is adjusted to be a few MHz lower in Rev E cards than in Rev. B cards. Rev. E uses different opamps as well as different RC poles.

Minimum Vcore

The minimum voltage level for Vcore is 3V for Rev. E cards while it was 2.5V for Rev. B cards.

8 in 1 serial ADC

An 8-channel 14-bit 50MS/s serial ADC (AD9252BCPZ-50) is used in Rev. F cards while a single channel 14-bit 50MS/s parallel ADC (AD6644AST) is used in Rev. D cards. The serial ADC accounts for most of the power saving.

Stratix III series FPGA

EP3SE50

A pin compatible bigger FPGA with more resources, i.e., memory, DSP multipliers, is used in Rev. E as oppose to Stratix I series FPGA in Rev. B.

FPGA configuration Device

A serial configuration device (EPCS64) is used in Rev. E compare to a parallel configuration device (EPC16) in Rev. B. This accounts to some power savings.

A *.jic file is needed to load permanent firmware on Rev. E cards as oppose to *.pof files for Rev. B cards.

SEU tolerance

The Stratix III FPGA in Rev. E has a CRC_ERROR pin that can be used to reconfigure the FPGA in case of an SEU hit on the FPGA configuration bits. This is not available on Rev. D. The option needs to yet be supported in firmware and software.

hard-wired pcb revision

In Rev. E, 4 pins are introduced to provide the ability of reading back the pcb revision by software. These 4 bits are reported in the upper 16 bits of card_type. e.g., in a *.run file:

RB rc2 card_type 00001282

translates to 0x502 or rc2 card_type 2 pcb_rev 5

card_type reads 00000002 for cards prior to Rev. E.

Silkscreen labeling of SSA_SIG and S1_FBv

Signals are more accurately labeled on Rev. E PCBs.

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