Difference between revisions of "Programming over Fibre"

From MCEWiki
(Introduction)
Line 5: Line 5:
 
= Introduction =
 
= Introduction =
  
Each of the Address Card, Bias Card, and Readout Card of the MCE has an Altera Stratix FPGA along with a configuration device. Clock-Card, however, has one FPGA with two configuration devices. FPGAs are RAM-based devices while configuration devices are Flash-based devices. Upon power up, each FPGA is loaded from its respective configuration device. The Clock Card FPGA is loaded from its factory configuration device, but after boot-up, it can switch to the firmware in the application configuration device by issuing a command.  
+
Each of the Address Card, Bias Card, and Readout Card of the MCE has an Altera Stratix FPGA along with a configuration device. Clock-Card, however, has one FPGA with two configuration devices. FPGAs are RAM-based devices while configuration devices are Flash-based devices. Upon power up, each FPGA is loaded from its respective configuration device. The Clock Card FPGA is loaded from its factory configuration device upon power up, but then later, the firmware in the application configuration device can be loaded into the FPGA by issuing a command, i.e., on mas PC: rs cc config_app 1.  
  
 
All these programmable parts with the exception of the factory configuration device are on a continous JTAG chain that can be controlled via the MCE front-panel connector with a USB-Blaster attached OR the Clock Card FPGA that runs the right firmware and is driven through the fibre interface.   
 
All these programmable parts with the exception of the factory configuration device are on a continous JTAG chain that can be controlled via the MCE front-panel connector with a USB-Blaster attached OR the Clock Card FPGA that runs the right firmware and is driven through the fibre interface.   

Revision as of 14:47, 7 December 2010

Remote Firmware Update (RFU), aka Remote Configuration is the ability to reprogram the MCE via the fibre-optic interface. This feature was implemented in February 2010.

This page details the steps to enable the remote update ability.

Introduction

Each of the Address Card, Bias Card, and Readout Card of the MCE has an Altera Stratix FPGA along with a configuration device. Clock-Card, however, has one FPGA with two configuration devices. FPGAs are RAM-based devices while configuration devices are Flash-based devices. Upon power up, each FPGA is loaded from its respective configuration device. The Clock Card FPGA is loaded from its factory configuration device upon power up, but then later, the firmware in the application configuration device can be loaded into the FPGA by issuing a command, i.e., on mas PC: rs cc config_app 1.

All these programmable parts with the exception of the factory configuration device are on a continous JTAG chain that can be controlled via the MCE front-panel connector with a USB-Blaster attached OR the Clock Card FPGA that runs the right firmware and is driven through the fibre interface.

The factory configuration device, however, is not on the same JTAG chain. It is only accessible through an on-board JTAG connector and can only be programmed with a USB-Blaster attached and Quartus Programmer.

In order to load temporary firmware, an sof file can be loaded into the FPGA. This firmware will be gone upon power cycle. In order to load permanent firmware, a pof file (or a jic file depending on EPC16 or EPCS64) can be loaded.

Firmware Requirements

In order to be setup for remote firmware update, the Clock Card FPGA has to run firmware revision 5.0.7 or later. Considering that Clock Card FPGA can be loaded through one of Factory or Application configuration devices, at least one of those need to have 5.0.7+ firmware. If you are running Clock Card firmware prior to 5.0.7, which means your factory configuration device is loaded with prior to 5.0.7, then attach USB-Blaster to the MCE front-panel connector. Run Quaruts Programmer, click on auto-detect, and program the second part from the bottom of the list, EPC16, with Clock Card firmware 5.0.7+.pof.

Then issue the following command:

rs cc config_app 1

read back the firmware revision to make sure the 5.0.7+ is now active.

Hardware Requirements

The buffer that controls whether the FPGA can drive the JTAG chain or not is controlled by BB_EN or SW1 dip switch setting on the Clock Card. Clock Cards shipped earlier do not have the right settings. You need to check this setting on your Clock Card. To do so, turn off the MCE power and unplug the Clock Card. The SW1.P1 labeled as "BB_EN" DIP should be on OPEN position.

  • Note that with this DIP switch setting, you can not program the FPGA(sof) from the front panel connector (USB_Blaster) anymore.
  • With this DIP switch setting, if CC firmware is pre-5.0.7, you can not access the JTAG chain from the front panel connector (USB_Blaster) anymore. Assuming you have 5.0.7+ in your configuration device, you need to issue: rs cc config_app 1 to be able to access front-panel JTAG.

Remote Configuration Software

Make sure mce_jam is installed. This is normally installed under /usr/mce/bin. If not, then you need to update your mas and mce_jam will be automatically installed. If you rather not upgrade mas, then just checkout the code under mas/applications/mce_jam, make it and copy it to the mas install directory.

The read_idcode.jam file is included in SVN as a test script to help you determine whether you have set up the system correctly.

mce_jam -u -v -f8000000 -aread_idcode read_idcode.jam                     // For Querying ID Codes

If you can run the read_idcode script, then you are ready to re-configure FPGA's, EPC16's and EPCS64's. For these devices, you will need to generate .jam files that are specifically suited to your JTAG chain's topology. You will need Quartus II software to do this. Instructions on generating .jam files are here: MCE Programming File Conversions. If you do not have access to Quartus II software, send the output of the read_idcode.jam script to UBC, and configuration .jam files can be generated for you.

mce_jam -u -v -f800000 -aprogram -dDO_VERIFY=0 cc_xfpga_rc_pof.jam        // For Programming EPC16's
mce_jam -u -v -f8000000 -aconfigure cc_xfpga_rc_sof.jam                   // For Configuring FPGA's

Note that programming an EPCS64 is a two-step process:

mce_jam -u -v -f8000000 -aconfigure cc_rcd_jic.jam                        // For Programming EPCS64's (Step 1 of 2)
mce_jam -u -v -f100000 -aprogram -dDO_VERIFY=0 cc_rcd_jic.jam             // For Programming EPCS64's (Step 2 of 2)

Footnotes

Generating .JAM Files for Remote Update

Porting Remote Configuration Sofware to DAS

The following C-code will need to be ported to DAS to enable Remote Configuration. You will need to convert the MCE WB and RB commands in the code to use DAS libraries and compile the code with the included Makefile:

Development Notes