Clock Card firmware
From MCEWiki
Clock Card firmware revisions may implement different data packet header formats. All of the different formats are documented here.
Recommended Firmware Revisions
- Please see the recommend firmware revisions page.
Firmware Revision Listing
Revision 5.0.5
- Filename: cc_v05000005_05mar2010.sof
- To Do:
- Features:
- Header Version 6
- Based on 5.0.4
- Implemented unpacking logic for TMS and TDI signals, and inferring logic for TCK. This is the solution to the JTAG packing problem.
- Details:
- Added the following commands:
- constant TMS_TDI_ADDR : std_logic_vector(WB_ADDR_WIDTH-1 downto 0) := x"50";
- constant TDO_ADDR : std_logic_vector(WB_ADDR_WIDTH-1 downto 0) := x"AA";
- constant TDO_SAMPLE_DLY_ADDR : std_logic_vector(WB_ADDR_WIDTH-1 downto 0) := x"AE";
- constant TCK_HALF_PERIOD_ADDR : std_logic_vector(WB_ADDR_WIDTH-1 downto 0) := x"AF";
- The TMS and TDI packing is done such that a "wb cc tms_tdi" command contains the following:
- Word 0: total number of valid bits contained in words 1-n
- Word 1-n: (tms,tdi) pairs starting from word 1 (bits 1,0), word 1 (bits 3,2), etc.
- The TDO packing is done differently.
- Added the following commands:
- Bugs:
- (non-critical) when a card does not return a valid reply, the clock card does not send an error reply back to the PC. Instead, it fills the data with whatever it had in its buffer from previous command and sends it to mas.
- FPGA Resource Usage (clk_card.fit.rpt):
- Timing Analyzer Summary (clk_card.tan.rpt):
Revision 5.0.4
- Filename: cc_v05000004_26feb2010.sof
- To Do:
- Features:
- Header Version 6
- Based on 5.0.3
- Added JTAG control registers that emulated a parallel port to allow Jam Player software to write to the MCE from a MAS PC and configure devices via JTAG.
- constant JTAG0_ADDR : std_logic_vector(WB_ADDR_WIDTH-1 downto 0) := x"BD"; -- Output data
- constant JTAG1_ADDR : std_logic_vector(WB_ADDR_WIDTH-1 downto 0) := x"BE"; -- Input data
- constant JTAG2_ADDR : std_logic_vector(WB_ADDR_WIDTH-1 downto 0) := x"BF"; -- JTAG Chain control
- Details:
- Remote Firmware Update.
- This version of firmware is compatible with ported JAM Player software that has been temporarily committed to CVS under \\mce\cards\clk_card\config_fpga\source\unix_code.
- Bugs:
- (non-critical) when a card does not return a valid reply, the clock card does not send an error reply back to the PC. Instead, it fills the data with whatever it had in its buffer from previous command and sends it to mas.
- FPGA Resource Usage (clk_card.fit.rpt):
+--------------------------------------------------------------------------+ ; Fitter Summary ; +--------------------------+-----------------------------------------------+ ; Fitter Status ; Successful - Thu Feb 25 19:22:18 2010 ; ; Quartus II Version ; 9.1 Build 304 01/25/2010 SP 1 SJ Full Version ; ; Revision Name ; clk_card ; ; Top-level Entity Name ; clk_card ; ; Family ; Stratix ; ; Device ; EP1S30F780C5 ; ; Timing Models ; Final ; ; Total logic elements ; 17,827 / 32,470 ( 55 % ) ; ; Total pins ; 261 / 598 ( 44 % ) ; ; Total virtual pins ; 0 ; ; Total memory bits ; 949,760 / 3,317,184 ( 29 % ) ; ; DSP block 9-bit elements ; 10 / 96 ( 10 % ) ; ; Total PLLs ; 2 / 6 ( 33 % ) ; ; Total DLLs ; 0 / 2 ( 0 % ) ; +--------------------------+-----------------------------------------------+ ; M512s ; 66 / 295 ( 22 % ) ; M4Ks ; 171 / 171 ( 100 % ) ; M-RAMs ; 3 / 4 ( 75 % )
- Timing Analyzer Summary (clk_card.tan.rpt):
+----------------------------------------------------------------------------------------------------------- ; Timing Analyzer Summary +----------------------------------------------------------------------------------------------+-----------+ ; Type ; Slack ; +----------------------------------------------------------------------------------------------+-----------+ ; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk0' ; 0.771 ns ; ; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk1' ; 1.576 ns ; ; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk2' ; 2.859 ns ; ; Clock Setup: 'fibre_rx_clkr' ; 13.822 ns ; ; Clock Setup: 'manch_pll:manch_pll_block|altpll:altpll_component|_clk0' ; 18.801 ns ; ; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk3' ; 35.630 ns ; ; Clock Hold: 'fibre_rx_clkr' ; 0.445 ns ; ; Clock Hold: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk0' ; 0.643 ns ; ; Clock Hold: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk3' ; 0.665 ns ; ; Clock Hold: 'manch_pll:manch_pll_block|altpll:altpll_component|_clk0' ; 0.676 ns ; ; Clock Hold: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk2' ; 0.679 ns ; ; Clock Hold: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk1' ; 2.989 ns ; ; Total number of failed paths ; ; +----------------------------------------------------------------------------------------------+-----------+
Revision 5.0.3
- Filename: cc_v05000003_13jan2010.sof
- To Do:
- ---
- Features:
- Header Version 6
- Based on 5.0.2
- Added a Stratix I generic parameter for synthesis-time library selection.
- Made a top-level modification that makes the interface compatible with the LM95235, while maintaining backwards compatibility.
- Added the following commands for applying maximum-length sequences to MCE outputs: AWG_SEQUENCE_LEN, AWG_DATA, AWG_ADDR. See Arbitrary Waveform Generator .
- Details:
- Arbitrary Waveform Generator (i.e. Maximum Length Sequences for Complex Impedance Measurements)
- Bugs:
- (non-critical) when a card does not return a valid reply, the clock card does not send an error reply back to the PC. Instead, it fills the data with whatever it had in its buffer from previous command and sends it to mas.
- FPGA Resource Usage (clk_card.fit.rpt):
+--------------------------------------------------------------------------+ ; Fitter Summary ; +--------------------------+-----------------------------------------------+ ; Fitter Status ; Successful - Mon Jan 25 20:10:18 2010 ; ; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Full Version ; ; Revision Name ; clk_card ; ; Top-level Entity Name ; clk_card ; ; Family ; Stratix ; ; Device ; EP1S30F780C5 ; ; Timing Models ; Final ; ; Total logic elements ; 18,095 / 32,470 ( 56 % ) ; ; Total pins ; 255 / 598 ( 43 % ) ; ; Total virtual pins ; 0 ; ; Total memory bits ; 949,760 / 3,317,184 ( 29 % ) ; ; DSP block 9-bit elements ; 10 / 96 ( 10 % ) ; ; Total PLLs ; 2 / 6 ( 33 % ) ; ; Total DLLs ; 0 / 2 ( 0 % ) ; +--------------------------+-----------------------------------------------+
- Timing Analyzer Summary (clk_card.tan.rpt):
+----------------------------------------------------------------------------------------------------------- ; Timing Analyzer Summary +----------------------------------------------------------------------------------------------+-----------+ ; Type ; Slack ; +----------------------------------------------------------------------------------------------+-----------+ ; Worst-case tsu ; N/A ; ; Worst-case tco ; N/A ; ; Worst-case tpd ; N/A ; ; Worst-case th ; N/A ; ; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk0' ; 1.547 ns ; ; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk2' ; 1.985 ns ; ; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk1' ; 2.067 ns ; ; Clock Setup: 'fibre_rx_clkr' ; 15.116 ns ; ; Clock Setup: 'manch_pll:manch_pll_block|altpll:altpll_component|_clk0' ; 18.723 ns ; ; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk3' ; 36.327 ns ; ; Clock Hold: 'fibre_rx_clkr' ; 0.445 ns ; ; Clock Hold: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk0' ; 0.643 ns ; ; Clock Hold: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk3' ; 0.643 ns ; ; Clock Hold: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk2' ; 0.689 ns ; ; Clock Hold: 'manch_pll:manch_pll_block|altpll:altpll_component|_clk0' ; 0.693 ns ; ; Clock Hold: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk1' ; 2.989 ns ; ; Total number of failed paths ; ; +----------------------------------------------------------------------------------------------+-----------+
Revision 5.0.2
- Filename: cc_v05000002_test00_tagged.sof
- To Do:
- ---
- Features:
- Header Version 6
- Based off of 5.0.1 and in parallel with 4.0.c (equivalent version)
- The Sync Box PLL was re-instated to the top level and routed to dv_rx. It was mistakenly removed after v4.0.9, which means that the sync box sequence number decoding has not worked since then! When collecting data while triggering off the Sync Box DV, the Clock Card would also sporadically trigger in between data frames.
- Fixed a bug in ret_dat_wbs that did not handle wb num_rows_reported and wb num_cols_reported commands correctly.
- Details:
- Bugs:
- (non-critical) when a card does not return a valid reply, the clock card does not send an error reply back to the PC. Instead, it fills the data with whatever it had in its buffer from previous command and sends it to mas.
- FPGA Resource Usage (clk_card.fit.rpt):
+--------------------------------------------------------------------------+ ; Fitter Summary ; +--------------------------+-----------------------------------------------+ ; Fitter Status ; Successful - Wed Jul 15 13:40:33 2009 ; ; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Full Version ; ; Revision Name ; clk_card ; ; Top-level Entity Name ; clk_card ; ; Family ; Stratix ; ; Device ; EP1S30F780C5 ; ; Timing Models ; Final ; ; Total logic elements ; 17,598 / 32,470 ( 54 % ) ; ; Total pins ; 254 / 598 ( 42 % ) ; ; Total virtual pins ; 0 ; ; Total memory bits ; 818,688 / 3,317,184 ( 25 % ) ; ; DSP block 9-bit elements ; 10 / 96 ( 10 % ) ; ; Total PLLs ; 2 / 6 ( 33 % ) ; ; Total DLLs ; 0 / 2 ( 0 % ) ; +--------------------------+-----------------------------------------------+
- Timing Analyzer Summary (clk_card.tan.rpt):
+----------------------------------------------------------------------------------------------------------- ; Timing Analyzer Summary +----------------------------------------------------------------------------------------------+-----------+ ; Type ; Slack ; +----------------------------------------------------------------------------------------------+-----------+ ; Worst-case tsu ; N/A ; ; Worst-case tco ; N/A ; ; Worst-case tpd ; N/A ; ; Worst-case th ; N/A ; ; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk0' ; 1.965 ns ; ; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk1' ; 2.041 ns ; ; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk2' ; 3.548 ns ; ; Clock Setup: 'fibre_rx_clkr' ; 14.442 ns ; ; Clock Setup: 'manch_pll:manch_pll_block|altpll:altpll_component|_clk0' ; 19.107 ns ; ; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk3' ; 35.792 ns ; ; Clock Hold: 'fibre_rx_clkr' ; 0.445 ns ; ; Clock Hold: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk0' ; 0.526 ns ; ; Clock Hold: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk2' ; 0.540 ns ; ; Clock Hold: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk3' ; 0.544 ns ; ; Clock Hold: 'manch_pll:manch_pll_block|altpll:altpll_component|_clk0' ; 0.547 ns ; ; Clock Hold: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk1' ; 2.989 ns ; ; Total number of failed paths ; ; +----------------------------------------------------------------------------------------------+-----------+
Revision 5.0.1 (Buggy)
- Filename: cc_v05000001_12may2009.sof
- To Do:
- ---
- Features:
- Based on 5.0.0 and in parallel with 4.0.b (equivalent version)
- Header Version 6
- STOP commands are meant to work in this revision. The successful execution of STOP commands through the system depends also on the PCI card firmware, and PCI driver. Modifications have been made to these, and their version numbers have been bumped to...
- Details:
- Bugs:
- There may be a problem with decoding sync numbers from the sync box.
- FPGA Resource Usage (clk_card.fit.rpt):
+---------------------------------------------------------------------+ ; Fitter Summary ; +--------------------------+------------------------------------------+ ; Fitter Status ; Successful - Tue May 12 16:12:06 2009 ; ; Quartus II Version ; 8.1 Build 163 10/28/2008 SJ Full Version ; ; Revision Name ; clk_card ; ; Top-level Entity Name ; clk_card ; ; Family ; Stratix ; ; Device ; EP1S30F780C5 ; ; Timing Models ; Final ; ; Total logic elements ; 18,286 / 32,470 ( 56 % ) ; ; Total pins ; 259 / 598 ( 43 % ) ; ; Total virtual pins ; 0 ; ; Total memory bits ; 1,537,536 / 3,317,184 ( 46 % ) ; ; DSP block 9-bit elements ; 10 / 96 ( 10 % ) ; ; Total PLLs ; 1 / 6 ( 17 % ) ; ; Total DLLs ; 0 / 2 ( 0 % ) ; +--------------------------+------------------------------------------+
- Timing Analyzer Summary (clk_card.tan.rpt):
+----------------------------------------------------------------------------------------------------------- ; Timing Analyzer Summary +----------------------------------------------------------------------------------------------+-----------+ ; Type ; Slack ; +----------------------------------------------------------------------------------------------+-----------+ ; Worst-case tsu ; N/A ; ; Worst-case tco ; N/A ; ; Worst-case tpd ; N/A ; ; Worst-case th ; N/A ; ; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk0' ; 1.995 ns ; ; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk2' ; 3.585 ns ; ; Clock Setup: 'altera_internal_jtag~TCKUTAP' ; 5.644 ns ; ; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk1' ; 9.234 ns ; ; Clock Setup: 'fibre_rx_clkr' ; 14.381 ns ; ; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk3' ; 34.916 ns ; ; Clock Hold: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk0' ; 0.445 ns ; ; Clock Hold: 'fibre_rx_clkr' ; 0.445 ns ; ; Clock Hold: 'altera_internal_jtag~TCKUTAP' ; 0.534 ns ; ; Clock Hold: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk3' ; 0.544 ns ; ; Clock Hold: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk2' ; 0.658 ns ; ; Clock Hold: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk1' ; 10.656 ns ; ; Total number of failed paths ; ; +----------------------------------------------------------------------------------------------+-----------+
Revision 5.0.0 (Buggy)
- Filename: cc_v05000000_22dec2008.sof (tagged as sys_v05000000_22dec2008)
- To Do:
- ---
- Features:
- Header Version 6
- IMPORTANT: Must be used in conjunction with firmware v05000000 of all other cards!!!
- This version is based on 4.0.a. That is, it includes all of the features that were under development in 4.0.a, even though 4.0.a was not released for telescope use.
- Added the ability to read out a single column of data continuously from one Readout Card
- New commands include: readout_col_index, readout_priority, num_cols_reported
- To allow enough data bandwidth, the spare LVDS line from each card to the Clock Card is now used
- Details:
- Bugs:
- There may be a problem with decoding sync numbers from the sync box.
- FPGA Resource Usage (clk_card.fit.rpt):
+---------------------------------------------------------------------+ ; Fitter Summary ; +--------------------------+------------------------------------------+ ; Fitter Status ; Successful - Thu Jan 15 17:18:34 2009 ; ; Quartus II Version ; 8.1 Build 163 10/28/2008 SJ Full Version ; ; Revision Name ; readout_card ; ; Top-level Entity Name ; readout_card ; ; Family ; Stratix ; ; Device ; EP1S40F780C6 ; ; Timing Models ; Final ; ; Total logic elements ; 26,607 / 41,250 ( 65 % ) ; ; Total pins ; 358 / 616 ( 58 % ) ; ; Total virtual pins ; 0 ; ; Total memory bits ; 406,016 / 3,423,744 ( 12 % ) ; ; DSP block 9-bit elements ; 76 / 112 ( 68 % ) ; ; Total PLLs ; 1 / 6 ( 17 % ) ; ; Total DLLs ; 0 / 2 ( 0 % ) ; +--------------------------+------------------------------------------+
- Timing Analyzer Summary (clk_card.tan.rpt):
+--------------------------------------------------------------------------- ; Timing Analyzer Summary +--------------------------------------------------------------+-----------+ ; Type ; Slack ; +--------------------------------------------------------------+-----------+ ; Worst-case tsu ; N/A ; ; Worst-case tco ; N/A ; ; Worst-case th ; N/A ; ; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.558 ns ; ; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.892 ns ; ; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.987 ns ; ; Clock Hold: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 0.741 ns ; ; Clock Hold: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 0.762 ns ; ; Clock Hold: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 0.763 ns ; ; Total number of failed paths ; ; +--------------------------------------------------------------+-----------+
Revision 4.0.c
- Filename: cc_v0400000c_24aug2009.sof
- To Do:
- ---
- Features:
- Header Version 6
- Based on v4.0.b, with a fix to the sync box interface for a bug that caused the Clock Card data collection logic to trigger sporadically.
- Details:
- clk_card.vhd: re-instantiated the manchester PLL, and routed the manch_clk to dv_rx.
- Bugs:
- None yet.
- FPGA Resource Usage (clk_card.fit.rpt):
+--------------------------------------------------------------------------+ ; Fitter Summary ; +--------------------------+-----------------------------------------------+ ; Fitter Status ; Successful - Mon Aug 24 14:18:05 2009 ; ; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Full Version ; ; Revision Name ; clk_card ; ; Top-level Entity Name ; clk_card ; ; Family ; Stratix ; ; Device ; EP1S30F780C5 ; ; Timing Models ; Final ; ; Total logic elements ; 14,965 / 32,470 ( 46 % ) ; ; Total pins ; 254 / 598 ( 42 % ) ; ; Total virtual pins ; 0 ; ; Total memory bits ; 812,544 / 3,317,184 ( 24 % ) ; ; DSP block 9-bit elements ; 10 / 96 ( 10 % ) ; ; Total PLLs ; 2 / 6 ( 33 % ) ; ; Total DLLs ; 0 / 2 ( 0 % ) ; +--------------------------+-----------------------------------------------+
- Timing Analyzer Summary (clk_card.tan.rpt):
+----------------------------------------------------------------------------------------------------------- ; Timing Analyzer Summary +----------------------------------------------------------------------------------------------+-----------+ ; Type ; Slack ; +----------------------------------------------------------------------------------------------+-----------+ ; Worst-case tsu ; N/A ; ; Worst-case tco ; N/A ; ; Worst-case tpd ; N/A ; ; Worst-case th ; N/A ; ; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk0' ; 1.646 ns ; ; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk1' ; 2.167 ns ; ; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk2' ; 2.919 ns ; ; Clock Setup: 'fibre_rx_clkr' ; 14.506 ns ; ; Clock Setup: 'manch_pll:manch_pll_block|altpll:altpll_component|_clk0' ; 19.104 ns ; ; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk3' ; 35.811 ns ; ; Clock Hold: 'fibre_rx_clkr' ; 0.445 ns ; ; Clock Hold: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk0' ; 0.528 ns ; ; Clock Hold: 'manch_pll:manch_pll_block|altpll:altpll_component|_clk0' ; 0.539 ns ; ; Clock Hold: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk2' ; 0.542 ns ; ; Clock Hold: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk3' ; 0.544 ns ; ; Clock Hold: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk1' ; 2.989 ns ; ; Total number of failed paths ; ; +----------------------------------------------------------------------------------------------+-----------+
Revision 4.0.b (Buggy)
- Filename: cc_v0400000b_03jun2009.sof
- To Do:
- ---
- Features:
- Header Version 6
- Based on v4.0.a, with the necessary bug fixes to be as stable as v5.0.1 without implementing the dual-LVDS feature.
- STOP commands are meant to work in this revision. The successful execution of STOP commands through the system depends also on the PCI card firmware, and PCI driver. Modifications have been made to these, and their version numbers have been bumped to...
- This firmware is a hybrid version that implements a single LVDS line, but has STOP and On-The-Fly capabilities built in. The purpose of this firmware is to give SCUBA-2 these features without forcing them to upgrade the firmware on all their other cards.
- Details:
- Bugs:
- There may be a problem with decoding sync numbers from the sync box.
- FPGA Resource Usage (clk_card.fit.rpt):
+---------------------------------------------------------------------+ ; Fitter Summary ; +--------------------------+------------------------------------------+ ; Fitter Status ; Successful - Wed Jun 03 15:35:18 2009 ; ; Quartus II Version ; 8.1 Build 163 10/28/2008 SJ Full Version ; ; Revision Name ; clk_card ; ; Top-level Entity Name ; clk_card ; ; Family ; Stratix ; ; Device ; EP1S30F780C5 ; ; Timing Models ; Final ; ; Total logic elements ; 15,023 / 32,470 ( 46 % ) ; ; Total pins ; 254 / 598 ( 42 % ) ; ; Total virtual pins ; 0 ; ; Total memory bits ; 812,544 / 3,317,184 ( 24 % ) ; ; DSP block 9-bit elements ; 10 / 96 ( 10 % ) ; ; Total PLLs ; 1 / 6 ( 17 % ) ; ; Total DLLs ; 0 / 2 ( 0 % ) ; +--------------------------+------------------------------------------+
- Timing Analyzer Summary (clk_card.tan.rpt):
+----------------------------------------------------------------------------------------------------------- ; Timing Analyzer Summary +----------------------------------------------------------------------------------------------+-----------+ ; Type ; Slack ; +----------------------------------------------------------------------------------------------+-----------+ ; Worst-case tsu ; N/A ; ; Worst-case tco ; N/A ; ; Worst-case tpd ; N/A ; ; Worst-case th ; N/A ; ; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk1' ; 1.328 ns ; ; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk0' ; 1.442 ns ; ; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk2' ; 3.383 ns ; ; Clock Setup: 'fibre_rx_clkr' ; 11.093 ns ; ; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk3' ; 36.700 ns ; ; Clock Hold: 'fibre_rx_clkr' ; 0.445 ns ; ; Clock Hold: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk0' ; 0.532 ns ; ; Clock Hold: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk3' ; 0.542 ns ; ; Clock Hold: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk2' ; 0.556 ns ; ; Clock Hold: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk1' ; 2.989 ns ; ; Total number of failed paths ; ; +----------------------------------------------------------------------------------------------+-----------+
Revision 4.0.a (Not for Telescope Use)
- Filename: cc_v0400000a_16oct2008
- To Do:
- Make sure that the errno word, and the cards to report word in the data frame header agree with cards_to_report
- Features:
- Header Version 6
- Based on 4.0.9
- Added stop_dly, rcs_to_report_data, and cards_to_report commands
- Added support for commands to the MCE during data acquisition
- Details:
- clk_card.vhd: incremented the firmware version number, and added cards_to_report interface signals; added support for the stop_dly, rcs_to_report_data, and cards_to_report commands; Removed the Manchester PLL because the only way to ensure that packets are received without trouble is for the main PLL to be locked on the Manchester clock. The Manchester PLL was a failed attempted around this.
- clock_card_pack.vhd: added support for the stop_dly, rcs_to_report_data, and cards_to_report commands
- issue_reply.vhd: added support for the stop_dly, rcs_to_report_data, and cards_to_report commands
- cmd_translator.vhd: split up command registers so that it can handle WB/RB/RS commands while acquiring data based on a GO command.
- issue_reply_pack.vhd: added indexing constants.
- reply_queue.vhd: modified the logic for calculating the reply data size, in response to the addition of the rcs_to_report_data, and cards_to_report commands
- reply_queue_sequencer.vhd: modified the logic for reading the data from the reply queues; modified the logic for determining when to stop readout from a card queue to ease timing constraints. Changed to logic for multiplexing the data buses from the reply queues to combinatorial logic to ease timing constraints.
- reply_translator.vhd: added a stop_delay counter for delaying the replies to 'stop ret_dat' commands; added the QUICK_REPLY and QUICK_REPLY_PAUSE states to pause the return of replies to stop commands; added extra handling to the LD_STATUS state to avoid mixing stop replies, and replies to data or simple commands; added stop reply pause logic to DONE state
- ret_dat_wbs.vhd: added the stop_delay_o, rcs_to_report_data, and cards_to_report_o interfaces; implemented a custom register from cards_to_report and stop_delay; removed the register for ret_dat_card_addr which was a special case of cards_to_report.
- ret_dat_wbs_pack: added the constant DEFAULT_CARDS_TO_REPORT
- Bugs:
- Reading back rcs_to_report_data returns zero (fixed)
- Can't issue simple commands during data taking
- Can't read from RC4 (fixed)
- There may be a problem with decoding sync numbers from the sync box.
- FPGA Resource Usage (clk_card.fit.rpt):
+--------------------------------------------------------------------------+ ; Fitter Summary ; +--------------------------+-----------------------------------------------+ ; Fitter Status ; Successful - Fri Nov 21 12:19:34 2008 ; ; Quartus II Version ; 8.0 Build 231 07/10/2008 SP 1 SJ Full Version ; ; Revision Name ; clk_card ; ; Top-level Entity Name ; clk_card ; ; Family ; Stratix ; ; Device ; EP1S30F780C5 ; ; Timing Models ; Final ; ; Total logic elements ; 14,542 / 32,470 ( 45 % ) ; ; Total pins ; 254 / 598 ( 42 % ) ; ; Total virtual pins ; 0 ; ; Total memory bits ; 812,544 / 3,317,184 ( 24 % ) ; ; DSP block 9-bit elements ; 8 / 96 ( 8 % ) ; ; Total PLLs ; 1 / 6 ( 17 % ) ; ; Total DLLs ; 0 / 2 ( 0 % ) ; +--------------------------+-----------------------------------------------+
- Timing Analyzer Summary (clk_card.tan.rpt):
+---------------------------------------+-----------+ ; Type ; Slack ; +---------------------------------------+-----------+ ; Worst-case tsu ; N/A ; ; Worst-case tco ; N/A ; ; Worst-case tpd ; N/A ; ; Worst-case th ; N/A ; ; Clock Setup: 'clk_switchover:t|_clk0' ; 1.712 ns ; ; Clock Setup: 'clk_switchover:t|_clk1' ; 2.632 ns ; ; Clock Setup: 'clk_switchover:t|_clk2' ; 3.884 ns ; ; Clock Setup: 'fibre_rx_clkr' ; 13.678 ns ; ; Clock Setup: 'clk_switchover:t|_clk3' ; 36.938 ns ; ; Clock Hold: 'fibre_rx_clkr' ; 0.445 ns ; ; Clock Hold: 'clk_switchover:c|_clk0' ; 0.531 ns ; ; Clock Hold: 'clk_switchover:c|_clk3' ; 0.541 ns ; ; Clock Hold: 'clk_switchover:c|_clk2' ; 0.544 ns ; ; Clock Hold: 'clk_switchover:c|_clk1' ; 2.989 ns ; ; Total number of failed paths ; ; +---------------------------------------+-----------+
Revision 4.0.9
- Filename: cc_v04000009
- Features:
- Header Version 6
- Integrated a bug fix for the sram_ctrl block
- Integrated new all_cards block of code which was causing a synthesis warning in ModelSim
- Two new commands added: card_type, scratch.
- Bugs:
- None to report so far
- FPGA Resource Usage (clk_card.fit.rpt):
+---------------------------------------------------------------------+ ; Fitter Summary ; +--------------------------+------------------------------------------+ ; Fitter Status ; Successful - Thu Feb 21 16:56:34 2008 ; ; Quartus II Version ; 6.1 Build 201 11/27/2006 SJ Full Version ; ; Revision Name ; clk_card ; ; Top-level Entity Name ; clk_card ; ; Family ; Stratix ; ; Device ; EP1S30F780C5 ; ; Timing Models ; Final ; ; Total logic elements ; 14,144 / 32,470 ( 44 % ) ; ; Total pins ; 254 / 598 ( 42 % ) ; ; Total virtual pins ; 0 ; ; Total memory bits ; 812,544 / 3,317,184 ( 24 % ) ; ; DSP block 9-bit elements ; 8 / 96 ( 8 % ) ; ; Total PLLs ; 2 / 6 ( 33 % ) ; ; Total DLLs ; 0 / 2 ( 0 % ) ; +--------------------------+------------------------------------------+
- Timing Analyzer Summary (clk_card.tan.rpt):
+----------------------------------------------------------------------------------------------------------- ; Timing Analyzer Summary +----------------------------------------------------------------------------------------------+-----------+ ; Type ; Slack ; +----------------------------------------------------------------------------------------------+-----------+ ; Worst-case tsu ; N/A ; ; Worst-case tco ; N/A ; ; Worst-case tpd ; N/A ; ; Worst-case th ; N/A ; ; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk1' ; 0.294 ns ; ; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk0' ; 2.091 ns ; ; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk2' ; 2.711 ns ; ; Clock Setup: 'fibre_rx_clkr' ; 16.125 ns ; ; Clock Setup: 'manch_pll:manch_pll_block|altpll:altpll_component|_clk0' ; 18.658 ns ; ; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk3' ; 35.366 ns ; ; Clock Hold: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk0' ; 0.445 ns ; ; Clock Hold: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk3' ; 0.445 ns ; ; Clock Hold: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk2' ; 0.542 ns ; ; Clock Hold: 'manch_pll:manch_pll_block|altpll:altpll_component|_clk0' ; 0.542 ns ; ; Clock Hold: 'fibre_rx_clkr' ; 0.543 ns ; ; Clock Hold: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk1' ; 2.989 ns ; ; Total number of failed paths ; ; +----------------------------------------------------------------------------------------------+-----------+
