Clock Card firmware
From MCEWiki
Clock Card firmware revisions may implement different data packet header formats. All of the different formats are documented here.
Contents
Firmware Revision Listing
Revision 4.0.a (under development)
- Filename: cc_v0400000a
- Features:
- Header Version 6
- In clk_card.vhd, incremented the firmware version number, and added cards_to_report interface signals
- Added support for the stop_dly and cards_to_report commands in clk_card.vhd, clock_card_pack.vhd, issue_reply.vhd.
- Removed the Manchester PLL because the only way to ensure that packets are received without trouble is for the main PLL to be locked on the Manchester clock. The Manchester PLL was a failed attempted around this.
- Split up command registers in cmd_queue.vhd so that it can handle WB/RB/RS commands while acquiring data based on a GO command.
- Added indexing constants to issue_reply_pack.vhd
- Modified the logic for calculating the reply data size in reply_queue.vhd because of the cards_to_report command
- Modified the logic for reading the data from the reply queues in reply_queue_sequencer.vhd
- Modified the logic for determining when to stop readout from a card queue in reply_queue_sequencer.vhd to ease timing constraints.
- Changed to logic for multiplexing the data buses from the reply queues in reply_queue_sequencer.vhd to combinatorial logic to ease timing constraints.
- Modified reply_translator.vhd
- Bugs:
- Synthesis Notes:
- The FPGA resource usage:
Revision 4.0.9 (latest)
- Filename: cc_v04000009
- Features:
- Header Version 6
- Integrated a bug fix for the sram_ctrl block
- Integrated new all_cards block of code which was causing a synthesis warning in ModelSim
- Two new commands added: card_type, scratch.
- Bugs:
- In fast DAS, if I try to issue ‘w cc led 1 2 3 … 58’, the MCE/ DAS will fail at the second command.
- Cards with no firmware loaded are treated as ‘not present’ and therefore replies come back as OK as oppose to ER. (comment added by MA)
- When PSUC is not present (or fails), rb psc psc_status comes back as OK with all entries as 0. (comment added by MA)
- fpga_temp readings are way off.
- Switching to Application Config sometimes fails and the red light comes up.
- If the FPGA on a card is not programmed, it does not report an error (it treats the card as the not-present card and therefore the error is masked).
- If PSUC is not present and not communicating, CC doesn't report error and instead reports RBOK
- None reported yet
- Synthesis Notes:
- The FPGA resource usage:
+------------------------------------------------------------------------------+ ; Fitter Resource Usage Summary ; +---------------------------------------------+--------------------------------+ ; Resource ; Usage ; +---------------------------------------------+--------------------------------+ ; Total logic elements ; 14,071 / 32,470 ( 43 % ) ; ; -- Combinational with no register ; 7328 ; ; -- Register only ; 1449 ; ; -- Combinational with a register ; 5294 ; ; ; ; ; Logic element usage by number of LUT inputs ; ; ; -- 4 input functions ; 7387 ; ; -- 3 input functions ; 2446 ; ; -- 2 input functions ; 2648 ; ; -- 1 input functions ; 879 ; ; -- 0 input functions ; 711 ; ; ; ; ; Logic elements by mode ; ; ; -- normal mode ; 11956 ; ; -- arithmetic mode ; 2115 ; ; -- qfbk mode ; 1236 ; ; -- register cascade mode ; 0 ; ; -- synchronous clear/load mode ; 3706 ; ; -- asynchronous clear/load mode ; 6387 ; ; ; ; ; Total registers ; 6,743 / 35,978 ( 19 % ) ; ; Total LABs ; 1,592 / 3,247 ( 49 % ) ; ; Logic elements in carry chains ; 2314 ; ; User inserted logic elements ; 0 ; ; Virtual pins ; 0 ; ; I/O pins ; 254 / 598 ( 42 % ) ; ; -- Clock pins ; 5 / 16 ( 31 % ) ; ; Global signals ; 10 ; ; M512s ; 24 / 295 ( 8 % ) ; ; M4Ks ; 171 / 171 ( 100 % ) ; ; M-RAMs ; 2 / 4 ( 50 % ) ; ; Total memory bits ; 812,544 / 3,317,184 ( 24 % ) ; ; Total RAM block bits ; 1,981,440 / 3,317,184 ( 60 % ) ; ; DSP block 9-bit elements ; 8 / 96 ( 8 % ) ; ; PLLs ; 2 / 6 ( 33 % ) ; ; Global clocks ; 10 / 16 ( 63 % ) ; ; Regional clocks ; 0 / 16 ( 0 % ) ; ; Fast regional clocks ; 0 / 16 ( 0 % ) ; ; SERDES transmitters ; 0 / 82 ( 0 % ) ; ; SERDES receivers ; 0 / 82 ( 0 % ) ; ; JTAGs ; 0 / 1 ( 0 % ) ; ; Average interconnect usage (total/H/V) ; 15% / 13% / 18% ; ; Peak interconnect usage (total/H/V) ; 44% / 38% / 55% ; ; Maximum fan-out node ; altpll:altpll_component|_clk0 ; ; Maximum fan-out ; 6750 ; ; Highest non-global fan-out signal ; wishbone|pres_state.wb_cycle ; ; Highest non-global fan-out ; 323 ; ; Total fan-out ; 68893 ; ; Average fan-out ; 4.74 ; +---------------------------------------------+--------------------------------+
