Difference between revisions of "Minimum Vcore for RC RevE"
From MCEWiki
| Line 4: | Line 4: | ||
Note that although DDR chips are not populated on RC Rev E2, but U31 regulator still powers up the FPGA IO banks dedicated to DDR IO. | Note that although DDR chips are not populated on RC Rev E2, but U31 regulator still powers up the FPGA IO banks dedicated to DDR IO. | ||
| − | [[Category: | + | [[Category:Power]] |
| + | [[Category:Readout Card]] | ||
Latest revision as of 16:23, 31 August 2016
On RC Rev E, the minimum Vcore is dictated by TPS76718QPWP regulators, U33 and U31, that generate VRDD=1VD8+ of the ADC chip, and 1.8V for DDR circuitry, respectively. The regulator datasheet specifies Vin(min)=2.7V. With 0.2V of margin, we need Vcore(min)=2.9V.
Note that although DDR chips are not populated on RC Rev E2, but U31 regulator still powers up the FPGA IO banks dedicated to DDR IO.
