Difference between revisions of "Testing Bias Cards"
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Load firmware into the configuration device as oppose to the FPGA now. The parallel configuration device, EPC16, is programmed through the JTAG port on the Clock-Card front panel. Here are the steps: | Load firmware into the configuration device as oppose to the FPGA now. The parallel configuration device, EPC16, is programmed through the JTAG port on the Clock-Card front panel. Here are the steps: | ||
* Run Quartus programmer and click on auto-detect. You should see 4 devices in the list. | * Run Quartus programmer and click on auto-detect. You should see 4 devices in the list. | ||
| − | * Select EPC16 device on top and click on change file to choose ''' | + | * Select EPC16 device on top and click on change file to choose ''' bc_v05030001_12apr2012.pof''' (found in http://e-mode.phas.ubc.ca/mce_firmware/ ) |
* Now select the device and click on program. | * Now select the device and click on program. | ||
* When programming is done, turn off the power and turn it back on. If the Green Light is on, it means that you have successfully programmed the configuration device. | * When programming is done, turn off the power and turn it back on. If the Green Light is on, it means that you have successfully programmed the configuration device. | ||
Revision as of 12:08, 23 November 2012
Contents
Testing MCE Bias Cards
Setup
The following equipments are needed:
- mas PC: An ubuntu-based PC with ARC-64 PCI card installed an running mas software.
- 2-slot backplane with Clock Card plugged in: Device under test (DUT) is plugged into this backplane during testing.
- fibre-optic cable: connects mas-PC to Clock Card.
- set of Linear supplies to power up the cards. (3V, 4.5V, 6.2V, -6.2V)
- Altera USB programmer: attached to the JTAG connector in Clock card front panel.
- PC with Quartus installed: used to program FPGA and configuration devices on Readout Card.
- Oscilloscope
If you have all the above and if your DUT has already been smoke tested, you are ready to start:
- connect them up an power up the 2-slot backplane.
- Load FPGA firmware using Quartus. Firmware is located at http://e-mode.phas.ubc.ca/mce_firmware/. Run auto-detect and you should see 4 devices. The part at the bottom of the list corresponts to Clock card FPGA. Load following firmware from the above directory: CC firmware 5.0.7, BC firmware bc_v05030001_12apr2012.sof
- On the 2-slot backplane there are two sets of dip switches. You need to set the one on the Bias card side to 1110 (0xe), otherwise bc1 replies do not come back, because the card is not identified properly.
- Now make sure both cards communicate with the PC. ssh to the PC running mas and connected to the 2-slot backplane trhough fibre cables and run the following command:
mce_cmd -x rb cc fw_rev
and you will see:
Line 0 : ok : 0x5000007
and then type:
mce_cmd -x rb bc1 fw_rev
and you will see
Line 0 : ok : 0x5000005
Testing General Features (card_all_test)
We run a scrip on the mas PC to issue commands over the fibre to test the Readout Card unit under test. In this script, the following circuits are tested: LEDs, silicon ID chip, slot-id and pcb-revision identification pins, FPGA and board temperature sense circuitry, LVDS communication pairs.
On mas PC, type: card_all_test
The output should look like:
****** Check to make sure the LEDs on the target card switched status! **** Unit Under Test : rc1 Serial Number : SRC-216 Firmware Revision: -0xfffa card_id : 0x20be502 slot_id : [4] card_type : [2] card_rev : 0 fpga_temp : 34 C pass card_temp : 28 C pass results are in : /data/cryo/current_data/SRC-216_1285959943_all_test
copy the results into the test logfile and record the card_id on MCE CARD Serial-Number Lookup
Testing DACS
In this stage, we test the 16-bit serial DACs: 32 single-ended bias lines and 12 differential bias lines (ln_bias). To run the test, on mas PC, type bc_test.
When the bc_test script is run, DACs are loaded with a set of fix values and then a ramp is applied and outputs need to be probed in all cases. For serial DACs, the script only tries loading 3 values: 0, midrange, full-range.
DAC outputs need to be measured on corresponding points on the 2-slot backplane connector. Here is a PASS criteria for the serial DACs. A similar table needs to be included in the test log.
| Output | 0x0000 | 0x8000 | 0xffff | 0-2.5V Ramp |
|---|---|---|---|---|
| D00 | +-100mV | 1.25V +-10mV | 2.5V +-10mV | OK |
| LN0 (in Rev D) | +-100mV | 1.25V +-10mV | 2.5V +-10mV | OK |
| LN0 (in Rev F) | -2.5V +-10mV | +-100mV | 2.5V +-10mV | OK |
Testing Serial Configuration device and FPGA reconfiguration
Load firmware into the configuration device as oppose to the FPGA now. The parallel configuration device, EPC16, is programmed through the JTAG port on the Clock-Card front panel. Here are the steps:
- Run Quartus programmer and click on auto-detect. You should see 4 devices in the list.
- Select EPC16 device on top and click on change file to choose bc_v05030001_12apr2012.pof (found in http://e-mode.phas.ubc.ca/mce_firmware/ )
- Now select the device and click on program.
- When programming is done, turn off the power and turn it back on. If the Green Light is on, it means that you have successfully programmed the configuration device.
- on mas prompt, type: mce_cmd -x rb bc1 fw_rev and you should see the firmware revision of the firmware you loaded. This is usually noted in the filename of the file you chose.
Record the result in logfile.
log results
