Difference between revisions of "Sync Box DC-in io"
From MCEWiki
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| + | :''[[Sync_Box#User.27s_Guide|Back to Sync Box Guide]]'' | ||
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; MCE0 to MCE7 | ; MCE0 to MCE7 | ||
: 8 Fibre outputs. Carries a 50 MHz Manchester-encoded signal containing data packets, which include incremented sequence numbers. Programmable as two sets of 4 outputs with differently spaced data packets on each. | : 8 Fibre outputs. Carries a 50 MHz Manchester-encoded signal containing data packets, which include incremented sequence numbers. Programmable as two sets of 4 outputs with differently spaced data packets on each. | ||
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; DATA_VALID | ; DATA_VALID | ||
: TTL input. Detects falling edges from a Real-Time Sequencer (implemented by SCUBA2) which tells the Sync box when to tell the MCE's to collect data. | : TTL input. Detects falling edges from a Real-Time Sequencer (implemented by SCUBA2) which tells the Sync box when to tell the MCE's to collect data. | ||
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; DATA_SYNC1 (formerly DV_SPARE1) | ; DATA_SYNC1 (formerly DV_SPARE1) | ||
: TTL output. Carries a 5 MHz clock signal that is synchronous with DATA_SYNC2. (WARNING: signal polarity may be swapped) | : TTL output. Carries a 5 MHz clock signal that is synchronous with DATA_SYNC2. (WARNING: signal polarity may be swapped) | ||
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:TTL output. asserted for 1us on an Address-Return-to-Zero(ARZ) if a DV pulse is detected since the last ARZ. | :TTL output. asserted for 1us on an Address-Return-to-Zero(ARZ) if a DV pulse is detected since the last ARZ. | ||
| − | === | + | === Pinout === |
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| − | = = | + | === Schematics === |
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| − | + | * [http://www.phas.ubc.ca/~mce/mcedocs/hardware/schematics/SyncBox/ELE-C589-102_Sync_Box_Connector_Pinouts_Rev2.pdf Connector Pinout] | |
| − | [http:// | + | * [http://www.phas.ubc.ca/~mce/mcedocs/hardware/board_block_diagram/ELE-C589-101B_DC-In_Sync_Blk_Diagram.pdf Block Diagram] |
Revision as of 17:02, 7 October 2010
- MCE0 to MCE7
- 8 Fibre outputs. Carries a 50 MHz Manchester-encoded signal containing data packets, which include incremented sequence numbers. Programmable as two sets of 4 outputs with differently spaced data packets on each.
- RS232 Command IO
- DB9 connector, TTL input and output, used to command the Sync Box from a PC using a regular RS232 cable.
- TTL-IN
- BNC connector, TTL input, spare input to the FPGA. ***Not currently used, and open for suggestions.
- TTL-OUT
- BNC connector, TTL output. Carries a 50 MHz clock signal.
Interface Connector
- A DB25 connector that provides the following auxiliary input/outputs:
- DATA_VALID
- TTL input. Detects falling edges from a Real-Time Sequencer (implemented by SCUBA2) which tells the Sync box when to tell the MCE's to collect data.
- DATA_SYNC1 (formerly DV_SPARE1)
- TTL output. Carries a 5 MHz clock signal that is synchronous with DATA_SYNC2. (WARNING: signal polarity may be swapped)
- DATA_SYNC2 (formerly DV_SPARE2)
- TTL output. Carries a 5 MHz data signal that is synchronized with DATA_SYNC1, and contains the same frame sequence numbers as the MCE(0-7) outputs. NOTE: This output only contains the DV info stream (40-bit), but not the occurrences of Addr_Return-to-Zero between DVs. (WARNING: signal polarity may be swapped)
- DATA_SYNC3
- TTL output. asserted for 1us on an Address-Return-to-Zero(ARZ) if a DV pulse is detected since the last ARZ.
- DATA_SYNC4
- TTL output. asserted for 1us on an Address-Return-to-Zero(ARZ) if a DV pulse is detected since the last ARZ.
Pinout
| Pin | Signal | Pin | Signal |
|---|---|---|---|
| 1 | Data_Valid+ | 14 | GND |
| 2 | Data_Valid- | 15 | Data_Sync1+ |
| 3 | GND | 16 | Data_Sync1- |
| 4 | Data_Sync2+ | 17 | GND |
| 5 | Data_Sync2- | 18 | Data_Sync3+ |
| 6 | GND | 19 | Data_Sync3- |
| 7 | Data_Sync3_TTL | 20 | GND |
| 8 | GND | 21 | Data_Sync4+ |
| 9 | Data_Sync4_TTL | 22 | Data_Sync4- |
| 10 | N/C | 23 | GND |
| 11 | N/C | 24 | N/C |
| 12 | N/C | 25 | N/C |
| 13 | N/C |
