Difference between revisions of "Bus Backplane"
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| − | The bus backplane distributes power to MCE cards and also provides the data bus which allows inter-card communication. | + | The bus backplane distributes power to MCE cards and also provides the data bus which allows inter-card communication. The data bus consist of a multi-drop 'command' line from the master slot (clock card) to all slave cards (readout, address, bias cards) and two point-to-point 'reply' lines from each slave card to the clock card. All JTAG signals are routed on the backplane to form a single JTAG chain that can be used to program all the cards in the MCE. Bypass buffers on the JTAG signals allow programming a partially populated MCE. |
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| + | == Schematics == | ||
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| + | * MCEv2 5-MDM D0 (C586-201) [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/schematics/mceV2_BusBackplane_RevD/ELE-C586-201_RevD0_BusBp_Schematics.pdf PDF]] | ||
| + | * MCEv2 3-MDM A (C586-101) [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/schematics/mceV2_BusBackplane_RevD/ELE-C586-101_BusBP_Schematic%20Prints.pdf PDF]] | ||
Revision as of 22:51, 27 May 2013
Template:Hierarchy header The bus backplane distributes power to MCE cards and also provides the data bus which allows inter-card communication. The data bus consist of a multi-drop 'command' line from the master slot (clock card) to all slave cards (readout, address, bias cards) and two point-to-point 'reply' lines from each slave card to the clock card. All JTAG signals are routed on the backplane to form a single JTAG chain that can be used to program all the cards in the MCE. Bypass buffers on the JTAG signals allow programming a partially populated MCE.
