Difference between revisions of "Readout Card Preamp Chain"

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A digital 4-pole Butterworth low-pass filter is implemented as 2 cascaded biquads (2-pole topology) in the Read-out card firmware of the MCE. Each biquad has the following functional form:
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== Preamp Chain in Readout Card ==
 +
The preamp chain consists of four stages of amplification which provide gain and act as a low pass filter. Six RC poles are included in the chain and act together to give a steep roll off which limits out-of-band noise.  The exact pole locations and filter cut-off frequency depends upon the particular readout-card revision, but the basic topology is consistent across all revisions up to the latest revision (E).  This topology consists of two initial low noise amplifier stages each with a single RC pole in their respective feedback loops (R12&C74 followed by R14&C75 in Rev B), followed by a third stage of gain which also includes another RC pole in its feedback loop (R16&C76 in Rev B), and finally a differential ADC driver which has symmetric RC poles on both the positive and negative outputs (R10&C73 and R24&C77 in Rev B).  There is also a low-pass RC filter between the first and second stages (R20&C78 in Rev B) and third and fourth stages (R21&C79 in Rev B).  
  
: H<sub>i</sub>(Z) = [1 + 2 x Z <sup> -1</sup> + Z<sup> -2</sup>] / [1 + b<sub>1i</sub> x Z<sup> -1</sup> + b<sub>2i</sub> x Z<sup> -2</sup>]
+
The plots shown here are generated by collecting [[Raw-mode readout | raw data]] sampled at 50 MHz, with the cold electronics replaced by test boards which short all of the instrument backplane lines with 50 ohm resistors.  A summary of the results is in the table below.
  
and the overall transfer function is:
+
{| class="wikitable"
: H(Z) = k x H<sub>1</sub>(Z) x H<sub>2</sub>(Z) where k is the DC gain.
+
|+ Preamp Bandwidth across Readout Card Revisions
 +
|-
 +
! Board Revision !! Noise (RMS) !! Bandwidth (f3dB)!! Attenuation at 500 kHz
 +
|-
 +
| [[Readout Card Preamp Chain#Rev_B9|B9 (shorted)]]
 +
|| 4.2 ADC units
 +
|| 5.7 MHz
 +
|| 0.1 dB
 +
|-
 +
| [[Readout Card Preamp Chain#Rev_B10|B10 (50 Ohm)]]
 +
|| 3.0 ADC units
 +
|| 1.27 MHz
 +
|| 0.6 dB
 +
|-
 +
| [[Readout Card Preamp Chain#Rev_E0|E0 (shorted)]]
 +
|| 3.2 ADC units
 +
|| 3.2 MHz
 +
|| 0.2 dB
 +
|-
 +
|}
  
== Rev B9 Bandwidth ==
 
Filter specification of the 4-pole Butterworth filter is determined by the filter coefficients b<sub>11</sub>, b<sub>12</sub>, b<sub>21</sub>, b<sub>22</sub>. These coefficients are currently hard-coded in the Readout-card firmware and depending on the firmware revision, the filter specification may vary.
 
  
Assume:  
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== Rev B9 ==
 +
[http://www.phas.ubc.ca/~mce/mcedocs/hardware/schematics/Readout%20Card%20RevD/RC_C582_101D0_Schematic.pdf RC Rev B9 Schematic (preamp chain on page 7)]
  
'''f<sub>3dB</sub>''' is the frequency at which the signal is <math>\sqrt2</math> of its maximum value and 
+
The gain distribution among different amplification stages in Revision B is: 4, 4, 6, 2, for a total gain of 192.  The card uses a 16 bit ADC with a 2.2 V reference, leading to a LSB size of 134 uV.  The 3dB cutoff frequency of the chain is about 6 MHz.  The noise of the preamp chain is approximately 5.4 ADC units with a 50 ohm resistor at the MDM connector, or about 4.2 ADC units with the preamp shorted.
  
'''f<sub>samp</sub>''' is the sampling frequency calculated as 50MHz/(num_rows * row_len). For example 50MHz(100*33)=15151.5Hz.
+
Test results using a Revision B9 card with a 50 ohm resistance at the MDM connector are shown below.
 +
{|"wikitable"
 +
|-
 +
|[[Image: dB_spectra_1267481760_raw.png|400px|thumb]]
 +
|-
 +
|[[Image: timestream_1267481760_raw.png|400px|thumb]]
 +
|-
 +
[[Image: spectra_1267481760_raw.png|400px|thumb]]
 +
|-
 +
|}
  
''Note that the filter f<sub>3dB</sub> scales if f<sub>samp</sub> changes.''
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== Rev B10 ==
 +
The schematic for Rev B10 is identical to that of B9, excepting 3 capacitor value changes on each channel of the preamp.  These capacitors were altered to reduce the cutoff frequency of the preamp chain in order to reduce out of band noise.  The designed cutoff frequency was reduced from 6MHz to about 1.4 MHz, which predicts a reduction in total noise across the full band of the ADC of approximately Sqrt(1.4/6), or a little bit better than 50%.
  
; Type 1
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The gain distribution of Revision B is: first stage 4, second stage 4, third stage 6, fourth stage 2, for a total gain of 192. The card uses a 16 bit ADC with a 2.2 V reference, leading to a LSB size of 134 uV. The measured noise was about 3.0 ADC units. The maximum signal frequency of interest (500 kHz) is attenuated by about 0.6 dB by the filter compared to DC gain.
: (supported in all rc except 5.0.7)
 
: DC amplification = 1217.9148
 
: f<sub>3dB</sub> / f<sub>samp</sub> = 122.226Hz / 15151Hz
 
: Gain @ 200Hz=0.14189148 (wrt the DC gain)
 
  
; Type 2
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In order to achieve the lower cutoff frequency, capacitors C74, C75 and C76 were altered to 470pF, 470pF, and 68pF respectively. This shifts the pole locations:  
: (supported in rc version 5.0.7)
 
: DC amplification = 2044
 
: f<sub>3dB</sub> / f<sub>samp</sub> = 75Hz / 30000Hz
 
  
; Type 256
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{| class="wikitable"
: ''Work in Progress:''  Filter coefficients b11, b12, b21, b22 are parametrized and programmable by software.
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|-
 +
! pole!! Components!! Frequency (MHz)<br>Rev B10!! Frequency (MHz)<br>Rev B9
 +
|-
 +
|pole 1 ||R12 & C74 || 3.4 MHz || 15.9 MHz
 +
|-
 +
|pole 2 ||R20 & C78 || 10.2 MHz ||(unchanged)
 +
|-
 +
|pole 3 ||R14 & C75 || 3.4 MHz || 15.9 MHz
 +
|-
 +
|pole 4 ||R21 & C79 || 10.2 MHz ||(unchanged)
 +
|-
 +
|pole 5 ||R16 & C76 || 2.3 MHz ||7.2 MHz
 +
|-
 +
|pole 6 ||R10 & C73, R24 & C77 || 7.2 MHz ||7.2
 +
|-
 +
|}
  
The fitler type can be determined by reading back the MCE parameter called ''filter_type'' (rb rc1 filter_type). (To be implemented in firmware 5.0.a+)
+
The combination of these poles results in a total cutoff frequency (calculated via SPICE simulation using ideal opamps) of 1.44 MHz.  The actual cutoff frequency is expected to be slightly lower than this due to the use of AD797 op amps in the first two stages, which have low roll off frequencies (estimated at between 10 and 20 MHz at a gain of 4) that contribute to further reduction of the overall cutoff frequency. The uncertainty in the resistors (1%) and capacitors (5%) result in a maximum variation of overall cutoff frequency between (calculated using SPICE simulation) 1.37 MHz and 1.53 MHz around the nominal value of 1.44 MHz.
  
The following plot shows the magnitude and the phase of Type 1 filter.
+
Test results using a Revision B10 card are shown below.
 +
{|"wikitable"
 +
|-
 +
|[[Image: dB_spectra_1267483256_raw.png|400px|thumb]]
 +
|-
 +
|[[Image: timestream_1267483256_raw.png|400px|thumb]]
 +
|-
 +
|[[Image: spectra_1267483256_raw.png|400px|thumb]]
 +
|-
 +
|}
  
 +
== Rev E0 ==
 +
[http://www.phas.ubc.ca/~mce/mcedocs/hardware/schematics/Readout%20Card%20RevE/RC_C582_101E0_Schematic.pdf RC Rev E0 Schematic (preamp chain on page 11)]
  
Here is Elia's original plot [[Media:BW_filter.ps]]. Then we see the same plot with the impulse-response also added (by Joe, Nov 29, 2007):
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The Rev E0 preamp chain has several changes. The first and second stage op amps have been changed from the AD797 to the ADA4898-1.  This change should provide improved flatness in frequency response, lower noise, and more predictable gain and bandwidth properties.  The gain structure and pole frequencies have also changed in an effort to reduce the noise contribution of the preamp itself, aliased squid noise, and thermal noise of the cable impedance.  By reducing the bandwidth to a minimum acceptable for the different cable impedances encountered in various experiments, the noise bandwidth is reduced.
[[Image: BW_filter2.png ]]
 
  
Here is the filter response for Scuba2 setting (f<sub>samp</sub>=9.5kHz, f<sub>readout</sub>=200Hz): [[Media: Filter fs10kHz 200Hzdecimated response.ps ]]
+
The new gain distribution between stages is: 6.13, 5.99, 5.52, 1 with an overall gain of 203.
  
== IDL Code ==
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The new pole frequencies are:
In this little IDL program you can find the functional form as a function of the frequency of the filter. First, Elia's original program, then as modified by Joe on November 29, 2007, then modified by Mandana on Jan. 14, 2009 for Scuba2 numbers.
+
{| class="wikitable"
 +
|-
 +
! pole!! Frequency (MHz)
 +
|-
 +
|pole 1|| 9.7 MHz
 +
|-
 +
|pole 2 || 15.2 MHz
 +
|-
 +
|pole 3|| 9.7 MHz
 +
|-
 +
|pole 4 || 15.2 MHz
 +
|-
 +
|pole 5 ||7.2 MHz
 +
|-
 +
|}
  
[[ Media: filter_pro.txt ]]
 
  
[[ Media: filter_pro2.txt ]]
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These poles, along with the roll off of the op amps resulting from internal compensation, yield an overall 3dB frequency for the preamp chain of approximately 3.2 MHz.  It is important to remember that this is the cutoff frequency of the preamp chain alone, and does not include the filter board capacitors (150pF) or cable impedance, which interact to form a low frequency pole which can dominate the overall cutoff frequency.  For example, a cable with impedance ~200ohms+100pF adds a pole near 3 MHz, which would reduce the overall bandwidth to about 2 MHz.
  
[[ Media: low_pass_filter_model_pro.txt ]]
+
The series resistor between the feedback network of the first stage op amp and the offset adjust DAC, R37, has also been changed.  It has been reduced to 681 ohms to allow a greater offset to be trimmed out.  This change has a minor effect on the gain due to the interaction between resistor R37 and R11, increasing the gain slightly.  This has already been included in the gain calculation above, and accounts for the difference in gain between the first and second stage.
  
== Filter Coefficients  ==
+
Some typical test results of a Rev E0 card are shown below.
  
The filter coefficients are generated using fdatool (filter-design & Analysis tool) in '''Matlab/Simulink'''. Once you launch the fdatool, choose the following settings:
+
{|"wikitable"
 +
|-
 +
|[[Image: dB spectra 1285875292 raw 690338270.png|400px|thumb]]
 +
|-
 +
|[[Image: Timestream 1285875292 raw 690338270.png|400px|thumb]]
 +
|-
 +
|[[Image: Spectra 1285875292 raw 690338270.png|400px|thumb]]
 +
|}
  
* Response Type: Low Pass
+
[[Category:Readout Card]]
 
 
* Design Method: Butterworth
 
 
 
* Filter Order: 4
 
 
 
* Frequency Specifications:
 
** For Type 1: F<sub>s</sub> = 12195 = (50000/100*41), F<sub>c</sub>=100
 
** For Type 2: F<sub>s</sub> = 30000 = (50000/100*41), F<sub>c</sub>=75
 
** (The attenuation at F<sub>c</sub> is fixed at 3dB (half the passband power))
 
 
 
Then click on Design Filter and you will get the following coefficients:
 
; Type 1
 
:Section 1:
 
::Numerator: 1  2  1 
 
::Denominator: 1  -1.9587428340882587  0.96134553442399129
 
::Gain = 1/k<sub>1</sub> = 0.00065067508393319923 (not implemented)
 
:Section 2:
 
::Numerator: 1  2  1 
 
::Denominator: 1  -1.9066292518523014  0.90916270571237567
 
::Gain = 1/k<sub>2</sub>= 0.00063336346501859835  (not implemented)
 
 
 
; Type 2
 
:Section 1:
 
::Numerator: 1  2  1 
 
::Denominator: 1  -1.9711486088510415  0.97139181456687917
 
:Section 2:
 
::Numerator: 1  2  1 
 
::Denominator: 1  -1.9878047097960421  0.98804997058724808
 
:Gain = 1/(k<sub>1</sub> * k<sub>2</sub>)= 0.0000000037280516432624239  (not implemented)
 
 
 
<br>
 
'''The following ONLY concerns the MCE firmware developers:'''
 
<br>
 
Now to include these floating numbers (coefficients) in MCE firmware, you need to convert the coefficients to signed binary fractional (SBF) 1.14 format where the right-most bit is the sign and the rest of the bits are the magnitude. For example, to convert b11=-1.9587428340882587, you multiply it by -2<sup>14</sup> and convert it to hex, it becomes 0x7D5C. Then the binary is 111 1101 0101 1100.
 
 
 
These values are then plugged in '''fsfb_calc_pack.vhd''' (FILTER_B11_COEF, FILTER_B12_COEF, FILTER_B21_COEFF, FILTER_B22_COEFF).
 
 
 
=== Calculating the DC Gain (k) ===
 
 
 
Note that in firmware, instead of k<sub>1</sub> and k<sub>2</sub>, an inter-biquad gain of k<sub>3</sub> (implemented as a binary shift) and k<sub>4</sub>, representing number of bits dropped after the second biquad, are implemented.
 
 
 
Hence, the overall gain becomes (k<sub>1</sub> x k<sub>2</sub>) / (k<sub>3</sub> x k<sub>4</sub>).
 
 
 
(Note for firmware developers: see FILTER_GAIN_WIDTH and FILTER_SCALE_LSB in '''fsfb_calc_pack.vhd'''.)
 
 
 
; Type 1
 
:k3 is 2<sup>11</sup>, the filter gain is estimated at 1184, but vhdl simulation results in a gain of 1216.
 
; Type 2
 
:k3 is 2<sup>14</sup> and k4 is 2<sup>3</sup>, the filter gain is estimated at 2046, but vhdl simulation results in a gain of ????.
 
 
 
The gain difference can be attributed to the coefficient quantization effects.
 

Latest revision as of 15:26, 31 August 2016

Preamp Chain in Readout Card

The preamp chain consists of four stages of amplification which provide gain and act as a low pass filter. Six RC poles are included in the chain and act together to give a steep roll off which limits out-of-band noise. The exact pole locations and filter cut-off frequency depends upon the particular readout-card revision, but the basic topology is consistent across all revisions up to the latest revision (E). This topology consists of two initial low noise amplifier stages each with a single RC pole in their respective feedback loops (R12&C74 followed by R14&C75 in Rev B), followed by a third stage of gain which also includes another RC pole in its feedback loop (R16&C76 in Rev B), and finally a differential ADC driver which has symmetric RC poles on both the positive and negative outputs (R10&C73 and R24&C77 in Rev B). There is also a low-pass RC filter between the first and second stages (R20&C78 in Rev B) and third and fourth stages (R21&C79 in Rev B).

The plots shown here are generated by collecting raw data sampled at 50 MHz, with the cold electronics replaced by test boards which short all of the instrument backplane lines with 50 ohm resistors. A summary of the results is in the table below.

Preamp Bandwidth across Readout Card Revisions
Board Revision Noise (RMS) Bandwidth (f3dB) Attenuation at 500 kHz
B9 (shorted) 4.2 ADC units 5.7 MHz 0.1 dB
B10 (50 Ohm) 3.0 ADC units 1.27 MHz 0.6 dB
E0 (shorted) 3.2 ADC units 3.2 MHz 0.2 dB


Rev B9

RC Rev B9 Schematic (preamp chain on page 7)

The gain distribution among different amplification stages in Revision B is: 4, 4, 6, 2, for a total gain of 192. The card uses a 16 bit ADC with a 2.2 V reference, leading to a LSB size of 134 uV. The 3dB cutoff frequency of the chain is about 6 MHz. The noise of the preamp chain is approximately 5.4 ADC units with a 50 ohm resistor at the MDM connector, or about 4.2 ADC units with the preamp shorted.

Test results using a Revision B9 card with a 50 ohm resistance at the MDM connector are shown below.

Spectra 1267481760 raw.png
DB spectra 1267481760 raw.png
Timestream 1267481760 raw.png

Rev B10

The schematic for Rev B10 is identical to that of B9, excepting 3 capacitor value changes on each channel of the preamp. These capacitors were altered to reduce the cutoff frequency of the preamp chain in order to reduce out of band noise. The designed cutoff frequency was reduced from 6MHz to about 1.4 MHz, which predicts a reduction in total noise across the full band of the ADC of approximately Sqrt(1.4/6), or a little bit better than 50%.

The gain distribution of Revision B is: first stage 4, second stage 4, third stage 6, fourth stage 2, for a total gain of 192. The card uses a 16 bit ADC with a 2.2 V reference, leading to a LSB size of 134 uV. The measured noise was about 3.0 ADC units. The maximum signal frequency of interest (500 kHz) is attenuated by about 0.6 dB by the filter compared to DC gain.

In order to achieve the lower cutoff frequency, capacitors C74, C75 and C76 were altered to 470pF, 470pF, and 68pF respectively. This shifts the pole locations:

pole Components Frequency (MHz)
Rev B10
Frequency (MHz)
Rev B9
pole 1 R12 & C74 3.4 MHz 15.9 MHz
pole 2 R20 & C78 10.2 MHz (unchanged)
pole 3 R14 & C75 3.4 MHz 15.9 MHz
pole 4 R21 & C79 10.2 MHz (unchanged)
pole 5 R16 & C76 2.3 MHz 7.2 MHz
pole 6 R10 & C73, R24 & C77 7.2 MHz 7.2

The combination of these poles results in a total cutoff frequency (calculated via SPICE simulation using ideal opamps) of 1.44 MHz. The actual cutoff frequency is expected to be slightly lower than this due to the use of AD797 op amps in the first two stages, which have low roll off frequencies (estimated at between 10 and 20 MHz at a gain of 4) that contribute to further reduction of the overall cutoff frequency. The uncertainty in the resistors (1%) and capacitors (5%) result in a maximum variation of overall cutoff frequency between (calculated using SPICE simulation) 1.37 MHz and 1.53 MHz around the nominal value of 1.44 MHz.

Test results using a Revision B10 card are shown below.

DB spectra 1267483256 raw.png
Timestream 1267483256 raw.png
Spectra 1267483256 raw.png

Rev E0

RC Rev E0 Schematic (preamp chain on page 11)

The Rev E0 preamp chain has several changes. The first and second stage op amps have been changed from the AD797 to the ADA4898-1. This change should provide improved flatness in frequency response, lower noise, and more predictable gain and bandwidth properties. The gain structure and pole frequencies have also changed in an effort to reduce the noise contribution of the preamp itself, aliased squid noise, and thermal noise of the cable impedance. By reducing the bandwidth to a minimum acceptable for the different cable impedances encountered in various experiments, the noise bandwidth is reduced.

The new gain distribution between stages is: 6.13, 5.99, 5.52, 1 with an overall gain of 203.

The new pole frequencies are:

pole Frequency (MHz)
pole 1 9.7 MHz
pole 2 15.2 MHz
pole 3 9.7 MHz
pole 4 15.2 MHz
pole 5 7.2 MHz


These poles, along with the roll off of the op amps resulting from internal compensation, yield an overall 3dB frequency for the preamp chain of approximately 3.2 MHz. It is important to remember that this is the cutoff frequency of the preamp chain alone, and does not include the filter board capacitors (150pF) or cable impedance, which interact to form a low frequency pole which can dominate the overall cutoff frequency. For example, a cable with impedance ~200ohms+100pF adds a pole near 3 MHz, which would reduce the overall bandwidth to about 2 MHz.

The series resistor between the feedback network of the first stage op amp and the offset adjust DAC, R37, has also been changed. It has been reduced to 681 ohms to allow a greater offset to be trimmed out. This change has a minor effect on the gain due to the interaction between resistor R37 and R11, increasing the gain slightly. This has already been included in the gain calculation above, and accounts for the difference in gain between the first and second stage.

Some typical test results of a Rev E0 card are shown below.

DB spectra 1285875292 raw 690338270.png
Timestream 1285875292 raw 690338270.png
Spectra 1285875292 raw 690338270.png