Difference between revisions of "Clock Card firmware"
From MCEWiki
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* '''FPGA Resource Usage''' (clk_card.fit.rpt): | * '''FPGA Resource Usage''' (clk_card.fit.rpt): | ||
| − | + | + | +--------------------------------------------------------------------------+ |
| − | ; Fitter | + | ; Fitter Summary ; |
| − | +----------------------------------------- | + | +--------------------------+-----------------------------------------------+ |
| − | ; | + | ; Fitter Status ; Successful - Fri Oct 24 17:45:36 2008 ; |
| − | + | ; Quartus II Version ; 8.0 Build 231 07/10/2008 SP 1 SJ Full Version ; | |
| − | + | ; Revision Name ; clk_card ; | |
| − | ; | + | ; Top-level Entity Name ; clk_card ; |
| − | ; | + | ; Family ; Stratix ; |
| − | ; | + | ; Device ; EP1S30F780C5 ; |
| − | ; | + | ; Timing Models ; Final ; |
| − | ; | + | ; Total logic elements ; 14,526 / 32,470 ( 45 % ) ; |
| − | ; | + | ; Total pins ; 254 / 598 ( 42 % ) ; |
| − | ; | + | ; Total virtual pins ; 0 ; |
| − | + | ; Total memory bits ; 812,544 / 3,317,184 ( 24 % ) ; | |
| − | + | ; DSP block 9-bit elements ; 8 / 96 ( 8 % ) ; | |
| − | + | ; Total PLLs ; 1 / 6 ( 17 % ) ; | |
| − | + | ; Total DLLs ; 0 / 2 ( 0 % ) ; | |
| − | + | +--------------------------+-----------------------------------------------+ | |
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| − | ; Total | ||
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| − | ; | ||
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| − | ; Total memory bits | ||
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| − | ; DSP block 9-bit elements | ||
| − | ; PLLs | ||
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| − | +----------------------------------------- | ||
* '''Timing Analyzer Summary''' (clk_card.tan.rpt): | * '''Timing Analyzer Summary''' (clk_card.tan.rpt): | ||
Revision as of 13:16, 28 October 2008
Clock Card firmware revisions may implement different data packet header formats. All of the different formats are documented here.
Contents
Firmware Revision Listing
Revision 4.0.a (under development)
- Filename: cc_v0400000a_16oct2008
- To Do:
- Make sure that the errno word, and the cards to report word in the data frame header agree with cards_to_report
- Features:
- Header Version 6
- Added stop_dly, rcs_to_report_data, and cards_to_report commands
- Added support for commands to the MCE during data acquisition
- Details:
- clk_card.vhd: incremented the firmware version number, and added cards_to_report interface signals; added support for the stop_dly, rcs_to_report_data, and cards_to_report commands; Removed the Manchester PLL because the only way to ensure that packets are received without trouble is for the main PLL to be locked on the Manchester clock. The Manchester PLL was a failed attempted around this.
- clock_card_pack.vhd: added support for the stop_dly, rcs_to_report_data, and cards_to_report commands
- issue_reply.vhd: added support for the stop_dly, rcs_to_report_data, and cards_to_report commands
- cmd_translator.vhd: split up command registers so that it can handle WB/RB/RS commands while acquiring data based on a GO command.
- issue_reply_pack.vhd: added indexing constants.
- reply_queue.vhd: modified the logic for calculating the reply data size, in response to the addition of the rcs_to_report_data, and cards_to_report commands
- reply_queue_sequencer.vhd: modified the logic for reading the data from the reply queues; modified the logic for determining when to stop readout from a card queue to ease timing constraints. Changed to logic for multiplexing the data buses from the reply queues to combinatorial logic to ease timing constraints.
- reply_translator.vhd: added a stop_delay counter for delaying the replies to 'stop ret_dat' commands; added the QUICK_REPLY and QUICK_REPLY_PAUSE states to pause the return of replies to stop commands; added extra handling to the LD_STATUS state to avoid mixing stop replies, and replies to data or simple commands; added stop reply pause logic to DONE state
- ret_dat_wbs.vhd: added the stop_delay_o, rcs_to_report_data, and cards_to_report_o interfaces; implemented a custom register from cards_to_report and stop_delay; removed the register for ret_dat_card_addr which was a special case of cards_to_report.
- ret_dat_wbs_pack: added the constant DEFAULT_CARDS_TO_REPORT
- Bugs:
- See MCE Bugs (Internal MCE Wiki)
- FPGA Resource Usage (clk_card.fit.rpt):
+--------------------------------------------------------------------------+ ; Fitter Summary ; +--------------------------+-----------------------------------------------+ ; Fitter Status ; Successful - Fri Oct 24 17:45:36 2008 ; ; Quartus II Version ; 8.0 Build 231 07/10/2008 SP 1 SJ Full Version ; ; Revision Name ; clk_card ; ; Top-level Entity Name ; clk_card ; ; Family ; Stratix ; ; Device ; EP1S30F780C5 ; ; Timing Models ; Final ; ; Total logic elements ; 14,526 / 32,470 ( 45 % ) ; ; Total pins ; 254 / 598 ( 42 % ) ; ; Total virtual pins ; 0 ; ; Total memory bits ; 812,544 / 3,317,184 ( 24 % ) ; ; DSP block 9-bit elements ; 8 / 96 ( 8 % ) ; ; Total PLLs ; 1 / 6 ( 17 % ) ; ; Total DLLs ; 0 / 2 ( 0 % ) ; +--------------------------+-----------------------------------------------+
- Timing Analyzer Summary (clk_card.tan.rpt):
+----------------------------------------------------------------------------------------------------------- ; Timing Analyzer Summary +----------------------------------------------------------------------------------------------+-----------+ ; Type ; Slack ; +----------------------------------------------------------------------------------------------+-----------+ ; Worst-case tsu ; N/A ; ; Worst-case tco ; N/A ; ; Worst-case tpd ; N/A ; ; Worst-case th ; N/A ; ; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk0' ; 1.875 ns ; ; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk1' ; 2.677 ns ; ; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk2' ; 3.865 ns ; ; Clock Setup: 'fibre_rx_clkr' ; 14.905 ns ; ; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk3' ; 36.768 ns ; ; Clock Hold: 'fibre_rx_clkr' ; 0.445 ns ; ; Clock Hold: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk0' ; 0.528 ns ; ; Clock Hold: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk3' ; 0.545 ns ; ; Clock Hold: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk2' ; 0.554 ns ; ; Clock Hold: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk1' ; 2.989 ns ; ; Total number of failed paths ; ; +----------------------------------------------------------------------------------------------+-----------+
Revision 4.0.9 (latest)
- Filename: cc_v04000009
- Features:
- Header Version 6
- Integrated a bug fix for the sram_ctrl block
- Integrated new all_cards block of code which was causing a synthesis warning in ModelSim
- Two new commands added: card_type, scratch.
- Bugs:
- In fast DAS, if I try to issue ‘w cc led 1 2 3 … 58’, the MCE/ DAS will fail at the second command.
- Cards with no firmware loaded are treated as ‘not present’ and therefore replies come back as OK as oppose to ER. (comment added by MA)
- When PSUC is not present (or fails), rb psc psc_status comes back as OK with all entries as 0. (comment added by MA)
- fpga_temp readings are way off.
- Switching to Application Config sometimes fails and the red light comes up.
- If the FPGA on a card is not programmed, it does not report an error (it treats the card as the not-present card and therefore the error is masked).
- If PSUC is not present and not communicating, CC doesn't report error and instead reports RBOK
- None reported yet
- Synthesis Notes:
- The FPGA resource usage:
+------------------------------------------------------------------------------+ ; Fitter Resource Usage Summary ; +---------------------------------------------+--------------------------------+ ; Resource ; Usage ; +---------------------------------------------+--------------------------------+ ; Total logic elements ; 14,071 / 32,470 ( 43 % ) ; ; -- Combinational with no register ; 7328 ; ; -- Register only ; 1449 ; ; -- Combinational with a register ; 5294 ; ; ; ; ; Logic element usage by number of LUT inputs ; ; ; -- 4 input functions ; 7387 ; ; -- 3 input functions ; 2446 ; ; -- 2 input functions ; 2648 ; ; -- 1 input functions ; 879 ; ; -- 0 input functions ; 711 ; ; ; ; ; Logic elements by mode ; ; ; -- normal mode ; 11956 ; ; -- arithmetic mode ; 2115 ; ; -- qfbk mode ; 1236 ; ; -- register cascade mode ; 0 ; ; -- synchronous clear/load mode ; 3706 ; ; -- asynchronous clear/load mode ; 6387 ; ; ; ; ; Total registers ; 6,743 / 35,978 ( 19 % ) ; ; Total LABs ; 1,592 / 3,247 ( 49 % ) ; ; Logic elements in carry chains ; 2314 ; ; User inserted logic elements ; 0 ; ; Virtual pins ; 0 ; ; I/O pins ; 254 / 598 ( 42 % ) ; ; -- Clock pins ; 5 / 16 ( 31 % ) ; ; Global signals ; 10 ; ; M512s ; 24 / 295 ( 8 % ) ; ; M4Ks ; 171 / 171 ( 100 % ) ; ; M-RAMs ; 2 / 4 ( 50 % ) ; ; Total memory bits ; 812,544 / 3,317,184 ( 24 % ) ; ; Total RAM block bits ; 1,981,440 / 3,317,184 ( 60 % ) ; ; DSP block 9-bit elements ; 8 / 96 ( 8 % ) ; ; PLLs ; 2 / 6 ( 33 % ) ; ; Global clocks ; 10 / 16 ( 63 % ) ; ; Regional clocks ; 0 / 16 ( 0 % ) ; ; Fast regional clocks ; 0 / 16 ( 0 % ) ; ; SERDES transmitters ; 0 / 82 ( 0 % ) ; ; SERDES receivers ; 0 / 82 ( 0 % ) ; ; JTAGs ; 0 / 1 ( 0 % ) ; ; Average interconnect usage (total/H/V) ; 15% / 13% / 18% ; ; Peak interconnect usage (total/H/V) ; 44% / 38% / 55% ; ; Maximum fan-out node ; altpll:altpll_component|_clk0 ; ; Maximum fan-out ; 6750 ; ; Highest non-global fan-out signal ; wishbone|pres_state.wb_cycle ; ; Highest non-global fan-out ; 323 ; ; Total fan-out ; 68893 ; ; Average fan-out ; 4.74 ; +---------------------------------------------+--------------------------------+
