Difference between revisions of "Clock Card firmware"
From MCEWiki
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== Programming File Catalog == | == Programming File Catalog == | ||
http://www.phas.ubc.ca/~mce/mcedocs/firmware/cc_fpga_programming_file_catalogue.pdf | http://www.phas.ubc.ca/~mce/mcedocs/firmware/cc_fpga_programming_file_catalogue.pdf | ||
| + | |||
| + | == To Do == | ||
| + | * Implement support for the cards_to_report command | ||
| + | * Implement support for the ret_dat_req and ret_dat_addr commands | ||
| + | * Fix the data rate parameter to reflect the actual spacing between data frames, even if the use_dv = 2 | ||
| + | * Finish supporting parameterized adjustments to the data pipeline stages | ||
| + | * Test internal command | ||
| + | * Implement a reset register | ||
| + | * Figure out why the CC is occasionally garbling the frame sequence number from the sync box | ||
| + | * Switch between factory and application does not work. | ||
| + | * Add a flag to the status block that indicates if the block has been updated since the last time it was read out. | ||
| + | * An additional flag is necessary in the PSUC software to indicate whether the status block has been updated on the PSUC too. This was added by RJ, and is in the location called ‘check bit’ in the status block. | ||
| + | * fpga_temp readings were unreliable because the firmware interface had marginal timing. In the process of fixing the firmware, I discovered that the capacitors on the SPI interface on the Address Card are the wrong values and need to be ECO’ed. Further investigation is needed to determine if we can leave them as they are and simply scale the readings. | ||
| + | * Implement the communications loss bit for the PSUC in the PSUC slave. | ||
| + | * Implement checksum error checking in the PSUC slave on communications with the PSUC | ||
| + | * Add a ‘target_card” command to the Clock Card. Then ret_dat can be a cc command. Make sure that firmware still supports DAS. | ||
| + | * Add logic in cmd_translator to shut down the MCE if over_temperature_o is asserted. | ||
| + | * Test BB id_thermo sensor block output | ||
| + | * Make sure that the stale data bit is being set properly in fpga_thermo and id_thermo. | ||
| + | * Fix the sync free run bit so that it is not set if the sync carrier signal is lost. same with sync sequence number. | ||
| + | * Work out the bugs in fpga_temp and card_temp. | ||
| + | * test box_temp/ box_id. | ||
| + | * Shutdown automatically in case of over-temperature. The code for this is in reply queue. | ||
| + | * Add a box_id_thermo slave to the Clock Card top level. Figure out what’s wrong with the BOX id_thermo block in the Clock Card top level. | ||
| + | * The ramp functionality now supports more than one data word. Simulate this. | ||
== 4.0.8 == | == 4.0.8 == | ||
Revision as of 16:32, 12 June 2008
Programming File Catalog
http://www.phas.ubc.ca/~mce/mcedocs/firmware/cc_fpga_programming_file_catalogue.pdf
To Do
- Implement support for the cards_to_report command
- Implement support for the ret_dat_req and ret_dat_addr commands
- Fix the data rate parameter to reflect the actual spacing between data frames, even if the use_dv = 2
- Finish supporting parameterized adjustments to the data pipeline stages
- Test internal command
- Implement a reset register
- Figure out why the CC is occasionally garbling the frame sequence number from the sync box
- Switch between factory and application does not work.
- Add a flag to the status block that indicates if the block has been updated since the last time it was read out.
- An additional flag is necessary in the PSUC software to indicate whether the status block has been updated on the PSUC too. This was added by RJ, and is in the location called ‘check bit’ in the status block.
- fpga_temp readings were unreliable because the firmware interface had marginal timing. In the process of fixing the firmware, I discovered that the capacitors on the SPI interface on the Address Card are the wrong values and need to be ECO’ed. Further investigation is needed to determine if we can leave them as they are and simply scale the readings.
- Implement the communications loss bit for the PSUC in the PSUC slave.
- Implement checksum error checking in the PSUC slave on communications with the PSUC
- Add a ‘target_card” command to the Clock Card. Then ret_dat can be a cc command. Make sure that firmware still supports DAS.
- Add logic in cmd_translator to shut down the MCE if over_temperature_o is asserted.
- Test BB id_thermo sensor block output
- Make sure that the stale data bit is being set properly in fpga_thermo and id_thermo.
- Fix the sync free run bit so that it is not set if the sync carrier signal is lost. same with sync sequence number.
- Work out the bugs in fpga_temp and card_temp.
- test box_temp/ box_id.
- Shutdown automatically in case of over-temperature. The code for this is in reply queue.
- Add a box_id_thermo slave to the Clock Card top level. Figure out what’s wrong with the BOX id_thermo block in the Clock Card top level.
- The ramp functionality now supports more than one data word. Simulate this.
4.0.8
- Filename : cc_v04000008_02feb2008.sof or .pof
- Feautres
- Bugs
- Switching to Application Config sometimes fails and the red light comes up.
- If the FPGA on a card is not programmed, it does not report an error (it treats the card as the not-present card and therefore the error is masked).
- If PSUC is not present and not communicating, CC doesn't report error and instead reports RBOK with all 0s.
