Sync Box firmware

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There is an Altera CPLD (EPM570T144C3) and an Atmel micro-controller (AT89C51) on in the Sync Box.

  • SyncBox CPLD Firmware Description [PDF] (SC2-ELE-S589-201)
  • SyncBox Microcontroller Software Description [PDF] (SC2-ELE-S589-202)

Consequently, there are two sets of firmware:

  • firmware for the CPLD part (*.pof file)
  • firmware for the microcontroller (*.hex file)

Firmware Upgrade Instructions

Downloads

Firmware is available from the MCE firmware repository:

To upgrade the Sync Box firmware, most times both the microcontroller and the CPLD firmware need to be reprogrammed.

CPLD programming (.pof file)

The CPLD firmware can be loaded using the Altera USB-Blaster that connects to the on-board P23 JTAG header, and Quartus Programmer software. A .pof file needs to be loaded. The P23 connector is not wired out to the sync box enclosure. To access it, remove the sync box cover plate.

Microcontroller programming (.hex file)

The microcontroller program is loaded over a USB cable that connects your computer to the on-board J1 (USB-B) connector. This connector is not wired out to the sync box enclosure: to access it, remove the top cover. In the past we used Atmel's Flip Programmer. Now we recommend running dfu-programmer on linux. See:

Enabling reprogramming over USB

Regardless of what you use to program the sync box, you need to get the sync box bootloader to restart in reprogramming mode. To do this, the procedure is:

  1. Start with the sync box powered off and disconnected from USB
  2. Depress both the on-board RESET switch and the PS_EN switch. The PS_EN switch may be labeled as PRG_EN. Both switches are located next to the USB J1 connector on the board. NB: This is not the reset switch on the outside of the sync box enclosure.
  3. Power on the sync box.
  4. Release the RESET switch
  5. Release the PS_EN switch
  6. Plug in the USB cable

If this procedure is successfully performed, the sync box will present itself as a USB device to your computer. Your computer should now detect the sync box as an Atmel AT89C5131 device. If the sync box isn't accepting USB protocol commands, turn it off and try the procedure again.

Releases

Firmware set Rev. 31

Filename
sync_box_v31_21Jun2016.hex
sync_box_v31_21Jun2016.pof
Features
The two banks of Manchester outputs can now be configured independently. This permits up to 4 MCEs to share one timing configuration, while up to 4 other MCEs share a second timing configuration.
The microprocessor's on-board EEPROM can be used to load and save configurations. A preferred configuration can be loaded "on startup", so there is no need for per-experiment defaults.
Notes
The firmware version is not reported by the serial interface. Subsequent versions will report the version, so if you see the "eeprom" menu but no version number then you're probably looking at v31!

Firmware set Rev. 30

Features
The microprocessor code has been ported to the sdcc compiler. There are no changes in behaviour. This code should continue to work with CPLD code from version 1f.

Firmware set Rev. 22

Filename
sync_box_v22_26sep2014.hex
no change to cpld code
Features
Sync Box default values are set for ACT values: fr=38, num_rows=33, row_len=50

Firmware set Rev. 21

Filename
sync_box_v21_02sep2014.pof
no change to microcontroller code or *.hex file
Features
DV_FTS and DV_POL are now duplicate copies of DV_SPARE1 and DV_SPARE2, respectively. See IO for rackmount AC-in Sync Box

Firmware set Rev. 20

Filename
sync_box_v20_22aug2013.hex
Features
hard-coded Spider values of fr=120, num_rows=33, row_len=53 (which translates to row_len=106 on mce front)
firmware revision on rs232 interface now shows 20

Firmware set Rev. 1f

Filename
sync_box_v1f_25feb2010.pof
sync_box_v1f_25feb2010.hex
Features
adds a ckd command to the rs232 interface to adjust the frequency of DV_Spare1 and DV_Spare2 by setting a 50MHz divisor through the command.
when you turn on the sync box, the firmware revision 1f appears on the rs232 terminal

Firmware set Rev. 1e (6e?)

Filename
sync_box_v6e_11aug2008.pof
sync_box_v1c_17nov2006.hex
Features
added a 50MHz clock on SMA output of the Sync box
Note
Since the microcontroller code is still 1c and that is what is reported in rs232 terminal, there is no way to identify this set from a 1c set.

Firmware set Rev. 1c

Filename
sync_box_v6c_19oct2006.pof
sync_box_v1c_17nov2006.hex
Features

original firmware

Source code

The sync box source (both CPLD and Atmel code) is available in the sync_box project in the Multi-Channel Electronics GitHub project. So, something like this might work: 

git clone https://github.com/multi-channel-electronics/sync_box.git

Building the code

The CPLD code needs to be rebuilt using Quartus. The Atmel code is compiled with sdcc, which is available in many Linux distributions. In Ubuntu: 

sudo apt-get install sdcc
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