MCEWiki - User contributions [en]

Bus Backplane

2022-01-31T23:50:48Z

Sfatigoni: /* Schematics */

{{Related|Backplanes}}
The bus backplane distributes power to MCE cards and also provides the data bus which allows inter-card communication. The data bus consist of a multi-drop 'command' line from the master slot (clock card) to all slave cards (readout, address, bias cards) and two point-to-point 'reply' lines from each slave card to the clock card. All JTAG signals are routed on the backplane to form a single JTAG chain that can be used to program all the cards in the MCE. Bypass buffers on the JTAG signals allow programming a partially populated MCE.

* [[MCE backplane protocol]]

== Schematics ==

* MCEv2 5-MDM E0 (C586-201) [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/schematics/mceV2_BusBackplane_RevE/ELE-C586-201E_Bus_BP_Schematics.PDF PDF]] (Double MCEs)
* MCEv2 5-MDM D0 (C586-201) [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/schematics/mceV2_BusBackplane_RevD/ELE-C586-201_RevD0_BusBp_Schematics.pdf PDF]]
* MCEv2 3-MDM A (C586-101) [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/schematics/mceV2_BusBackplane_RevD/ELE-C586-101_BusBP_Schematic%20Prints.pdf PDF]]

[[Category:Backplanes]]

Bus Backplane

2022-01-31T23:43:31Z

Sfatigoni:

{{Related|Backplanes}}
The bus backplane distributes power to MCE cards and also provides the data bus which allows inter-card communication. The data bus consist of a multi-drop 'command' line from the master slot (clock card) to all slave cards (readout, address, bias cards) and two point-to-point 'reply' lines from each slave card to the clock card. All JTAG signals are routed on the backplane to form a single JTAG chain that can be used to program all the cards in the MCE. Bypass buffers on the JTAG signals allow programming a partially populated MCE.

* [[MCE backplane protocol]]

== Schematics ==

* MCEv2 5-MDM E0 (C586-201) [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/schematics/mceV2_BusBackplane_RevD/ELE-C586-201E_Bus_BP_Schematics.PDF PDF]] (Double MCEs)
* MCEv2 5-MDM D0 (C586-201) [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/schematics/mceV2_BusBackplane_RevD/ELE-C586-201_RevD0_BusBp_Schematics.pdf PDF]]
* MCEv2 3-MDM A (C586-101) [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/schematics/mceV2_BusBackplane_RevD/ELE-C586-101_BusBP_Schematic%20Prints.pdf PDF]]

[[Category:Backplanes]]

Bus Backplane

2022-01-31T23:42:32Z

Sfatigoni: /* Schematics */

{{Related|Backplanes}}
The bus backplane distributes power to MCE cards and also provides the data bus which allows inter-card communication. The data bus consist of a multi-drop 'command' line from the master slot (clock card) to all slave cards (readout, address, bias cards) and two point-to-point 'reply' lines from each slave card to the clock card. All JTAG signals are routed on the backplane to form a single JTAG chain that can be used to program all the cards in the MCE. Bypass buffers on the JTAG signals allow programming a partially populated MCE.

* [[MCE backplane protocol]]

== Schematics ==

* MCEv2 5-MDM E0 (C586-201) [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/schematics/doublemce_BusBp/ELE-C586-201E_Bus_BP_Schematics.PDF PDF]] (Double MCEs)
* MCEv2 5-MDM D0 (C586-201) [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/schematics/mceV2_BusBackplane_RevD/ELE-C586-201_RevD0_BusBp_Schematics.pdf PDF]]
* MCEv2 3-MDM A (C586-101) [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/schematics/mceV2_BusBackplane_RevD/ELE-C586-101_BusBP_Schematic%20Prints.pdf PDF]]

[[Category:Backplanes]]

Instrument Backplane

2022-01-31T23:37:40Z

Sfatigoni: /* 5MDM */

{{Related|Backplanes}}
== Functional Description ==
The Instrument backplane (IB) board distributes the cryostat signals on the 3 or 5 MDM connectors to the circuit boards in
the chassis. There are series load resistors for sq1_bias, ssa_fb, sq2_bias, sq2_fb, sq1_fb on the IB card.

There are two different types of IB cards to support 3-MDM or 5-MDM MCE crates.

The 5-MDM circuit board contains nine 96 pin 2mm connectors. Only eight connectors are used as the Clock Card connector has no analog signals. The backplane has 5 gold dot areas for mating to Delphi gold dot flex circuits (MCEv1) or 5 Hirose connectors (MCEv2). The 5 flex sections or Hirose connectors go to 5 pcb-mounted 100 pin MDM connectors.

Some spare signals are connected between the MDM connectors and the Instrument Backplane. These terminate at surface mount pads on the backplane.

* [[ Instrument Backplane MCEv1(S587-101) to MCEv2 (C587-201) changes ]]
* [[ Instrument Backplane 3-MDM Rev B to Rev C changes ]]
* [[ Instrument Backplane 3-MDM Rev C to Rev D changes]]
* [[Instrument Backplane Tester]] (IB Tester; Continuity Checker)

== Schematics ==
* MCEv2 3-MDM D0 (C587-101) [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/schematics/mceV2_InstrumentBackplane/ELE-C587-101_RevD0_3MDM_Inst_Backplane_Schematics.PDF PDF]] (differential Bias Lines routed, accomodates one-BC subrack for mux11 configuration)

* MCEv2 5-MDM B0 (C587-201) [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/schematics/mceV2_InstrumentBackplane/ELE_C587-201_RevB0_Inst_Backplane_Schematics.pdf PDF]] (one detector bias per column)

== end-of-life schematics==

=== 3MDM ===
* MCEv2 3-MDM B (C587-101) [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/schematics/mceV2_InstrumentBackplane/ELE-C587-101_RevB_Inst_Backplane_Schematic.pdf PDF]] (BC3 DAC00 to DAC15 are routed to TES 00 to 15, not configurable)
* MCEv2 3-MDM C1 (C587-101) [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/schematics/mceV2_InstrumentBackplane/ELE-C587-101_RevC1_3MDM_Inst_Backplane_Schematics.pdf PDF]] (Configurable jumpers route BC3 DAC00 to DAC15 to TES 00 to 15)
* MCEv2 3-MDM C2 (C587-101) [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/schematics/mceV2_InstrumentBackplane/ELE-C587-101_RevC2_3MDM_Inst_Backplane_Schematics.pdf PDF]] (Configurable jumpers route BC2 DAC16 to DAC31 to TES 00 to 15)

=== 5MDM ===
* MCEv2 5-MDM C0 (C587-201) [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/schematics/mceV2_InstrumentBackplane/ELE_C587-201_Rev_C0_INST_BP_Schematics.pdf PDF]] (Double MCEs)
* MCEv2 5-MDM A0 (C587-201) [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/schematics/mceV2_InstrumentBackplane/ELE_C587-201_RevA0_Inst_Backplane_Schematics.pdf PDF]] (one detector bias per column)
* MCEv1 5-MDM C3 (S587-101) [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/schematics/Instrument%20Backplane%20RevC/S587-101_Inst_Backplane_Schematics.pdf PDF]] (1 detector bias, 1 pixel heater, Rs1fb=2.0k)
* MCEv1 5-MDM C5 (S587-101) [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/schematics/Instrument%20Backplane%20RevC/S587-101CI5_Inst_Backplane_Schematics.pdf PDF]] (3 detector bias, Rs1fb=6.8k)
[[Category:Backplanes]]

Bus Backplane

2022-01-18T02:08:44Z

Sfatigoni: /* Schematics */

{{Related|Backplanes}}
The bus backplane distributes power to MCE cards and also provides the data bus which allows inter-card communication. The data bus consist of a multi-drop 'command' line from the master slot (clock card) to all slave cards (readout, address, bias cards) and two point-to-point 'reply' lines from each slave card to the clock card. All JTAG signals are routed on the backplane to form a single JTAG chain that can be used to program all the cards in the MCE. Bypass buffers on the JTAG signals allow programming a partially populated MCE.

* [[MCE backplane protocol]]

== Schematics ==

* MCEv2 5-MDM E0 (C586-201) [[https://phas.ubc.ca/~scuba2/sc2mce/system/bus_bp/design/protel/doubleMCE/ELE-C586-201E_Bus_BP_Schematics.PDF PDF]] (Double MCEs)
* MCEv2 5-MDM D0 (C586-201) [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/schematics/mceV2_BusBackplane_RevD/ELE-C586-201_RevD0_BusBp_Schematics.pdf PDF]]
* MCEv2 3-MDM A (C586-101) [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/schematics/mceV2_BusBackplane_RevD/ELE-C586-101_BusBP_Schematic%20Prints.pdf PDF]]

[[Category:Backplanes]]

Instrument Backplane

2022-01-18T02:02:05Z

Sfatigoni:

{{Related|Backplanes}}
== Functional Description ==
The Instrument backplane (IB) board distributes the cryostat signals on the 3 or 5 MDM connectors to the circuit boards in
the chassis. There are series load resistors for sq1_bias, ssa_fb, sq2_bias, sq2_fb, sq1_fb on the IB card.

There are two different types of IB cards to support 3-MDM or 5-MDM MCE crates.

The 5-MDM circuit board contains nine 96 pin 2mm connectors. Only eight connectors are used as the Clock Card connector has no analog signals. The backplane has 5 gold dot areas for mating to Delphi gold dot flex circuits (MCEv1) or 5 Hirose connectors (MCEv2). The 5 flex sections or Hirose connectors go to 5 pcb-mounted 100 pin MDM connectors.

Some spare signals are connected between the MDM connectors and the Instrument Backplane. These terminate at surface mount pads on the backplane.

* [[ Instrument Backplane MCEv1(S587-101) to MCEv2 (C587-201) changes ]]
* [[ Instrument Backplane 3-MDM Rev B to Rev C changes ]]
* [[ Instrument Backplane 3-MDM Rev C to Rev D changes]]
* [[Instrument Backplane Tester]] (IB Tester; Continuity Checker)

== Schematics ==
* MCEv2 3-MDM D0 (C587-101) [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/schematics/mceV2_InstrumentBackplane/ELE-C587-101_RevD0_3MDM_Inst_Backplane_Schematics.PDF PDF]] (differential Bias Lines routed, accomodates one-BC subrack for mux11 configuration)

* MCEv2 5-MDM B0 (C587-201) [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/schematics/mceV2_InstrumentBackplane/ELE_C587-201_RevB0_Inst_Backplane_Schematics.pdf PDF]] (one detector bias per column)

== end-of-life schematics==

=== 3MDM ===
* MCEv2 3-MDM B (C587-101) [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/schematics/mceV2_InstrumentBackplane/ELE-C587-101_RevB_Inst_Backplane_Schematic.pdf PDF]] (BC3 DAC00 to DAC15 are routed to TES 00 to 15, not configurable)
* MCEv2 3-MDM C1 (C587-101) [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/schematics/mceV2_InstrumentBackplane/ELE-C587-101_RevC1_3MDM_Inst_Backplane_Schematics.pdf PDF]] (Configurable jumpers route BC3 DAC00 to DAC15 to TES 00 to 15)
* MCEv2 3-MDM C2 (C587-101) [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/schematics/mceV2_InstrumentBackplane/ELE-C587-101_RevC2_3MDM_Inst_Backplane_Schematics.pdf PDF]] (Configurable jumpers route BC2 DAC16 to DAC31 to TES 00 to 15)

=== 5MDM ===
* MCEv2 5-MDM C0 (C587-201) [[https://phas.ubc.ca/~scuba2/sc2mce/system/instr_bp/design/protel/doubleMCE/IB_C587-201_C/ELE_C587-201_Rev_C0_INST_BP_Schematics.pdf PDF]] (Double MCEs)
* MCEv2 5-MDM A0 (C587-201) [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/schematics/mceV2_InstrumentBackplane/ELE_C587-201_RevA0_Inst_Backplane_Schematics.pdf PDF]] (one detector bias per column)
* MCEv1 5-MDM C3 (S587-101) [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/schematics/Instrument%20Backplane%20RevC/S587-101_Inst_Backplane_Schematics.pdf PDF]] (1 detector bias, 1 pixel heater, Rs1fb=2.0k)
* MCEv1 5-MDM C5 (S587-101) [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/schematics/Instrument%20Backplane%20RevC/S587-101CI5_Inst_Backplane_Schematics.pdf PDF]] (3 detector bias, Rs1fb=6.8k)
[[Category:Backplanes]]

Instrument Backplane

2022-01-18T02:00:08Z

Sfatigoni:

{{Related|Backplanes}}
== Functional Description ==
The Instrument backplane (IB) board distributes the cryostat signals on the 3 or 5 MDM connectors to the circuit boards in
the chassis. There are series load resistors for sq1_bias, ssa_fb, sq2_bias, sq2_fb, sq1_fb on the IB card.

There are two different types of IB cards to support 3-MDM or 5-MDM MCE crates.

The 5-MDM circuit board contains nine 96 pin 2mm connectors. Only eight connectors are used as the Clock Card connector has no analog signals. The backplane has 5 gold dot areas for mating to Delphi gold dot flex circuits (MCEv1) or 5 Hirose connectors (MCEv2). The 5 flex sections or Hirose connectors go to 5 pcb-mounted 100 pin MDM connectors.

Some spare signals are connected between the MDM connectors and the Instrument Backplane. These terminate at surface mount pads on the backplane.

* [[ Instrument Backplane MCEv1(S587-101) to MCEv2 (C587-201) changes ]]
* [[ Instrument Backplane 3-MDM Rev B to Rev C changes ]]
* [[ Instrument Backplane 3-MDM Rev C to Rev D changes]]
* [[Instrument Backplane Tester]] (IB Tester; Continuity Checker)

== Schematics ==
* MCEv2 3-MDM D0 (C587-101) [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/schematics/mceV2_InstrumentBackplane/ELE-C587-101_RevD0_3MDM_Inst_Backplane_Schematics.PDF PDF]] (differential Bias Lines routed, accomodates one-BC subrack for mux11 configuration)

* MCEv2 5-MDM B0 (C587-201) [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/schematics/mceV2_InstrumentBackplane/ELE_C587-201_RevB0_Inst_Backplane_Schematics.pdf PDF]] (one detector bias per column)

== end-of-life schematics==

=== 3MDM ===
* MCEv2 3-MDM B (C587-101) [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/schematics/mceV2_InstrumentBackplane/ELE-C587-101_RevB_Inst_Backplane_Schematic.pdf PDF]] (BC3 DAC00 to DAC15 are routed to TES 00 to 15, not configurable)
* MCEv2 3-MDM C1 (C587-101) [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/schematics/mceV2_InstrumentBackplane/ELE-C587-101_RevC1_3MDM_Inst_Backplane_Schematics.pdf PDF]] (Configurable jumpers route BC3 DAC00 to DAC15 to TES 00 to 15)
* MCEv2 3-MDM C2 (C587-101) [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/schematics/mceV2_InstrumentBackplane/ELE-C587-101_RevC2_3MDM_Inst_Backplane_Schematics.pdf PDF]] (Configurable jumpers route BC2 DAC16 to DAC31 to TES 00 to 15)

=== 5MDM ===
* MCEv2 5-MDM C0 (C587-201) [[https://phas.ubc.ca/~scuba2/sc2mce/system/instr_bp/design/protel/doubleMCE/IB_C587-201_C/ELE_C587-201_Rev_C0_INST_BP_Schematics.pdf PDF]]
* MCEv2 5-MDM A0 (C587-201) [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/schematics/mceV2_InstrumentBackplane/ELE_C587-201_RevA0_Inst_Backplane_Schematics.pdf PDF]] (one detector bias per column)
* MCEv1 5-MDM C3 (S587-101) [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/schematics/Instrument%20Backplane%20RevC/S587-101_Inst_Backplane_Schematics.pdf PDF]] (1 detector bias, 1 pixel heater, Rs1fb=2.0k)
* MCEv1 5-MDM C5 (S587-101) [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/schematics/Instrument%20Backplane%20RevC/S587-101CI5_Inst_Backplane_Schematics.pdf PDF]] (3 detector bias, Rs1fb=6.8k)
[[Category:Backplanes]]

Instrument Backplane

2022-01-18T01:32:43Z

Sfatigoni:

{{Related|Backplanes}}
== Functional Description ==
The Instrument backplane (IB) board distributes the cryostat signals on the 3 or 5 MDM connectors to the circuit boards in
the chassis. There are series load resistors for sq1_bias, ssa_fb, sq2_bias, sq2_fb, sq1_fb on the IB card.

There are two different types of IB cards to support 3-MDM or 5-MDM MCE crates.

The 5-MDM circuit board contains nine 96 pin 2mm connectors. Only eight connectors are used as the Clock Card connector has no analog signals. The backplane has 5 gold dot areas for mating to Delphi gold dot flex circuits (MCEv1) or 5 Hirose connectors (MCEv2). The 5 flex sections or Hirose connectors go to 5 pcb-mounted 100 pin MDM connectors.

Some spare signals are connected between the MDM connectors and the Instrument Backplane. These terminate at surface mount pads on the backplane.

* [[ Instrument Backplane MCEv1(S587-101) to MCEv2 (C587-201) changes ]]
* [[ Instrument Backplane 3-MDM Rev B to Rev C changes ]]
* [[ Instrument Backplane 3-MDM Rev C to Rev D changes]]
* [[Instrument Backplane Tester]] (IB Tester; Continuity Checker)

== Schematics ==
* MCEv2 3-MDM D0 (C587-101) [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/schematics/mceV2_InstrumentBackplane/ELE-C587-101_RevD0_3MDM_Inst_Backplane_Schematics.PDF PDF]] (differential Bias Lines routed, accomodates one-BC subrack for mux11 configuration)

* MCEv2 5-MDM B0 (C587-201) [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/schematics/mceV2_InstrumentBackplane/ELE_C587-201_RevB0_Inst_Backplane_Schematics.pdf PDF]] (one detector bias per column)

== end-of-life schematics==

=== 3MDM ===
* MCEv2 3-MDM B (C587-101) [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/schematics/mceV2_InstrumentBackplane/ELE-C587-101_RevB_Inst_Backplane_Schematic.pdf PDF]] (BC3 DAC00 to DAC15 are routed to TES 00 to 15, not configurable)
* MCEv2 3-MDM C1 (C587-101) [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/schematics/mceV2_InstrumentBackplane/ELE-C587-101_RevC1_3MDM_Inst_Backplane_Schematics.pdf PDF]] (Configurable jumpers route BC3 DAC00 to DAC15 to TES 00 to 15)
* MCEv2 3-MDM C2 (C587-101) [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/schematics/mceV2_InstrumentBackplane/ELE-C587-101_RevC2_3MDM_Inst_Backplane_Schematics.pdf PDF]] (Configurable jumpers route BC2 DAC16 to DAC31 to TES 00 to 15)

=== 5MDM ===
* MCEv2 5-MDM C0 (C587-201) [[ PDF]]
* MCEv2 5-MDM A0 (C587-201) [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/schematics/mceV2_InstrumentBackplane/ELE_C587-201_RevA0_Inst_Backplane_Schematics.pdf PDF]] (one detector bias per column)
* MCEv1 5-MDM C3 (S587-101) [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/schematics/Instrument%20Backplane%20RevC/S587-101_Inst_Backplane_Schematics.pdf PDF]] (1 detector bias, 1 pixel heater, Rs1fb=2.0k)
* MCEv1 5-MDM C5 (S587-101) [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/schematics/Instrument%20Backplane%20RevC/S587-101CI5_Inst_Backplane_Schematics.pdf PDF]] (3 detector bias, Rs1fb=6.8k)
[[Category:Backplanes]]

MCE hardware

2021-12-07T01:34:15Z

Sfatigoni:

{{Related|Hardware}}
== General information ==
* [http://www.phas.ubc.ca/~mce/mcedocs/overview/functional_desc.pdf Functional Description of the Multi-Channel Electronics (PDF)] (Sep. 27, 2003)
* [http://www.phas.ubc.ca/~mce/mcedocs/overview/SC2_ELE_S580_520_mce_getting_started_manual.pdf MCE Getting-Started Manual : Cryostat installation, troubleshooting, firmware upgrade (PDF)]
* [[ MCE Accessories ]]
* [[ Ordering MCE Hardware ]]
* [[ MCE Power Requirements ]]
* [http://www.phas.ubc.ca/~mce/mcedocs/hardware/Characteristics/MUX_drive_ubc_actual_values_Rev1.7.xls Output Drive Calculations (XLS)]
* [[Noise Calculations]]

== Subrack interface and mounting ==
* [[Subrack|MCE Subrack]] (volume, mass, configuration)
* [http://www.phas.ubc.ca/~mce/mcedocs/overview/SC2_ELE_S580_005_Rev4.0_mce_interfaces.pdf Hardware Interface Block Diagram(PDF)]
* '''Proposed''' MCE signal assignment scheme: [http://www.phas.ubc.ca/~mce/mcedocs/system/mce_mdm_signal_names_and_pinouts.pdf [PDF]] [http://www.phas.ubc.ca/~mce/mcedocs/system/mce_mdm_signal_names_and_pinouts.xls [XLS]]
* MCE-Cryostat Diagram - cartoons of squid chain setup, servo loop calculations, and word-sizes [[http://www.phas.ubc.ca/~mce/mcedocs/system/Cryo_MCE%20Block%20Diagram.pdf PDF]]

== Hardware documents ==
'''Caveat lector:''' some of the documents in the following tables are obsolete, and have not been updated recently. They may contain incorrect or outdated information. Read with caution.
{{MCE hardware table}}

=== Other component details ===

* [[MCE FPGA Types]]
* [[ MCE CARD Serial-Number Lookup ]]

== Production testing ==
* [[ Test plans ]]

[[Category:Hardware| ]]

Programming over Fibre

2021-12-04T00:23:02Z

Sfatigoni:

{{Related|Development Tools}}
The procedure to update the [[MCE firmware]] over the fibre interface using a [[MAS]] PC, also known as "Remote Firmware Update", is described here.

= Introduction =

Each of the Address Card, Bias Cards, and Readout Cards of the MCE has an Altera Stratix FPGA along with a configuration device ([[MCE FPGA Types | See here]]). The Clock Card, however, has one FPGA with two configuration devices. FPGAs are RAM-based devices while configuration devices are Flash-based devices. Upon power up, each FPGA is loaded from its respective configuration device. The Clock Card FPGA is loaded from its factory configuration device upon power up, but then later, the firmware in the application configuration device can be loaded into the FPGA by issuing a command, i.e.:

mce_cmd -x rs cc {{param|cc|config_app}}

All these programmable parts, with the exception of the factory configuration device, are on a continuous JTAG chain that can be controlled via the MCE front-panel connector with an attached USB-Blaster, ''or'' via the Clock Card FPGA, provided it is running the right firmware, and is driven through the fibre interface.

The factory configuration device, however, is not on the same JTAG chain. It is only accessible through an on-board JTAG connector and can only be programmed with a USB-Blaster attached and Quartus Programmer.

In order to load temporary firmware, an sof file can be loaded into the FPGA. This firmware will be lost upon power cycle. To load permanent firmware, a pof file (or a jic file depending on EPC16 or EPCS64) can be loaded.

= Remote Update: step by step =
This can be done in 3 steps:
# Scan JTAG chain
# Generate JAM file
# Update Firmware
== Scan JTAG Chain ==

Run '''mce_auto_detect''':
user@ubuntu:~$ mce_auto_detect
mce_scan version 1
card_scan
# card card_id card_type pcb_rev slot_id
2 0x124fb77 3 0 8
3 0x19c74de 2 0 4
4 0x1256aa5 2 0 5
7 0x19c0a93 1 6 1
8 0x19c3071 1 6 2
9 0x19c1455 1 6 3
10 0x19c6305 0 0 0
jtag_scan
# id device
1 EPC4/EPC8/EPC16
2 EP1S40
3 EPC4/EPC8/EPC16
4 EP1S40
5 EPC4/EPC8/EPC16
6 EP1S10
7 EPC4/EPC8/EPC16
8 EP1S10
9 EPC4/EPC8/EPC16
10 EP1S10
11 EPC4/EPC8/EPC16
12 EP1S10
13 EPC4/EPC8/EPC16

Note that the order of devices are cc (#1), rc2 (device #2, #3), rc1(#4, #5), bc3 (#6, #7), bc2(#8, #9), bc1(#10, #11), ac(#12, #13).

Device #1 refers to the Application configuration device on Clock Card.

If there are no devices listed below "jtag_scan", you probably have to flip a jumper on your clock card. See the section below on [[ #Hardware Requirements ]].

== Generate Jam File ==
You need to update firmware on one device type at a time, i.e., EPC only, or FPGA only, or EPCS64 only.

'''If you have access to internet:'''
# Go to MCE Firmware Canning Party webpage: http://e-mode.phas.ubc.ca/mcefcp/
# copy and paste the result of mce_auto_detect on that webpage.
# Choose the target device(s) you want to program and a drop down menu of available firmware revisions will appear.
# Choose the firmware revision and click generate (find out which is the appropriate firmware version here: https://e-mode.phas.ubc.ca/mcewiki/index.php/MCE_firmware and download the firmware from here: https://e-mode.phas.ubc.ca/mce/firmware/).
# Save the generated file somewhere on your mas PC.

'''If you do NOT have access to internet:'''
# Install Quartus II Web Edition on Linux [[Quartus II Installation | See Instructions here]]
# make a cdf file from the output of mce_auto_detect. Here is a sample cdf file [http://www.phas.ubc.ca/~mce/mcedocs/software/sample.cdf CDF]
# generate a jam file by typing:
quartus_cpf -c <cdf_file_name> <jamfilename>

== Update Firmware==

Run '''mce_fw_update''':
Usage: /usr/mce/mce_script/script/mce_fw_update <device> <jamfilename>
device one of:
FPGA: for temporary firmware (sof)
EPC16: for permanent firmware on any card other than RC Rev. E (pof)
EPCS64: for permanent firmware on RC Rev. E (jic)
jamfilename either an absolute pathname, or a file in $MCE_JAM_DIR

If you are programming FPGA parts (temporary firmware), this step takes seconds. However, it takes minutes to program permanent firmware into EPC16 or EPCS64 devices, e.g. '''13 minutes''' to program 2 rev F. Readout Cards.

If the programming fails, you might need to mess with the programming frequencies. These are passed to mce_jam via the -f flag, as frequencies in Hz. See the mce_fw_update script, and try decreasing the frequency by a factor of 10.

Note that when programming permanent firmware, the fw_rev will not immediately be updated. The new firmware will not be loaded until the card is power cycled.

= Troubleshooting Remote Update =
== Software Requirements ==
Make sure the following are installed.
From the MAS repository:
* mce_jam : This will be installed under /usr/mce/bin/.
From the MCE script repository (trunk):
* read_idcode.jam : This should be in $MAS_TEMPLATE directory.
* $MCE_JAM_DIR is set : This is set through mas_env.bash.
* mce_auto_detect (in mce_script directory)
* mce_fw_update (in mce_script directory)
== Firmware Requirements ==
The Clock Card FPGA has to run firmware revision 5.0.7 or later. Considering that Clock Card FPGA can be loaded through either the Factory or Application configuration devices, at least one of these need to have 5.0.7+ firmware. If you are running Clock Card firmware prior to 5.0.7, which means your factory configuration device is loaded with firmware prior to 5.0.7, then attach USB-Blaster to the MCE front-panel connector. Run Quaruts Programmer, click on auto-detect, and program the second part from the bottom of the list, EPC16, with Clock Card firmware 5.0.7+.pof.

Then issue the following command:
mce_cmd -x rs cc {{param|cc|config_app}}
to switch to the new firmware. (Read back the firmware revision to make sure the new firmware is now active.)

== Hardware Requirements ==
The buffer that controls whether the FPGA can drive the JTAG chain or not is controlled by BB_EN or SW1 dip switch setting on the Clock Card. Clock Cards shipped earlier than Dec. 2010, do not have the right settings. To check this setting on your Clock Card, turn off the MCE power and unplug the Clock Card. The SW1.P1 labeled as "BB_EN" DIP should be on OPEN position.

* Note that with DIP switch SW1.P1 set to OPEN, you can not program the FPGA(sof) from the front panel connector (USB_Blaster) anymore.
* With DIP switch set to OPEN, if CC firmware is pre-5.0.7, you can not access the JTAG chain from the front panel connector (USB_Blaster) anymore. Assuming you have 5.0.7+ in your configuration device, you need to issue: <code>mce_cmd -x rs cc config_app 1</code> to be able to access front-panel JTAG.

= Footnotes =
== Porting Remote Configuration Sofware to DAS ==
The following C-code will need to be ported to DAS to enable Remote Configuration. You will need to convert the MCE WB and RB commands in the code to use DAS libraries and compile the code with the included Makefile:
*[http://www.phas.ubc.ca/~mce/mcedocs/software/mce_jam/ MCE Jam Player -- SVN revision 16 (~/jp_25/mce_jam/trunk)].
** '''jam_mce.c''': contains low-level MCE routines used during programming
** all other files should be fine.

== Development Notes ==
* [[intmce:Remote Firmware Update]]

[[Category:Firmware]]
[[Category:MAS]]
[[Category:MCE Script]]
[[Category:Development Tools]]

Programming over Fibre

2021-12-04T00:22:21Z

Sfatigoni:

{{Related|Development Tools}}
The procedure to update the [[MCE firmware]] over the fibre interface using a [[MAS]] PC, also known as "Remote Firmware Update", is described here.

= Introduction =

Each of the Address Card, Bias Cards, and Readout Cards of the MCE has an Altera Stratix FPGA along with a configuration device ([[MCE FPGA Types | See here]]). The Clock Card, however, has one FPGA with two configuration devices. FPGAs are RAM-based devices while configuration devices are Flash-based devices. Upon power up, each FPGA is loaded from its respective configuration device. The Clock Card FPGA is loaded from its factory configuration device upon power up, but then later, the firmware in the application configuration device can be loaded into the FPGA by issuing a command, i.e.:

mce_cmd -x rs cc {{param|cc|config_app}}

All these programmable parts, with the exception of the factory configuration device, are on a continuous JTAG chain that can be controlled via the MCE front-panel connector with an attached USB-Blaster, ''or'' via the Clock Card FPGA, provided it is running the right firmware, and is driven through the fibre interface.

The factory configuration device, however, is not on the same JTAG chain. It is only accessible through an on-board JTAG connector and can only be programmed with a USB-Blaster attached and Quartus Programmer.

In order to load temporary firmware, an sof file can be loaded into the FPGA. This firmware will be lost upon power cycle. To load permanent firmware, a pof file (or a jic file depending on EPC16 or EPCS64) can be loaded.

= Remote Update: step by step =
This can be done in 3 steps:
# Scan JTAG chain
# Generate JAM file
# Update Firmware
== Scan JTAG Chain ==

Run '''mce_auto_detect''':
user@ubuntu:~$ mce_auto_detect
mce_scan version 1
card_scan
# card card_id card_type pcb_rev slot_id
2 0x124fb77 3 0 8
3 0x19c74de 2 0 4
4 0x1256aa5 2 0 5
7 0x19c0a93 1 6 1
8 0x19c3071 1 6 2
9 0x19c1455 1 6 3
10 0x19c6305 0 0 0
jtag_scan
# id device
1 EPC4/EPC8/EPC16
2 EP1S40
3 EPC4/EPC8/EPC16
4 EP1S40
5 EPC4/EPC8/EPC16
6 EP1S10
7 EPC4/EPC8/EPC16
8 EP1S10
9 EPC4/EPC8/EPC16
10 EP1S10
11 EPC4/EPC8/EPC16
12 EP1S10
13 EPC4/EPC8/EPC16

Note that the order of devices are cc (#1), rc2 (device #2, #3), rc1(#4, #5), bc3 (#6, #7), bc2(#8, #9), bc1(#10, #11), ac(#12, #13).

Device #1 refers to the Application configuration device on Clock Card.

If there are no devices listed below "jtag_scan", you probably have to flip a jumper on your clock card. See the section below on [[ #Hardware Requirements ]].

== Generate Jam File ==
You need to update firmware on one device type at a time, i.e., EPC only, or FPGA only, or EPCS64 only.

'''If you have access to internet:'''
# Go to MCE Firmware Canning Party webpage: http://e-mode.phas.ubc.ca/mcefcp/
# copy and paste the result of mce_auto_detect on that webpage.
# Choose the target device(s) you want to program and a drop down menu of available firmware revisions will appear.
# Choose the firmware revision and click generate.
(find out which is the appropriate firmware version here: https://e-mode.phas.ubc.ca/mcewiki/index.php/MCE_firmware and download the firmware from here: https://e-mode.phas.ubc.ca/mce/firmware/)
# Save the generated file somewhere on your mas PC.

'''If you do NOT have access to internet:'''
# Install Quartus II Web Edition on Linux [[Quartus II Installation | See Instructions here]]
# make a cdf file from the output of mce_auto_detect. Here is a sample cdf file [http://www.phas.ubc.ca/~mce/mcedocs/software/sample.cdf CDF]
# generate a jam file by typing:
quartus_cpf -c <cdf_file_name> <jamfilename>

== Update Firmware==

Run '''mce_fw_update''':
Usage: /usr/mce/mce_script/script/mce_fw_update <device> <jamfilename>
device one of:
FPGA: for temporary firmware (sof)
EPC16: for permanent firmware on any card other than RC Rev. E (pof)
EPCS64: for permanent firmware on RC Rev. E (jic)
jamfilename either an absolute pathname, or a file in $MCE_JAM_DIR

If you are programming FPGA parts (temporary firmware), this step takes seconds. However, it takes minutes to program permanent firmware into EPC16 or EPCS64 devices, e.g. '''13 minutes''' to program 2 rev F. Readout Cards.

If the programming fails, you might need to mess with the programming frequencies. These are passed to mce_jam via the -f flag, as frequencies in Hz. See the mce_fw_update script, and try decreasing the frequency by a factor of 10.

Note that when programming permanent firmware, the fw_rev will not immediately be updated. The new firmware will not be loaded until the card is power cycled.

= Troubleshooting Remote Update =
== Software Requirements ==
Make sure the following are installed.
From the MAS repository:
* mce_jam : This will be installed under /usr/mce/bin/.
From the MCE script repository (trunk):
* read_idcode.jam : This should be in $MAS_TEMPLATE directory.
* $MCE_JAM_DIR is set : This is set through mas_env.bash.
* mce_auto_detect (in mce_script directory)
* mce_fw_update (in mce_script directory)
== Firmware Requirements ==
The Clock Card FPGA has to run firmware revision 5.0.7 or later. Considering that Clock Card FPGA can be loaded through either the Factory or Application configuration devices, at least one of these need to have 5.0.7+ firmware. If you are running Clock Card firmware prior to 5.0.7, which means your factory configuration device is loaded with firmware prior to 5.0.7, then attach USB-Blaster to the MCE front-panel connector. Run Quaruts Programmer, click on auto-detect, and program the second part from the bottom of the list, EPC16, with Clock Card firmware 5.0.7+.pof.

Then issue the following command:
mce_cmd -x rs cc {{param|cc|config_app}}
to switch to the new firmware. (Read back the firmware revision to make sure the new firmware is now active.)

== Hardware Requirements ==
The buffer that controls whether the FPGA can drive the JTAG chain or not is controlled by BB_EN or SW1 dip switch setting on the Clock Card. Clock Cards shipped earlier than Dec. 2010, do not have the right settings. To check this setting on your Clock Card, turn off the MCE power and unplug the Clock Card. The SW1.P1 labeled as "BB_EN" DIP should be on OPEN position.

* Note that with DIP switch SW1.P1 set to OPEN, you can not program the FPGA(sof) from the front panel connector (USB_Blaster) anymore.
* With DIP switch set to OPEN, if CC firmware is pre-5.0.7, you can not access the JTAG chain from the front panel connector (USB_Blaster) anymore. Assuming you have 5.0.7+ in your configuration device, you need to issue: <code>mce_cmd -x rs cc config_app 1</code> to be able to access front-panel JTAG.

= Footnotes =
== Porting Remote Configuration Sofware to DAS ==
The following C-code will need to be ported to DAS to enable Remote Configuration. You will need to convert the MCE WB and RB commands in the code to use DAS libraries and compile the code with the included Makefile:
*[http://www.phas.ubc.ca/~mce/mcedocs/software/mce_jam/ MCE Jam Player -- SVN revision 16 (~/jp_25/mce_jam/trunk)].
** '''jam_mce.c''': contains low-level MCE routines used during programming
** all other files should be fine.

== Development Notes ==
* [[intmce:Remote Firmware Update]]

[[Category:Firmware]]
[[Category:MAS]]
[[Category:MCE Script]]
[[Category:Development Tools]]

DoubleMCE

2020-11-30T18:21:40Z

Sfatigoni:

A Double MCE is a 2 x 72-HP subrack containing 10 MDM connectors and eight read-out cards.
Functionally, one Double MCE behaves exactly like two single 72-HP MCEs. In this version, the MDM connectors have been rotated of 90 degrees with respect to the previous orientation.
Double MCEs have been designed to meet the mechanical constraints of the Bicep Array 150GHz Receiver.

* [https://drive.google.com/drive/folders/1OhS9kcsLWslnPfeDhU6YB-EDDkGrySsb?usp=sharing First prototype - pictures and videos ]

DoubleMCE

2020-11-30T18:21:07Z

Sfatigoni:

DoubleMCE

2020-11-24T15:49:47Z

Sfatigoni: