MCEWiki - User contributions [en]

Vicor Power Assembly

2026-05-22T00:13:58Z

Dvw:

{{Related|Power}}
The MCE can be equipped with a 24V DC-in or 48V DC-in switching supply designed for use in balloon-based experiments. This unit contains a set of Vicor DC-DC converters that are trimmed to accommodate losses from cables of up to 2-metres, so they can be located up to 2-m away from the actual MCE [[subrack]].
== Specification==

;DC input
: Either:
:* 24V (18-36V) - Rev. C, Issues 1, 2, 5, 6
:* 48V (36-60V) - Rev. C, Issues 3, 4, 7
: 3A at 24V to power one 3-MDM MCE48 crate (6A for two)

;DC output
: Va+: 6.1 to 6.3 V
: Va−: -6.1 to -6.3 V
: Vlvd: 4.4 to 4.7 V
: Vcore: 2.9 to 3.2 V
* ''Note:'' The VPA does not provide the obsolete Vah used by rev.A and B [[Readout card]]s and rev.A through D [[Bias card]]s

; Power: 100W

; Regulated: Yes

; Efficiency: 75%
; Dimensions (L x W x H):
: 24cm x 20cm x 5cm
; Weight:
: < 2kg and a 1-m power cable is ~1kg

== Connectors ==
; Input:
* '''Writing harness''': [http://www.phas.ubc.ca/~scuba2/sc2mce/system/power_supply_of_all_kinds/psu_Vicor/design/protel/vpa-c585-401d/ELE-S585-401C3_Schematics.PDF PDF]
* '''Connector''': Amphenol PTC-2A-14-5P
[[File:24-48Vin.png|400px]]
; Output:
* '''Wiring harness''': [http://www.phas.ubc.ca/~mce/mcedocs/hardware/schematics/PowerSupplyVicor/ELE-C584-402_RevA_Wiring_Harness.pdf PDF]
* '''Connector''': Winchester MRA34SG. '''[[MCE Power#Connector & pinout|Pinout]]'''
* ''Note:'' The VPA can power one 72-HP subrack, or two 48-HP subracks. Early revisions of the VPA had two output connectors. Currently, all VPAs have only one Winchester connector for power output, and a wye cable is used when powering pairs of 48-HP subracks.
== Schematics ==
* Vicor Power Supply Rev C2, PCB Schematics [https://phas.ubc.ca/~mce/mcedocs/hardware/schematics/PowerSupplyVicor/ELE_C585-401_RevC2_VicorPSU_Schematics.pdf]
* Vicor Power Supply Rev C3, PCB Schematics [https://phas.ubc.ca/~mce/mcedocs/hardware/schematics/PowerSupplyVicor/ELE_C585-401_RevC3_VicorPSU_Schematics.pdf]
* Wiring [https://phas.ubc.ca/~mce/mcedocs/hardware/schematics/PowerSupplyVicor/ELE-C584-402_RevA_Wiring_Harness.pdf]
== Mechanical Drawings ==
* Assembled Box: [http://www.phas.ubc.ca/~scuba2/sc2mce/system/power_supply_of_all_kinds/psu_Vicor/design/mech/Aluminum_Box/MEC-C585-416D_Enclosure.PDF MEC-C585-416D]
* Box Lid: [http://www.phas.ubc.ca/~scuba2/sc2mce/system/power_supply_of_all_kinds/psu_Vicor/design/mech/Aluminum_Box/MEC-C585-405D_Enclosure_Lid.PDF MEC-C585-405D]
* Unfolded Box: [http://www.phas.ubc.ca/~scuba2/sc2mce/system/power_supply_of_all_kinds/psu_Vicor/design/mech/Aluminum_Box/MEC-C585-404D_Enclosure_Box_Unfolded.PDF MEC-C585-404D]
* Mounting Flange: [http://www.phas.ubc.ca/~scuba2/sc2mce/system/power_supply_of_all_kinds/psu_Vicor/design/mech/Aluminum_Box/MEC-C585-406B_Enclosure_Flange.PDF MEC-C585-406B]

== Cooling ==
For Spider, the mounting/heat extraction block is bolted to a heat exchanger through which the 4He blow-off from the cryostat's vapour-cooled shield is vented.

== Photos ==
<gallery>
File:Vicor supply 1.jpg|Vicor supply attached to a subrack
File:Vicor supply 2.jpg|Vicor supply top face with heat pipes
File:Vicor supply 3.jpg|Vicor supply attached to a subrack
File:Vicor in spider flingle 1.jpg|3 vicor supplies in Spider mounting bracket, connector side
File:Vicor in spider flingle 2.jpg|3 vicor supplies in Spider mounting bracket, mounting/cooling side
</gallery>

== Testing ==
* [[Testing VPA]]

== ==
* back to [[MCE_Power]]

[[Category:Accessories]]
[[Category:Power]]

Digital 4-pole Butterworth Low-pass filter

2026-01-06T06:24:10Z

Dvw:

== Overview ==
A digital 4-pole Butterworth low-pass filter is implemented as 2 cascaded biquads (2-pole topology) in the '''[[Readout card firmware]]''' of the MCE. The transfer function of the IIR filter is:
<center>[[File:Math_butterworth.png|900px|alt=H(z) {{=}} \frac {1+2 z^{-1}+z^{-2}}{1+b^*_{11} z^{-1}+b^*_{12} z^{-2}} \cdot 2^{-k_2} \cdot \frac {1+2z^{-1}+z^{-2}}{1+b^*_{21} z^{-1}+b^*_{22} z^{-2}} \cdot {2^{-k_1}}]]</center>

Filter coefficients [[File:math_b11_star.png|30px|alt=b^*_{11}]], [[File:math_b12_star.png|30px|alt=b^*_{12}]], [[File:math_b21_star.png|30px|alt=b^*_{21}]], [[File:math_b22_star.png|30px|alt=b^*_{22}]], and truncation factors, ''k''1 and ''k''2, are hard coded in older firmware (before '''version 5.1.0'''), but with modern firmware, they can be programmed through software:

wb rca {{param|rc|fltr_coeff}} ''b''11 ''b''12 ''b''21 ''b''22 ''k''1 ''k''2

where ''bxy'' is a quantized version of [[File:math_bxy_star.png|30px|alt=b^*_{xy}]] computed as: [[File:Math_bxy_eq.png|150px|alt=b_{xy} {{=}} \left\lfloor\left{{bar}}b^*_{xy}\right{{bar}} \times 2^{14}\right\rfloor]], where ⌊•⌋ indicates the floor function. Note that in order to accommodate the quantization effects, you have to follow the recipe prescribed in the [[#Filter Coefficients|Filter Coefficients section]] below when specifying the coefficients and truncation factors.

There are 3 filter-related MCE parameters/commands:
* {{param|rc|fltr_type}}: to determine whether filter coefficients are hard-coded or configurable
* {{param|rc|fltr_coeff}}: to specify filter coefficients
* {{param|rc|fltr_rst}}: to reset the filter pipeline after changing coefficients

== Filter Specification ==
Filter specification of the 4-pole Butterworth filter is determined by the filter coefficients [[File:math_b11_star.png|30px|alt=b^*_{11}]], [[File:math_b12_star.png|30px|alt=b^*_{12}]], [[File:math_b21_star.png|30px|alt=b^*_{21}]], [[File:math_b22_star.png|30px|alt=b^*_{22}]], described earlier.

Assume:

* '''''f''cutoff''' is the frequency at which the signal after filtering is √2 of its maximum value (nominally the read-out rate Nyquist frequency), and
* '''''f''samp''' is the sampling frequency, calculated as <code>(50 Mhz) / (num_rows × row_len)</code>. For example: <code>50 MHz / (33 × 100) = 15151.5 Hz</code>.

''Note that the filter ''f''cutoff scales if ''f''samp changes.''

; Type 1 (hard-coded coefficients)
: ''supported in all rc '''except''' 5.0.7''
: DC amplification = 1217.9148
: ''f''cutoff / ''f''samp = 122.226 Hz / 15151 Hz
: Gain @ 200 Hz = 0.14189148 (wrt the DC gain)

; Type 2 (hard-coded coefficients)
: ''supported '''only''' in rc version 5.0.7''
: DC amplification = 2044
: ''f''cutoff / ''f''samp = 75 Hz / 30000 Hz
: A plot of the transfer function generated by simulating MCE firmware (VHDL)
[[File:mce_filter_type2_magnitude.png |150px]][[File:mce_filter_type2_phase.png|150px]]

; Type 255 (configurable coefficients)
: ''supported in rc 5.1.0+''
: Quantized filter coefficients ''b''11, ''b''12, ''b''21, ''b''22 and truncation factors, ''k''1, ''k''2 are parameterized and programmable by software.

The fitler type can be determined by reading back the MCE parameter called {{param|rc|fltr_type}}. (supported in firmware 5.0.a+)

The following plot shows the magnitude and the phase of Type 1 filter.

Here is Elia's original plot [[Media:BW_filter.ps]]. Then we see the same plot with the impulse-response also added (by Joe, Nov 29, 2007):
[[Image: BW_filter2.png]]

Here is the filter response for Scuba2 setting (''f''samp = 9.5 kHz, ''f''readout = 200 Hz): [[Media: Filter fs10kHz 200Hzdecimated response.ps ]]

== Filter-related Software changes ==

=== Determining the filter type ===

A {{param|rc|fltr_type}} parameter is introduced starting firmware 5.0.a:
* '''{{param|rc|fltr_type}} = 1''': ''f''cutoff / ''f''samp = 122.226 Hz / 15151 Hz
* '''{{param|rc|fltr_type}} = 2''': ''f''cutoff / ''f''samp = 75 Hz / 30000 Hz
* '''{{param|rc|fltr_type}} = 255''': configurable coefficient

All earlier firmware revisions are set to filter type 1 by default, except version 5.0.7 which is set to filter type 2.

=== Software requirements ===

* MAS - use mas/trunk r493 or later to get access to the {{param|rc|fltr_coeff}} MCE parameter.
** In [[mce.cin]], specify <code>$fw_rev["rc"] = 0x5010000</code> or greater.
* mce_script - use mce_script/trunk r764 or later
* In [[Mce config template system#experiment.cfg | experiment.cfg]]:
**specify one of:
config_filter = 0; # do not write filter coefficients to the MCE
config_filter = 1; # write filter coefficients to the MCE
and when config_filter = 1, the filter coefficients to be written to the MCE must be specified in the "filter_params" parameter, in the order [''b''11, ''b''12, ''b''21, ''b''22, ''k''1, ''k''2], e.g.:
filter_params = [ 32092, 15750, 31238, 14895, 0, 11]; # type 1 filter, ''f''cutoff/''f''samp = 122.226 Hz / 15.151 kHz
filter_params = [ 32295, 15915, 32568, 16188, 3, 14]; # type 2 filter, ''f''cutoff/''f''samp = 75 Hz / 30 kHz
filter_params = [ 32295, 15915, 32568, 16188, 5, 12]; # type 2 filter with more inter-biquad dynamic range (recommended)
filter_params = [ 32297, 15934, 31683, 15320, 0, 11]; # SCUBA-2 filter after 2011-06, ''f''cutoff/''f''samp = 75 Hz / 12.97 kHz

== Code for simulations ==

Note that as of mce_script r902, '''mce_data.py''' contains code for handling the MCE Butterworth filters. This can be used to load filter parameters from a runfile, and to get the complex frequency response of a filter. See [[mce_data.py#MCEButterworth_class]].

A smaller, quicker python example:
[[ Media: mce_filt_py.txt ]]

In this little IDL program you can find the functional form as a function of the frequency of the filter. First, Elia's original program, then as modified by Joe on November 29, 2007, then modified by Mandana on Jan. 14, 2009 for Scuba2 numbers:
* [[ Media: filter_pro.txt ]]
* [[ Media: filter_pro2.txt ]]
* [[ Media: low_pass_filter_model_pro.txt ]]

=== Digital, time domain simulation codes ===

Python-based model of a single biquad, in the time domain, for exploring digitization and dynamic range:
* [[ Media: biquad_time_domain_py.txt ]]

== Filter Coefficients ==
=== Butterworth Coefficients ===
The filter coefficients are generated using ''fdatool'' (Filter-design & Analysis tool, part of DSP Toolbox) in '''MATLAB/Simulink'''. These coefficients are floating numbers and in order to feed them to MCE firmware, they need to be quantized by converting to signed binary fractional (SBF) 1.14 format. You may use [[#Alternative to fdatool|alternate methods]] to generate coefficients. Here, we explain the method using ''fdatool''.

Once you launch the ''fdatool'', choose the following settings:

* Response Type: Low Pass
* Design Method: Butterworth
* Filter Order: 4

* Frequency Specifications:
** For Type 1:
*** ''f''samp = 12,195 Hz = 50 MHz/ (100 × 41)
*** ''f''cutoff = 100 Hz
** For Type 2:
*** ''f''samp = 30,000 Hz ≈ 50 MHz / (50 × 33)
*** ''f''cutoff = 75 Hz
** For Type 255:
*** ''f''samp = 50 MHz / ({{param|sys|row_len}} × {{param|sys|num_rows}})
*** ''f''cutoff=''f''readout / 2 (= ''f''samp / {{param|cc|data_rate}} / 2, if using internal CC triggering)
* The attenuation at ''f''cutoff is fixed at 3 dB (half the passband power)

Then click on Design Filter and you will get the following coefficients:
; Type 1
:Section 1:
::Numerator: 1 2 1
::Denominator: 1 -1.9587428340882587 0.96134553442399129
::Gain = 1/''g''1 = 0.00065067508393319923 (not implemented)
:Section 2:
::Numerator: 1 2 1
::Denominator: 1 -1.9066292518523014 0.90916270571237567
::Gain = 1/''g''2= 0.00063336346501859835 (not implemented)

; Type 2
:Section 1:
::Numerator: 1 2 1
::Denominator: 1 -1.9711486088510415 0.97139181456687917
:Section 2:
::Numerator: 1 2 1
::Denominator: 1 -1.9878047097960421 0.98804997058724808
:Gain = 1/(''g''1 × ''g''2)= 0.0000000037280516432624239 (not implemented)

; Type 255
: Plug in your desired ''f''samp and ''f''cutoff in MATLAB fdatool and you will get a set of coefficients:
:Section 1:
::Numerator: 1 2 1
::Denominator: 1 [[File:math_b11_star.png|30px|alt=b^*_{11}]], [[File:math_b12_star.png|30px|alt=b^*_{12}]]
:: Gain = 1/''g''1
:Section 2:
::Numerator: 1 2 1
::Denominator: 1 [[File:math_b21_star.png|30px|alt=b^*_{21}]], [[File:math_b22_star.png|30px|alt=b^*_{22}]]
::Gain = 1/''g''2

=== Coefficient Quantization ===
The quantization format is signed-binary fractional (SBF) 1.14 and then 2's complement to be able to account for positive and negative values.
* Compute the quantised coefficients ''bxy'' via: [[File:Math_bxy_eq.png|150px|alt=b_{xy} {{=}} \left\lfloor\left{{bar}}b^*_{xy}\right{{bar}} \times 2^{14}\right\rfloor]] (i.e. take the absolute value, multiply by 214 and then drop the fractional part).
* [[File:Math_k1_eq.png|170px|alt=k_1 {{=}} \left\lfloor \log_2 g_2 \right\rfloor - 10]], the output-truncation (10 is a historical constant)
* [[File:Math_k2_eq.png|160px|alt=k_2 = 1 + \left\lfloor \log_2 g_1 \right\rfloor]], the inter-stage truncation

For example, if we use this formula to quantize Type 1 coefficients listed above:
<center>[[File:Math_coeff_calc.png|800px|alt=\begin{align}
b_{11} &{{=}} \lfloor 1.9587428340882587 \times 2^{14}\rfloor &{{=}}&\ 32092\\
b_{12} &{{=}} \lfloor 0.96134553442399129 \times 2^{14}\rfloor &{{=}}&\ 15750\\
b_{21} &{{=}} \lfloor 1.9066292518523014 \times 2^{14}\rfloor &{{=}}&\ 31238\\
b_{22} &{{=}} \lfloor 0.90916270571237567 \times 2^{14}\rfloor &{{=}}&\ 14895\\
k_1 &{{=}} \left\lfloor \log_2 \left(1 / 0.00065067508393319923 \right)\right\rfloor - 10 &{{=}}&\ 0\\
k_2 &{{=}} 1 + \left\lfloor \log_2 \left(1 / 0.00063336346501859835 \right)\right\rfloor &{{=}}&\ 11
\end{align}]]</center>

* ''k''1 < 16 and ''k''2 < 32
* Now, if 32 − ''k''1 + ''k''2 > 32, then you have to talk to UBC!

:'''''The following ONLY concerns the MCE firmware developers:'''

:Prior to firmware 5.1.0, the coefficients were hardcoded in '''fsfb_calc_pack.vhd''' (FILTER_B11_COEF, FILTER_B12_COEF, FILTER_B21_COEFF, FILTER_B22_COEFF, FILTER_GAIN_WIDTH, FILTER_SCALE_LSB).''

=== Calculating the DC Gain (''k'') ===
Note that in firmware, instead of ''g''1 and ''g''2, an inter-biquad truncation of ''k''2 (implemented as a binary shift) and ''k''1, number of bits dropped after the second biquad, are implemented.

Hence, the overall gain becomes [[File:Math_gain_eq.png|60px|alt=\frac {g_1 g_2} {2^{(k_1 + k_2)}}]].

:''(Note for firmware developers: see FILTER_GAIN_WIDTH and FILTER_SCALE_LSB in '''fsfb_calc_pack.vhd'''.) ''

; Type 1
:''k''2 = 11, ''k''1 = 0, the filter gain is estimated at 1184, but VHDL simulation results in a gain of 1216.
; Type 2
:''k''2 = 14, ''k''1 = 3, the filter gain is estimated at 2046, but VHDL simulation results in a gain of 2181.

The gain difference can be attributed to the rounding effects associated with fixed-width arithmetic.

To roughly compute the gain, including the effects from truncating the coefficients, reverse the quantization process to obtain the floating point values associated with your coefficients, and plug into the filter definition. Here is a rough python program which computes the true gain for our Type 1 filter (''b''11 = 32092, ''b''12 = 15750, ''b''21 = 31238, ''b''22 = 14895, ''k''1 = 0, ''k''2 = 11):
from numpy import *
# Sum of k1 and k2 shifts:
k12 = 11+0
# Quantized coefficients b11, b12, b21, b22:
n = array([32092, 15750, 31238, 14895]).astype('float')
# Re-float
f = n/2**14
# Compute gain
gain = 16. / (2**k12 * (1 - f[0] + f[1]) * (1 - f[2] + f[3]))
print gain
# Result: 1217.8583043

== Useful Links ==
http://www.phas.ubc.ca/~mce/mcedocs/hardware/Firmware_block_spec/reaout_card/fsfb_calculations_rev1.11.pdf

http://www.planetanalog.com/showArticle.jhtml?articleID=12802683

== Alternative to fdatool ==
If you do not have access to fdatool or do not have DSP toolbox installed, you can use the following MATLAB functions (or equivalent in other packages) to get the coefficients:
* butter: is a matlab function to generate butterworth coefficients
* sos2tf: matlab function to break a transfer function to second-order sections
* bilinear: converts an s-domain (continuous) transfer function to z-domain (discrete) transfer function.
* Then run the following in matlab (or whatever syntax your tool has):
num=[1 2 1]
denum=[1 -1.9711486088510415 0.97139181456687917]
max(dbode(num, denum, 1/fsamp) but also look at the bode-plot to make sure it is flat, otherwise read the max from the flat portion of the plot instead of the max function.

'''Note:''' When I used coefficients generated by [a,b] = butter(2, 50/20000); [SOS,G]=tf2sos(a,b), the filter was not as robust. not sure why?!

[[Category:Readout Card Firmware]]

Digital 4-pole Butterworth Low-pass filter

2026-01-05T23:26:16Z

Dvw:

== Overview ==
A digital 4-pole Butterworth low-pass filter is implemented as 2 cascaded biquads (2-pole topology) in the '''[[Readout card firmware]]''' of the MCE. The transfer function of the IIR filter is:
<center>[[File:Math_butterworth.png|900px|alt=H(z) {{=}} \frac {1+2 z^{-1}+z^{-2}}{1+b^*_{11} z^{-1}+b^*_{12} z^{-2}} \cdot 2^{-k_2} \cdot \frac {1+2z^{-1}+z^{-2}}{1+b^*_{21} z^{-1}+b^*_{22} z^{-2}} \cdot {2^{-k_1}}]]</center>

Filter coefficients [[File:math_b11_star.png|30px|alt=b^*_{11}]], [[File:math_b12_star.png|30px|alt=b^*_{12}]], [[File:math_b21_star.png|30px|alt=b^*_{21}]], [[File:math_b22_star.png|30px|alt=b^*_{22}]], and truncation factors, ''k''1 and ''k''2, are hard coded in older firmware (before '''version 5.1.0'''), but with modern firmware, they can be programmed through software:

wb rca {{param|rc|fltr_coeff}} ''b''11 ''b''12 ''b''21 ''b''22 ''k''1 ''k''2

where ''bxy'' is a quantized version of [[File:math_bxy_star.png|30px|alt=b^*_{xy}]] computed as: [[File:Math_bxy_eq.png|150px|alt=b_{xy} {{=}} \left\lfloor\left{{bar}}b^*_{xy}\right{{bar}} \times 2^{14}\right\rfloor]], where ⌊•⌋ indicates the floor function. Note that in order to accommodate the quantization effects, you have to follow the recipe prescribed in the [[#Filter Coefficients|Filter Coefficients section]] below when specifying the coefficients and truncation factors.

There are 3 filter-related MCE parameters/commands:
* {{param|rc|fltr_type}}: to determine whether filter coefficients are hard-coded or configurable
* {{param|rc|fltr_coeff}}: to specify filter coefficients
* {{param|rc|fltr_rst}}: to reset the filter pipeline after changing coefficients

== Filter Specification ==
Filter specification of the 4-pole Butterworth filter is determined by the filter coefficients [[File:math_b11_star.png|30px|alt=b^*_{11}]], [[File:math_b12_star.png|30px|alt=b^*_{12}]], [[File:math_b21_star.png|30px|alt=b^*_{21}]], [[File:math_b22_star.png|30px|alt=b^*_{22}]], described earlier.

Assume:

* '''''f''cutoff''' is the frequency at which the signal after filtering is √2 of its maximum value (nominally the read-out rate Nyquist frequency), and
* '''''f''samp''' is the sampling frequency, calculated as <code>(50 Mhz) / (num_rows × row_len)</code>. For example: <code>50 MHz / (33 × 100) = 15151.5 Hz</code>.

''Note that the filter ''f''3dB scales if ''f''samp changes.''

; Type 1 (hard-coded coefficients)
: ''supported in all rc '''except''' 5.0.7''
: DC amplification = 1217.9148
: ''f''cutoff / ''f''samp = 122.226 Hz / 15151 Hz
: Gain @ 200 Hz = 0.14189148 (wrt the DC gain)

; Type 2 (hard-coded coefficients)
: ''supported '''only''' in rc version 5.0.7''
: DC amplification = 2044
: ''f''cutoff / ''f''samp = 75 Hz / 30000 Hz
: A plot of the transfer function generated by simulating MCE firmware (VHDL)
[[File:mce_filter_type2_magnitude.png |150px]][[File:mce_filter_type2_phase.png|150px]]

; Type 255 (configurable coefficients)
: ''supported in rc 5.1.0+''
: Quantized filter coefficients ''b''11, ''b''12, ''b''21, ''b''22 and truncation factors, ''k''1, ''k''2 are parameterized and programmable by software.

The fitler type can be determined by reading back the MCE parameter called {{param|rc|fltr_type}}. (supported in firmware 5.0.a+)

The following plot shows the magnitude and the phase of Type 1 filter.

Here is Elia's original plot [[Media:BW_filter.ps]]. Then we see the same plot with the impulse-response also added (by Joe, Nov 29, 2007):
[[Image: BW_filter2.png]]

Here is the filter response for Scuba2 setting (''f''samp = 9.5 kHz, ''f''readout = 200 Hz): [[Media: Filter fs10kHz 200Hzdecimated response.ps ]]

== Filter-related Software changes ==

=== Determining the filter type ===

A {{param|rc|fltr_type}} parameter is introduced starting firmware 5.0.a:
* '''{{param|rc|fltr_type}} = 1''': ''f''cutoff / ''f''samp = 122.226 Hz / 15151 Hz
* '''{{param|rc|fltr_type}} = 2''': ''f''cutoff / ''f''samp = 75 Hz / 30000 Hz
* '''{{param|rc|fltr_type}} = 255''': configurable coefficient

All earlier firmware revisions are set to filter type 1 by default, except version 5.0.7 which is set to filter type 2.

=== Software requirements ===

* MAS - use mas/trunk r493 or later to get access to the {{param|rc|fltr_coeff}} MCE parameter.
** In [[mce.cin]], specify <code>$fw_rev["rc"] = 0x5010000</code> or greater.
* mce_script - use mce_script/trunk r764 or later
* In [[Mce config template system#experiment.cfg | experiment.cfg]]:
**specify one of:
config_filter = 0; # do not write filter coefficients to the MCE
config_filter = 1; # write filter coefficients to the MCE
and when config_filter = 1, the filter coefficients to be written to the MCE must be specified in the "filter_params" parameter, in the order [''b''11, ''b''12, ''b''21, ''b''22, ''k''1, ''k''2], e.g.:
filter_params = [ 32092, 15750, 31238, 14895, 0, 11]; # type 1 filter, ''f''cutoff/''f''samp = 122.226 Hz / 15.151 kHz
filter_params = [ 32295, 15915, 32568, 16188, 3, 14]; # type 2 filter, ''f''cutoff/''f''samp = 75 Hz / 30 kHz
filter_params = [ 32295, 15915, 32568, 16188, 5, 12]; # type 2 filter with more inter-biquad dynamic range (recommended)
filter_params = [ 32297, 15934, 31683, 15320, 0, 11]; # SCUBA-2 filter after 2011-06, ''f''cutoff/''f''samp = 75 Hz / 12.97 kHz

== Code for simulations ==

Note that as of mce_script r902, '''mce_data.py''' contains code for handling the MCE Butterworth filters. This can be used to load filter parameters from a runfile, and to get the complex frequency response of a filter. See [[mce_data.py#MCEButterworth_class]].

A smaller, quicker python example:
[[ Media: mce_filt_py.txt ]]

In this little IDL program you can find the functional form as a function of the frequency of the filter. First, Elia's original program, then as modified by Joe on November 29, 2007, then modified by Mandana on Jan. 14, 2009 for Scuba2 numbers:
* [[ Media: filter_pro.txt ]]
* [[ Media: filter_pro2.txt ]]
* [[ Media: low_pass_filter_model_pro.txt ]]

=== Digital, time domain simulation codes ===

Python-based model of a single biquad, in the time domain, for exploring digitization and dynamic range:
* [[ Media: biquad_time_domain_py.txt ]]

== Filter Coefficients ==
=== Butterworth Coefficients ===
The filter coefficients are generated using ''fdatool'' (Filter-design & Analysis tool, part of DSP Toolbox) in '''MATLAB/Simulink'''. These coefficients are floating numbers and in order to feed them to MCE firmware, they need to be quantized by converting to signed binary fractional (SBF) 1.14 format. You may use [[#Alternative to fdatool|alternate methods]] to generate coefficients. Here, we explain the method using ''fdatool''.

Once you launch the ''fdatool'', choose the following settings:

* Response Type: Low Pass
* Design Method: Butterworth
* Filter Order: 4

* Frequency Specifications:
** For Type 1:
*** ''f''samp = 12,195 Hz = 50 MHz/ (100 × 41)
*** ''f''cutoff = 100 Hz
** For Type 2:
*** ''f''samp = 30,000 Hz ≈ 50 MHz / (50 × 33)
*** ''f''cutoff = 75 Hz
** For Type 255:
*** ''f''samp = 50 MHz / ({{param|sys|row_len}} × {{param|sys|num_rows}})
*** ''f''cutoff=''f''readout / 2 (= ''f''samp / {{param|cc|data_rate}} / 2, if using internal CC triggering)
* The attenuation at ''f''cutoff is fixed at 3 dB (half the passband power)

Then click on Design Filter and you will get the following coefficients:
; Type 1
:Section 1:
::Numerator: 1 2 1
::Denominator: 1 -1.9587428340882587 0.96134553442399129
::Gain = 1/''g''1 = 0.00065067508393319923 (not implemented)
:Section 2:
::Numerator: 1 2 1
::Denominator: 1 -1.9066292518523014 0.90916270571237567
::Gain = 1/''g''2= 0.00063336346501859835 (not implemented)

; Type 2
:Section 1:
::Numerator: 1 2 1
::Denominator: 1 -1.9711486088510415 0.97139181456687917
:Section 2:
::Numerator: 1 2 1
::Denominator: 1 -1.9878047097960421 0.98804997058724808
:Gain = 1/(''g''1 × ''g''2)= 0.0000000037280516432624239 (not implemented)

; Type 255
: Plug in your desired ''f''samp and ''f''cutoff in MATLAB fdatool and you will get a set of coefficients:
:Section 1:
::Numerator: 1 2 1
::Denominator: 1 [[File:math_b11_star.png|30px|alt=b^*_{11}]], [[File:math_b12_star.png|30px|alt=b^*_{12}]]
:: Gain = 1/''g''1
:Section 2:
::Numerator: 1 2 1
::Denominator: 1 [[File:math_b21_star.png|30px|alt=b^*_{21}]], [[File:math_b22_star.png|30px|alt=b^*_{22}]]
::Gain = 1/''g''2

=== Coefficient Quantization ===
The quantization format is signed-binary fractional (SBF) 1.14 and then 2's complement to be able to account for positive and negative values.
* Compute the quantised coefficients ''bxy'' via: [[File:Math_bxy_eq.png|150px|alt=b_{xy} {{=}} \left\lfloor\left{{bar}}b^*_{xy}\right{{bar}} \times 2^{14}\right\rfloor]] (i.e. take the absolute value, multiply by 214 and then drop the fractional part).
* [[File:Math_k1_eq.png|170px|alt=k_1 {{=}} \left\lfloor \log_2 g_2 \right\rfloor - 10]], the output-truncation (10 is a historical constant)
* [[File:Math_k2_eq.png|160px|alt=k_2 = 1 + \left\lfloor \log_2 g_1 \right\rfloor]], the inter-stage truncation

For example, if we use this formula to quantize Type 1 coefficients listed above:
<center>[[File:Math_coeff_calc.png|800px|alt=\begin{align}
b_{11} &{{=}} \lfloor 1.9587428340882587 \times 2^{14}\rfloor &{{=}}&\ 32092\\
b_{12} &{{=}} \lfloor 0.96134553442399129 \times 2^{14}\rfloor &{{=}}&\ 15750\\
b_{21} &{{=}} \lfloor 1.9066292518523014 \times 2^{14}\rfloor &{{=}}&\ 31238\\
b_{22} &{{=}} \lfloor 0.90916270571237567 \times 2^{14}\rfloor &{{=}}&\ 14895\\
k_1 &{{=}} \left\lfloor \log_2 \left(1 / 0.00065067508393319923 \right)\right\rfloor - 10 &{{=}}&\ 0\\
k_2 &{{=}} 1 + \left\lfloor \log_2 \left(1 / 0.00063336346501859835 \right)\right\rfloor &{{=}}&\ 11
\end{align}]]</center>

* ''k''1 < 16 and ''k''2 < 32
* Now, if 32 − ''k''1 + ''k''2 > 32, then you have to talk to UBC!

:'''''The following ONLY concerns the MCE firmware developers:'''

:Prior to firmware 5.1.0, the coefficients were hardcoded in '''fsfb_calc_pack.vhd''' (FILTER_B11_COEF, FILTER_B12_COEF, FILTER_B21_COEFF, FILTER_B22_COEFF, FILTER_GAIN_WIDTH, FILTER_SCALE_LSB).''

=== Calculating the DC Gain (''k'') ===
Note that in firmware, instead of ''g''1 and ''g''2, an inter-biquad truncation of ''k''2 (implemented as a binary shift) and ''k''1, number of bits dropped after the second biquad, are implemented.

Hence, the overall gain becomes [[File:Math_gain_eq.png|60px|alt=\frac {g_1 g_2} {2^{(k_1 + k_2)}}]].

:''(Note for firmware developers: see FILTER_GAIN_WIDTH and FILTER_SCALE_LSB in '''fsfb_calc_pack.vhd'''.) ''

; Type 1
:''k''2 = 11, ''k''1 = 0, the filter gain is estimated at 1184, but VHDL simulation results in a gain of 1216.
; Type 2
:''k''2 = 14, ''k''1 = 3, the filter gain is estimated at 2046, but VHDL simulation results in a gain of 2181.

The gain difference can be attributed to the rounding effects associated with fixed-width arithmetic.

To roughly compute the gain, including the effects from truncating the coefficients, reverse the quantization process to obtain the floating point values associated with your coefficients, and plug into the filter definition. Here is a rough python program which computes the true gain for our Type 1 filter (''b''11 = 32092, ''b''12 = 15750, ''b''21 = 31238, ''b''22 = 14895, ''k''1 = 0, ''k''2 = 11):
from numpy import *
# Sum of k1 and k2 shifts:
k12 = 11+0
# Quantized coefficients b11, b12, b21, b22:
n = array([32092, 15750, 31238, 14895]).astype('float')
# Re-float
f = n/2**14
# Compute gain
gain = 16. / (2**k12 * (1 - f[0] + f[1]) * (1 - f[2] + f[3]))
print gain
# Result: 1217.8583043

== Useful Links ==
http://www.phas.ubc.ca/~mce/mcedocs/hardware/Firmware_block_spec/reaout_card/fsfb_calculations_rev1.11.pdf

http://www.planetanalog.com/showArticle.jhtml?articleID=12802683

== Alternative to fdatool ==
If you do not have access to fdatool or do not have DSP toolbox installed, you can use the following MATLAB functions (or equivalent in other packages) to get the coefficients:
* butter: is a matlab function to generate butterworth coefficients
* sos2tf: matlab function to break a transfer function to second-order sections
* bilinear: converts an s-domain (continuous) transfer function to z-domain (discrete) transfer function.
* Then run the following in matlab (or whatever syntax your tool has):
num=[1 2 1]
denum=[1 -1.9711486088510415 0.97139181456687917]
max(dbode(num, denum, 1/fsamp) but also look at the bode-plot to make sure it is flat, otherwise read the max from the flat portion of the plot instead of the max function.

'''Note:''' When I used coefficients generated by [a,b] = butter(2, 50/20000); [SOS,G]=tf2sos(a,b), the filter was not as robust. not sure why?!

[[Category:Readout Card Firmware]]

Data accumulation rate

2026-01-05T23:20:32Z

Dvw: de-<math>

This page gives some rules for estimating the accumulation rate of data on disk for a running MCE.

== Rate calculations ==
In general, during a regular acquisition, the data rate (bit rate) of an MCE is:

:''S''w × (''S''head + ''N''c × ''N''RC × ''N''rro + ''S''chk) × ''f''DV
where:
* ''S''w is the word size (=32 bits)
* ''S''head is the size (in words) of the [[frame header]] (=43 words)
* ''N''c is the number of columns per [[readout card]] (=8)
* ''N''RC is the number of readout cards read out (see {{param|cc|rcs_to_report_data}})
* ''N''rro is the number of rows read out (i.e. {{param|cc|num_rows_reported}})
* ''S''chk is the size (in words) of the frame checksum (=1 word)
* ''f''DV is the read-out data rate. When in internal-DV mode (i.e. {{param|cc|use_dv}} is zero), this is:
::''f''DV = 50 MHz / (''N''dr × ''N''r × ''N''rl)
::      ≡ ''f''ARZ / ''N''dr
where:
* 50 MHz is the clock rate
* ''N''dr is the number of samples co-added into an output frame (i.e. {{param|cc|data_rate}})
* ''N''r is the number of rows servoed (i.e. {{param|sys|num_rows}})
* ''N''rl is the row dwell-time in clock periods (i.e. {{param|sys|row_len}}), and
* ''f''ARZ is the Address-return-to-zero rate, i.e. the frequency at which a single pixel is visited

A useful approximation is:
* a single readout card reading 41 rows at 400 Hz is ≈ 0.5 megabytes/second.

== Tables ==
Here are some tables of accumulation rates for both kinds of subracks for various data rates and numbers of rows:

{| class="wikitable" style="text-align: right"
|+ MCE data accumulation rate in Megabits per second (Mbps)
|-
! rowspan="2" |  
! colspan="4" | 48HP
! rowspan="5" |  
! colspan="4" | 72HP
|-
! 100 Hz
! 150 Hz
! 200 Hz
! 400 Hz
! 100 Hz
! 150 Hz
! 200 Hz
! 400 Hz
|-
! 25 rows
| 1.28
| 1.92
| 2.56
| 5.12
| 2.56
| 3.84
| 5.12
| 10.24
|-
! 33 rows
| 1.69
| 2.53
| 3.38
| 6.76
| 3.38
| 5.07
| 6.76
| 13.52
|-
! 41 rows
| 0.94
| 1.42
| 1.89
| 3.78
| 1.42
| 2.83
| 3.78
| 7.56
|}

{| class="wikitable" style="text-align: right"
|+ MCE data accumulation rate in Gigabytes (109 bytes) per hour
|-
! rowspan="2" |  
! colspan="4" | 48HP
! rowspan="5" |  
! colspan="4" | 72HP
|-
! 100 Hz
! 150 Hz
! 200 Hz
! 400 Hz
! 100 Hz
! 150 Hz
! 200 Hz
! 400 Hz
|-
! 25 rows
| 0.58
| 0.86
| 1.15
| 2.30
| 1.15
| 1.73
| 2.30
| 4.61
|-
! 33 rows
| 0.76
| 1.14
| 1.52
| 3.04
| 1.52
| 2.28
| 3.04
| 6.08
|-
! 41 rows
| 2.10
| 3.15
| 4.20
| 8.40
| 4.20
| 6.30
| 8.40
| 16.79
|}

{| class="wikitable" style="text-align: right"
|+ MCE data accumulation rate in Gigabytes (109 bytes) per day
|-
! rowspan="2" |  
! colspan="4" | 48HP
! rowspan="5" |  
! colspan="4" | 72HP
|-
! 100 Hz
! 150 Hz
! 200 Hz
! 400 Hz
! 100 Hz
! 150 Hz
! 200 Hz
! 400 Hz
|-
! 25 rows
| 13.8
| 20.7
| 27.7
| 55.3
| 27.7
| 41.5
| 55.3
| 110.6
|-
! 33 rows
| 18.1
| 27.4
| 36.5
| 73.0
| 36.5
| 54.7
| 73.0
| 146.0
|-
! 41 rows
| 22.7
| 34.0
| 45.3
| 90.7
| 45.3
| 68.0
| 90.7
| 181.4
|}

[[Category:Software]]

Bias Card low noise bias lines noise analysis

2026-01-05T23:10:18Z

Dvw: math

:''The following discussion is valid for '''BC Rev. F0, F1, F2, F3, F4''' where LN_BIAS DACs are used in bipolar configuration and U16 and U17 are populated with AD797A.''

The low noise detector bias lines in Rev F [[bias card]]s are driven by a bipolar DAC (MAX5444AEUB+) whose output is buffered by an opamp (AD797) in a non-inverting configuration (gain G=2), and inverted by a second opamp (AD797). These two signals are then each fed through a series resistance before going to the backplane and MDM connectors. The noise performance of these bias lines is determined by summing the noise contributions of:

* the input resistance to the op amp: ''Ri'' = ~6.3kΩ, mostly due to the output resistance of the DAC
* the matched feedback resistances of the buffer, which are internal to the DAC (RFB and INV pins): not listed in the datasheet, but measured as ''Rf1'' = ''Rf2'' = ~12kΩ
* the voltage noise of the AD797: ''en'' = 0.9 nV/√Hz at 1kHz
* the voltage noise of the DAC 2.5V reference voltage, ADR441: ''en,ref'' = ~50 nV/√Hz
* current noise of the AD797: ''in'' = 2.0 pA/√Hz, which multiplies both the input resistance to the non-inverting input (~6.3kΩ) and the parallel combination of the feedback resistors at the inverting input (~12kΩ each)

Using these numbers, the total noise at 1 kHz and ''T'' = 300K can be calculated as:
<center>[[File:Math_vnt_calc.png|1000px|alt=\begin{align}
v_{nt}(1\;\mathrm{kHz},300\;\mathrm{K}) &{{=}} \sqrt{ \quad 4kTR_i \quad + 4kT \left(R_{f_1}^{-1} + R_{f_2}^{-1}\right)^{-1} + \qquad e_n^2 \qquad + \quad\; e_{n,ref}^2 \quad\;+ i_n^2 \left[ R_i^2 + \left(R_{f_1}^{-1} + R_{f_2}^{-1}\right)^{-2}\right]}\\
&\approx \sqrt{\left(10.2\;\frac{\mathrm{nV}}{\sqrt{\mathrm{Hz}}}\right)^2 + \left(10.0\frac{\mathrm{nV}}{\sqrt{\mathrm{Hz}}}\right)^2 + \left(0.9\frac{\mathrm{nV}}{\sqrt{\mathrm{Hz}}}\right)^2 + \left(50\frac{\mathrm{nV}}{\sqrt{\mathrm{Hz}}}\right)^2 + \qquad \left(17.4\frac{\mathrm{nV}}{\sqrt{\mathrm{Hz}}}\right)^2}\\
&\approx 55 \frac{\mathrm{nV}}{\sqrt{\mathrm{Hz}}}
\end{align}]]</center>

This characterizes the flat high frequency noise spectrum of the positive polarity bias line before the series resistance. The dominant source of noise is the voltage reference (''en,ref''). The ~233Ω of series resistance has a thermal noise of about 2 nV/√Hz, which summed in quadrature does not contribute to the overall noise. The noise of the negative bias line is small compared to the output noise of the first stage buffer in the positive line. The negative line doubles the total noise by inverting the output noise of the positive line and adding this noise to the output, but offsets this by also doubling the resistance in the bias line. The total current noise through a detector bias element winds up roughly the same as if it were a single ended bias line.

Also, the detector band of interest is up to only 10 Hz, where 1/''f'' noise is important. The 1/''f'' characteristics of the op amp and voltage reference are not well documented in the respective datasheets.

[[Category:Bias Card]]

File:Math vnt calc.png

2026-01-05T23:03:40Z

Dvw: /* Summary */

== Summary ==
\begin{align}
v_{nt}(1\;\mathrm{kHz},300\;\mathrm{K}) &= \sqrt{ \quad 4kTR_i \quad + 4kT \left(R_{f_1}^{-1} + R_{f_2}^{-1}\right)^{-1} + \qquad e_n^2 \qquad + \quad\; e_{n,ref}^2 \quad\;+ i_n^2 \left[ R_i^2 + \left(R_{f_1}^{-1} + R_{f_2}^{-1}\right)^{-2}\right]}\\
&\approx \sqrt{\left(10.2\;\frac{\mathrm{nV}}{\sqrt{\mathrm{Hz}}}\right)^2 + \left(10.0\frac{\mathrm{nV}}{\sqrt{\mathrm{Hz}}}\right)^2 + \left(0.9\frac{\mathrm{nV}}{\sqrt{\mathrm{Hz}}}\right)^2 + \left(50\frac{\mathrm{nV}}{\sqrt{\mathrm{Hz}}}\right)^2 + \qquad \left(17.4\frac{\mathrm{nV}}{\sqrt{\mathrm{Hz}}}\right)^2}\\
&\approx 55 \frac{\mathrm{nV}}{\sqrt{\mathrm{Hz}}}
\end{align}

File:Math vnt calc.png

2026-01-05T23:02:53Z

Dvw: \begin{align} v_{nt}(1\;\mathrm{kHz},300\;\mathrm{K}) &= \sqrt{ \quad 4kTR_i \quad + 4kT \left(R_{f_1}^{-1} + R_{f_2}^{-1}\right)^{-1} + \qquad e_n^2 \qquad + \quad\; e_{n,ref}^2 \quad\;+ i_n^2 \left[ R_i^2 + \left(R_{f_1}^{-1} + R_{f_2}^{-1}\right)^...

MCE commands

2026-01-05T22:50:38Z

Dvw:

{{Related|Commanding}}
This document lists the commands used to communicate with the MCE over the fibre-optic interface. These are low-level commands sent directly to the cards in command packets. In general, MAS abstracts these commands, providing a higher-level interface to MCE commanding. In MAS, [[mce_cmd]] is used to issue commands to the MCE, and the MCE commands and their encodings are defined in the hardware description file: [[mce.cfg]].

= Firmware version 6 updates =
Firmware version 6 increases the maximum number of rows supported from 41 to 64. Unfortunately, the [[MCE fibre protocol#Command packet|MCE protocol command packet]] has a fixed size, allowing at most 58 parameter elements to be written at once. To enable parameters with 64 elements in a backwards-compatible way, firmware version six adds ''upper [[Card ID]]s'' which can be used to address the top portion of the parameter array. Upper card IDs exist for the readout cards, bias cards and address card only. An upper card IDs are is the original (lower) Card ID with <tt>0x10</tt> added (so, for RC1, whose lower card ID is <tt>0x03</tt>, the upper card ID is <tt>0x13</tt>). Accessing an upper card ID has the effect of offsetting the parameter element index by 32 (e.g. writing, say, five values to an upper card ID will store them in elements 32 through 36 of the specified parameter).

Parameters which have more than 58 parameter elements, and so require the upper Card ID to write the upper portion of the data, are marked in the table below with an asterisk in the Data column.

'''Note:''' When commanding via [[MAS]], the library handles splitting commands across the lower and upper card IDs. Users need not worry about which underlying card ID is used (unless using [[mce_cmd#Raw commands|raw commanding]] via bare numeric addresses).

= Command list =
The following list omits unimplemented commands and commands obsoleted before firmware version 5. In the lists below, in general, the '''type''' column indicates whether the parameter can be read from ('''rb''') or written to ('''wb''') or both ('''rb,wb'''). A few commands are interacted with in other ways (indicated by '''rs''' or '''go,st'''); for these special commands see the discussion of low-level MCE commands in the [[mce_cmd#Low-level MCE commands|mce_cmd description]].

The command '''ID''' listed here is the name given to the command by MAS in the hardware description file ([[mce.cfg]]). These IDs are not used in the command packets; only the register address (given in the '''Addr.''' column) is used to identify commands in the command packet. As a result, these IDs are not part of the low-level MCE command protocol and other MCE documentation may refer to any given command register by a different name. Because the MCE command protocol deals only with register addresses, changing the name does not affect the purpose or action associated with the register.

The '''Data''' column indicates the data consumed by a write ('''wb''') or returned by a read ('''rb'''). A few commands only permit a single word with a value of 1 for the command data. These are indicated by a bold-faced '''1'''. The Version 6 Firmware increases the size of row-sized parameters to 64 from 41. This is noted in the tables below with an asterisk in this column.

In general, the '''FW Rev.''' provides the range of firmware release supporting the command. It may omit a few pre-v5 firmware releases.

== General card commands ==
These commands can be issued to any card in the MCE (cc, rc1 to rc4, bc1, bc2, bc3, ac).
{{cmdrow header}}

{{cmdrow|id=fpga_temp|addr=91|type=rb|params=FPGA temp.|desc=Return the FPGA temperature of a card}}

{{cmdrow|id=card_temp|addr=92|type=rb|params=card temp.|desc=Return the card temperature from a IC sensor}}

{{cmdrow|id=card_id|addr=93|type=rb|params=card ID|desc=Return card ID from on-board silicon-ID chip}}

{{cmdrow|id=card_type|addr=94|type=rb|params=card type
|desc=Return Card Type and PCB revision:
*'''Bit 31 to 16''': ''unused''
*'''Bit 15 to 8''': PCB revision: 1=A, 2=B, 3=C, &c.
*'''Bit 7 to 3''': ''unused''
*'''Bit 2 to 0''': Card type: 0=[[AC]], including [[BAC]], 1=[[BC]], 2=[[RC]], 3=[[CC]], 4=[[PSUC]]
Early firmware and hardware revisions do not report PCB revision.
}}

{{cmdrow|id=slot_id|addr=95|type=rb|params=slot ID|desc=Return slot ID:
* '''0x09''': [[PSUC]] (obsolete)
* '''0x08''': [[CC]]
* '''0x07''': [[RC]]4
* '''0x05''': [[RC]]2
* '''0x05''': [[RC]]2
* '''0x04''': [[RC]]1
* '''0x03''': [[BC]]3
* '''0x02''': [[BC]]2 or [[BAC]]
* '''0x01''': [[BC]]1
* '''0x00''': [[AC]]}}

{{cmdrow|id=fw_rev|addr=96|type=rb|params=revision|desc=
Return firmware revision, eg 0x0501000D for rev.5.1.d:
* '''Bit 31 to 24''': major revision number (e.g., for rev.5.1.d: 0x05)
* '''Bit 23 to 16''': minor revision number (e.g., for rev.5.1.d: 0x01)
* '''Bit 15 to 0''': build number (e.g., for rev.5.1.d: 0x000D)
}}

{{cmdrow|id=led|addr=99|params=status|desc=Set and return the status of the front-panel LEDs. When writing to the LEDs, the value supplied is XOR’d with the current value of the LED status to produce the new status (i.e. a 1 bit toggles the corresponding LED). So, passing 0 will return the value of the LEDs without changing them.}}

{{cmdrow|id=scratch|addr=9A|params=word[0..7]|desc=These are read/write registers to be used for arbitrary purposes. An example is to use one to detect undesired reset of MCE.}}

{{cmdrow|id=critical_error_rst|addr=9B|type=wb|params='''1'''|desc=Writing to this register triggers a reconfiguration of the FPGA from it's configuration device and therefore the card is unresponsive for a few seconds.|fwrev=5.2.0}}

{{cmdrow|id=fpga_clr|addr=9C|type=wb|params='''1'''|desc=Writing to this register clears all the registers in firmware, but ''not'' the RAM blocks in the FPGA.|fwrev=5.2.0}}

{{cmdrow footer}}

== System Commands ==
These commands affect the timing of the system – which means that they must be issued to all cards in the MCE at the same time. They are addressed to every card in the MCE by using the "sys" card address.
{{cmdrow header}}

{{cmdrow|card=sys|id=row_len|addr=30|params=# cycles|desc=number of 50MHz clock cycles that are spent per row during multiplexing. Default = 64. Maximum = 65,535}}

{{cmdrow|card=sys|id=num_rows|addr=31|params=# rows|desc=number of rows to be multiplexed. Default = 41. Maximum = 2147483647/{{param|sys|row_len}}, although version 5 firmware cannot servo more than 64 rows (41 in v5 firmware)}}

{{cmdrow footer}}

== Clock card commands ==
{{cmdrow header}}

{{cmdrow|card=cc|id=config_app|addr=52|type=rs|params='''1'''|desc=Configure the FPGA with the image in the application configuration device (EPC16).|fwrev=3.0.1}}

{{cmdrow|card=cc|id=config_fac|addr=51|type=rs|params='''1'''|desc=Configure the FPGA with the image in the factory configuration device (EPC16).|fwrev=3.0.1}}

{{cmdrow|card=cc|id=ret_dat_s|addr=53|params=start, stop|desc=Specify the starting and ending sequence-numbers for data frames that the MCE is to return. Each frame of data will have a sequence number affixed to it. Sequence numbers will be assigned to data frames in increasing order, beginning with the starting sequence number, and finishing with the ending sequence number. Both parameters may range between 0x00000000 and 0xFFFFFFFF. If both starting and ending sequence numbers are the same, then a single frame of data will be returned. If the starting sequence number is larger than the ending sequence number, then frames will be returned until the sequence number has wrapped around and reached the stopping sequence number. Starting and stopping sequence numbers are expected for all modes of data acquisition—including for DV pulses.}}

{{cmdrow|card=cc|id=use_dv|addr=54|params=mode|desc=Set the DV mode. The Clock Card can return data frames at an internal rate specified by {{param|cc|data_rate}}, or in response to Data-Valid pulses from the Sync Box manchester input.[[#cc_sync_note|&dagger;]] Default = 0. Allowed values:
* '''mode=0''': internal DV generated by the MCE
* '''mode=2''': external DV on the "SYNC IN" input fibre}}

{{cmdrow|card=cc|id=array_id|addr=58|type=rb|params=array ID|desc=Read the ID of the sub-array that a MCE box is connected to, if equipped with an IR array ID reader.}}

{{cmdrow|card=cc|id=box_id|addr=59|type=rb|params=box ID|desc=Read the identification of the sub-rack. Each production sub-rack has a unique Silicon ID IC mounted on the Bus Backplane.}}

{{cmdrow|card=cc|id=sram_data|addr=5C|params=word[0..n]|desc=Read/write a block of 32-bit data to SRAM at address specified by the {{param|cc|sram_addr}} parameter.|fwrev=4.0.9}}

{{cmdrow|card=cc|id=sram_addr|addr=5E|params=address|desc=Specify the starting address for subsequent read/write operation to the 1024k x 32-bit SRAM. The, physical addresses range between 0x00000000 and 0x000FFFFF|fwrev=4.0.9}}

{{cmdrow|card=cc|id=data_rate|addr=A0|params=# periods|desc=Specify the rate at which data frames are collected by the MCE if DV pulses are not being used (see {{param|cc|use_dv}}). The rate is specified as the time between data packets measured in frame periods, i.e. a value of 11 will return one data packet every 11 frame periods. A frame period is the amount of time required for the multiplexer to address all the rows on a MUX. Default = 47}}

{{cmdrow|card=cc|id=mce_bclr|addr=AB|type=rs|params='''1'''|desc=Clear the registers on all the cards in the MCE, including the Clock Card|fwrev=3.0.4}}

{{cmdrow|card=cc|id=cc_bclr|addr=AC|type=rs|params='''1'''|desc=Clear the registers on the clock card only|fwrev=3.0.4}}

{{cmdrow|card=cc|id=box_temp|addr=A8|type=rb|params=box temp.|desc=Return the temperature measured by the sensor on the bus backplane.}}

{{cmdrow|card=cc|id=crc_err_en|addr=A9|params=mode|desc=Set the reply packet CRC mode:
* '''mode=0''': Normal CRC calculation performed
* '''mode=1''': CRC word forced to be 0xFFFFFFFF
|fwrev=3.0.1}}

{{cmdrow|card=cc|id=use_sync|addr=A1|params=mode|desc=Specify the sync mode. The Clock Card can return to address 0 using its internal timing, or in response to sync pulses from the Manchester input.[[#cc_sync_note|&dagger;]] Default = 0. Allowed values:
* '''mode=0''': internal timing generated by the MCE
* '''mode=2''': external timing on the "SYNC IN" input fibre}}

{{cmdrow|card=cc|id=select_clk|addr=A2|params=source|desc=Select the source of the clock input to the Clock Card's PLL, either the Manchester input clock, or the on-board crystal clock. Both are nominally 25 MHz.[[#cc_sync_note|&dagger;]] Default = 0. Allowed values:
* '''source=0''': internally generated by the MCE
* '''source=1''': externally input on the "SYNC IN" input fibre
When source=1, and the external Manchester Clock disappears, the firmware automatically switches back to the internal clock. After the switch-back, reading back {{param|cc|select_clk}} will return 0. Writing the same value to select_clk as what it is does not cause a clock glitch. Writing a different value causes a realignment of the PLL output clock to the new input, which takes two 25MHz clock cycles, or 80ns. See Altera Application Note 313.}}

{{cmdrow|card=cc|id=internal_cmd_mode|addr=B0|params=mode|desc=Enable or disable internal housekeeping/ramping commands. Default = 0. Allowed values:
* '''mode=0''': internal commands disabled
* '''mode=1''': housekeeping commands enabled
* '''mode=2''': ramp commands enabled
* '''mode=3''': arbitrary waveform (AWG) commands enabled
|fwrev=4.0.0}}

{{cmdrow|card=cc|id=ramp_step_period|addr=B1|params=# periods|desc=Specify the number of frame periods between each ramp step.|fwrev=4.0.0}}

{{cmdrow|card=cc|id=ramp_min_val|addr=B2|type=rb,wb|params=value|desc=Specify the minimum value of the ramp that is to be applied. Must be less than {{param|cc|ramp_max_val}}|fwrev=4.0.0}}

{{cmdrow|card=cc|id=ramp_step_size|addr=B3|params=step|desc=Specify the ramp step size. If '''step''' = {{param|cc|ramp_max_val}} – {{param|cc|ramp_min_val}}, then the ramp will be a square wave|fwrev=4.0.0}}

{{cmdrow|card=cc|id=ramp_max_val|addr=B4|type=rb,wb|params=value|desc=Specify the maximum value of the ramp that is to be applied. Must be greater than {{param|cc|ramp_min_val}}|fwrev=4.0.0}}

{{cmdrow|card=cc|id=ramp_param_id|addr=B5|params=address|desc=Specify the parameter ID (register address) of the register to be ramped|fwrev=4.0.0}}

{{cmdrow|card=cc|id=ramp_card_addr|addr=B6|params=address|desc=Specify the card address of the register to be ramped|fwrev=4.0.0}}

{{cmdrow|card=cc|id=ramp_step_data_num|addr=B7|params=count|desc=Specify the number of data that are to be written per ramp command|fwrev=4.0.0}}

{{cmdrow|card=cc|id=ramp_step_phase|addr=BB|params=offset|desc=Specify the phase offset of the start of the ramp|fwrev=5.0.b}}

{{cmdrow|card=cc|id=awg_sequence_len|addr=B9|params=length|desc=Specify the length of the Arbitrary Waveform Generator (AWG) sequence that is loaded in RAM. This parameter tells the internal commanding FSM how many values to apply before restarting at the beginning|fwrev=5.0.3}}

{{cmdrow|card=cc|id=awg_data|addr=BA|params=datum[0..n]|desc=Load the Arbitrary Waveform Generator (AWG) sequence into RAM on the Clock Card. The RAM has 8192 indices. This may be expanded later if there are enough resources still available on the Clock Card|fwrev=5.0.3}}

{{cmdrow|card=cc|id=awg_addr|addr=BC|params=address|desc=Specify the starting address for reading from or writing to the Arbitrary Waveform Generator (AWG) RAM. This parameter also affects the memory address of the internal commanding FSM|fwrev=5.0.3}}

{{cmdrow|card=cc|id=cards_present|addr=5A|type=rb|params=card list|desc=Report which cards are present in the MCE:
* '''Bit 9''': Address card
* '''Bit 8''': Bias card #1
* '''Bit 7''': Bias card #2
* '''Bit 6''': Bias card #3
* '''Bit 5''': Readout card #1
* '''Bit 4''': Readout card #2
* '''Bit 3''': Readout card #3
* '''Bit 2''': Readout card #4
* '''Bit 1''': Clock card
* '''Bit 0''': unused
|fwrev=4.0.8}}

{{cmdrow|card=cc|id=cards_to_report|addr=5B|params=card list|desc=Specify which cards are present in the MCE subrack, and will return data over the bus backplane. This command can be used in situations where certain cards are not present in the subrack, and should not return data in replies. The default value for this register is 1 for every possible card. To stop a card from returning data, set its corresponding bit to '''0'''. See {{param|cc|cards_present}} for bit assignments|fwrev=4.0.a}}

{{cmdrow|card=cc|id=rcs_to_report_data|addr=5F|params=card list|desc='''This command is ''not'' redundant with {{param|cc|cards_to_report}}.''' It applies only to Readout Cards, and only for data taking ({{param|rc|ret_dat}}) commands. This register sets which Readout Cards return data during a data run. This command allows the selective return of data without affecting which cards respond to all other commands, which is useful if a data run fails. See {{param|cc|cards_present}} for bit assignments, but note that only RC bits are honoured|fwrev=4.0.a}}

{{cmdrow|card=cc|id=stop_dly|addr=B8|params=delay|desc=Specify the time delay between the return of the next data frame and the return of the reply to a stop command. The time specified is in microseconds. This command is used to test the robustness of the PCI card to replies following immediately on the heels of a data packet.|fwrev=4.0.a}}

{{cmdrow|card=cc|id=num_rows_reported|addr=55|params=# rows|desc=number of rows of data that are reported in a data packet. This parameter is set also available on readout cards; see: {{param|rc|num_rows_reported |rc num_rows_reported}}. See also {{param|cc|num_cols_reported}}. Default = 41|fwrev=4.0.0}}

{{cmdrow|card=cc|id=run_id|addr=56|params=value|desc=Specify an ID number that will be stored in every data packet header returned to the PC. On ACT, the ID number corresponds to the C time at which data acquisition began. ACT's data files are also named by the same C time, so that the data pipeline can easily track which files the data are from|fwrev=4.0.2}}

{{cmdrow|card=cc|id=user_word|addr=57|params=value|desc=Specify a value that will be stored in every data packet header returned to the PC. This register is used by ACT to store a combination of {{param|cc|array_id}} and {{param|rc|data_mode}} information. At Caltech, it is used during IV curves to store the value of the TES bias applied.|fwrev=4.0.2}}

{{cmdrow|card=cc|id=upload_fw|addr=50|type=wb|params=count, datum[0..n]|desc=Specify '''count''' (≤57) doublets of packed JTAG data. The first word of the command specifies the total number of [TMS,TDI] doublets contained in the rest of the data. The rest of the words consist of '''count''' [TMS,TDI] doublets starting from the LSB. The TCK signal is implied. The JTAG FSM automatically runs through a TCK cycle after asserting each new doublet consisting of one TMS and one TDI bit. Command execution:
# Apply [TMS,TDI] doublet to JTAG interface,
# Assert TCK (automatic) and wait for {{param|cc|tck_half_period}}. While waiting, store TDO (automatic) after {{param|cc|tdo_sample_dly}} cycles after the assertion of TCK,
# De-assert TCK (automatic) and wait for {{param|cc|tck_half_period}}|fwrev=5.0.5}}

{{cmdrow|card=cc|id=config_jtag|addr=AA|type=rb|params=datum[0..n]|desc=Read back ≤57 bits of packed JTAG data. Unlike the {{param|cc|upload_fw}} command above, the first word returned does not contain the number of bits read out. It is assumed that following every {{param|cc|upload_fw}} command, this command will be called and will thus return the same number of single bits as there were doublets of [TMS,TDI] data transmitted. Every new {{param|cc|upload_fw}} command overwrites the TDO data from the previous {{param|cc|upload_fw}} command. The [[mce_jam]] player can ignore TDO data that is not important.|fwrev=5.0.5}}

{{cmdrow|card=cc|id=num_cols_reported|addr=AD|type=wb|params=# columns|desc=number of columns of data that are reported in a data packet. This parameter is also available on readout cards; see: {{param|rc|num_cols_reported |rc num_cols_reported}}. See also {{param|cc|num_rows_reported}}. Default = 8|fwrev=5.0.0}}

{{cmdrow|card=cc|id=tdo_sample_dly|addr=AE|params=delay|desc=Specify the number of clock cycles after the assertion of TCK that TDO should be sampled. Default = 2. The default value is tuned to the MCE, so leave this as is|fwrev=5.0.5}}

{{cmdrow|card=cc|id=tck_half_period|addr=AF|params=½ period|desc=Specify the number of clock cycles that TCK should remain high, and then remain low. Default = 8. The default value is tuned to the MCE, so leave this as is|fwrev=5.0.5}}

{{cmdrow footer}}
<div style="font-size: small" id="cc_sync_note">
:'''&dagger;''': If {{param|cc|select_clk}}=0, then the user must set {{param|cc|use_sync}}=0 and {{param|cc|use_dv}}=0, otherwise timing artifacts will appear in data. The following combinations are OK:
::{| class="wikitable"
! {{param|cc|select_clk}} !! {{param|cc|use_sync}} !! {{param|cc|use_dv}}
|-
| 0 || 0 || 0
|-
| 1 || 2 || 0
|-
| 1 || 0 || 0
|-
| 1 || 2 || 2
|-
| 1 || 0 || 2
|}
</div>

== Readout card commands ==
Similar to the '''sys''' card used to issue commands to all cards, [[MAS]] provides the special physical card '''rca''' which can be used to issue '''rb''' or '''wb''' commands to all installed readout cards. The firmware also implements the special physical card '''rcs''' which is used to issue commands to the {{param|rc|ret_dat}} register on all cards.
{{cmdrow header}}

{{cmdrow|card=rc|id=sa_bias|addr=10|params=bias[0..7]|desc=Read/write the SA bias values for all columns on a readout card}}

{{cmdrow|card=rc|id=offset|addr=11|params=offset[0..7]|desc=Read/write the SA offset values for all columns on a readout card}}

{{cmdrow|span=8|paramspan=4|card=rc|id=gainp0|addr=70|params=gainp[0..40]|desc=Read/write the Readout Card's P coefficients for any given column. P gains are signed 10-bit values}}
{{cmdrow|short=1|card=rc|id=gainp1|addr=71}}
{{cmdrow|short=1|card=rc|id=gainp2|addr=72}}
{{cmdrow|short=1|card=rc|id=gainp3|addr=73}}
{{cmdrow|short=1|paramspan=4|card=rc|id=gainp4|addr=74|params6=gainp[0..63]}}
{{cmdrow|short=1|card=rc|id=gainp5|addr=75}}
{{cmdrow|short=1|card=rc|id=gainp6|addr=76}}
{{cmdrow|short=1|card=rc|id=gainp7|addr=77}}

{{cmdrow|span=8|paramspan=4|card=rc|id=gaini0|addr=78|params=gaini[0..40]|desc=Read/write the Readout Card's I coefficients for any given column. I gains are signed 10-bit values}}
{{cmdrow|short=1|card=rc|id=gaini1|addr=79}}
{{cmdrow|short=1|card=rc|id=gaini2|addr=7A}}
{{cmdrow|short=1|card=rc|id=gaini3|addr=7B}}
{{cmdrow|short=1|paramspan=4|card=rc|id=gaini4|addr=7C|params6=gaini[0..63]}}
{{cmdrow|short=1|card=rc|id=gaini5|addr=7D}}
{{cmdrow|short=1|card=rc|id=gaini6|addr=7E}}
{{cmdrow|short=1|card=rc|id=gaini7|addr=7F}}

{{cmdrow|span=8|paramspan=4|card=rc|id=flx_quanta0|addr=80|params=quantum[0..40]|desc=Read/write the Readout Card's flux quanta for any given column. Flux Quanta are used to calculate the SQ1 feedback value}}
{{cmdrow|short=1|card=rc|id=flx_quanta1|addr=81}}
{{cmdrow|short=1|card=rc|id=flx_quanta2|addr=82}}
{{cmdrow|short=1|card=rc|id=flx_quanta3|addr=83}}
{{cmdrow|short=1|paramspan=4|card=rc|id=flx_quanta4|addr=84|params6=quantum[0..63]}}
{{cmdrow|short=1|card=rc|id=flx_quanta5|addr=85}}
{{cmdrow|short=1|card=rc|id=flx_quanta6|addr=86}}
{{cmdrow|short=1|card=rc|id=flx_quanta7|addr=87}}

{{cmdrow|span=8|paramspan=4|card=rc|id=gaind0|addr=88|params=gaind[0..40]|desc=Read/write the Readout Card's D coefficients for any given column. D gains are signed 10-bit values}}
{{cmdrow|short=1|card=rc|id=gaind1|addr=89}}
{{cmdrow|short=1|card=rc|id=gaind2|addr=8A}}
{{cmdrow|short=1|card=rc|id=gaind3|addr=8B}}
{{cmdrow|short=1|paramspan=4|card=rc|id=gaind4|addr=8C|params6=gaind[0..63]}}
{{cmdrow|short=1|card=rc|id=gaind5|addr=8D}}
{{cmdrow|short=1|card=rc|id=gaind6|addr=8E}}
{{cmdrow|short=1|card=rc|id=gaind7|addr=8F}}

{{cmdrow|span=8|paramspan=4|card=rc|id=adc_offset0|addr=68|params=offset[0..40]|desc=Read/write the Readout Card's ADC offsets for any given column. The ADC Offset coefficients are used to digitally offset each 50 MHz ADC sample on the Readout Cards}}
{{cmdrow|short=1|card=rc|id=adc_offset1|addr=69}}
{{cmdrow|short=1|card=rc|id=adc_offset2|addr=6A}}
{{cmdrow|short=1|card=rc|id=adc_offset3|addr=6B}}
{{cmdrow|short=1|paramspan=4|card=rc|id=adc_offset4|addr=6C|params6=offset[0..63]}}
{{cmdrow|short=1|card=rc|id=adc_offset5|addr=6D}}
{{cmdrow|short=1|card=rc|id=adc_offset6|addr=6E}}
{{cmdrow|short=1|card=rc|id=adc_offset7|addr=6F}}

{{cmdrow|card=rc|id=readout_row_index|addr=13|params=index|desc=Specify the starting row index of data to be returned in a data block. Default = 0. Note: if {{param|rc|num_rows_reported}} > {{param|sys|num_rows}} – {{param|rc|readout_row_index}} – 1, then the readout row index will wrap around to 0 during readout|fwrev=4.0.0}}

{{cmdrow|card=rc|id=ret_dat|addr=16|type=go,st|params='''1'''|desc=Return data frames. Prior to this command, the Clock Card expects a {{param|cc|ret_dat_s}} command to set up how many frames are to be collected and what sequence numbers to assign. Following that, a single {{param|rc|ret_dat}} command triggers the return of all requested data frames. To simultaneously start or stop data return for all cards, this parameter should be accessed via the special '''<tt>rcs</tt>''' card.}}

{{cmdrow|card=rc|id=en_fb_jump|addr=15|params=enabled|desc=Enable (=1) or disable (=0) flux jumping on the Readout Card. The size of flux jumps is specified by the {{param|rc|flx_quanta0|flx_quanta''#''}} commands}}

{{cmdrow|card=rc|id=data_mode|addr=17|params=mode|desc=Set/return [[data mode]]. Not all data modes are supported by all firmware revisions.}}

{{cmdrow|card=rc|id=captr_raw|addr=18|params=enabled|desc=Capture (=1) a 64k timestream snapshot of the error signal when Address-Return-to-Zero is asserted. 65,536 50MHz ADC samples from the channel specified by {{param|rc|readout_col_index}} are stored in the raw-data buffer on the Readout Card|fwrev=5.0.1}}

{{cmdrow|card=rc|id=servo_mode|addr=1B|params=mode[0..7]|desc=Set the per-column servo mode on the Readout Cards. Available modes are:
* '''mode=0 or 1''': constant feedback mode as specified by {{param|rc|fb_const}} parameter
* '''mode=2''': ramp mode
* '''mode=3''': PID-loop lock mode}}

{{cmdrow|card=rc|id=ramp_dly|addr=1C|params=# frames|desc=Specify the number of frame-periods before the next step in a ramp function. This delay can be tuned to the data-frame readout rate ({{param|cc|data_rate}}), so that one frame of data is read out per ramp step}}

{{cmdrow|card=rc|id=ramp_amp|addr=1D|params=value|desc=Specify the maximum ramp value, in 14-bits}}

{{cmdrow|card=rc|id=ramp_step|addr=1E|params=step|desc=Specify what the step size of each step in the ramp is, max 14-bit}}

{{cmdrow|card=rc|id=fb_const|addr=1F|params=fb_const[0..7]|desc=Specify the constant feedback DAC value for a each column when the servo is in constant mode (see {{param|rc|servo_mode}}). Applied to SQ1 feedback. Range: -8192 to 8191. The constant value is applied to the Readout Card DAC repetitively for every new row}}

{{cmdrow|card=rc|id=sample_dly|addr=32|params=# cycles|desc=Specify the number of 50MHz clock cycles from the start of a row during which ADC samples do not contribute to a co-added value on the Readout Cards}}

{{cmdrow|card=rc|id=sample_num|addr=33|params=count|desc=Specify the number of 50MHz samples which are co-added during a row-period on the Readout Cards. Co-addition begins after the sample delay, and one value is co-added per 50MHz clock cycle. Note that default is 0 and therefore you need to explicitly set this parameter}}

{{cmdrow|card=rc|id=fb_dly|addr=34|params=# cycles|desc=Specify the number of 50MHz clock-cycles between the start of a row and the assertion of the row's feed-back value on the Readout Cards. (minimum is 7 with flux-jumping off, 10 or 18 (depending on firmware revision) when flux-jumping is on).}}

{{cmdrow|card=rc|id=flx_lp_init|addr=37|type=wb|params='''1'''|desc=Initialize/reset the PID loop calculations on the Readout Cards for new PID parameters to take effect}}

{{cmdrow|card=rc|id=readout_col_index|addr=19|params=column|desc=Specify the starting column index of data to be returned in a data block. Default = 0. Note: if {{param|rc|num_rows_reported}} > {{param|sys|num_rows}} – {{param|rc|readout_row_index}} – 1, then the readout row index will wrap around to 0 during readout. During raw readout, this parameter specifies the index of the column for which raw data is stored|fwrev=5.0.1}}

{{cmdrow|card=rc|id=num_rows_reported|addr=55|params=# rows|desc=number of rows of data that are reported in a data packet. This parameter is set in conjunction with the {{param|rc|readout_row_index}}. This parameter is also available on clock cards; see: {{param|cc|num_rows_reported|cc num_rows_reported}}. See also {{param|rc|num_cols_reported}}, {{param|rc|readout_col_index}}. Default = 41|fwrev=4.0.0}}

{{cmdrow|card=rc|id=num_cols_reported|addr=AD|type=wb|params=# columns|desc=number of columns of data that are reported in a data packet. This parameter is set in conjunction with the {{param|rc|readout_col_index}}. This parameter is also available on clock cards; see: {{param|cc|num_cols_reported|cc num_cols_reported}}. See also {{param|rc|num_rows_reported}}, {{param|rc|readout_row_index}}. Default = 8|fwrev=5.0.0}}



{{cmdrow|card=rc|id=integral_clamp|addr=66|params=value|desc=This parameter is used to clamp the integral term used in SQ1 feedback calculation. Once this value is reached, the integral term is permanently clamped and can only be reset by issuing a {{param|rc|flx_lp_init}} command or reset. This is invented to prevent ramping of unlocked pixels and mitigate the adverse effects of the ramping pixels on locked pixels. See [[integral clamp]].|fwrev=5.0.9}}

{{cmdrow|card=rc|id=servo_rst_arm|addr=F8|type=wb|params='''1'''|desc=When set to 1, the flux-loop servo on all detectors flagged by {{param|rc|servo_rst_col0|servo_rst_col''#''}} are reset; see [[Flux-loop reset per detector]]|fwrev=5.2.0}}

{{cmdrow|span=8|paramspan=4|card=rc|id=servo_rst_col0|addr=F0|params=reset_row[0..40]|desc=A per-detector flag indicating which pixels to reset when {{param|rc|servo_rst_arm}} is set to 1; see [[Flux-loop reset per detector]]|fwrev=5.2.0}}
{{cmdrow|short=1|card=rc|id=servo_rst_col1|addr=F1}}
{{cmdrow|short=1|card=rc|id=servo_rst_col2|addr=F2}}
{{cmdrow|short=1|card=rc|id=servo_rst_col3|addr=F3}}
{{cmdrow|short=1|paramspan=4|card=rc|id=servo_rst_col4|params6=reset_row[0..63]|addr=F4}}
{{cmdrow|short=1|card=rc|id=servo_rst_col5|addr=F5}}
{{cmdrow|short=1|card=rc|id=servo_rst_col6|addr=F6}}
{{cmdrow|short=1|card=rc|id=servo_rst_col7|addr=F7}}

{{cmdrow|card=rc|id=fltr_rst|addr=14|type=wb|params='''1'''|desc=Reset the filter data pipeline. Triggering {{param|rc|flx_lp_init}} also automatically triggers {{param|rc|fltr_rst}}}}

{{cmdrow|card=rc|id=fltr_coeff|addr=1A|params=b11, b12, b21, b22, k1, k2|desc=Specifies a set of 6 filter parameters for the low-pass Butterworth filter, the first 4 are the biquad coefficients followed by k1 and k2; see [[Digital 4-pole Butterworth Low-pass filter]]|fwrev=5.1.0}}

{{cmdrow|card=rc|id=fltr_type|addr=65|params=type|desc=Specify the filter type. Default is 1. Allowed values:
* '''type=1''': ''f''cutoff / ''f''samp = 122.226Hz / 15151Hz
* '''type=2''': ''f''cutoff / ''f''samp = 75Hz / 30000Hz
* '''type=255''': filter specified by {{param|rc|fltr_coeff}}|fwrev=5.0.a}}

{{cmdrow|card=rc|id=pterm_decay_bits|addr=64|type=rb,wb|params=bit count|desc=This is the value ''k'' in the p-term calculation: [[File:Math_pn_calc.png|250px|alt=p_n {{=}} \mathrm{err}_n + \left(1 - \frac{1}{2^k}\right) p_{n-1}]]. Setting this to zero (the default) disables the decay, which is the behaviour in older firmwares.|fwrev=5.1.a}}
{{cmdrow footer}}

== Bias card commands ==
{{cmdrow header}}

{{cmdrow|card=bc|id=flux_fb|addr=20|params=flux_fb[0..31]|desc=Specify the flux feedback for all 32 16-bit DAC channels on the Bias Cards. The mapping between DAC channels and SQUIDs is hardware dependent. For 32-column systems (72-HP subracks):
* BC1 flux_fb[0..31] ↔ SA feedback
* BC2 flux_fb[0..31] ↔ SQ2 feedback
* BC3 flux_fb[0..31] ↔ SQ2 bias
For most 16-column systems (48-HP subracks):
* BC1 flux_fb[0..15] ↔ SA feedback
* BC1 flux_fb[16..31] ↔ SQ2 bias
* BC2 flux_fb[0..15] ↔ SQ2 feedback
* BC3 flux_fb[0..15] ↔ TES bias
For 16-column systems with only two bias cards, the TES bias mapping is, instead:
* BC2 flux_fb[16..31] ↔ TES bias
These maps are abstracted in MAS by the sa, sq1, sq2, and tes virtual cards. MAS supports any arbitrary mapping.}}

{{cmdrow|card=bc|id=bias|addr=21|params=bias[0..11]|desc=Read/Write the low-noise LVDS 16-bit DACs that are typically used to supply TES bias or pixel heater currents. Rev. E and later Bias Cards have 12 low-noise bias lines while Rev D. and earlier have only one, with the nominal mapping of [BC1 bias ↔ Pixel Heater] and [BC2 bias ↔ TES Bias]
Firmware revisions before 5.0.4 support only one value for this register.
}}

{{cmdrow|card=bc|id=flux_fb_upper|addr=24|params=flux_fb[16..31]|desc=Specify the flux feedback for 16 upper 16-bit DACs, i.e. channel 16 to 31 on bias cards. This command was implemented to match the cryostat wiring for the MCEv2 subracks, which use the upper 16 channels of BC1 to supply the SQ2 Bias. See <tt>flux_fb</tt> above.|fwrev=1.4.0}}

{{cmdrow|span=32|paramspan=16|card=bc|id=fb_col0|addr=C0|params=fb_row[0..40]|desc=When {{param|bc|enbl_mux}} = 1 or multiplexing mode is enabled, then these commands specify the per-row multiplexing values for each of the 32 DAC channels ({{param|bc|fb_col0|fb_col''#''}}) on the bias card|fwrev=5.0.3}}

{{cmdrow|short=1|card=bc|id=fb_col1 |addr=C1}}
{{cmdrow|short=1|card=bc|id=fb_col2 |addr=C2}}
{{cmdrow|short=1|card=bc|id=fb_col3 |addr=C3}}
{{cmdrow|short=1|card=bc|id=fb_col4 |addr=C4}}
{{cmdrow|short=1|card=bc|id=fb_col5 |addr=C5}}
{{cmdrow|short=1|card=bc|id=fb_col6 |addr=C6}}
{{cmdrow|short=1|card=bc|id=fb_col7 |addr=C7}}
{{cmdrow|short=1|card=bc|id=fb_col8 |addr=C8}}
{{cmdrow|short=1|card=bc|id=fb_col9 |addr=C9}}
{{cmdrow|short=1|card=bc|id=fb_col10|addr=CA}}
{{cmdrow|short=1|card=bc|id=fb_col11|addr=CB}}
{{cmdrow|short=1|card=bc|id=fb_col12|addr=CC}}
{{cmdrow|short=1|card=bc|id=fb_col13|addr=CD}}
{{cmdrow|short=1|card=bc|id=fb_col14|addr=CE}}
{{cmdrow|short=1|card=bc|id=fb_col15|addr=CF}}
{{cmdrow|short=1|paramspan=16|card=bc|id=fb_col16|addr=D0|params6=fb_row[0..63]}}
{{cmdrow|short=1|card=bc|id=fb_col17|addr=D1}}
{{cmdrow|short=1|card=bc|id=fb_col18|addr=D2}}
{{cmdrow|short=1|card=bc|id=fb_col19|addr=D3}}
{{cmdrow|short=1|card=bc|id=fb_col20|addr=D4}}
{{cmdrow|short=1|card=bc|id=fb_col21|addr=D5}}
{{cmdrow|short=1|card=bc|id=fb_col22|addr=D6}}
{{cmdrow|short=1|card=bc|id=fb_col23|addr=D7}}
{{cmdrow|short=1|card=bc|id=fb_col24|addr=D8}}
{{cmdrow|short=1|card=bc|id=fb_col25|addr=D9}}
{{cmdrow|short=1|card=bc|id=fb_col26|addr=DA}}
{{cmdrow|short=1|card=bc|id=fb_col27|addr=DB}}
{{cmdrow|short=1|card=bc|id=fb_col28|addr=DC}}
{{cmdrow|short=1|card=bc|id=fb_col29|addr=DD}}
{{cmdrow|short=1|card=bc|id=fb_col30|addr=DE}}
{{cmdrow|short=1|card=bc|id=fb_col31|addr=DF}}

{{cmdrow|card=bc|id=enbl_mux|addr=05|params=mode[0..31]|desc=enable/disable per-column multiplexing DAC values. Default = 0. Allowed values:
* '''mode=0''': disables multiplexing on the particular column. The column DAC is updated only once when a new value is commanded by issuing a {{param|bc|flux_fb}} command. This is the legacy behavior prior to introducing {{param|bc|enbl_mux}} and {{param|bc|fb_col0|fb_col''#''}} parameters.
* '''mode=1''': enables multiplexing on the particular column. The column DAC is updated at every row visit by values specified through {{param|bc|fb_col0|fb_col''#''}} parameters|fwrev=5.0.3}}

{{cmdrow|card=bc|id=enbl_flux_fb_mod|addr=25|params=enabled[0..31]|desc=Enable (=1) or disable (=0) the per-column addition of {{param|bc|mod_val}} to {{param|bc|flux_fb}} values for regular DACs|fwrev=5.3.0}}

{{cmdrow|card=bc|id=enbl_bias_mod|addr=26|params=enabled[0..31]|desc=Enable (=1) or disable (=0) the per-column addition of {{param|bc|mod_val}} to {{param|bc|bias}} values for low-noise bias DACs|fwrev=5.3.0}}

{{cmdrow|card=bc|id=mod_val|addr=27|params=value|desc=Modulation value to be added to either of {{param|bc|flux_fb}} or {{param|bc|bias}} values depending on whether modulation is enabled or not. (see {{param|bc|enbl_flux_fb_mod}} and {{param|bc|enbl_bias_mod}})|fwrev=5.3.0}}

{{cmdrow|card=bc|id=num_rows_idle|addr=28|params=# rows|desc=number of rows at the start of each ARZ that no bias is applied, only valid when multiplexing is enabled or ({{param|bc|enbl_mux}} is 1). |fwrev=5.3.5}}

{{cmdrow footer}}

== Address card commands ==
{{cmdrow header}}

{{cmdrow|card=ac|id=row_order|addr=01|params=row_num[0..40]|params6=row_num[0..63]|desc='''This command is relevant when {{param|ac|enbl_mux}} = 1 or 2.''' Read/write the row-addressing order. A sequence of up to 41 (v5 firmware) or 64 (v6 firmware) rows is specified at once. The row numbers that are specified with this command refer to the physical channel numbers on the Address Card. Note: After this command is issued, a {{param|rc|flx_lp_init}} command must be issued to all the readout cards to discard previous PID-loop calculations and to clean out the rest of the data pipeline. Default = 0,0,0,...}}

{{cmdrow|card=ac|id=on_bias|addr=02|params=bias_row[0..40]|desc='''Applies when {{param|ac|enbl_mux}} = 1 or 3.''' Read/write the14-bit on-bias values for all 41 channels of the DACs on the Address Card. Bias values are stored in the order of physical channels on the Address card – which is not necessarily the multiplexing order specified with {{param|ac|row_order}}. This command is nominally is used to specify the SQ1 "on" biases, and are applied one at a time in the sequence specified by {{param|ac|row_order}}. Default = 0,0,0,...}}

{{cmdrow|card=ac|id=off_bias|addr=03|params=bias_row[0..40]|desc='''Applies when {{param|ac|enbl_mux}} = 1 or 3.''' Read/write the 14-bit off-bias values for all 41 channels of the row-addressing DACs on the Address Card. Bias values are stored in the order of physical channels on the Address card – which is not necessarily the multiplexing order specified with {{param|ac|row_order}}. This command is nominally is used to specify the SQ1 "off" biases. Default = 0,0,0,...}}

{{cmdrow|card=ac|id=enbl_mux|addr=05|params=mode|desc=Start/stop array multiplexing. Default: 0. Allowed values:
* '''mode=0''': Multiplexing off. This is the default value.
* '''mode=1''': Multiplexing on. The Address Card turns one DAC "on" and one DAC "off" at every row switch. The multiplexed values are specified by {{param|ac|on_bias}} and {{param|ac|off_bias}}. The values are applied in the first two clock cycles after a row switch.
* '''mode=2''': Multiplexing on. The Address Card changes the values on all the DACs at every row switch. The multiplexed values are specified by {{param|ac|fb_col0|fb_col''#''}}. All 41 DAC values are applied in the first 4 clock cycles after a row switch. This mode is only used by [[Biasing Address Card]]s.
* '''mode=3''': Special multiplexing on. In the first {{param|ac|heater_bias_len}} clock cycles of each row visit, the {{param|ac|heater_bias}} values are applied to the DACs, the remaining time, the {{param|ac|on_bias}} values are applied}}

{{cmdrow|card=ac|id=bias_start|addr=09|params=start[0..40]|desc='''Applies only when {{param|ac|enbl_mux}} = 1.''' Specify the point during each row dwell period when the SQ1 bias is applied. This is specified on a row-by-row basis so that SCUBA2 can do differential bias heating across the rows of their arrays.|fwrev=5.0.1}}

{{cmdrow|card=ac|id=heater_bias|addr=0A|params=bias[0..40]|desc=When {{param|ac|enbl_mux}}=3, specify the magnitude of the SQ1-bias heating pulse in DAC units (0 to 16383) during the initial {{param|ac|heater_bias_len}} period of each row visit.|fwrev=5.0.2}}

{{cmdrow|card=ac|id=heater_bias_len|addr=0B|params=# cycles|desc=When {{param|ac|enbl_mux}}=3, specify the length of the SQ1 bias heating pulses at the beginning of every new row period.|fwrev=5.0.2}}

{{cmdrow|span=32|card=ac|id=fb_col0|addr=E3|params=fb_row[0..40]|desc='''These commands are relevant when {{param|ac|enbl_mux}} = 2.''' Specifies the 41 multiplexing values for each DAC channel on the Address Card, and for each row that the channel is to multiplex. There are 41 channels on the Address Card, and up to 41 rows per channel that need to be specified. These commands are used only when the address card is used from a bias card slot (see [[Biasing Address Card]]).|fwrev=2.0.5}}

{{cmdrow|short=1|card=ac|id=fb_col1 |addr=E1}}
{{cmdrow|short=1|card=ac|id=fb_col2 |addr=DF}}
{{cmdrow|short=1|card=ac|id=fb_col3 |addr=DD}}
{{cmdrow|short=1|card=ac|id=fb_col4 |addr=DB}}
{{cmdrow|short=1|card=ac|id=fb_col5 |addr=D9}}
{{cmdrow|short=1|card=ac|id=fb_col6 |addr=D7}}
{{cmdrow|short=1|card=ac|id=fb_col7 |addr=D5}}
{{cmdrow|short=1|card=ac|id=fb_col8 |addr=D3}}
{{cmdrow|short=1|card=ac|id=fb_col9 |addr=D1}}
{{cmdrow|short=1|card=ac|id=fb_col10|addr=CF}}
{{cmdrow|short=1|card=ac|id=fb_col11|addr=CD}}
{{cmdrow|short=1|card=ac|id=fb_col12|addr=CB}}
{{cmdrow|short=1|card=ac|id=fb_col13|addr=C9}}
{{cmdrow|short=1|card=ac|id=fb_col14|addr=C7}}
{{cmdrow|short=1|card=ac|id=fb_col15|addr=C5}}
{{cmdrow|short=1|card=ac|id=fb_col16|addr=E2}}
{{cmdrow|short=1|card=ac|id=fb_col17|addr=E0}}
{{cmdrow|short=1|card=ac|id=fb_col18|addr=DE}}
{{cmdrow|short=1|card=ac|id=fb_col19|addr=DC}}
{{cmdrow|short=1|card=ac|id=fb_col20|addr=DA}}
{{cmdrow|short=1|card=ac|id=fb_col21|addr=D8}}
{{cmdrow|short=1|card=ac|id=fb_col22|addr=D6}}
{{cmdrow|short=1|card=ac|id=fb_col23|addr=D4}}
{{cmdrow|short=1|card=ac|id=fb_col24|addr=D2}}
{{cmdrow|short=1|card=ac|id=fb_col25|addr=D0}}
{{cmdrow|short=1|card=ac|id=fb_col26|addr=CE}}
{{cmdrow|short=1|card=ac|id=fb_col27|addr=CC}}
{{cmdrow|short=1|card=ac|id=fb_col28|addr=CA}}
{{cmdrow|short=1|card=ac|id=fb_col29|addr=C8}}
{{cmdrow|short=1|card=ac|id=fb_col30|addr=C6}}
{{cmdrow|short=1|card=ac|id=fb_col31|addr=C4}}

{{cmdrow|card=ac|id=const_mode|addr=06|params=mode[0..40]|desc=Specify which DAC channels are held at a constant value regardless of the value of {{param|ac|enbl_mux}}. A constant value is applied once only, and is specified by const_val. In addition, DACs for which const_mode=1 do not receive data strobes during multiplexing – so that there are no glitches or excess noise on the DAC outputs.
* '''mode=0''': this DAC channel is multiplexed when {{param|ac|enbl_mux}} = 1, 2, or 3
* '''mode=1''': this DAC channel is held at a constant value and not strobed when {{param|ac|enbl_mux}} = 1, or 2 ([[Biasing Address Card]] only)|fwrev=2.0.6}}

{{cmdrow|card=ac|id=const_val|addr=07|params=val[0..40]|desc=Specify values for the DACs that are held constant. '''val[n]''' is asserted by DAC '''n''' when {{param|ac|const_mode}}[n] = 1. In addition, all constant values are applied to each respective DAC when {{param|ac|enbl_mux}} = 0. When {{param|ac|enbl_mux}}, {{param|ac|const_mode}}, or {{param|ac|const_val}} values are changed, all the DACs that are being held constant have their values re-strobed ([[Biasing Address Card]] only)|fwrev=2.0.6}}

{{cmdrow footer}}

= Legacy documents =
The document linked below provides the same information as this page, except that it includes obsolete and unimplemented commands. It was last updated in April of 2013, an does not list any command added after that time. In some instances the command names listed in the following document are different than the command names used by MAS (which are listed above). The description of some commands may be obsolete.

* [http://www.phas.ubc.ca/~mce/mcedocs/software/SC2_ELE_S580_515_mce_command_description.pdf SC2_ELE_S580_515_mce_command_description.pdf]
[[Category:Address Card Firmware]]
[[Category:Bias Card Firmware]]
[[Category:Clock Card Firmware]]
[[Category:Readout Card Firmware]]
[[Category:Commanding| ]]

File:Math pn calc.png

2026-01-05T22:48:31Z

Dvw: p_n = \mathbf{err}_n + \left(1 - \frac{1}{2^k}\right) p_{n-1}

== Summary ==
p_n = \mathbf{err}_n + \left(1 - \frac{1}{2^k}\right) p_{n-1}

Data mode

2026-01-05T22:46:55Z

Dvw: math

During data readout from the MCE, there are different types of data associated with each detector. These are:

# calculated SQ1 feedback ('''''sq1_fb'''''):
#*[[File:Math_sq1_fb_eq.png|800px|alt=\mathbf{sq1\_fb}_{n+1} {{=}} \frac{1}{2^{12}} \left[\left(\mathbf{gainp} \times q_{n}\right) + \left(\mathbf{gaini} \times \sum_{i=1}^{n} \mathbf{error}_i\right) + \left(\mathbf{gaind} \times [\mathbf{error}_n - \mathbf{error}_{n-1}]\right)\right] ]]
#* where ''q''''n'' = '''error'''n + ''b'' × ''q''''n''-1
#* ''n'' is the multiplexing-frame index
#*''i'' is reset when the PID servo is restarted by setting the {{param|rc|servo_mode}} to 3 or {{param|rc|flx_lp_init}} to 1.
#*''b'' < 1 and specified by {{param|rc|pterm_decay_bits}}
# coadded error ('''''error'''''):
#* calculated from the Series-Array signal sampled @ 50MHz by the ADC
#* [[File:Math_error_eq.png|400px|alt=error {{=}} \sum_{1}^{sample\_num} (adc\_reading_{i} - adc\_offset)]]
# low-pass filtered SQ1 feedback ('''''sq1_fb_filtered'''''):
#*see [[ Digital 4-pole Butterworth Low-pass filter|4-pole Butterworth low-pass filter]].
#* The effective DC gain, including quantization error, is approximately: '''sq1_fb_filtered'''''n'' ≈ 1218 × '''sq1_fb'''''n''-1
# flux-jump counter ('''''num_flux_jumps'''''). See [[ Flux jumping ]].
# raw ADC samples @ 50 MHz ('''''raw'''''). See [[ Raw-mode readout ]].

Note that '''''error''''', '''''sq1_fb''''', and '''''sq1_fb_filtered''''' are internally stored as 32 bits while '''''num_flux_jumps''''' are stored as 8 bits and '''''raw''''' as 14 bits. During readout the appropriate windowing is chosen for each data type.
== Data Modes and Windowing ==
The type of data reported by the MCE during data acquisition is determined by the MCE parameter {{param|rc|data_mode}}. Depending on the data mode, the reported data will be windowed in a different way. The notes in the table below explain the windowing, in terms of how many bits are reported and the relative scaling of the windowed value relative to some reference data mode. The reference data modes for error, sq1fb and filtered_sq1fb are, respectively, 0, 1, and 2.

{| class="wikitable"
|-
! data-mode !! data-type !! Description !! RC Firmware Revision
|-
| 0
|| <center>''error''</center>
|| 32b (signed) co-added error 
* [31:0] = error

|| all
|-
| 1
|| <center>''sq1_fb''</center>
|| 32b (signed) calculated SQ1 feedback.
* [31:0] = sq1_fb * 212 when {{param|rc|servo_mode}} = 3
* [31:0] = sq1_fb when {{param|rc|servo_mode}} != 3
''Note that {{param|rc|servo_mode}}=3 is the normal running condition. The non-servoing form, used at times during array-auto-tune for example, is included here for completeness.
''
|| all
|-
| 2
|| <center>''filtered_sq1_fb''</center>
||32b (signed) low-pass filtered SQ1 feedback data. 
* [31:0] = sq1_fb_filtered

|| 2.0.5 and later
|-
| 3 obsolete (see 12)
|| <center>raw</center>
|| Raw 50 MHz ADC samples raw[13:i], where i=0 in rev. 4.3.7 and i=6 in all previous firmware. 
* [31:0] = raw_data / (2i),

|| Only 3.0.6, 3.0.16, 3.0.25, 4.1.7, 4.2.7, 4.3.7
|-
| 4
|| <center>18:14 mixed </center>
||signed 18b SQ1 feedback + signed 14b coadded error 
* [31:14] = sq1_fb
* [13:0] = error

|| 2.0.9 and later
|-
| 5
|| <center>24:8 mixed </center>
|| signed 24b SQ1 feedback + signed 8b num_flux_jumps[7:0]. 
* [31:8] = sq1_fb * 24
* [7:0] = num_flux_jumps

|| all
|-
| 6 obsolete
|| <center>18:14 mixed</center>
|| signed 18b filtered data + signed 14b co-added 
* [31:13] = sq1_fb_filtered / (211)
* [12:0] = error

|| 3.0.30 to 4.0.6 only
|-
| 7
|| <center>22:10 mixed</center>
|| signed 22b filtered data + signed 10b coadded error 
* [31:10] = sq1_fb_filtered / (27)
* [9:0] = error / (24)

|| 4.0.2 and later
|-
| 8 obsolete
||<center>24:8 mixed</center>
|| signed 24b filtered data + signed 8b num_flux_jumps[7:0]. 
* [31:8] = sq1_fb_filtered / (28)
* [7:0] = num_flux_jumps

|| 4.0.4 only
|-
| 9 obsolete
|| <center>24:8 mixed </center>
|| signed 24b filtered data + signed 8b num_flux_jumps[7:0]. 
* [31:8] = sq1_fb_filtered/ (21)
* [7:0] = num_flux_jumps

|| 4.0.5 till 4.0.a
|-
| 10
|| <center>25:7 mixed</center>
|| Signed 25b filtered data + signed 7b num_flux_jumps. 
* [31:7] = sq1_fb_filtered / (23)
* [6:0] = num_flux_jumps

|| 4.1.6, 4.0.b and later
|-
| 11
|| <center>6:3 mixed, debugging mode </center>
|| Unsigned 6b row_index + unsigned 3b column_index. 
* [31:10] '''----'''
* [9:3] '''row_index'''
* [2:0] '''column_index'''

|| 5.0.0 and later
|-
| 12
||<center> raw</center>
|| Raw 50 MHz ADC samples raw[13:0], sign-extended to 32 bits.
* [31:0] = raw_data

|| 4.0.d, 4.0.e, 5.0.1+
|}

== Links ==
* [[ MCE firmware ]]

[[Category:Readout Card Firmware]]
[[Category:MAS]]
[[Category:MCE Script]]

File:Math error eq.png

2026-01-05T22:42:58Z

Dvw: \mathbf{error} = \sum_{1}^{\mathrm{sample\_num}} (\mathbf{adc\_reading}_{i} - \mathbf{adc\_offset})

== Summary ==
\mathbf{error} = \sum_{1}^{\mathrm{sample\_num}} (\mathbf{adc\_reading}_{i} - \mathbf{adc\_offset})

File:Math sq1 fb eq.png

2026-01-05T22:36:07Z

Dvw: \mathbf{sq1\_fb}_{n+1} = \frac{1}{2^{12}} \left[\left(\mathbf{gainp} \times q_{n}\right) + \left(\mathbf{gaini} \times \sum_{i=1}^{n} \mathbf{error}_i\right) + \left(\mathbf{gaind} \times [\mathbf{error}_n - \mathbf{error}_{n-1}]\right)\right]

== Summary ==
\mathbf{sq1\_fb}_{n+1} = \frac{1}{2^{12}} \left[\left(\mathbf{gainp} \times q_{n}\right) + \left(\mathbf{gaini} \times \sum_{i=1}^{n} \mathbf{error}_i\right) + \left(\mathbf{gaind} \times [\mathbf{error}_n - \mathbf{error}_{n-1}]\right)\right]

Digital 4-pole Butterworth Low-pass filter

2026-01-05T22:33:58Z

Dvw: /* Filter Specification */

== Overview ==
A digital 4-pole Butterworth low-pass filter is implemented as 2 cascaded biquads (2-pole topology) in the '''[[Readout card firmware]]''' of the MCE. The transfer function of the IIR filter is:
<center>[[File:Math_butterworth.png|1000px|alt=H(z) {{=}} \frac {1+2 z^{-1}+z^{-2}}{1+b^*_{11} z^{-1}+b^*_{12} z^{-2}} \cdot 2^{-k_2} \cdot \frac {1+2z^{-1}+z^{-2}}{1+b^*_{21} z^{-1}+b^*_{22} z^{-2}} \cdot {2^{-k_1}}]]</center>

Filter coefficients [[File:math_b11_star.png|30px|alt=b^*_{11}]], [[File:math_b12_star.png|30px|alt=b^*_{12}]], [[File:math_b21_star.png|30px|alt=b^*_{21}]], [[File:math_b22_star.png|30px|alt=b^*_{22}]], and truncation factors, ''k''1 and ''k''2, are hard coded in older firmware (before '''version 5.1.0'''), but with modern firmware, they can be programmed through software:

wb rca {{param|rc|fltr_coeff}} ''b''11 ''b''12 ''b''21 ''b''22 ''k''1 ''k''2

where ''bxy'' is a quantized version of [[File:math_bxy_star.png|30px|alt=b^*_{xy}]] computed as: [[File:Math_bxy_eq.png|150px|alt=b_{xy} {{=}} \left\lfloor\left{{bar}}b^*_{xy}\right{{bar}} \times 2^{14}\right\rfloor]], where ⌊•⌋ indicates the floor function. Note that in order to accommodate the quantization effects, you have to follow the recipe prescribed in the [[#Filter Coefficients|Filter Coefficients section]] below when specifying the coefficients and truncation factors.

There are 3 filter-related MCE parameters/commands:
* {{param|rc|fltr_type}}: to determine whether filter coefficients are hard-coded or configurable
* {{param|rc|fltr_coeff}}: to specify filter coefficients
* {{param|rc|fltr_rst}}: to reset the filter pipeline after changing coefficients

== Filter Specification ==
Filter specification of the 4-pole Butterworth filter is determined by the filter coefficients [[File:math_b11_star.png|30px|alt=b^*_{11}]], [[File:math_b12_star.png|30px|alt=b^*_{12}]], [[File:math_b21_star.png|30px|alt=b^*_{21}]], [[File:math_b22_star.png|30px|alt=b^*_{22}]], described earlier.

Assume:

* '''''f''cutoff''' is the frequency at which the signal after filtering is √2 of its maximum value (nominally the read-out rate Nyquist frequency), and
* '''''f''samp''' is the sampling frequency, calculated as <code>(50 Mhz) / (num_rows × row_len)</code>. For example: <code>50 MHz / (33 × 100) = 15151.5 Hz</code>.

''Note that the filter ''f''3dB scales if ''f''samp changes.''

; Type 1 (hard-coded coefficients)
: ''supported in all rc '''except''' 5.0.7''
: DC amplification = 1217.9148
: ''f''cutoff / ''f''samp = 122.226 Hz / 15151 Hz
: Gain @ 200 Hz = 0.14189148 (wrt the DC gain)

; Type 2 (hard-coded coefficients)
: ''supported '''only''' in rc version 5.0.7''
: DC amplification = 2044
: ''f''cutoff / ''f''samp = 75 Hz / 30000 Hz
: A plot of the transfer function generated by simulating MCE firmware (VHDL)
[[File:mce_filter_type2_magnitude.png |150px]][[File:mce_filter_type2_phase.png|150px]]

; Type 255 (configurable coefficients)
: ''supported in rc 5.1.0+''
: Quantized filter coefficients ''b''11, ''b''12, ''b''21, ''b''22 and truncation factors, ''k''1, ''k''2 are parameterized and programmable by software.

The fitler type can be determined by reading back the MCE parameter called {{param|rc|fltr_type}}. (supported in firmware 5.0.a+)

The following plot shows the magnitude and the phase of Type 1 filter.

Here is Elia's original plot [[Media:BW_filter.ps]]. Then we see the same plot with the impulse-response also added (by Joe, Nov 29, 2007):
[[Image: BW_filter2.png]]

Here is the filter response for Scuba2 setting (''f''samp = 9.5 kHz, ''f''readout = 200 Hz): [[Media: Filter fs10kHz 200Hzdecimated response.ps ]]

== Filter-related Software changes ==

=== Determining the filter type ===

A {{param|rc|fltr_type}} parameter is introduced starting firmware 5.0.a:
* '''{{param|rc|fltr_type}} = 1''': ''f''cutoff / ''f''samp = 122.226 Hz / 15151 Hz
* '''{{param|rc|fltr_type}} = 2''': ''f''cutoff / ''f''samp = 75 Hz / 30000 Hz
* '''{{param|rc|fltr_type}} = 255''': configurable coefficient

All earlier firmware revisions are set to filter type 1 by default, except version 5.0.7 which is set to filter type 2.

=== Software requirements ===

* MAS - use mas/trunk r493 or later to get access to the {{param|rc|fltr_coeff}} MCE parameter.
** In [[mce.cin]], specify <code>$fw_rev["rc"] = 0x5010000</code> or greater.
* mce_script - use mce_script/trunk r764 or later
* In [[Mce config template system#experiment.cfg | experiment.cfg]]:
**specify one of:
config_filter = 0; # do not write filter coefficients to the MCE
config_filter = 1; # write filter coefficients to the MCE
and when config_filter = 1, the filter coefficients to be written to the MCE must be specified in the "filter_params" parameter, in the order [''b''11, ''b''12, ''b''21, ''b''22, ''k''1, ''k''2], e.g.:
filter_params = [ 32092, 15750, 31238, 14895, 0, 11]; # type 1 filter, ''f''cutoff/''f''samp = 122.226 Hz / 15.151 kHz
filter_params = [ 32295, 15915, 32568, 16188, 3, 14]; # type 2 filter, ''f''cutoff/''f''samp = 75 Hz / 30 kHz
filter_params = [ 32295, 15915, 32568, 16188, 5, 12]; # type 2 filter with more inter-biquad dynamic range (recommended)
filter_params = [ 32297, 15934, 31683, 15320, 0, 11]; # SCUBA-2 filter after 2011-06, ''f''cutoff/''f''samp = 75 Hz / 12.97 kHz

== Code for simulations ==

Note that as of mce_script r902, '''mce_data.py''' contains code for handling the MCE Butterworth filters. This can be used to load filter parameters from a runfile, and to get the complex frequency response of a filter. See [[mce_data.py#MCEButterworth_class]].

A smaller, quicker python example:
[[ Media: mce_filt_py.txt ]]

In this little IDL program you can find the functional form as a function of the frequency of the filter. First, Elia's original program, then as modified by Joe on November 29, 2007, then modified by Mandana on Jan. 14, 2009 for Scuba2 numbers:
* [[ Media: filter_pro.txt ]]
* [[ Media: filter_pro2.txt ]]
* [[ Media: low_pass_filter_model_pro.txt ]]

=== Digital, time domain simulation codes ===

Python-based model of a single biquad, in the time domain, for exploring digitization and dynamic range:
* [[ Media: biquad_time_domain_py.txt ]]

== Filter Coefficients ==
=== Butterworth Coefficients ===
The filter coefficients are generated using ''fdatool'' (Filter-design & Analysis tool, part of DSP Toolbox) in '''MATLAB/Simulink'''. These coefficients are floating numbers and in order to feed them to MCE firmware, they need to be quantized by converting to signed binary fractional (SBF) 1.14 format. You may use [[#Alternative to fdatool|alternate methods]] to generate coefficients. Here, we explain the method using ''fdatool''.

Once you launch the ''fdatool'', choose the following settings:

* Response Type: Low Pass
* Design Method: Butterworth
* Filter Order: 4

* Frequency Specifications:
** For Type 1:
*** ''f''samp = 12,195 Hz = 50 MHz/ (100 × 41)
*** ''f''cutoff = 100 Hz
** For Type 2:
*** ''f''samp = 30,000 Hz ≈ 50 MHz / (50 × 33)
*** ''f''cutoff = 75 Hz
** For Type 255:
*** ''f''samp = 50 MHz / ({{param|sys|row_len}} × {{param|sys|num_rows}})
*** ''f''cutoff=''f''readout / 2 (= ''f''samp / {{param|cc|data_rate}} / 2, if using internal CC triggering)
* The attenuation at ''f''cutoff is fixed at 3 dB (half the passband power)

Then click on Design Filter and you will get the following coefficients:
; Type 1
:Section 1:
::Numerator: 1 2 1
::Denominator: 1 -1.9587428340882587 0.96134553442399129
::Gain = 1/''g''1 = 0.00065067508393319923 (not implemented)
:Section 2:
::Numerator: 1 2 1
::Denominator: 1 -1.9066292518523014 0.90916270571237567
::Gain = 1/''g''2= 0.00063336346501859835 (not implemented)

; Type 2
:Section 1:
::Numerator: 1 2 1
::Denominator: 1 -1.9711486088510415 0.97139181456687917
:Section 2:
::Numerator: 1 2 1
::Denominator: 1 -1.9878047097960421 0.98804997058724808
:Gain = 1/(''g''1 × ''g''2)= 0.0000000037280516432624239 (not implemented)

; Type 255
: Plug in your desired ''f''samp and ''f''cutoff in MATLAB fdatool and you will get a set of coefficients:
:Section 1:
::Numerator: 1 2 1
::Denominator: 1 [[File:math_b11_star.png|30px|alt=b^*_{11}]], [[File:math_b12_star.png|30px|alt=b^*_{12}]]
:: Gain = 1/''g''1
:Section 2:
::Numerator: 1 2 1
::Denominator: 1 [[File:math_b21_star.png|30px|alt=b^*_{21}]], [[File:math_b22_star.png|30px|alt=b^*_{22}]]
::Gain = 1/''g''2

=== Coefficient Quantization ===
The quantization format is signed-binary fractional (SBF) 1.14 and then 2's complement to be able to account for positive and negative values.
* Compute the quantised coefficients ''bxy'' via: [[File:Math_bxy_eq.png|150px|alt=b_{xy} {{=}} \left\lfloor\left{{bar}}b^*_{xy}\right{{bar}} \times 2^{14}\right\rfloor]] (i.e. take the absolute value, multiply by 214 and then drop the fractional part).
* [[File:Math_k1_eq.png|170px|alt=k_1 {{=}} \left\lfloor \log_2 g_2 \right\rfloor - 10]], the output-truncation (10 is a historical constant)
* [[File:Math_k2_eq.png|160px|alt=k_2 = 1 + \left\lfloor \log_2 g_1 \right\rfloor]], the inter-stage truncation

For example, if we use this formula to quantize Type 1 coefficients listed above:
<center>[[File:Math_coeff_calc.png|800px|alt=\begin{align}
b_{11} &{{=}} \lfloor 1.9587428340882587 \times 2^{14}\rfloor &{{=}}&\ 32092\\
b_{12} &{{=}} \lfloor 0.96134553442399129 \times 2^{14}\rfloor &{{=}}&\ 15750\\
b_{21} &{{=}} \lfloor 1.9066292518523014 \times 2^{14}\rfloor &{{=}}&\ 31238\\
b_{22} &{{=}} \lfloor 0.90916270571237567 \times 2^{14}\rfloor &{{=}}&\ 14895\\
k_1 &{{=}} \left\lfloor \log_2 \left(1 / 0.00065067508393319923 \right)\right\rfloor - 10 &{{=}}&\ 0\\
k_2 &{{=}} 1 + \left\lfloor \log_2 \left(1 / 0.00063336346501859835 \right)\right\rfloor &{{=}}&\ 11
\end{align}]]</center>

* ''k''1 < 16 and ''k''2 < 32
* Now, if 32 − ''k''1 + ''k''2 > 32, then you have to talk to UBC!

:'''''The following ONLY concerns the MCE firmware developers:'''

:Prior to firmware 5.1.0, the coefficients were hardcoded in '''fsfb_calc_pack.vhd''' (FILTER_B11_COEF, FILTER_B12_COEF, FILTER_B21_COEFF, FILTER_B22_COEFF, FILTER_GAIN_WIDTH, FILTER_SCALE_LSB).''

=== Calculating the DC Gain (''k'') ===
Note that in firmware, instead of ''g''1 and ''g''2, an inter-biquad truncation of ''k''2 (implemented as a binary shift) and ''k''1, number of bits dropped after the second biquad, are implemented.

Hence, the overall gain becomes [[File:Math_gain_eq.png|60px|alt=\frac {g_1 g_2} {2^{(k_1 + k_2)}}]].

:''(Note for firmware developers: see FILTER_GAIN_WIDTH and FILTER_SCALE_LSB in '''fsfb_calc_pack.vhd'''.) ''

; Type 1
:''k''2 = 11, ''k''1 = 0, the filter gain is estimated at 1184, but VHDL simulation results in a gain of 1216.
; Type 2
:''k''2 = 14, ''k''1 = 3, the filter gain is estimated at 2046, but VHDL simulation results in a gain of 2181.

The gain difference can be attributed to the rounding effects associated with fixed-width arithmetic.

To roughly compute the gain, including the effects from truncating the coefficients, reverse the quantization process to obtain the floating point values associated with your coefficients, and plug into the filter definition. Here is a rough python program which computes the true gain for our Type 1 filter (''b''11 = 32092, ''b''12 = 15750, ''b''21 = 31238, ''b''22 = 14895, ''k''1 = 0, ''k''2 = 11):
from numpy import *
# Sum of k1 and k2 shifts:
k12 = 11+0
# Quantized coefficients b11, b12, b21, b22:
n = array([32092, 15750, 31238, 14895]).astype('float')
# Re-float
f = n/2**14
# Compute gain
gain = 16. / (2**k12 * (1 - f[0] + f[1]) * (1 - f[2] + f[3]))
print gain
# Result: 1217.8583043

== Useful Links ==
http://www.phas.ubc.ca/~mce/mcedocs/hardware/Firmware_block_spec/reaout_card/fsfb_calculations_rev1.11.pdf

http://www.planetanalog.com/showArticle.jhtml?articleID=12802683

== Alternative to fdatool ==
If you do not have access to fdatool or do not have DSP toolbox installed, you can use the following MATLAB functions (or equivalent in other packages) to get the coefficients:
* butter: is a matlab function to generate butterworth coefficients
* sos2tf: matlab function to break a transfer function to second-order sections
* bilinear: converts an s-domain (continuous) transfer function to z-domain (discrete) transfer function.
* Then run the following in matlab (or whatever syntax your tool has):
num=[1 2 1]
denum=[1 -1.9711486088510415 0.97139181456687917]
max(dbode(num, denum, 1/fsamp) but also look at the bode-plot to make sure it is flat, otherwise read the max from the flat portion of the plot instead of the max function.

'''Note:''' When I used coefficients generated by [a,b] = butter(2, 50/20000); [SOS,G]=tf2sos(a,b), the filter was not as robust. not sure why?!

[[Category:Readout Card Firmware]]

Digital 4-pole Butterworth Low-pass filter

2026-01-05T22:33:11Z

Dvw:

== Overview ==
A digital 4-pole Butterworth low-pass filter is implemented as 2 cascaded biquads (2-pole topology) in the '''[[Readout card firmware]]''' of the MCE. The transfer function of the IIR filter is:
<center>[[File:Math_butterworth.png|1000px|alt=H(z) {{=}} \frac {1+2 z^{-1}+z^{-2}}{1+b^*_{11} z^{-1}+b^*_{12} z^{-2}} \cdot 2^{-k_2} \cdot \frac {1+2z^{-1}+z^{-2}}{1+b^*_{21} z^{-1}+b^*_{22} z^{-2}} \cdot {2^{-k_1}}]]</center>

Filter coefficients [[File:math_b11_star.png|30px|alt=b^*_{11}]], [[File:math_b12_star.png|30px|alt=b^*_{12}]], [[File:math_b21_star.png|30px|alt=b^*_{21}]], [[File:math_b22_star.png|30px|alt=b^*_{22}]], and truncation factors, ''k''1 and ''k''2, are hard coded in older firmware (before '''version 5.1.0'''), but with modern firmware, they can be programmed through software:

wb rca {{param|rc|fltr_coeff}} ''b''11 ''b''12 ''b''21 ''b''22 ''k''1 ''k''2

where ''bxy'' is a quantized version of [[File:math_bxy_star.png|30px|alt=b^*_{xy}]] computed as: [[File:Math_bxy_eq.png|150px|alt=b_{xy} {{=}} \left\lfloor\left{{bar}}b^*_{xy}\right{{bar}} \times 2^{14}\right\rfloor]], where ⌊•⌋ indicates the floor function. Note that in order to accommodate the quantization effects, you have to follow the recipe prescribed in the [[#Filter Coefficients|Filter Coefficients section]] below when specifying the coefficients and truncation factors.

There are 3 filter-related MCE parameters/commands:
* {{param|rc|fltr_type}}: to determine whether filter coefficients are hard-coded or configurable
* {{param|rc|fltr_coeff}}: to specify filter coefficients
* {{param|rc|fltr_rst}}: to reset the filter pipeline after changing coefficients

== Filter Specification ==
Filter specification of the 4-pole Butterworth filter is determined by the filter coefficients [[File:math_b11_star.png|30px|alt=b^*_{11}]], [[File:math_b12_star.png|30px|alt=b^*_{12}]], [[File:math_b21_star.png|30px|alt=b^*_{21}]], [[File:math_b22_star.png|30px|alt=b^*_{22}]], described earlier.

Assume:

* '''''f''cutoff''' is the frequency at which the signal after filtering is √2 of its maximum value (nominally the read-out rate Nyquist frequency), and
* '''''f''samp''' is the sampling frequency, calculated as <code>(50&nbspMhz) / (num_rows × row_len)</code>. For example: <code>50 MHz / (33 × 100) = 15151.5 Hz</code>.

''Note that the filter ''f''3dB scales if ''f''samp changes.''

; Type 1 (hard-coded coefficients)
: ''supported in all rc '''except''' 5.0.7''
: DC amplification = 1217.9148
: ''f''cutoff / ''f''samp = 122.226 Hz / 15151 Hz
: Gain @ 200 Hz = 0.14189148 (wrt the DC gain)

; Type 2 (hard-coded coefficients)
: ''supported '''only''' in rc version 5.0.7''
: DC amplification = 2044
: ''f''cutoff / ''f''samp = 75 Hz / 30000 Hz
: A plot of the transfer function generated by simulating MCE firmware (VHDL)
[[File:mce_filter_type2_magnitude.png |150px]][[File:mce_filter_type2_phase.png|150px]]

; Type 255 (configurable coefficients)
: ''supported in rc 5.1.0+''
: Quantized filter coefficients ''b''11, ''b''12, ''b''21, ''b''22 and truncation factors, ''k''1, ''k''2 are parameterized and programmable by software.

The fitler type can be determined by reading back the MCE parameter called {{param|rc|fltr_type}}. (supported in firmware 5.0.a+)

The following plot shows the magnitude and the phase of Type 1 filter.

Here is Elia's original plot [[Media:BW_filter.ps]]. Then we see the same plot with the impulse-response also added (by Joe, Nov 29, 2007):
[[Image: BW_filter2.png]]

Here is the filter response for Scuba2 setting (''f''samp = 9.5 kHz, ''f''readout = 200 Hz): [[Media: Filter fs10kHz 200Hzdecimated response.ps ]]

== Filter-related Software changes ==

=== Determining the filter type ===

A {{param|rc|fltr_type}} parameter is introduced starting firmware 5.0.a:
* '''{{param|rc|fltr_type}} = 1''': ''f''cutoff / ''f''samp = 122.226 Hz / 15151 Hz
* '''{{param|rc|fltr_type}} = 2''': ''f''cutoff / ''f''samp = 75 Hz / 30000 Hz
* '''{{param|rc|fltr_type}} = 255''': configurable coefficient

All earlier firmware revisions are set to filter type 1 by default, except version 5.0.7 which is set to filter type 2.

=== Software requirements ===

* MAS - use mas/trunk r493 or later to get access to the {{param|rc|fltr_coeff}} MCE parameter.
** In [[mce.cin]], specify <code>$fw_rev["rc"] = 0x5010000</code> or greater.
* mce_script - use mce_script/trunk r764 or later
* In [[Mce config template system#experiment.cfg | experiment.cfg]]:
**specify one of:
config_filter = 0; # do not write filter coefficients to the MCE
config_filter = 1; # write filter coefficients to the MCE
and when config_filter = 1, the filter coefficients to be written to the MCE must be specified in the "filter_params" parameter, in the order [''b''11, ''b''12, ''b''21, ''b''22, ''k''1, ''k''2], e.g.:
filter_params = [ 32092, 15750, 31238, 14895, 0, 11]; # type 1 filter, ''f''cutoff/''f''samp = 122.226 Hz / 15.151 kHz
filter_params = [ 32295, 15915, 32568, 16188, 3, 14]; # type 2 filter, ''f''cutoff/''f''samp = 75 Hz / 30 kHz
filter_params = [ 32295, 15915, 32568, 16188, 5, 12]; # type 2 filter with more inter-biquad dynamic range (recommended)
filter_params = [ 32297, 15934, 31683, 15320, 0, 11]; # SCUBA-2 filter after 2011-06, ''f''cutoff/''f''samp = 75 Hz / 12.97 kHz

== Code for simulations ==

Note that as of mce_script r902, '''mce_data.py''' contains code for handling the MCE Butterworth filters. This can be used to load filter parameters from a runfile, and to get the complex frequency response of a filter. See [[mce_data.py#MCEButterworth_class]].

A smaller, quicker python example:
[[ Media: mce_filt_py.txt ]]

In this little IDL program you can find the functional form as a function of the frequency of the filter. First, Elia's original program, then as modified by Joe on November 29, 2007, then modified by Mandana on Jan. 14, 2009 for Scuba2 numbers:
* [[ Media: filter_pro.txt ]]
* [[ Media: filter_pro2.txt ]]
* [[ Media: low_pass_filter_model_pro.txt ]]

=== Digital, time domain simulation codes ===

Python-based model of a single biquad, in the time domain, for exploring digitization and dynamic range:
* [[ Media: biquad_time_domain_py.txt ]]

== Filter Coefficients ==
=== Butterworth Coefficients ===
The filter coefficients are generated using ''fdatool'' (Filter-design & Analysis tool, part of DSP Toolbox) in '''MATLAB/Simulink'''. These coefficients are floating numbers and in order to feed them to MCE firmware, they need to be quantized by converting to signed binary fractional (SBF) 1.14 format. You may use [[#Alternative to fdatool|alternate methods]] to generate coefficients. Here, we explain the method using ''fdatool''.

Once you launch the ''fdatool'', choose the following settings:

* Response Type: Low Pass
* Design Method: Butterworth
* Filter Order: 4

* Frequency Specifications:
** For Type 1:
*** ''f''samp = 12,195 Hz = 50 MHz/ (100 × 41)
*** ''f''cutoff = 100 Hz
** For Type 2:
*** ''f''samp = 30,000 Hz ≈ 50 MHz / (50 × 33)
*** ''f''cutoff = 75 Hz
** For Type 255:
*** ''f''samp = 50 MHz / ({{param|sys|row_len}} × {{param|sys|num_rows}})
*** ''f''cutoff=''f''readout / 2 (= ''f''samp / {{param|cc|data_rate}} / 2, if using internal CC triggering)
* The attenuation at ''f''cutoff is fixed at 3 dB (half the passband power)

Then click on Design Filter and you will get the following coefficients:
; Type 1
:Section 1:
::Numerator: 1 2 1
::Denominator: 1 -1.9587428340882587 0.96134553442399129
::Gain = 1/''g''1 = 0.00065067508393319923 (not implemented)
:Section 2:
::Numerator: 1 2 1
::Denominator: 1 -1.9066292518523014 0.90916270571237567
::Gain = 1/''g''2= 0.00063336346501859835 (not implemented)

; Type 2
:Section 1:
::Numerator: 1 2 1
::Denominator: 1 -1.9711486088510415 0.97139181456687917
:Section 2:
::Numerator: 1 2 1
::Denominator: 1 -1.9878047097960421 0.98804997058724808
:Gain = 1/(''g''1 × ''g''2)= 0.0000000037280516432624239 (not implemented)

; Type 255
: Plug in your desired ''f''samp and ''f''cutoff in MATLAB fdatool and you will get a set of coefficients:
:Section 1:
::Numerator: 1 2 1
::Denominator: 1 [[File:math_b11_star.png|30px|alt=b^*_{11}]], [[File:math_b12_star.png|30px|alt=b^*_{12}]]
:: Gain = 1/''g''1
:Section 2:
::Numerator: 1 2 1
::Denominator: 1 [[File:math_b21_star.png|30px|alt=b^*_{21}]], [[File:math_b22_star.png|30px|alt=b^*_{22}]]
::Gain = 1/''g''2

=== Coefficient Quantization ===
The quantization format is signed-binary fractional (SBF) 1.14 and then 2's complement to be able to account for positive and negative values.
* Compute the quantised coefficients ''bxy'' via: [[File:Math_bxy_eq.png|150px|alt=b_{xy} {{=}} \left\lfloor\left{{bar}}b^*_{xy}\right{{bar}} \times 2^{14}\right\rfloor]] (i.e. take the absolute value, multiply by 214 and then drop the fractional part).
* [[File:Math_k1_eq.png|170px|alt=k_1 {{=}} \left\lfloor \log_2 g_2 \right\rfloor - 10]], the output-truncation (10 is a historical constant)
* [[File:Math_k2_eq.png|160px|alt=k_2 = 1 + \left\lfloor \log_2 g_1 \right\rfloor]], the inter-stage truncation

For example, if we use this formula to quantize Type 1 coefficients listed above:
<center>[[File:Math_coeff_calc.png|800px|alt=\begin{align}
b_{11} &{{=}} \lfloor 1.9587428340882587 \times 2^{14}\rfloor &{{=}}&\ 32092\\
b_{12} &{{=}} \lfloor 0.96134553442399129 \times 2^{14}\rfloor &{{=}}&\ 15750\\
b_{21} &{{=}} \lfloor 1.9066292518523014 \times 2^{14}\rfloor &{{=}}&\ 31238\\
b_{22} &{{=}} \lfloor 0.90916270571237567 \times 2^{14}\rfloor &{{=}}&\ 14895\\
k_1 &{{=}} \left\lfloor \log_2 \left(1 / 0.00065067508393319923 \right)\right\rfloor - 10 &{{=}}&\ 0\\
k_2 &{{=}} 1 + \left\lfloor \log_2 \left(1 / 0.00063336346501859835 \right)\right\rfloor &{{=}}&\ 11
\end{align}]]</center>

* ''k''1 < 16 and ''k''2 < 32
* Now, if 32 − ''k''1 + ''k''2 > 32, then you have to talk to UBC!

:'''''The following ONLY concerns the MCE firmware developers:'''

:Prior to firmware 5.1.0, the coefficients were hardcoded in '''fsfb_calc_pack.vhd''' (FILTER_B11_COEF, FILTER_B12_COEF, FILTER_B21_COEFF, FILTER_B22_COEFF, FILTER_GAIN_WIDTH, FILTER_SCALE_LSB).''

=== Calculating the DC Gain (''k'') ===
Note that in firmware, instead of ''g''1 and ''g''2, an inter-biquad truncation of ''k''2 (implemented as a binary shift) and ''k''1, number of bits dropped after the second biquad, are implemented.

Hence, the overall gain becomes [[File:Math_gain_eq.png|60px|alt=\frac {g_1 g_2} {2^{(k_1 + k_2)}}]].

:''(Note for firmware developers: see FILTER_GAIN_WIDTH and FILTER_SCALE_LSB in '''fsfb_calc_pack.vhd'''.) ''

; Type 1
:''k''2 = 11, ''k''1 = 0, the filter gain is estimated at 1184, but VHDL simulation results in a gain of 1216.
; Type 2
:''k''2 = 14, ''k''1 = 3, the filter gain is estimated at 2046, but VHDL simulation results in a gain of 2181.

The gain difference can be attributed to the rounding effects associated with fixed-width arithmetic.

To roughly compute the gain, including the effects from truncating the coefficients, reverse the quantization process to obtain the floating point values associated with your coefficients, and plug into the filter definition. Here is a rough python program which computes the true gain for our Type 1 filter (''b''11 = 32092, ''b''12 = 15750, ''b''21 = 31238, ''b''22 = 14895, ''k''1 = 0, ''k''2 = 11):
from numpy import *
# Sum of k1 and k2 shifts:
k12 = 11+0
# Quantized coefficients b11, b12, b21, b22:
n = array([32092, 15750, 31238, 14895]).astype('float')
# Re-float
f = n/2**14
# Compute gain
gain = 16. / (2**k12 * (1 - f[0] + f[1]) * (1 - f[2] + f[3]))
print gain
# Result: 1217.8583043

== Useful Links ==
http://www.phas.ubc.ca/~mce/mcedocs/hardware/Firmware_block_spec/reaout_card/fsfb_calculations_rev1.11.pdf

http://www.planetanalog.com/showArticle.jhtml?articleID=12802683

== Alternative to fdatool ==
If you do not have access to fdatool or do not have DSP toolbox installed, you can use the following MATLAB functions (or equivalent in other packages) to get the coefficients:
* butter: is a matlab function to generate butterworth coefficients
* sos2tf: matlab function to break a transfer function to second-order sections
* bilinear: converts an s-domain (continuous) transfer function to z-domain (discrete) transfer function.
* Then run the following in matlab (or whatever syntax your tool has):
num=[1 2 1]
denum=[1 -1.9711486088510415 0.97139181456687917]
max(dbode(num, denum, 1/fsamp) but also look at the bode-plot to make sure it is flat, otherwise read the max from the flat portion of the plot instead of the max function.

'''Note:''' When I used coefficients generated by [a,b] = butter(2, 50/20000); [SOS,G]=tf2sos(a,b), the filter was not as robust. not sure why?!

[[Category:Readout Card Firmware]]

File:Math gain eq.png

2026-01-05T22:27:39Z

Dvw: \frac {g_1 g_2} {2^{(k_1 + k_2)}}

== Summary ==
\frac {g_1 g_2} {2^{(k_1 + k_2)}}

File:Math coeff calc.png

2026-01-05T22:20:52Z

Dvw: \begin{align} b_{11} &= \lfloor 1.9587428340882587 \times 2^{14}\rfloor &=&\ 32092\\ b_{12} &= \lfloor 0.96134553442399129 \times 2^{14}\rfloor &=&\ 15750\\ b_{21} &= \lfloor 1.9066292518523014 \times 2^{14}\rfloor &=&\ 31238\\ b_{22} &...

== Summary ==
\begin{align}
b_{11} &= \lfloor 1.9587428340882587 \times 2^{14}\rfloor &=&\ 32092\\
b_{12} &= \lfloor 0.96134553442399129 \times 2^{14}\rfloor &=&\ 15750\\
b_{21} &= \lfloor 1.9066292518523014 \times 2^{14}\rfloor &=&\ 31238\\
b_{22} &= \lfloor 0.90916270571237567 \times 2^{14}\rfloor &=&\ 14895\\
k_1 &= \left\lfloor \log_2 \left(1 / 0.00065067508393319923 \right)\right\rfloor - 10 &=&\ 0\\
k_2 &= 1 + \left\lfloor \log_2 \left(1 / 0.00063336346501859835 \right)\right\rfloor &=&\ 11
\end{align}

File:Math k2 eq.png

2026-01-05T22:13:58Z

Dvw: k_2 = 1 + \left\lfloor \log_2 g_1 \right\rfloor

== Summary ==
k_2 = 1 + \left\lfloor \log_2 g_1 \right\rfloor

File:Math k1 eq.png

2026-01-05T22:12:03Z

Dvw:

== Summary ==
k_1 = \left\lfloor \log_2 g_2 \right\rfloor - 10

File:Math k1 eq.png

2026-01-05T22:11:52Z

Dvw: k_1 = \left\lfloor \log_2 g_2 \right\rfloor - 10<

== Summary ==
k_1 = \left\lfloor \log_2 g_2 \right\rfloor - 10<

Template:Bar

2026-01-05T22:04:19Z

Dvw:

<nowiki>|</nowiki><noinclude>
== Documentation ==
This template can be used when you want to use a pipe/bar: "|" symbol somewhere where MediaWiki would treat it specially (e.g. in a template parameter).
</noinclude>

Template:Bar

2026-01-05T22:01:19Z

Dvw: Created page with "|<noinclude> == Documentation == This template can be used when you want to use a pipe/bar: "|" symbol somewhere where MediaWiki would treat it specially (e.g. in a template p..."

|<noinclude>
== Documentation ==
This template can be used when you want to use a pipe/bar: "|" symbol somewhere where MediaWiki would treat it specially (e.g. in a template parameter).
</noinclude>

Template:=

2026-01-05T21:54:01Z

Dvw: Created page with "=<noinclude> == Documentation == This template can be used to insert an equals sign in places where an equals sign is treated specially by the WikiMedia software (e.g. in temp..."

=<noinclude>
== Documentation ==
This template can be used to insert an equals sign in places where an equals sign is treated specially by the WikiMedia software (e.g. in template arguments).
</noinclude>

File:Math bxy eq.png

2026-01-05T21:49:03Z

Dvw: b_{xy} = \left\lfloor\left|b^*_{xy}\right| \times 2^{14}\right\rfloor

== Summary ==
b_{xy} = \left\lfloor\left|b^*_{xy}\right| \times 2^{14}\right\rfloor

File:Math bxy star.png

2026-01-05T21:47:17Z

Dvw: b^*_{xy}

== Summary ==
b^*_{xy}

File:Math b22 star.png

2026-01-05T21:46:20Z

Dvw: b^*_{22}

== Summary ==
b^*_{22}

File:Math b21 star.png

2026-01-05T21:45:04Z

Dvw: b^*_{21}

== Summary ==
b^*_{21}

File:Math b12 star.png

2026-01-05T21:43:32Z

Dvw: b^*_{12}

== Summary ==
b^*_{12}

File:Math butterworth.png

2026-01-05T21:41:21Z

Dvw:

== Summary ==
Butterworth filter.

H(z) = \frac {1+2 z^{-1}+z^{-2}}{1+b^*_{11} z^{-1}+b^*_{12} z^{-2}} \cdot 2^{-k_2} \cdot \frac {1+2z^{-1}+z^{-2}}{1+b^*_{21} z^{-1}+b^*_{22} z^{-2}} \cdot {2^{-k_1}}

File:Math b11 star.png

2026-01-05T21:40:48Z

Dvw: b^*_{11}

== Summary ==
b^*_{11}

File:Math butterworth.png

2026-01-05T21:36:08Z

Dvw: Butterworth filter.

== Summary ==
Butterworth filter.

MCE firmware

2025-01-31T21:29:15Z

Dvw:

{{Related|Firmware}}
== Releases ==
All firmware can be downloaded from [http://e-mode.phas.ubc.ca/mce/firmware/ http://e-mode.phas.ubc.ca/mce/firmware/]. Release notes for each firmware release can be found below:
* [[ Clock Card firmware]]
* [[ Readout Card firmware]]
* [[ Bias Card firmware]]
* [[ Address Card firmware]]
* [[ PCI card firmware ]]
* [[ Sync Box Firmware ]]

See also:
* [[Recommended firmware versions]]

== Loading firmware onto cards ==

There are two ways to load MCE firmware:
# [[ Remote Firmware Update | Remote firmware update over the MCE fibre interface]]
# Using Altera-supplied Hardware/Software and MCE Front-panel Connector
#* [[ USB Blaster | step-by-step instructions ]]

Things to bear in mind:
* In v5+ firmware, if you update firmware on any readout card, the card doesn't reply to any command unless the Clock Card is also reprogrammed.
* Always cleanly reset the MCE after a power-up or a reconfiguration! If not, MCE communication with the PC or Sync Box may not work. On MAS prompt, type: '''''mce_reset_clean'''''

== Implementation Details ==

* Source on GitHub: https://github.com/multi-channel-electronics/mce_firmware
* [[ MCE Timing Diagram ]]
* [[MCE fibre protocol]] - communication between the MCE and the controlling PC over the fibre-optic link
* [[MCE backplane protocol]] - communication between cards within the MCE
* Monitoring MCE Status [[http://www.phas.ubc.ca/%7Emce/mcedocs/system/monitoring_mce_status.doc DOC]] (Nov. 9, 2006)
* [[MCE commands]]

== Firmware Development Tools ==
* [[ Quartus II Installation ]]
* [[ ModelSim SE Installation ]]
** [[ Setting up Altera libraries in ModelSim SE ]]
* [[ JAM Player ]]
* [[ Convert sof to jic for EPCS64 Serial Configuration Device ]]

== Development notes ==
* [[intmce:MCE bugs]]
* [[intmce:Firmware Features Under Development]]
* [[intmce:Closed firmware features]]

[[Category:Firmware]]

Template:MCE hardware table

2022-07-08T17:43:02Z

Dvw:

<includeonly>{| class="wikitable"
! Component
! Type{{#if: {{{obsolete|}}}|/Part}}
! Doc. Id
! Technical Description&dagger;
! Block Diagram&dagger;
! Schematics
! Rev.
! Notes
|-
| colspan="2" | [[Clock Card]]
| S581
| [[http://www.phas.ubc.ca/~mce/mcedocs/hardware/tech_description/CC_TechDescr.pdf PDF]]
| [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/board_block_diagram/cc_bd.pdf PDF]]
| [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/schematics/Clock%20Card%20RevB/SC2-ELE-S581-101_RevB5_CC_Schematics.pdf PDF]]
| B5
|
|-
| colspan="2" rowspan="2" | [[Readout Card]]
| rowspan="2" | S582
| rowspan="2" | [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/tech_description/SC2_ELE_S582_501_readout_card_description.pdf PDF]]
| rowspan="2" | [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/board_block_diagram/rc_bd.pdf PDF]]
| [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/schematics/Readout%20Card%20RevB/RO_S582_101BIss9_Schematic.pdf PDF]]
| B9
|-
| [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/schematics/Readout%20Card%20RevE/RC_C582_101E0_Schematic.pdf PDF]]
| E0
| Low-power RC
|-
| colspan="2" rowspan="9" | [[Bias Card]]
| rowspan="9" | S583
| rowspan="9" | [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/tech_description/SC2_ELE_S583_501_bias_card_description.pdf PDF]]
| rowspan="9" | [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/board_block_diagram/bc_bd.pdf PDF]]
| [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/schematics/Bias%20Card%20RevD/BC_S583_101DIss6_Schematics.pdf PDF]]
| D6
| Original design
|-
| [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/schematics/Bias%20Card%20RevD/SC2-ELE-S583-101-RevDIss7&8_BiasCard_Schematics.pdf PDF]]
| D7/8
| High-current det_bias
|-
| [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/schematics/Bias%20Card%20RevD/SC2-ELE-S583-101D10_D11_BC_Schematic.PDF PDF]]
| D11
| High-current det_bias/no heater
|-
| [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/schematics/Bias%20Card%20RevE/BC_ELE_C583_101E0_Schematic.pdf PDF]]
| E0
| Multiple det_bias lines
|-
| [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/schematics/Bias%20Card%20RevF/ELE-C583-101F_BiasCard_Schematic.PDF PDF]]
| F0
| Multi det_bias & MHz-response bias lines; Low-noise bias lines turned off
|-
| [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/schematics/Bias%20Card%20RevF/ELE-C583-101F1_BiasCard_Schematic.PDF PDF]]
| F1
| Power turned off on ln_bias
|-
| [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/schematics/Bias%20Card%20RevF/ELE-C583-101F2_BiasCard_Schematic.PDF PDF]]
| F2
| Minor change in ln_bias circuit
|-
| [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/schematics/Bias%20Card%20RevF/ELE-C583-101F3_BiasCard_Schematic.PDF PDF]]
| F3
| low 1/f-noise opamp for channel 0-15
|-
| [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/schematics/Bias%20Card%20RevF/ELE-C583-101F4_BiasCard_Schematic.PDF PDF]]
| F4
| low 1/f-noise opamp for channel 15-31
|-
| colspan="2" rowspan="2" | [[Address Card]]
| rowspan="2" | S584
| rowspan="2" | [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/tech_description/AC_TechDescr.pdf PDF]]
| rowspan="2" | [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/board_block_diagram/ac_bd.pdf PDF]]
| [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/schematics/Address%20Card%20RevC/AC_S584_101CIss4_Schematics.pdf PDF]]
| C4
|
|-
| [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/schematics/Address%20Card%20RevD/AC_S584_101_RevDIss0_Schematics.pdf PDF]]
| D0
|
{{#if: {{{obsolete|}}}|
{{!}}-
{{!}} rowspan="6" {{!}} [[Instrument Backplane]]
{{!}} rowspan="2" {{!}} MCEv1
{{!}} rowspan="2" {{!}} S587-101
{{!}} rowspan="6" {{!}} [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/tech_description/instr_backplane_descr.pdf PDF]]
{{!}} rowspan="2" {{!}} —
{{!}} [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/schematics/Instrument%20Backplane%20RevC/S587-101_Inst_Backplane_Schematics.pdf PDF]]
{{!}} C3
{{!}} Obsolete
{{!}}-
{{!}} [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/schematics/Instrument%20Backplane%20RevC/S587-101CI5_Inst_Backplane_Schematics.pdf PDF]]
{{!}} C5
{{!}}
}}
|-
{{#if: {{{obsolete|}}}||
{{!}} rowspan="4" {{!}} [[Instrument Backplane]]
}}
| {{#if: {{{obsolete|}}}|MCEv2}} 5MDM
| C587-201
{{#if: {{{obsolete|}}}||
{{!}} rowspan="4" {{!}} [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/tech_description/instr_backplane_descr.pdf PDF]]
}}
| —
| [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/schematics/mceV2_InstrumentBackplane/ELE_C587-201_RevA0_Inst_Backplane_Schematics.pdf PDF]]
| A
|
|-
| rowspan="3" | {{#if: {{{obsolete|}}}|MCEv2}} 3MDM
| rowspan="3" | C587-101
| rowspan="3" | [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/board_block_diagram/ELE-C580-100_MCEv2_Instrument_Bus_Block_Diagram.pdf PDF]]
| [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/schematics/mceV2_InstrumentBackplane/ELE-C587-101_RevB_Inst_Backplane_Schematic.pdf PDF]]
| B
|
|-
| [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/schematics/mceV2_InstrumentBackplane/ELE-C587-101_RevC1_3MDM_Inst_Backplane_Schematics.pdf PDF]]
| C1
|
|-
| [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/schematics/mceV2_InstrumentBackplane/ELE-C587-101_RevC2_3MDM_Inst_Backplane_Schematics.pdf PDF]]
| C2
|
{{#if: {{{obsolete|}}}|
{{!}}-
{{!}} rowspan="3" {{!}} [[Bus Backplane]]
{{!}} MCEv1
{{!}} S586
{{!}} rowspan="3" {{!}} [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/tech_description/bus_backplane_descr.pdf PDF]]
{{!}} [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/Firmware_block_spec/atc_blkdia/fw_blkdia/Subrack.pdf PDF]]
{{!}} —
{{!}} C
{{!}} Obsolete
}}
|-
{{#if: {{{obsolete|}}}||
{{!}} rowspan="2" {{!}} [[Bus Backplane]]
}}
| {{#if: {{{obsolete|}}}|MCEv2}} 3MDM
| C586-101
{{#if: {{{obsolete|}}}||
{{!}} rowspan="2" {{!}} [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/tech_description/bus_backplane_descr.pdf PDF]]
}}
| rowspan="2" | —
| [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/schematics/mceV2_BusBackplane_RevD/ELE-C586-101_BusBP_Schematic%20Prints.pdf PDF]]
| A
|
|-
| {{#if: {{{obsolete|}}}|MCEv2}} 5MDM
| C586-201
| [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/schematics/mceV2_BusBackplane_RevD/ELE-C586-201_RevD0_BusBp_Schematics.pdf PDF]]
| D
|
{{#if: {{{obsolete|}}}|
{{!}}-
{{!}} rowspan="3" {{!}} [[Filter Board]]
{{!}} MCEv1
{{!}} S587-111
{{!}} rowspan="3" {{!}} —
{{!}} rowspan="3" {{!}} —
{{!}} [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/schematics/Filter%20Board/FB_S587_111BIss2_Schematics.pdf PDF]]
{{!}} B2
{{!}} Obsolete
}}
|-
{{#if: {{{obsolete|}}}||
{{!}} rowspan="2" {{!}} [[Filter Board]]
}}
| {{#if: {{{obsolete|}}}|MCEv2}} 3MDM
| C587-111
{{#if: {{{obsolete|}}}||
{{!}} rowspan="2" {{!}} —
{{!}} rowspan="2" {{!}} —
}}
| [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/schematics/mceV2_Filter_Board/ELE-C587-111_Filter_Schematic.pdf PDF]]
| A
|
|-
| {{#if: {{{obsolete|}}}|MCEv2}} 5MDM
| C587-210
| [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/schematics/mceV2_Filter_Board/ELE-C587-210_Filter_Schematics.pdf PDF]]
| A
|
{{#if: {{{obsolete|}}}|
{{!}}-
{{!}} rowspan="3" {{!}} [[Power Supply Assembly]]
{{!}} [[PSU]]
{{!}} S585-103
{{!}} —
{{!}} rowspan="3" {{!}} [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/tech_description/SCUBA-2%20Power%20Supply%20Specification%20Aug-26-2005%20JM%20WH.doc DOC]]
{{!}} [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/schematics/PowerSupplyUnit/PSU_S585_103B_20060502_schematics.pdf PDF]]
{{!}} B
{{!}} rowspan="3" {{!}} Obsolete
{{!}}-
{{!}} [[PSUC]]
{{!}} S585-102
{{!}} —
{{!}} [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/schematics/PowerSupplyController/PSUC%20S585_102GIss8%20Schematic.pdf PDF]]
{{!}} G8
{{!}}-
{{!}} Wiring
{{!}} S585-104
{{!}} —
{{!}} [[http://www.phas.ubc.ca/%7Emce/mcedocs/documentation/schematics_pcb/SC2-ELE-S585-104_RevB_PSA_Wiring_Diagram.pdf PDF]]
{{!}} B
}}
|}
'''&dagger;''': Not updated since early design stages.

=== External Hardware and Accessories ===
{| class="wikitable"
|-
! Component
! Part
! Doc. Id
! Technical Description&dagger;
! Block Diagram
! Schematics
! Rev.
! Notes
|-
| colspan="2" | [[MDM Breakout Board]]
| S58H
| —
| —
| [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/schematics/MDM%20Pinout/SubrackIB-TestPinouts1b_Rev2.1.xls XLS]]
| B
|
|-
| colspan="2" | [[Linear Feed Card]]
| C585-104
| —
| —
| [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/schematics/PLA/Linear_PS_MCE_Adaptor-ELE-C585-104_RevB.pdf PDF]]
| B
|
|-
| rowspan="2" | [[Vicor Power Assembly]]
| PCB
| C585-401
| rowspan="2" | —
| —
| [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/schematics/PowerSupplyVicor/ELE_C585-401_RevC2_VicorPSU_Schematics.pdf PDF]]
| C2
|
|-
| Wiring Harness
| C584-402
| —
| [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/schematics/PowerSupplyVicor/ELE-C584-402_RevA_Wiring_Harness.pdf PDF]]
| A
|
|-
| rowspan="4" | [[Sync Box]]
| PCB
| S589-101
| rowspan="4" | [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/tech_description/SyncBox_UserGuide_S589_502.pdf PDF]]
| —
| [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/schematics/SyncBox/SC2-ELE-S589-101_RevA2_SyncGen_Schematics.pdf PDF]]
| A2
| Used in both Sync Box enclosures
|-
| AC-in: Internal Wiring
| S589-102
| rowspan="2" | [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/board_block_diagram/S589-001_Syncbox_Block_Diagram.pdf PDF]]
| [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/schematics/SyncBox/S589-102_SyncBox_Wiring_Diagram.pdf PDF]]
| rowspan="2" | A2
|
|-
| AC-in: Cable Wiring
| S589-103
| [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/schematics/SyncBox/S589-103_SyncBox_IO_Cable_Wiring.pdf PDF]]
|
|-
| DC-in: Internal Wiring
| C589-102
| [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/board_block_diagram/ELE-C589-101B_DC-In_Sync_Blk_Diagram.pdf PDF]]
| [[https://phas.ubc.ca/~mce/mcedocs/hardware/schematics/SyncBox/ELE-C589-102_Sync_Box_Connector_Pinouts_Rev4.pdf PDF]]
| A
|
|-
| colspan="2" | [[PCI fibre card]]
| —
| —
| —
| [[http://www.phas.ubc.ca/%7Emce/mcedocs/others/SDSU/250hzPCI_schematic.pdf PDF]]
| 5A
|
|-
| colspan="2" | [[Extender Card]]
| S565-008
| [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/tech_description/ext_card_descr.pdf PDF]]
| —
| [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/schematics/ExtenderCard/extender_card_sc2_ele_s58A_101B PDF]]
|
|
|-
| colspan="2" | [[IB Tester]]
| S58E-502
| [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/tech_description/sc2-ele-s58e-502_gpib_ib_tester_description.pdf PDF]]
| —
| [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/schematics/IB%20Tester/ELE-S58E-101C_GPIB_IB_Tester_Schmatics.pdf PDF]]
| C
|
|-
| colspan="2" rowspan="2" | [[2-slot Backplane]]
| rowspan="2" | S58G
| —
| —
| [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/schematics/2slot_bp/SC2_ELE_S58G_101.pdf PDF]]
| A
|
|-
| —
| —
| [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/schematics/2slot_bp/2-slot_bp_SC2_ELE_S565_101_RevB0.pdf PDF]]
| B
|
{{#if: {{{obsolete|}}}|
{{!}}-
{{!}} colspan="2" {{!}} SCUBA2 24V Power Distribution
{{!}} S565-010
{{!}} [[http://www.phas.ubc.ca/%7Emce/mcedocs/pdrdocs/24v_ps_descr.pdf PDF]]
{{!}} [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/board_block_diagram/24v_pwr_distr.pdf PDF]]
{{!}} —
{{!}}
{{!}} Obsolete
{{!}}-
{{!}} rowspan="3" {{!}} [[AC-DC Unit]]
{{!}} Rectifier Board
{{!}} S588-103
{{!}} rowspan="3" {{!}} [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/schematics/PowerSupplyUnit/SCUBA-2%20Power%20Supply%20Specification%20Aug-26-2005%20JM%20WH.doc DOC]]
{{!}} rowspan="3" {{!}} —
{{!}} [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/schematics/acdcu/S588_103A_acdcu_rect_%28051128gf%29.pdf PDF]]
{{!}} A
{{!}} rowspan="3" {{!}} Obsolete
{{!}}-
{{!}} Controller Board
{{!}} S588-104
{{!}} [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/schematics/acdcu/S588_104A_acdcu_cntrl_%28060719gf%29.pdf PDF]]
{{!}} A
{{!}}-
{{!}} Wiring
{{!}} S588-105
{{!}} [[http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/schematics/acdcu/S588_105A_acdcu_wiring_%28060719gf%29.pdf PDF]]
{{!}} A
}}
|}
'''&dagger;''': Not updated since early design stages.</includeonly><noinclude>
This template contains the hardware document table. It comes in two flavours:

== Modern ==
{{MCE hardware table}}

is used on [[MCE hardware]] and produces:
{{MCE hardware table}}

== Legacy ==
{{MCE hardware table{{!}}obsolete=yes}}
is used on [[Old MCE Documents]] and produces:
{{MCE hardware table|obsolete=yes}}
</noinclude>

Sync Box

2022-06-11T02:18:28Z

Dvw: /* Documents */

{{Related|Sync Box}}
[[Image:Sync_Box_DC-In_Chassis.JPG|thumb| A 5VDC-in Sync Box with six of eight transmitters installed]]
[[Image:Sync_Box_AC-In_Rack_Mount.JPG|thumb|A rack-mount AC-in Sync Box - Back]]
[[Image:Sync_Box_AC-In_Rack_Mount_Front.JPG|thumb|A rack-mount AC-in Sync Box - Front]]
The '''Sync Box''' generates a data-valid pulse along with a sequential 32-bit number to synchronize the data-acquisition operation of up-to 8 MCE subracks and other housekeeping equipment. The 32-bit number can be used to stamp all collected data points. The Sync Box has 8 fibre outputs to connect to the MCE subracks and few TTL/RS485 outputs to be used by other housekeeping equipment. User commands are input to the Sync Box via RS-232. The CPLD generates a serial bit stream which is Manchester encoded with a 25MHz clock, and contains information for occurrences of <tt>address_zero</tt>, <tt>data_valid</tt>, and also a frame sequence number.

== Specifications ==
=== Power consumption ===
Excluding the fibre transmitters, the sync box consumes 1.35W. Each fibre transmitter (Avago HFBR-1119TZ) consumes 185mA x 5V = 0.925W, so a sync box with all eight tranmitters populated consumes 8.75W. To minimise power consumption, only the required number of transmitters should be populated. Input power is either 5V or 24V, depending on configuration.

=== Approximate dimensions ===
;Size: 5cm × 20cm × 25cm
;Weight: 600 grams

The obsolete, rack-mount AC-in sync box was 2U (9cm) × 19 inches (48cm) × 21cm deep and weighed 1.9kg.

== External connectors and I/O ==
:''These are the connectors and pinout for the DC-in sync box. For the connector pinout of the obsolete AC-in sync box, see [[Sync Box AC-in Rack Mount I/O]].

=== CP1: DC power in ===
Different connectors are used for 5V and 24V input.
;5V
* Box connector is an AMP 206486-1. +5VDC on pins 1 and 2. Return on pins 3 and 6. Other pins not populated. Pins 3 and 6 are connected to sync box ground.
:[[File:Sync box 5v in.png]]
* mating connector on the power brick is: AMP 206485-1
;24V
* Box connector is an Amphenol PT-2A-14-5P. +24VDC on pins B and C. Return on pins D and E. Pin A is not connected. Unlike the 5V-in sync box, the 24V-in sync box isolates pins D and E from sync box ground.
:[[File:small_mcc_power.png]]

=== CJ2: RS-232 command port ===
A nine pin DE-9F provides the serial command port. See [[#RS-232 communication and commanding|RS-232 communication and commanding]] below for details. The only lines wired through to the Atmel processor are:
{| class="wikitable"
|-
! Pin !! Signal
|-
| 2 || TxD
|-
| 3 || RxD
|-
| 4 || DSR
|-
| 5 || GND
|}
Don't rely on <tt>DSR</tt>. Assume no hardware or software flow control.

=== CJ3: Digital I/O ===
A twenty five pin DB-25F is used for digital I/O. Pins 1, 2, and 14 are inputs. All other pins are outputs. All grounds, including pin 14, are connected in the sync box to sync box ground.

In [[#RTS mode vs Free-run mode|RTS mode]], any falling edge of <tt>Data_Valid</tt> will be taken as a RTS DV signal. In Free Run mode, this input is ignored.

There are two pairs of RS485 outputs which provide a NRZ and clock version of the DV sync word. <tt>Data_Sync_1</tt> and <tt>Data_Sync_4</tt> have the clock and <tt>Data_Sync_2</tt> and <tt>Data_Sync_3</tt> have the NRZ sync word. There are also TTL versions of <tt>Data_sync_3</tt> and <tt>Data_Sync_4</tt>.

Note: the output contains only the DV sync word, not the single-zero-bit ARZ occurrences between DVs. For firmware versions before 1f, the clock rate is fixed at 5MHz. Later versions allow changing the clock rate by setting a divisor, ''d'', with the '''<tt>ckd</tt>''' command. In these versions the clock rate is 50MHz ÷ ''d''. The default value of ''d'' is 10 (meaning the default clock rate remains 5MHz).

{| class="wikitable"
|-
! Pin || Signal !! Pin !! Signal
|-
| style="background: #F99" rowspan="2" | 1 || style="background: #F99" rowspan=2" | Data_Valid RS485− || colspan="2" |  
|-
| style="background: #F99" rowspan="2" | 14 || style="background: #F99" rowspan=2" | GND
|-
| style="background: #F99" rowspan="2" | 2 || style="background: #F99" rowspan=2" | Data_Valid RS485+
|-
| style="background: #9F9" rowspan="2" | 15 || style="background: #9F9" rowspan=2" | Data_Sync_1 RS485−
|-
| style="background: #9F9" rowspan="2" | 3 || style="background: #9F9" rowspan=2" | GND
|-
| style="background: #9F9" rowspan="2" | 16 || style="background: #9F9" rowspan=2" | Data_Sync_1 RS485+
|-
| style="background: #99F" rowspan="2" | 4 || style="background: #99F" rowspan=2" | Data_Sync_2 RS485−
|-
| style="background: #99F" rowspan="2" | 17 || style="background: #99F" rowspan=2" | GND
|-
| style="background: #99F" rowspan="2" | 5 || style="background: #99F" rowspan=2" | Data_Sync_2 RS485+
|-
| style="background: #FF9" rowspan="2" | 18 || style="background: #FF9" rowspan=2" | Data_Sync_3 RS485−
|-
| style="background: #FF9" rowspan="2" | 6 || style="background: #FF9" rowspan=2" | GND
|-
| style="background: #FF9" rowspan="2" | 19 || style="background: #FF9" rowspan=2" | Data_Sync_3 RS485+
|-
| style="background: #EE9" rowspan="2" | 7 || style="background: #EE9" rowspan=2" | Data_Sync_3 TTL
|-
| style="background: #EE9" rowspan="2" | 20 || style="background: #EE9" rowspan=2" | GND
|-
| style="background: #F9F" rowspan="2" | 8 || style="background: #F9F" rowspan=2" | GND
|-
| style="background: #F9F" rowspan="2" | 21 || style="background: #F9F" rowspan=2" | Data_Sync_4 RS485−
|-
| style="background: #E9E" rowspan="2" | 9 || style="background: #E9E" rowspan=2" | Data_Sync_4 TTL
|-
| style="background: #F9F" rowspan="2" | 22 || style="background: #F9F" rowspan=2" | Data_Sync_4 RS485+
|-
| rowspan="2" | 10 || rowspan=2" | ''N/C''
|-
| style="background: #E9E" rowspan="2" | 23 || style="background: #E9E" rowspan=2" | GND
|-
| rowspan="2" | 11 || rowspan=2" | ''N/C''
|-
| rowspan="2" | 24 || rowspan=2" | ''N/C''
|-
| rowspan="2" | 12 || rowspan=2" | ''N/C''
|-
| rowspan="2" | 25 || rowspan=2" | ''N/C''
|-
| rowspan="2" | 13 || rowspan=2" | ''N/C''
|-
| colspan="2" |  
|}

=== CP4: ACDCU ===
:''Note: to make full use of these, firmware updates are needed.''
The ACDCU connector is a DB-25M. It can be used for general purpose I/O. Originally, these lines were used to control associated [[AC-DC Unit]]s, which are no longer in production. In most cases, this connector is left unpopulated. All grounds are connected in the sync box to sync box ground. The '''<tt>ps</tt>''' command will read these lines and report them as a hex-encoded byte:
Synco> ps
ACDCU_Status = 0X7B
The '''<tt>dpu</tt>''', '''<tt>dpa</tt>''', '''<tt>epa</tt>''', and '''<tt>pof</tt>''' commands can be used to control them.

{| class="wikitable"
|-
! Pin || Signal !! Pin !! Signal
|-
| style="background: #FFBE99" rowspan="2" | 1 || style="background: #FFBE99" rowspan=2" | Aux_in_1 || colspan="2" |  
|-
| style="background: #FFBE99" rowspan="2" | 14 || style="background: #FFBE99" rowspan=2" | GND
|-
| style="background: #FFBE99" rowspan="2" | 2 || style="background: #FFBE99" rowspan=2" | Aux_out_1
|-
| style="background: #99FFD8" rowspan="2" | 15 || style="background: #99FFD8" rowspan=2" | Aux_in_2
|-
| style="background: #99FFD8" rowspan="2" | 3 || style="background: #99FFD8" rowspan=2" | GND
|-
| style="background: #99FFD8" rowspan="2" | 16 || style="background: #99FFD8" rowspan=2" | Aux_out_2
|-
| style="background: #F199FF" rowspan="2" | 4 || style="background: #F199FF" rowspan=2" | Aux_in_3
|-
| style="background: #F199FF" rowspan="2" | 17 || style="background: #F199FF" rowspan=2" | GND
|-
| style="background: #F199FF" rowspan="2" | 5 || style="background: #F199FF" rowspan=2" | Aux_out_3
|-
| style="background: #F3FF99" rowspan="2" | 18 || style="background: #F3FF99" rowspan=2" | Aux_in_4
|-
| style="background: #F3FF99" rowspan="2" | 6 || style="background: #F3FF99" rowspan=2" | GND
|-
| style="background: #F3FF99" rowspan="2" | 19 || style="background: #F3FF99" rowspan=2" | Aux_out_4
|-
| style="background: #99DAFF" rowspan="2" | 7 || style="background: #99DAFF" rowspan=2" | Aux_in_5
|-
| style="background: #99DAFF" rowspan="2" | 20 || style="background: #99DAFF" rowspan=2" | GND
|-
| style="background: #99DAFF" rowspan="2" | 8 || style="background: #99DAFF" rowspan=2" | Aux_out_5
|-
| style="background: #FF99C0" rowspan="2" | 21 || style="background: #FF99C0" rowspan=2" | Aux_in_6
|-
| style="background: #FF99C0" rowspan="2" | 9 || style="background: #FF99C0" rowspan=2" | GND
|-
| style="background: #FF99C0" rowspan="2" | 22 || style="background: #FF99C0" rowspan=2" | Aux_out_6
|-
| style="background: #A7FF99" rowspan="2" | 10 || style="background: #A7FF99" rowspan=2" | Aux_in_7
|-
| style="background: #A7FF99" rowspan="2" | 23 || style="background: #A7FF99" rowspan=2" | GND
|-
| style="background: #A7FF99" rowspan="2" | 11 || style="background: #A7FF99" rowspan=2" | Aux_out_7
|-
| style="background: #A599FF" rowspan="2" | 24 || style="background: #A599FF" rowspan=2" | Aux_in_8
|-
| style="background: #A599FF" rowspan="2" | 12 || style="background: #A599FF" rowspan=2" | GND
|-
| style="background: #A599FF" rowspan="2" | 25 || style="background: #A599FF" rowspan=2" | Aux_out_8
|-
| rowspan="2" | 13 || rowspan=2" | ''N/C''
|-
| colspan="2" |  
|}

=== CJ5: TTL in ===
A female BNC used to provide an external TTL clock. The line is 50-ohm terminated. Ground (outer conductor) is connected to sync box ground. ''Note: this input is currently ignored in firmware.''

=== CJ6: TTL out ===
A female BNC providing a NRZ version of the [[#The Manchester output stream|output stream]]. The line is 50-ohm terminated. Ground (outer conductor) is connected to sync box ground.

=== MCE0 through MCE7: Fibre outputs ===
There are up to eight fibre-optic outputs (some which may not be populated to reduce power consumption). These outputs are connected to MCE [[Clock Card]] sync-in connection. The fibre-optic outputs are divided into two groups of four each, which allow the possibility for dual-rate operation. All outputs provide the [[#The Manchester output stream|Manchester-encoded output stream]].

=== Reset button ===
Pressing the reset momentary switch restarts the sync box control program and resets all parameters to their default values.

=== Front panel LEDs ===
* '''Power (green)''': The power LED is on whenever the sync box is powered on. Note: because the power for this LED is teed off of the power wiring harness (see schematic above), in cases where P5 has become disconnected, with external power applied, this lamp will be lit without the sync box actually being powered.
* '''Free run (yellow)''': The free-run LED is on whenever the sync box is in free-run mode.
* '''DV error (red)''': The DV error LED is turned on whenever more than one [[#CJ3|RTS DV pulse]] is received between successive address-reutrns-to-zero (ARZs); see [[#The Manchester output stream|The Manchester output stream]] below. It is turned off at the next ARZ. This cannot occur in free-run mode.

== Schematics ==
Here is a box diagram of the 5VDC-in sync box. The 24VDC-in sync box includes a 24-to-5V DC-DC converter module between the front panel power connector (CP1) and P5 on the sync board. The obsolete AC-in sync box also uses the same sync board, but has different external connections. 
[[File:Sync box schematic.jpg]]

=== Documents ===
* [http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/schematics/SyncBox/SC2-ELE-S589-101_RevA2_SyncGen_Schematics.pdf Sync Board Schematics (S589-101)]
* Block Diagram:
** [http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/board_block_diagram/S589-001_Syncbox_Block_Diagram.pdf rack-mount AC-in Sync Box (S589-001)]
** [http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/board_block_diagram/ELE-C589-111A_5VDC_Sync_Box_Block_Diagram.pdf 5V DC-in Sync Box (C589-111A)]
** [http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/board_block_diagram/ELE-C589-121A_24VDC_Sync_Box_Block_Diagram.pdf 24V DC-in Sync Box (C589-121A)]
* Wiring Diagrams
** [http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/schematics/SyncBox/ELE-C589-102_Sync_Box_Connector_Pinouts_Rev4.pdf DC-in Sync Box Wiring (C589-102)]
** [http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/schematics/SyncBox/S589-102_SyncBox_Wiring_Diagram.pdf rack-mount AC-in Sync Box Wiring]
** [http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/schematics/SyncBox/S589-103_SyncBox_IO_Cable_Wiring.pdf Cable connection to rack-mount Sync Box]

== RTS mode vs Free-run mode ==
The sync box operates either in free-run mode (the default) or else RTS mode. When in free-run mode, the sync box generates its own data valid (DV) triggers by down-counting occurrences of address-return-to-zero (ARZ), which occur at a rate of 25MHz × <tt>row_len</tt> × <tt>num_rows</tt>. The <tt>data_rate</tt> parameter to '''<tt>fr</tt>''' indicates how many ARZ occurrences occur between successive DVs.

In RTS mode, <tt>data_rate</tt> is ignored. Instead, the sync box waits for a falling edge on the <tt>[[#CJ3|Data_Valid]]</tt> RS485 digital input. When a falling edge is detected, a DV will be output on the next ARZ. If multiple falling edges are detected before an ARZ, only a single DV will be issued. (That is: only one external DV trigger is honoured per ARZ.)

These days, almost everyone uses free-run mode.

== The Manchester output stream ==
By default, the Manchester output bit-stream encodes simply the 25MHz clock as a series of (Manchester-encoded) one bits. Exceptions to this are:
* '''Address-Return-to-Zero (ARZ)''': Occurrences of ARZ are encoded into the Manchester bit-stream as a single binary zero. ARZ occurs at a rate of 25MHz × <tt>row_len</tt> × <tt>num_rows</tt>, regardless of operating mode (free-run or RTS).
* '''Data Valid sync word''': This is a 40-bit sequence which is output on certain ARZ occurrences. In free-run mode, the <tt>data_rate</tt> parameter indicates the number of ARZs between successive DV sync word output. In [[#RTS mode vs Free-run mode|RTS mode]], it can be output on ''every'' ARZ, but only if a [[#CJ3|RTS DV pulse]] has arrived since the last ARZ. On ARZs where the DV sync word is not output, only the ARZ bit will be zero (all other bits will be 1).

:The 40-bit DV sync word looks like this; bit zero is sent first:

zd-fe--- Nnnnnnnn nnnnnnnn nnnnnnnn nnnnnnnn
0 0 1 2 3
0 8 6 4 2

:where:

:* '''<tt>z</tt>''' is the address-return-to-zero (ARZ) bit (always zero)
:* '''<tt>d</tt>''' is the data valid bit (always zero)
:* '''<tt>-</tt>''' are reserved (unused) sync-word status bits
:* '''<tt>f</tt>''' is one when operating in free-run mode and zero when in RTS mode
:* '''<tt>e</tt>''' is the <tt>dv_error</tt> bit. It is one if in RTS mode and more than one RTS DV pulse was received since the last ARZ. Zero otherwise (including always zero in free-run mode).
:* '''<tt>Nnn...</tt>''' is the 32-bit frame sequence number. The most significant bit (''N'') is sent first.

== Firmware ==
:''See: [[Sync Box Firmware]]''
The sync box program comes in two parts: a program that runs on the Atmel microcontroller, and another that runs on the CPLD. For information on how to obtain the firmware, how to reprogram your sync box, and access to the source code, see [[Sync Box Firmware]].

== RS-232 communication and commanding ==
Commands are sent to the Sync Box over a 9600 baud RS-232 link, with no hardware or software flow control, connected to an Atmel AT89C5131A-M, an 8-bit, 80C51-compatible single-chip microcontroller. Input command variables are checked by the command processor and loaded one byte at a time into the sync generator CPLD over programmed I/O connections with eight bits for data and an eight-bit address.

Text returned by the sync box over RS232 use carriage return for line termination. Most Linux users will need to tell minicom (or whatever serial terminal they use) to add line feeds to avoid all output being overwritten on the same line.

More than one command may be put on a single input command line, up to a maximum of 12 tokens (commands + arguments), and 80 characters.

=== Command summary ===
The sync box responds to the following commands over the RS-232 link:
{| class="wikitable"
|-
! Command
! Description
! Default
! [[Sync Box Firmware|FW]] Version
|-
! <tt>h</tt>
| Help: print a list of commands.
| rowspan="2" | —
| rowspan="2" | all
|-
! <tt>?</tt>
| Shows the [[#Status output|current sync box parameters and status]].
|-
! rowspan="3" | <tt>rl</tt> ''n''
| rowspan="3" | Set <tt>row_len</tt> to ''n'' where 1 ≤ ''n'' ≤ 4095 
'''''NB:''''' Because the sync box clock is 25MHz, this value should be ''half'' the value of the corresponding MCE {{param|sys|row_len}}. For example, to have a {{param|sys|row_len}} of 100 on the MCE, set this value to 50. Also, <tt>row_len</tt> × <tt>num_rows</tt> must be ≥ 250.
| 64
| ≤ 1f
|-
| 53
| 20, 21
|-
| 50
| ≥ 22
|-
! rowspan="2" | <tt>nr</tt> ''n''
| rowspan="2" | Set {{param|cc|num_rows}} to ''n'' where 1 ≤ ''n'' ≤ 63 
Note: <tt>row_len</tt> × <tt>num_rows</tt> must be ≥ 250.
| 41
| ≤ 1f
|-
| 33
| ≥ 20
|-
! <tt>rt</tt>
| Enable RTS mode (turn off free-run mode).
| Off
| all
|-
! rowspan="3" | <tt>fr</tt> [''n'']
| rowspan="3" | Enable free-run mode (turn off RTS mode) and set {{param|cc|data_rate}} to ''n'' where 1 ≤ ''n'' ≤ 4095. If ''n'' is omitted, the previously commanded value for <tt>data_rate</tt> is re-used.
| 47
| ≤ 1f
|-
| 120
| 20, 21
|-
| 38
| ≥ 22
|-
! <tt>fn</tt> ''n''
| Set frame sequence number to ''n'' where 0 ≤ ''n'' ≤ 232−1
| —
| all
|-
! <tt>ckd</tt> ''n''
| Set the clock divisor to ''n'' where 1 ≤ ''n'' ≤ 255. The NRZ output clock is 50MHz ÷ ''n''. Before version 1f, the divisor is fixed at 10 (5MHz clock).
| 10
| ≥ 1f
|-
! <tt>go</tt>
| Enable Manchester and DV outputs.
| rowspan="2" | On
| rowspan="7" | all
|-
! <tt>st</tt>
| Disable Manchester and DV outputs.
|-
! <tt>dpa</tt>
| Disable all power outputs.
| rowspan="3" | All on
|-
! <tt>dpu</tt> ''n''
| Disable power output ''n'' where 0 ≤ ''n'' ≤ 7
|-
! <tt>epu</tt> ''n''
| Enable power output ''n'' where 0 ≤ ''n'' ≤ 7
|-
! <tt>pof</tt>
| Get ACDCU on/off control byte
| rowspan="2" | —
|-
! <tt>ps</tt>
| Get ACDCU status byte
|-
! <tt>bank</tt> ''n''
| Change target MCE bank for commands. ''n''=0 for both (unbanked); ''n''=1 for low bank (MCE1–4); ''n''=2 for high bank (MCE5–8)
| 0
| rowspan="2" | ≥ 31
|-
! <tt>eeprom</tt>
| Enter [[#EEPROM manipulation mode|EEPROM manipulation mode]]
| rowspan="2" | —
|-
! <tt>re</tt>
| Reset sync box to default state.
| all
|-
! colspan="4" style="text-align:center" |
=== EEPROM manipulation mode ===
|-
| colspan="4" | ''Note: this menu is activated by the ''<tt>eeprom</tt>'' command from the main menu.''
|-
! <tt>h</tt>
| Help: print a list of EEPROM manipulation mode commands.
| rowspan="5" | —
| rowspan="7" | ≥ 31
|-
! <tt>exit</tt>
| Leave EEPROM manipulation mode and return to the main menu.
|-
! <tt>dump</tt>
| Dump the contents of the EEPROM.
|-
! <tt>load</tt>
| Load the Sync Box configuration saved to the EEPROM, overwriting the currently-running configuration.
|-
! <tt>save</tt>
| Save the currently-running Sync Box configuration to the EEPROM.
|-
! <tt>enable_boot</tt>
| Load the saved configuration from the EEPROM on boot.
| rowspan="2" | Off
|-
! <tt>disable_boot</tt>
| Don't load the configuration saved to EEPROM on boot. Instead, the baked-in default configuration hard-coded in the code will be used.
|}

=== Status output ===
The '''<tt>?</tt>''' command produces output similar to this:

Synco> ?
Mancho_Enable = ON
DV_Mode = FreeRun_DV
Frun_Count = 47
Row_len = 64
Num_Row = 41
ACDCU_onoff = 0X00

=== Command error messages ===
Some example error messages:
Synco> xx WHAT? "xx" // Unrecognised command
Synco> rl 9999 TOO BIG "9999" // Parameter too large
Synco> rl 0 TOO SMALL "0" // Parameter too small
Synco> rl xx WHAT? "xx" // Parameter could not be parsed

=== Using minicom in Linux ===
To issue commands to a Sync Box over an RS-232 line, you can use a Linux program called <tt>minicom</tt>. To install this application, do:
sudo apt-get install minicom
To start MiniCom:
sudo minicom
Minicom needs the following options changed for it to work properly:
<ctrl-a>, <z>, <a> (to turn on line feeds)
<ctrl-a>, <z>, <o>, <Serial port setup> <Serial Device> = /dev/ttyS0
<ctrl-a>, <z>, <o>, <Serial port setup> <Bps/Par/Bits> = 9600 8N1
<ctrl-a>, <z>, <o>, <Serial port setup> <Hardware Flow Control> = No
<ctrl-a>, <z>, <o>, <Serial port setup> <Software Flow Control> = No
<ctrl-a>, <z>, <o>, <Modem and dialing> <Modem has DCD line> = No
After you modify these settings, remember to save, exit, and restart Minicom.

== Enabling sync box use in the MCE ==
To check that the sync box is connected correctly to the MCE, issue the command
wb cc {{param|cc|select_clk}} 1
and then read back the value:
rb cc {{param|cc|select_clk}}
Line 0 : ok : 1

Setting {{param|cc|select_clk}} to 1 tells the MCE to sync its internal clock with the clock signal encoded from the sync box. If the MCE does not see the sync box, the parameter will revert to zero (internal clock) in about one second.

To accept sync triggers and serial numbers from the sync box, two more commands are needed:
wb cc {{param|cc|use_sync}} 2
wb cc {{param|cc|use_dv}} 2

These registers are configured automatically by the config system if the parameters <tt>hardware_sync=1</tt> and <tt>config_sync=1</tt> in [[experiment.cfg]]. If you change the values in <tt>$MAS_DATA/experiment.cfg</tt> instead of <tt>$MAS_CONFIG/experiment.cfg</tt>, remember to run <tt>[[mce_make_config]]</tt> before re-running the config script.

Also be sure that you have the correct [[mce.cfg]] file. A quick way to check that sync numbers are getting into the MCE frame data is to take some frames and check the data using the [[eat_packets]] tool:

$ mce_run sync_test 400 s
RUNFILE_NAME=/data/cryo/current_data//sync_test.run
FRAME_BASENAME=/data/cryo/current_data//sync_test

$ eat_packets -n 5424 -f $MAS_DATA/sync_test
Forced frame_size=1356 (5424)
offset frm_idx frame#
0000000000 0 0 surprise sync_dv 4168076, after sequence [0,0)
EOF, exiting after 10000 frames + 0 bytes

If the <tt>[[mce_run]]</tt> does not terminate quickly, the sync box may not be properly connected to the MCE. If <tt>eat_packets</tt> complains only about the first frame (offset 00000000), then the sync numbers are intact and incrementing contiguously. If <tt>eat_packets</tt> complains about pretty much every frame, the sync numbers are not being inserted into the frame data.

== Legacy documents ==
* The original "Sync Box User's Guide" is available here:
:http://www.phas.ubc.ca/~mce/mcedocs/hardware/tech_description/SyncBox_UserGuide_S589_502.pdf
:'''Please note:''' it is rather out of date (being last updated in 2007), and known to be wrong in places. All relevant information from the guide should be available on this wiki.

[[Category:Sync Box| ]]

Sync Box

2022-06-11T02:15:43Z

Dvw: /* CJ3: Digital I/O */

{{Related|Sync Box}}
[[Image:Sync_Box_DC-In_Chassis.JPG|thumb| A 5VDC-in Sync Box with six of eight transmitters installed]]
[[Image:Sync_Box_AC-In_Rack_Mount.JPG|thumb|A rack-mount AC-in Sync Box - Back]]
[[Image:Sync_Box_AC-In_Rack_Mount_Front.JPG|thumb|A rack-mount AC-in Sync Box - Front]]
The '''Sync Box''' generates a data-valid pulse along with a sequential 32-bit number to synchronize the data-acquisition operation of up-to 8 MCE subracks and other housekeeping equipment. The 32-bit number can be used to stamp all collected data points. The Sync Box has 8 fibre outputs to connect to the MCE subracks and few TTL/RS485 outputs to be used by other housekeeping equipment. User commands are input to the Sync Box via RS-232. The CPLD generates a serial bit stream which is Manchester encoded with a 25MHz clock, and contains information for occurrences of <tt>address_zero</tt>, <tt>data_valid</tt>, and also a frame sequence number.

== Specifications ==
=== Power consumption ===
Excluding the fibre transmitters, the sync box consumes 1.35W. Each fibre transmitter (Avago HFBR-1119TZ) consumes 185mA x 5V = 0.925W, so a sync box with all eight tranmitters populated consumes 8.75W. To minimise power consumption, only the required number of transmitters should be populated. Input power is either 5V or 24V, depending on configuration.

=== Approximate dimensions ===
;Size: 5cm × 20cm × 25cm
;Weight: 600 grams

The obsolete, rack-mount AC-in sync box was 2U (9cm) × 19 inches (48cm) × 21cm deep and weighed 1.9kg.

== External connectors and I/O ==
:''These are the connectors and pinout for the DC-in sync box. For the connector pinout of the obsolete AC-in sync box, see [[Sync Box AC-in Rack Mount I/O]].

=== CP1: DC power in ===
Different connectors are used for 5V and 24V input.
;5V
* Box connector is an AMP 206486-1. +5VDC on pins 1 and 2. Return on pins 3 and 6. Other pins not populated. Pins 3 and 6 are connected to sync box ground.
:[[File:Sync box 5v in.png]]
* mating connector on the power brick is: AMP 206485-1
;24V
* Box connector is an Amphenol PT-2A-14-5P. +24VDC on pins B and C. Return on pins D and E. Pin A is not connected. Unlike the 5V-in sync box, the 24V-in sync box isolates pins D and E from sync box ground.
:[[File:small_mcc_power.png]]

=== CJ2: RS-232 command port ===
A nine pin DE-9F provides the serial command port. See [[#RS-232 communication and commanding|RS-232 communication and commanding]] below for details. The only lines wired through to the Atmel processor are:
{| class="wikitable"
|-
! Pin !! Signal
|-
| 2 || TxD
|-
| 3 || RxD
|-
| 4 || DSR
|-
| 5 || GND
|}
Don't rely on <tt>DSR</tt>. Assume no hardware or software flow control.

=== CJ3: Digital I/O ===
A twenty five pin DB-25F is used for digital I/O. Pins 1, 2, and 14 are inputs. All other pins are outputs. All grounds, including pin 14, are connected in the sync box to sync box ground.

In [[#RTS mode vs Free-run mode|RTS mode]], any falling edge of <tt>Data_Valid</tt> will be taken as a RTS DV signal. In Free Run mode, this input is ignored.

There are two pairs of RS485 outputs which provide a NRZ and clock version of the DV sync word. <tt>Data_Sync_1</tt> and <tt>Data_Sync_4</tt> have the clock and <tt>Data_Sync_2</tt> and <tt>Data_Sync_3</tt> have the NRZ sync word. There are also TTL versions of <tt>Data_sync_3</tt> and <tt>Data_Sync_4</tt>.

Note: the output contains only the DV sync word, not the single-zero-bit ARZ occurrences between DVs. For firmware versions before 1f, the clock rate is fixed at 5MHz. Later versions allow changing the clock rate by setting a divisor, ''d'', with the '''<tt>ckd</tt>''' command. In these versions the clock rate is 50MHz ÷ ''d''. The default value of ''d'' is 10 (meaning the default clock rate remains 5MHz).

{| class="wikitable"
|-
! Pin || Signal !! Pin !! Signal
|-
| style="background: #F99" rowspan="2" | 1 || style="background: #F99" rowspan=2" | Data_Valid RS485− || colspan="2" |  
|-
| style="background: #F99" rowspan="2" | 14 || style="background: #F99" rowspan=2" | GND
|-
| style="background: #F99" rowspan="2" | 2 || style="background: #F99" rowspan=2" | Data_Valid RS485+
|-
| style="background: #9F9" rowspan="2" | 15 || style="background: #9F9" rowspan=2" | Data_Sync_1 RS485−
|-
| style="background: #9F9" rowspan="2" | 3 || style="background: #9F9" rowspan=2" | GND
|-
| style="background: #9F9" rowspan="2" | 16 || style="background: #9F9" rowspan=2" | Data_Sync_1 RS485+
|-
| style="background: #99F" rowspan="2" | 4 || style="background: #99F" rowspan=2" | Data_Sync_2 RS485−
|-
| style="background: #99F" rowspan="2" | 17 || style="background: #99F" rowspan=2" | GND
|-
| style="background: #99F" rowspan="2" | 5 || style="background: #99F" rowspan=2" | Data_Sync_2 RS485+
|-
| style="background: #FF9" rowspan="2" | 18 || style="background: #FF9" rowspan=2" | Data_Sync_3 RS485−
|-
| style="background: #FF9" rowspan="2" | 6 || style="background: #FF9" rowspan=2" | GND
|-
| style="background: #FF9" rowspan="2" | 19 || style="background: #FF9" rowspan=2" | Data_Sync_3 RS485+
|-
| style="background: #EE9" rowspan="2" | 7 || style="background: #EE9" rowspan=2" | Data_Sync_3 TTL
|-
| style="background: #EE9" rowspan="2" | 20 || style="background: #EE9" rowspan=2" | GND
|-
| style="background: #F9F" rowspan="2" | 8 || style="background: #F9F" rowspan=2" | GND
|-
| style="background: #F9F" rowspan="2" | 21 || style="background: #F9F" rowspan=2" | Data_Sync_4 RS485−
|-
| style="background: #E9E" rowspan="2" | 9 || style="background: #E9E" rowspan=2" | Data_Sync_4 TTL
|-
| style="background: #F9F" rowspan="2" | 22 || style="background: #F9F" rowspan=2" | Data_Sync_4 RS485+
|-
| rowspan="2" | 10 || rowspan=2" | ''N/C''
|-
| style="background: #E9E" rowspan="2" | 23 || style="background: #E9E" rowspan=2" | GND
|-
| rowspan="2" | 11 || rowspan=2" | ''N/C''
|-
| rowspan="2" | 24 || rowspan=2" | ''N/C''
|-
| rowspan="2" | 12 || rowspan=2" | ''N/C''
|-
| rowspan="2" | 25 || rowspan=2" | ''N/C''
|-
| rowspan="2" | 13 || rowspan=2" | ''N/C''
|-
| colspan="2" |  
|}

=== CP4: ACDCU ===
:''Note: to make full use of these, firmware updates are needed.''
The ACDCU connector is a DB-25M. It can be used for general purpose I/O. Originally, these lines were used to control associated [[AC-DC Unit]]s, which are no longer in production. In most cases, this connector is left unpopulated. All grounds are connected in the sync box to sync box ground. The '''<tt>ps</tt>''' command will read these lines and report them as a hex-encoded byte:
Synco> ps
ACDCU_Status = 0X7B
The '''<tt>dpu</tt>''', '''<tt>dpa</tt>''', '''<tt>epa</tt>''', and '''<tt>pof</tt>''' commands can be used to control them.

{| class="wikitable"
|-
! Pin || Signal !! Pin !! Signal
|-
| style="background: #FFBE99" rowspan="2" | 1 || style="background: #FFBE99" rowspan=2" | Aux_in_1 || colspan="2" |  
|-
| style="background: #FFBE99" rowspan="2" | 14 || style="background: #FFBE99" rowspan=2" | GND
|-
| style="background: #FFBE99" rowspan="2" | 2 || style="background: #FFBE99" rowspan=2" | Aux_out_1
|-
| style="background: #99FFD8" rowspan="2" | 15 || style="background: #99FFD8" rowspan=2" | Aux_in_2
|-
| style="background: #99FFD8" rowspan="2" | 3 || style="background: #99FFD8" rowspan=2" | GND
|-
| style="background: #99FFD8" rowspan="2" | 16 || style="background: #99FFD8" rowspan=2" | Aux_out_2
|-
| style="background: #F199FF" rowspan="2" | 4 || style="background: #F199FF" rowspan=2" | Aux_in_3
|-
| style="background: #F199FF" rowspan="2" | 17 || style="background: #F199FF" rowspan=2" | GND
|-
| style="background: #F199FF" rowspan="2" | 5 || style="background: #F199FF" rowspan=2" | Aux_out_3
|-
| style="background: #F3FF99" rowspan="2" | 18 || style="background: #F3FF99" rowspan=2" | Aux_in_4
|-
| style="background: #F3FF99" rowspan="2" | 6 || style="background: #F3FF99" rowspan=2" | GND
|-
| style="background: #F3FF99" rowspan="2" | 19 || style="background: #F3FF99" rowspan=2" | Aux_out_4
|-
| style="background: #99DAFF" rowspan="2" | 7 || style="background: #99DAFF" rowspan=2" | Aux_in_5
|-
| style="background: #99DAFF" rowspan="2" | 20 || style="background: #99DAFF" rowspan=2" | GND
|-
| style="background: #99DAFF" rowspan="2" | 8 || style="background: #99DAFF" rowspan=2" | Aux_out_5
|-
| style="background: #FF99C0" rowspan="2" | 21 || style="background: #FF99C0" rowspan=2" | Aux_in_6
|-
| style="background: #FF99C0" rowspan="2" | 9 || style="background: #FF99C0" rowspan=2" | GND
|-
| style="background: #FF99C0" rowspan="2" | 22 || style="background: #FF99C0" rowspan=2" | Aux_out_6
|-
| style="background: #A7FF99" rowspan="2" | 10 || style="background: #A7FF99" rowspan=2" | Aux_in_7
|-
| style="background: #A7FF99" rowspan="2" | 23 || style="background: #A7FF99" rowspan=2" | GND
|-
| style="background: #A7FF99" rowspan="2" | 11 || style="background: #A7FF99" rowspan=2" | Aux_out_7
|-
| style="background: #A599FF" rowspan="2" | 24 || style="background: #A599FF" rowspan=2" | Aux_in_8
|-
| style="background: #A599FF" rowspan="2" | 12 || style="background: #A599FF" rowspan=2" | GND
|-
| style="background: #A599FF" rowspan="2" | 25 || style="background: #A599FF" rowspan=2" | Aux_out_8
|-
| rowspan="2" | 13 || rowspan=2" | ''N/C''
|-
| colspan="2" |  
|}

=== CJ5: TTL in ===
A female BNC used to provide an external TTL clock. The line is 50-ohm terminated. Ground (outer conductor) is connected to sync box ground. ''Note: this input is currently ignored in firmware.''

=== CJ6: TTL out ===
A female BNC providing a NRZ version of the [[#The Manchester output stream|output stream]]. The line is 50-ohm terminated. Ground (outer conductor) is connected to sync box ground.

=== MCE0 through MCE7: Fibre outputs ===
There are up to eight fibre-optic outputs (some which may not be populated to reduce power consumption). These outputs are connected to MCE [[Clock Card]] sync-in connection. The fibre-optic outputs are divided into two groups of four each, which allow the possibility for dual-rate operation. All outputs provide the [[#The Manchester output stream|Manchester-encoded output stream]].

=== Reset button ===
Pressing the reset momentary switch restarts the sync box control program and resets all parameters to their default values.

=== Front panel LEDs ===
* '''Power (green)''': The power LED is on whenever the sync box is powered on. Note: because the power for this LED is teed off of the power wiring harness (see schematic above), in cases where P5 has become disconnected, with external power applied, this lamp will be lit without the sync box actually being powered.
* '''Free run (yellow)''': The free-run LED is on whenever the sync box is in free-run mode.
* '''DV error (red)''': The DV error LED is turned on whenever more than one [[#CJ3|RTS DV pulse]] is received between successive address-reutrns-to-zero (ARZs); see [[#The Manchester output stream|The Manchester output stream]] below. It is turned off at the next ARZ. This cannot occur in free-run mode.

== Schematics ==
Here is a box diagram of the 5VDC-in sync box. The 24VDC-in sync box includes a 24-to-5V DC-DC converter module between the front panel power connector (CP1) and P5 on the sync board. The obsolete AC-in sync box also uses the same sync board, but has different external connections. 
[[File:Sync box schematic.jpg]]

=== Documents ===
* [http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/schematics/SyncBox/SC2-ELE-S589-101_RevA2_SyncGen_Schematics.pdf Sync Board Schematics (S589-101)]
* Block Diagram:
** [http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/board_block_diagram/S589-001_Syncbox_Block_Diagram.pdf rack-mount AC-in Sync Box (S589-001)]
** [http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/board_block_diagram/ELE-C589-111A_5VDC_Sync_Box_Block_Diagram.pdf 5V DC-in Sync Box (C589-111A)]
** [http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/board_block_diagram/ELE-C589-121A_24VDC_Sync_Box_Block_Diagram.pdf 24V DC-in Sync Box (C589-121A)]
* Wiring Diagrams
** [http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/schematics/SyncBox/ELE-C589-102_Sync_Box_Connector_Pinouts_Rev3.pdf DC-in Sync Box Wiring (C589-102)]
** [http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/schematics/SyncBox/S589-102_SyncBox_Wiring_Diagram.pdf rack-mount AC-in Sync Box Wiring]
** [http://www.phas.ubc.ca/%7Emce/mcedocs/hardware/schematics/SyncBox/S589-103_SyncBox_IO_Cable_Wiring.pdf Cable connection to rack-mount Sync Box]

== RTS mode vs Free-run mode ==
The sync box operates either in free-run mode (the default) or else RTS mode. When in free-run mode, the sync box generates its own data valid (DV) triggers by down-counting occurrences of address-return-to-zero (ARZ), which occur at a rate of 25MHz × <tt>row_len</tt> × <tt>num_rows</tt>. The <tt>data_rate</tt> parameter to '''<tt>fr</tt>''' indicates how many ARZ occurrences occur between successive DVs.

In RTS mode, <tt>data_rate</tt> is ignored. Instead, the sync box waits for a falling edge on the <tt>[[#CJ3|Data_Valid]]</tt> RS485 digital input. When a falling edge is detected, a DV will be output on the next ARZ. If multiple falling edges are detected before an ARZ, only a single DV will be issued. (That is: only one external DV trigger is honoured per ARZ.)

These days, almost everyone uses free-run mode.

== The Manchester output stream ==
By default, the Manchester output bit-stream encodes simply the 25MHz clock as a series of (Manchester-encoded) one bits. Exceptions to this are:
* '''Address-Return-to-Zero (ARZ)''': Occurrences of ARZ are encoded into the Manchester bit-stream as a single binary zero. ARZ occurs at a rate of 25MHz × <tt>row_len</tt> × <tt>num_rows</tt>, regardless of operating mode (free-run or RTS).
* '''Data Valid sync word''': This is a 40-bit sequence which is output on certain ARZ occurrences. In free-run mode, the <tt>data_rate</tt> parameter indicates the number of ARZs between successive DV sync word output. In [[#RTS mode vs Free-run mode|RTS mode]], it can be output on ''every'' ARZ, but only if a [[#CJ3|RTS DV pulse]] has arrived since the last ARZ. On ARZs where the DV sync word is not output, only the ARZ bit will be zero (all other bits will be 1).

:The 40-bit DV sync word looks like this; bit zero is sent first:

zd-fe--- Nnnnnnnn nnnnnnnn nnnnnnnn nnnnnnnn
0 0 1 2 3
0 8 6 4 2

:where:

:* '''<tt>z</tt>''' is the address-return-to-zero (ARZ) bit (always zero)
:* '''<tt>d</tt>''' is the data valid bit (always zero)
:* '''<tt>-</tt>''' are reserved (unused) sync-word status bits
:* '''<tt>f</tt>''' is one when operating in free-run mode and zero when in RTS mode
:* '''<tt>e</tt>''' is the <tt>dv_error</tt> bit. It is one if in RTS mode and more than one RTS DV pulse was received since the last ARZ. Zero otherwise (including always zero in free-run mode).
:* '''<tt>Nnn...</tt>''' is the 32-bit frame sequence number. The most significant bit (''N'') is sent first.

== Firmware ==
:''See: [[Sync Box Firmware]]''
The sync box program comes in two parts: a program that runs on the Atmel microcontroller, and another that runs on the CPLD. For information on how to obtain the firmware, how to reprogram your sync box, and access to the source code, see [[Sync Box Firmware]].

== RS-232 communication and commanding ==
Commands are sent to the Sync Box over a 9600 baud RS-232 link, with no hardware or software flow control, connected to an Atmel AT89C5131A-M, an 8-bit, 80C51-compatible single-chip microcontroller. Input command variables are checked by the command processor and loaded one byte at a time into the sync generator CPLD over programmed I/O connections with eight bits for data and an eight-bit address.

Text returned by the sync box over RS232 use carriage return for line termination. Most Linux users will need to tell minicom (or whatever serial terminal they use) to add line feeds to avoid all output being overwritten on the same line.

More than one command may be put on a single input command line, up to a maximum of 12 tokens (commands + arguments), and 80 characters.

=== Command summary ===
The sync box responds to the following commands over the RS-232 link:
{| class="wikitable"
|-
! Command
! Description
! Default
! [[Sync Box Firmware|FW]] Version
|-
! <tt>h</tt>
| Help: print a list of commands.
| rowspan="2" | —
| rowspan="2" | all
|-
! <tt>?</tt>
| Shows the [[#Status output|current sync box parameters and status]].
|-
! rowspan="3" | <tt>rl</tt> ''n''
| rowspan="3" | Set <tt>row_len</tt> to ''n'' where 1 ≤ ''n'' ≤ 4095 
'''''NB:''''' Because the sync box clock is 25MHz, this value should be ''half'' the value of the corresponding MCE {{param|sys|row_len}}. For example, to have a {{param|sys|row_len}} of 100 on the MCE, set this value to 50. Also, <tt>row_len</tt> × <tt>num_rows</tt> must be ≥ 250.
| 64
| ≤ 1f
|-
| 53
| 20, 21
|-
| 50
| ≥ 22
|-
! rowspan="2" | <tt>nr</tt> ''n''
| rowspan="2" | Set {{param|cc|num_rows}} to ''n'' where 1 ≤ ''n'' ≤ 63 
Note: <tt>row_len</tt> × <tt>num_rows</tt> must be ≥ 250.
| 41
| ≤ 1f
|-
| 33
| ≥ 20
|-
! <tt>rt</tt>
| Enable RTS mode (turn off free-run mode).
| Off
| all
|-
! rowspan="3" | <tt>fr</tt> [''n'']
| rowspan="3" | Enable free-run mode (turn off RTS mode) and set {{param|cc|data_rate}} to ''n'' where 1 ≤ ''n'' ≤ 4095. If ''n'' is omitted, the previously commanded value for <tt>data_rate</tt> is re-used.
| 47
| ≤ 1f
|-
| 120
| 20, 21
|-
| 38
| ≥ 22
|-
! <tt>fn</tt> ''n''
| Set frame sequence number to ''n'' where 0 ≤ ''n'' ≤ 232−1
| —
| all
|-
! <tt>ckd</tt> ''n''
| Set the clock divisor to ''n'' where 1 ≤ ''n'' ≤ 255. The NRZ output clock is 50MHz ÷ ''n''. Before version 1f, the divisor is fixed at 10 (5MHz clock).
| 10
| ≥ 1f
|-
! <tt>go</tt>
| Enable Manchester and DV outputs.
| rowspan="2" | On
| rowspan="7" | all
|-
! <tt>st</tt>
| Disable Manchester and DV outputs.
|-
! <tt>dpa</tt>
| Disable all power outputs.
| rowspan="3" | All on
|-
! <tt>dpu</tt> ''n''
| Disable power output ''n'' where 0 ≤ ''n'' ≤ 7
|-
! <tt>epu</tt> ''n''
| Enable power output ''n'' where 0 ≤ ''n'' ≤ 7
|-
! <tt>pof</tt>
| Get ACDCU on/off control byte
| rowspan="2" | —
|-
! <tt>ps</tt>
| Get ACDCU status byte
|-
! <tt>bank</tt> ''n''
| Change target MCE bank for commands. ''n''=0 for both (unbanked); ''n''=1 for low bank (MCE1–4); ''n''=2 for high bank (MCE5–8)
| 0
| rowspan="2" | ≥ 31
|-
! <tt>eeprom</tt>
| Enter [[#EEPROM manipulation mode|EEPROM manipulation mode]]
| rowspan="2" | —
|-
! <tt>re</tt>
| Reset sync box to default state.
| all
|-
! colspan="4" style="text-align:center" |
=== EEPROM manipulation mode ===
|-
| colspan="4" | ''Note: this menu is activated by the ''<tt>eeprom</tt>'' command from the main menu.''
|-
! <tt>h</tt>
| Help: print a list of EEPROM manipulation mode commands.
| rowspan="5" | —
| rowspan="7" | ≥ 31
|-
! <tt>exit</tt>
| Leave EEPROM manipulation mode and return to the main menu.
|-
! <tt>dump</tt>
| Dump the contents of the EEPROM.
|-
! <tt>load</tt>
| Load the Sync Box configuration saved to the EEPROM, overwriting the currently-running configuration.
|-
! <tt>save</tt>
| Save the currently-running Sync Box configuration to the EEPROM.
|-
! <tt>enable_boot</tt>
| Load the saved configuration from the EEPROM on boot.
| rowspan="2" | Off
|-
! <tt>disable_boot</tt>
| Don't load the configuration saved to EEPROM on boot. Instead, the baked-in default configuration hard-coded in the code will be used.
|}

=== Status output ===
The '''<tt>?</tt>''' command produces output similar to this:

Synco> ?
Mancho_Enable = ON
DV_Mode = FreeRun_DV
Frun_Count = 47
Row_len = 64
Num_Row = 41
ACDCU_onoff = 0X00

=== Command error messages ===
Some example error messages:
Synco> xx WHAT? "xx" // Unrecognised command
Synco> rl 9999 TOO BIG "9999" // Parameter too large
Synco> rl 0 TOO SMALL "0" // Parameter too small
Synco> rl xx WHAT? "xx" // Parameter could not be parsed

=== Using minicom in Linux ===
To issue commands to a Sync Box over an RS-232 line, you can use a Linux program called <tt>minicom</tt>. To install this application, do:
sudo apt-get install minicom
To start MiniCom:
sudo minicom
Minicom needs the following options changed for it to work properly:
<ctrl-a>, <z>, <a> (to turn on line feeds)
<ctrl-a>, <z>, <o>, <Serial port setup> <Serial Device> = /dev/ttyS0
<ctrl-a>, <z>, <o>, <Serial port setup> <Bps/Par/Bits> = 9600 8N1
<ctrl-a>, <z>, <o>, <Serial port setup> <Hardware Flow Control> = No
<ctrl-a>, <z>, <o>, <Serial port setup> <Software Flow Control> = No
<ctrl-a>, <z>, <o>, <Modem and dialing> <Modem has DCD line> = No
After you modify these settings, remember to save, exit, and restart Minicom.

== Enabling sync box use in the MCE ==
To check that the sync box is connected correctly to the MCE, issue the command
wb cc {{param|cc|select_clk}} 1
and then read back the value:
rb cc {{param|cc|select_clk}}
Line 0 : ok : 1

Setting {{param|cc|select_clk}} to 1 tells the MCE to sync its internal clock with the clock signal encoded from the sync box. If the MCE does not see the sync box, the parameter will revert to zero (internal clock) in about one second.

To accept sync triggers and serial numbers from the sync box, two more commands are needed:
wb cc {{param|cc|use_sync}} 2
wb cc {{param|cc|use_dv}} 2

These registers are configured automatically by the config system if the parameters <tt>hardware_sync=1</tt> and <tt>config_sync=1</tt> in [[experiment.cfg]]. If you change the values in <tt>$MAS_DATA/experiment.cfg</tt> instead of <tt>$MAS_CONFIG/experiment.cfg</tt>, remember to run <tt>[[mce_make_config]]</tt> before re-running the config script.

Also be sure that you have the correct [[mce.cfg]] file. A quick way to check that sync numbers are getting into the MCE frame data is to take some frames and check the data using the [[eat_packets]] tool:

$ mce_run sync_test 400 s
RUNFILE_NAME=/data/cryo/current_data//sync_test.run
FRAME_BASENAME=/data/cryo/current_data//sync_test

$ eat_packets -n 5424 -f $MAS_DATA/sync_test
Forced frame_size=1356 (5424)
offset frm_idx frame#
0000000000 0 0 surprise sync_dv 4168076, after sequence [0,0)
EOF, exiting after 10000 frames + 0 bytes

If the <tt>[[mce_run]]</tt> does not terminate quickly, the sync box may not be properly connected to the MCE. If <tt>eat_packets</tt> complains only about the first frame (offset 00000000), then the sync numbers are intact and incrementing contiguously. If <tt>eat_packets</tt> complains about pretty much every frame, the sync numbers are not being inserted into the frame data.

== Legacy documents ==
* The original "Sync Box User's Guide" is available here:
:http://www.phas.ubc.ca/~mce/mcedocs/hardware/tech_description/SyncBox_UserGuide_S589_502.pdf
:'''Please note:''' it is rather out of date (being last updated in 2007), and known to be wrong in places. All relevant information from the guide should be available on this wiki.

[[Category:Sync Box| ]]

Configuration for mux11d operation

2021-11-17T02:24:09Z

Dvw: /* Software requirements */

{{Related|Mux11d}}
:'''This topic is undergoing active development; information on this page is more subject to change than usual!'''

== Hardware configuration ==
The following diagram shows a conceptual schematic of using the MCE hardware with mux11d SQUID chips [http://www.phas.ubc.ca/~mce/mcedocs/system/mux11d_and_mce.pdf mux11d_with_mce.pdf] (prepared by Jimmy Grayson at Stanford)

For the reference: [[Media:Mux11d_bias_simple_diagram.pdf]]

Here is the proposed MCE signal assignment scheme: [http://www.phas.ubc.ca/~mce/mcedocs/system/mce_mdm_signal_names_and_pinouts.pdf [PDF]] [http://www.phas.ubc.ca/~mce/mcedocs/system/mce_mdm_signal_names_and_pinouts.xls [XLS]]

Note that the signals the MCE must provide to the mux11d SQUID system are:
* SA BIAS per column, constant
* SA FB per column, fast-switching
* SQ1 BIAS per column, fast-switching
* "Rowsel" feedback per row, multiplexing (one value when active, another value when not active)

== Software requirements ==

=== MAS ===

The mux11d support in MAS has been merged back into trunk and the former mux11d branch deleted. You can check out a new tree:

git clone https://github.com/multi-channel-electronics/mas.git

The only mux11d-specific features are in the "mux_lock" applications (2 new programs) and in the config2 system (mce.cfg).

=== mce_script ===

Updates for mux11d have been put right into mce_script, starting with r914. Just run "svn update" on your checked out copy. The major changes so far are:
* [[ experiment.cfg ]] has extra parameters to configure and enable fast SA feedback and fast SQ1 bias switching, and to guide the new servo applications.
* the config script generation code (script/bits) will set up the MCE for mux11d operation depending on variables in experiment.cfg

== Configuration ==

=== mce.cfg ===

When constructing [[ mce.cfg ]], start from templates/mce_v1_mux11d.cin or templates/mce_v2_mux11d.cin. These will map SQ1 bias as a per-column register, and properly expose fast switching of the SA FB and SQ1 bias. Since there is no "SQ2" in mux11d, this register is not defined.

The default mux11d configuration maps:
* SA FB to BC1 FLUX_FB
* SQ1 BIAS to BC2 FLUX_FB

There are other ways one might choose to do this mapping. The SQ1 bias card and offset, can be overridden in mce.cin by changing these variables:
/* These are only used if hw_mux11d != 0; they specify the bias card
* and offset of the flux_fb register used for the SQ1 bias. */
$mux11d_sq1_bc = "bc2";
$mux11d_sq1_offset = 0;

At the MCE command level, fast-switching on the SA FB and SQ1 BIAS is accomplished with the same bias card registers used for Fast SQ2 switching (see [[Row-specific SQ2FB (fast switching)#Firmware_requirements|firmware requirements]]). As an example, to load per-row values into the SA FB on column 5, and then enable muxing on that column, you could do the following:
wb sa fb_col5 123 432 514 451 434 653 123 ...
wra sa enbl_mux 5 1
Then to set a constant value on column 5, and disable muxing:
wra sa fb 5 400
wra sa enbl_mux 5 0

The SQ1 BIAS is exposed in a similar way. For example, the column 5 biases are exposed through:
wb sq1 bias_col5 123 432 514 451 434 653 123 ...
wra sq1 enbl_mux 5 1

In practice users don't write these MCE commands directly, and instead use the slightly higher-level of support provided by the experiment.cfg / config script system.

=== experiment.cfg ===

A number of parameters have been added to experiment.cfg to allow the config script system to set up fast-switching on the SA FB and SQ1 BIAS. These are:

* Enable:
**'''hardware_mux11d = 1;''': triggers handling of all the other mux11d specific settings.
* Row Select DAC control; these are arrays of up to 41 integers representing values for the "row select" (AC ON_BIAS) and "row deselect" (AC OFF_BIAS) DACs.
**'''row_select = [...];''': will be written to "row select" by the config script.
**'''row_deselect = [...];''': will be written to "row deselect" by the config script.
**'''default_row_select, default_row_deselect''': Eventually these will be used by the tuning to select default row_select and row_deselect values if the tuning has been instructed not to try to choose them.
* SA FB control:
** '''config_fast_sa_fb = 0;''': When set to 0, MCE will be set up for constant SA FB output, with values obtained from the setting "sa_fb". When set to 1, MCE will be set up for fast-switching of SA FB output, with values obtained from '''sa_fb_set'''.
** '''sa_fb_set = [...];''': A 1d array encoding SA FB values for each row and column. (As usual the values are arranged as the 41 values for column 0, followed by the 41 values for column 1, etc.)
* SQ1 BIAS control - these work exactly like SA FB above.
** '''config_fast_sq1_bias = 1;'''
** '''sq1_bias_set = [...];'''

For the purposes of array tuning the '''sq1_servo_*''' parameters will be used by the new '''sq1servo_sa''' program, which ramps the SQ1 FB and servos with the fast-switching SA FB (on each row independently). This may optionally be done for a series of SQ1 bias values.

A new set of servo control parameters, '''rowsel_servo_*''' (taking the same suffixes as the sq1_servo_* variables) has been introduced to control the new '''rs_servo''' program, which ramps the "row select" DACs and servos with the fast-switching SA FB (optionally at a series of SQ1 biases). In particular these parameters are:
;; rowsel_servo_gain, rowsel_servo_flux_start, rowsel_servo_flux_count, rowsel_servo_flux_step, rowsel_servo_bias_ramp, rowsel_servo_bias_start, rowsel_servo_bias_count, rowsel_servo_bias_step

== Usage ==

=== auto_setup, mux11d edition ===

The auto_setup code has been updated to support mux11d. I am uncertain as to how well-tested this code is, however.

The steps in tuning a mux11d system are:
* '''sa_ramp''' -- same as classic tuning; select SA FB (and possibly also SA BIAS).
* '''rs_servo''' -- trace out the "Row Select" V-phi curves (all rows), probably at several different S1 bias values; pick a reasonable S1 BIAS (one value per row, column) and ROWSEL/ROWDESEL feedbacks (one value per row). The algorithm for selecting ROWSEL/ROWDESEL feedback values is:
** All (row select) V-phi curves are analyzed to identify the first minimum and next maximum in the V-phi response. Each V-phi curve (bias,row,column) is flagged as valid, or not. Only valid curves are used when determining optimal biases and feedbacks for each column/row.
** '''SQ1 bias choice:''' If the SQ1 bias was ramped, an optimal SQ1 bias is chosen for each column and row by finding the bias at which the maximum peak-to-peak response is seen.
** '''ROWSEL/ROWDESEL choice''': For a given row select V-phi curve, the ROWDESEL point is the first minimum (probably near FB=0) and the ROWSEL point is the first maximum to the right of the ROWDESEL point. For each row, the ROWSEL and ROWDESEL feedback values are taken as the median of those values over all columns in the row. Only the values corresponding to the optimal SQ1 bias are considered.
* '''sq1_servo_sa''' -- trace out the S1 V-phi curves (all rows), probably at several different S1 bias values; pick final fast-switching S1 BIAS values and fast-switching SA FB set-points.
** This is probably not fully implemented.
* '''sq1_ramp''', '''sq1_ramp_check''', '''sq1_ramp_tes''' -- as in classic tuning; check your open loop response.

=== Using the new servo programs ===

This is only relevant if you're trying to run the servo programs yourself on the command line. The auto_setup should already know how to do all of this stuff correctly.

The servo programs make a lot of assumptions about the state of the MCE before beginning their job. Preparation is usually handled by the tuning code. To run these programs manually, the biggest thing to be careful of is that you have enabled (or disabled) fast-switching on the relevant stages. Here's a sequence of terminal commands which should work:

# Disable fast switching
mas_param set config_fast_sa_fb 0
mas_param set config_fast_sq1_bias 0
# Basic MCE setup and SA tuning
auto_setup --last-stage sa_ramp
mas_param set config_fast_sa_fb 1
# Recreate config script and run it to program the MCE.
mce_make_config -x
# Run the servos on RC2
sq1servo_sa 2 myservo1
rs_servo 2 myservo2

Later, once you have set up the "sq1_bias_set" values:
mas_param set config_fast_sq1_bias 1
mce_make_config -x

[[Category:Bias Card]]
[[Category:MAS]]
[[Category:MCE Script]]
[[Category:Mux11d]]

Code repositories

2021-11-17T02:21:31Z

Dvw:

The MCE software is available on GitHub in several repositories:

:https://github.com/multi-channel-electronics

The most common things you'll need are:
* the [[MAS]] code here: https://github.com/multi-channel-electronics/mas
** MAS uses the GNU autotools for a bit of configuration work.
* the [[MCE script]]s here: https://github.com/multi-channel-electronics/mce_script
See [[MAS OS setup]] for information on how to build and install these packages.

Also available:
* [[Sync box firmware]]: https://github.com/multi-channel-electronics/sync_box
** both CPLD and Atmel code are available
* [[PCI card firmware]]: https://github.com/multi-channel-electronics/arc_pci

== What about card firmware? ==

That's still in a CVS respository somewhere at UBC. Ask us for it.

[[Category:MAS]]
[[Category:MCE Script]]
[[Category:Sync Box Firmware]]

MCE script

2021-11-17T02:20:52Z

Dvw:

{{Related|MCE Script}}
The '''MCE script''' project is a collection of array setup tools and other utilities, built on top of [[MAS]], useful for running experiments. MCE script can be obtained from GitHub. See [[Code repositories]] for details on downloading MCE script.

= Tutorials =

* [[ Basic mce_script configuration ]]
* [[ Series array setup ]]

= Tool descriptions =
* Auto-tuning system
** [[ Auto-setup (python) ]] - an integrated tool set for dealing with SQUID data.
** [[ auto_setup_squids.pro | Auto-setup (IDL) ]] - IDL-based auto-tuning code (obsolete)
** [[ experiment.cfg ]] - array and auto-setup configuration data.
** [[ mce_config_template system ]]
* Other scripts
** [[MCE Test Scripts]]
** [[MCE script utilities]]
** [[ place_sq1.pro ]] for row selection for the purposes of sq1servo
** [[ IV curves ]] - acquire and analyze TES IV curves
** [[ special_ops.py ]]
** [[ measure_quanta.py ]] - Analyzes tuning data to determine SQUID phi0.
* Scripting tools
** [[ mce_internal_ramp ]] - configure and run MCE internal command ramps
** [[Environmental variables]]

= Other resources =

* Educational tools
** [[ Media:MAS_auto-tuning_20090529.pdf ]] - Some quick graphical depictions of auto-tuning. (Not a stand-alone presentation!)
** Characterization and Locking SQUIDs with Multi-Channel Electronics [[http://www.phas.ubc.ca/%7Emce/mcedocs/software/locking_squids.pdf PDF]] (Jun. 07, 2005)

* Sample auto-tune plots:
** [http://www.phas.ubc.ca/%7Emce/mcedocs/auto_tune_results/biasing_ac_sq2fb_switching biasing ac sq2fb switching]
** [http://www.phas.ubc.ca/%7Emce/mcedocs/auto_tune_results/biasing_ac_not_switching biasing ac not switching]
[[Category:MCE Script| ]]

MAS

2021-11-17T02:20:22Z

Dvw:

{{Related|MAS}}
== Overview ==

"MAS" is meant to refer primarily to the lowest levels of the control software, including the PCI card driver, command line utilities, and basic python modules.

For information on higher-level programs, such as the auto-tuning codes, please see [[MCE script]].

== Usage ==

* System applications
** [[mce_cmd]]
** [[mce_status]]
** [[maslog]]
** [[dsp_cmd]]

* Special applications
** [[ sq1_servo and sq2_servo ]]
** [[ mce_ramp ]]
** [[ psc_status ]]

* Utilities
** [[mas_param]]
** [[mas_var]]
:These two utilities may be compiled separately from the rest of MAS, even on systems (ie. MacOS X) which are unable to run the control software. See [[Mas param#Building_mas_param_on_MacOS_X|Building <tt>mas_param</tt> on MacOS X]] for instructions.

* MAS configuration
** [[ MAS start/stop ]]
** [[ mce.cfg ]]
** [[ mas.cfg ]]
** [[ MAS array_id and array_list | array_id and array_list ]]
** [[Environmental variables]]

* MAS file formats
** [[ Runfile format v2 ]]
** [[ MCE flat-file format ]]
** [[ dirfile support ]]

* Utilities for loading data
** IDL [[ mas_data.pro | data ]] and [[ mas_runfile.pro and mas_runparam.pro | runfile]] scripts
** [[ Python data and runfile modules ]]

* IDL scripts
** [[ auto_setup_squids.pro ]]

* Help
** [[MCE script utilities]], useful debugging programs
** [[ MCE Recovery During Acquisition ]]

== Development ==

* [[ MAS Bug List ]]
* [[ MAS feature requests ]]

== Installation / configuration ==

* [[ MAS PC requirements and initial setup | PC requirements and initial setup]]
* [[ MAS OS setup | OS setup]]
* [[Multicard MAS]], running MAS on a system with multiple fibre cards
* [[ MAS user setup ]]
* [[ MAS kernel patch compilation | kernel patch compilation]]
* [[ Code repositories ]]
* [[ Hardware goodlist/badlist ]]

== Trouble-shooting ==

* [[ MAS malfunction diagnosis | diagnosis ]]

[[Category:MAS| ]]

PCI card firmware

2021-11-17T02:19:52Z

Dvw:

{{Related|PCI Card Firmware}}
UBC-produced firmware for the ARC-64 [[PCI card]]. [[MAS]] provides a linux kernel driver for this firmware.
== Download ==

These S-record files should work with any reasonable EEPROM programmer:
* U0107 (recommended) - http://e-mode.phas.ubc.ca/mce/firmware/sdsu/SDSU_RevU0107.s
* U0106 (old stable) - http://e-mode.phas.ubc.ca/mce/firmware/sdsu/SDSU_RevU0106.s
** 8-bit checksum 6FCDCE
** Scrubber file - try writing all ones to your this to your chip first if your programmer won't let you "erase" it:
** http://e-mode.phas.ubc.ca/mce/firmware/sdsu/special/scrubber_RevU0106.s
* U0105 (deprecated) - http://e-mode.phas.ubc.ca/mce/firmware/sdsu/SDSU_RevU0105.s
* U0104 (deprecated) - http://e-mode.phas.ubc.ca/mce/firmware/sdsu/SDSU_RevU0104.s

The full source code is available in these archives (it will not compile unless you get the correct assembler and stuff):
* U0106 - http://e-mode.phas.ubc.ca/mce/arc_pci/source_code/arc_pci-U0106.tar.gz
* U0105 - http://e-mode.phas.ubc.ca/mce/arc_pci/source_code/arc_pci-U0105.tar.gz
* U0104 - http://e-mode.phas.ubc.ca/mce/arc_pci/source_code/arc_pci-U0104.tar.gz

The subversion tree can be obtained like this (you may not have access to this repository; contact UBC);
git clone https://github.com/multi-channel-electronics/arc_pci.git

It is laid out roughly as follows:
/trunk main line of development
/releases tagged versions of code
/tools debugging tools
/clash stuff for making CLAS work with wine and linux
/docs useful (though maybe not to you) notes

== Firmware version notes ==

=== U0107 (recommended) ===

* This firmware can operate in either of two modes:
** '''U0106 compatibility mode''': the firmware will work with classic MAS driver, just like U0106 (plus some bugfixes).
** '''New Master-only mode''': when activated, uses new set of protocols for communication with the MAS driver. These have proven to be much more stable on some systems. Also, bigphysarea is no longer needed.
* Downloads:
** S-rec for release candidates here: http://e-mode.phas.ubc.ca/mce/firmware/sdsu/
** Soft-patches for upgrading U0106 to pseudo-U0107 temporarily: http://e-mode.phas.ubc.ca/mce/firmware/sdsu/patches/
* Some additional notes specific to U0107: [[U0107 Series Firmware]]

=== U0106 (2011-11-21): Old stable version ===

* Not recommended for new projects
* Backward compatible with U0104 and U0105.
* Fixes bug introduced in U0105 that prevented handling of some PCI bus errors.
* Introduction of command to update PCI burst size.
* Bugs:
** Versions U0104-6 all suffer from the following issues:
*** Host interrupts use bit-test instructions, which are not interrupt safe; consequence is a race condition that can upset ongoing tasks such as FO downloads and PCI bursts. Patch for this issue, applicable to firmware versions U0104-6:
**** http://e-mode.phas.ubc.ca/mce/arc_pci/firmware/patches/patch_U0106_safetyize_vector_ints.bash
*** Multiple simultaneous PCI bus errors are not handled properly, leading to stale bits in the error register. This is an unlikely error vector, but should be fixed.

=== U0105 (2009-06-08) ===

* Backward compatible with U0104.
* Support for MCE STOP commands and commands-on-the-fly.
* Accelerated MCE command code (along with Quiet-RP this increases commanding rate to ~6 kHz).
* Quiet-RP simplifies the protocol for MCE reply handling.
* Low-level improvements:
** CON is done as PCI burst
** Fibre-optic FIFO is emptied with timed read instead of polling.
** Hand-shaking for interrupts instead of host command to clear INTA and HC3.
** Non-interrupt context code disables interrupts when performing PCI transactions.
** Host vector interrupts are otherwise enabled, so PC doesn't have to force with HNMI bit.
* Bugs and fixes:
** Some PCI bus arbitration conditions are mis-handled. This is fixed in U0106; alternately the commands below can be issued to patch active U0105 firmware. (The patch will not survive a power cycle.):
*** http://e-mode.phas.ubc.ca/mce/arc_pci/firmware/patches/patch_U0105_unignore_pci_errors.bash
** Also this (see description in U0106):
*** http://e-mode.phas.ubc.ca/mce/arc_pci/firmware/patches/patch_U0106_safetyize_vector_ints.bash

=== U0104: First version with non-realtime linux support ===

* Implements quiet transfer mode! Remains backwards compatible with A1.4.
* Fixes the 64k boundary crossing issue
* Moves parameters that enter via interrupt out of registers and into variables
* Version reporting tag-along to RDM command (sending 'VER' to RDM's vector address returns the code version).
* Maximum burst length is reduced to 64 bytes, and is configurable.
* Reset (RST) clears the fibre fifo
* Bugs:
** This (see description in U0106):
*** http://e-mode.phas.ubc.ca/mce/arc_pci/firmware/patches/patch_U0106_safetyize_vector_ints.bash

== U0103: Oldest UBC release ==

* Minor modifications of SCUBA2's A1.4 firmware, to improve PCI stability.
* Not compatible with non-realtime systems.

== Programming the ARC64 Flash memory ==

To program or upgrade the PCI card's firmware, it is necessary to remove the flash memory chip from the card and program it using a standard EEPROM programmer.

# Obviously you should turn off your computer and stuff first.
# The chip is a large DIP located at U5 on the PCI board. To remove the chip you may use one of the following (in increasing order of risk, and decreasing order of barbarism):
## telekinesis
## a chip removal tool
## needle-nose pliers
## a screw-driver
## thumb and finger
## fingers only
# The chip is a standard 256 Kbit electrically erasable Flash ROM. If you can't find the particular part in your EEPROM programmer software, try using one of these compatible parts:
## Fujitsu MBM28C256
## CSI (Catalyst) CAT28C256 L
## Anything else that has 28C256 in its name as long as it is a 28-pin DIP package and you are using the right socket for your programmer.
# Some programmers won't recognize this chip as erasable. You can just try programming the chip with the new firmware, or pseudo-erasing it first using a "scrubber" file (available for U0106 in the links above).
# The firmware we provide is compiled into a [ http://en.wikipedia.org/wiki/SREC_%28file_format%29 Motorola S-record format ] hex file. This is a standard format that your programmer software should be able to cope with.
# When placing the chip back in the board, the notch on the chip should be at the same end as the notch on the socket.

== Other information ==

* [[ PCI card bug list ]]
* [[ PCI card hacking ]]
* [[ PCI card code assembly on Linux ]]
* [[MCE fibre protocol]]

[[Category:PCI Card Firmware| ]]

PCI card firmware

2021-11-17T02:19:31Z

Dvw:

{{Related|PCI Card Firmware}}
UBC-produced firmware for the ARC-64 [[PCI card]]. [[MAS]] provides a linux kernel driver for this firmware.
== Download ==

These S-record files should work with any reasonable EEPROM programmer:
* U0107 (recommended) - http://e-mode.phas.ubc.ca/mce/firmware/sdsu/SDSU_RevU0107.s
* U0106 (old stable) - http://e-mode.phas.ubc.ca/mce/firmware/sdsu/SDSU_RevU0106.s
** 8-bit checksum 6FCDCE
** Scrubber file - try writing all ones to your this to your chip first if your programmer won't let you "erase" it:
** http://e-mode.phas.ubc.ca/mce/firmware/sdsu/special/scrubber_RevU0106.s
* U0105 (deprecated) - http://e-mode.phas.ubc.ca/mce/firmware/sdsu/SDSU_RevU0105.s
* U0104 (deprecated) - http://e-mode.phas.ubc.ca/mce/firmware/sdsu/SDSU_RevU0104.s

The full source code is available in these archives (it will not compile unless you get the correct assembler and stuff):
* U0106 - http://e-mode.phas.ubc.ca/mce/arc_pci/source_code/arc_pci-U0106.tar.gz
* U0105 - http://e-mode.phas.ubc.ca/mce/arc_pci/source_code/arc_pci-U0105.tar.gz
* U0104 - http://e-mode.phas.ubc.ca/mce/arc_pci/source_code/arc_pci-U0104.tar.gz

The subversion tree can be obtained like this (you may not have access to this repository; contact UBC);
git clone https://github.com/multi-channel-electronics/arc_pci

It is laid out roughly as follows:
/trunk main line of development
/releases tagged versions of code
/tools debugging tools
/clash stuff for making CLAS work with wine and linux
/docs useful (though maybe not to you) notes

== Firmware version notes ==

=== U0107 (recommended) ===

* This firmware can operate in either of two modes:
** '''U0106 compatibility mode''': the firmware will work with classic MAS driver, just like U0106 (plus some bugfixes).
** '''New Master-only mode''': when activated, uses new set of protocols for communication with the MAS driver. These have proven to be much more stable on some systems. Also, bigphysarea is no longer needed.
* Downloads:
** S-rec for release candidates here: http://e-mode.phas.ubc.ca/mce/firmware/sdsu/
** Soft-patches for upgrading U0106 to pseudo-U0107 temporarily: http://e-mode.phas.ubc.ca/mce/firmware/sdsu/patches/
* Some additional notes specific to U0107: [[U0107 Series Firmware]]

=== U0106 (2011-11-21): Old stable version ===

* Not recommended for new projects
* Backward compatible with U0104 and U0105.
* Fixes bug introduced in U0105 that prevented handling of some PCI bus errors.
* Introduction of command to update PCI burst size.
* Bugs:
** Versions U0104-6 all suffer from the following issues:
*** Host interrupts use bit-test instructions, which are not interrupt safe; consequence is a race condition that can upset ongoing tasks such as FO downloads and PCI bursts. Patch for this issue, applicable to firmware versions U0104-6:
**** http://e-mode.phas.ubc.ca/mce/arc_pci/firmware/patches/patch_U0106_safetyize_vector_ints.bash
*** Multiple simultaneous PCI bus errors are not handled properly, leading to stale bits in the error register. This is an unlikely error vector, but should be fixed.

=== U0105 (2009-06-08) ===

* Backward compatible with U0104.
* Support for MCE STOP commands and commands-on-the-fly.
* Accelerated MCE command code (along with Quiet-RP this increases commanding rate to ~6 kHz).
* Quiet-RP simplifies the protocol for MCE reply handling.
* Low-level improvements:
** CON is done as PCI burst
** Fibre-optic FIFO is emptied with timed read instead of polling.
** Hand-shaking for interrupts instead of host command to clear INTA and HC3.
** Non-interrupt context code disables interrupts when performing PCI transactions.
** Host vector interrupts are otherwise enabled, so PC doesn't have to force with HNMI bit.
* Bugs and fixes:
** Some PCI bus arbitration conditions are mis-handled. This is fixed in U0106; alternately the commands below can be issued to patch active U0105 firmware. (The patch will not survive a power cycle.):
*** http://e-mode.phas.ubc.ca/mce/arc_pci/firmware/patches/patch_U0105_unignore_pci_errors.bash
** Also this (see description in U0106):
*** http://e-mode.phas.ubc.ca/mce/arc_pci/firmware/patches/patch_U0106_safetyize_vector_ints.bash

=== U0104: First version with non-realtime linux support ===

* Implements quiet transfer mode! Remains backwards compatible with A1.4.
* Fixes the 64k boundary crossing issue
* Moves parameters that enter via interrupt out of registers and into variables
* Version reporting tag-along to RDM command (sending 'VER' to RDM's vector address returns the code version).
* Maximum burst length is reduced to 64 bytes, and is configurable.
* Reset (RST) clears the fibre fifo
* Bugs:
** This (see description in U0106):
*** http://e-mode.phas.ubc.ca/mce/arc_pci/firmware/patches/patch_U0106_safetyize_vector_ints.bash

== U0103: Oldest UBC release ==

* Minor modifications of SCUBA2's A1.4 firmware, to improve PCI stability.
* Not compatible with non-realtime systems.

== Programming the ARC64 Flash memory ==

To program or upgrade the PCI card's firmware, it is necessary to remove the flash memory chip from the card and program it using a standard EEPROM programmer.

# Obviously you should turn off your computer and stuff first.
# The chip is a large DIP located at U5 on the PCI board. To remove the chip you may use one of the following (in increasing order of risk, and decreasing order of barbarism):
## telekinesis
## a chip removal tool
## needle-nose pliers
## a screw-driver
## thumb and finger
## fingers only
# The chip is a standard 256 Kbit electrically erasable Flash ROM. If you can't find the particular part in your EEPROM programmer software, try using one of these compatible parts:
## Fujitsu MBM28C256
## CSI (Catalyst) CAT28C256 L
## Anything else that has 28C256 in its name as long as it is a 28-pin DIP package and you are using the right socket for your programmer.
# Some programmers won't recognize this chip as erasable. You can just try programming the chip with the new firmware, or pseudo-erasing it first using a "scrubber" file (available for U0106 in the links above).
# The firmware we provide is compiled into a [ http://en.wikipedia.org/wiki/SREC_%28file_format%29 Motorola S-record format ] hex file. This is a standard format that your programmer software should be able to cope with.
# When placing the chip back in the board, the notch on the chip should be at the same end as the notch on the socket.

== Other information ==

* [[ PCI card bug list ]]
* [[ PCI card hacking ]]
* [[ PCI card code assembly on Linux ]]
* [[MCE fibre protocol]]

[[Category:PCI Card Firmware| ]]

Auto-setup

2021-11-17T02:18:49Z

Dvw:

{{Related|Tuning}}
The python-based auto-setup is the primary tool used to tune the TES array. It provides a modular, flexible approach to tuning. The actions of acquisition, analysis, and plotting have been carefully separated. Objects exist to manage the locations of data and outputs to provide flexibility. Tools are provided to assist with loading and analyzing existing tuning data.

Currently the python auto-setup relies on scripts such as ramp_sa_bias and the mux_lock C programs to acquire the tuning data. Inside the python environment, data is loaded and manipulated as numpy arrays.

= Obtaining python auto_setup =

Auto-setup is part of the [[MCE script]] project. See the <tt>python/auto_setup</tt> subdirectory. You can get MCE script from the [[Code repositories|GitHub]].

= Script-level support =

Pass "-h" to any of the scripts below to get a usage message.

== auto_setup ==

The executable script '''auto_setup''' can be used to tune SQUID arrays from the command line.

== plot_tuning ==

The executable script '''plot_tuning''' can be used create plots from existing tuning data.

= The "auto_setup" module =

The following classes may be useful for off-line analysis of tuning data. Note that the *Ramp and *Servo classes all inherit from the RCData class, takes a slightly eccentric approach to indexing the data it contains.

== class util.FileSet ==

The FileSet class can be used to locate and group tuning data files, so that they can be more easily loaded as *Ramp and *Servo objects. Use like this:

import auto_setup as ast
tuning_dir = '/data/cryo/current_data/1234560000'
fs = ast.util.FileSet(tuning_dir)
for stage in ['sa_ramp', 'sq2_servo', 'sq1_servo', 'sq1_ramp']:
print fs.stage_all(stage)

This will print out the data files associated with each tuning stage. They can be loaded and combined using a join method, e.g.:
sa_ramps = [SARamp(f) for f in fs.stage_all('sa_ramp')] # individual ramps per RC
sa_ramp = SARamp.join(sa_ramps) # single, coherent ramp data object

Note that this join procedure isn't necessary if there is only one data file per squid stage (the default in modern python auto_setup). Older code acquired tuning data on each readout card individually; so the join procedure outlined should permit convenient loading of legacy data.

== class util.mas_path ==

The mas_path class can be used to simplify path look-up. In the past this was simply done using environmental variables. That method doesn't work that well with [[Multicard MAS]]; mas_path abstracts path look-up, hiding the details of how paths are determined from the caller. Use like this:

from auto_setup.util import mas_path
mp = mas_path()
print mp.data_dir()

mas_path figures out paths by performing the following tests:
# if [[mas_var]] is present, it is run to determine the path
# if that doesn't work, mas_path looks in the environment for an appropriately named MAS_<...> variable and reports its value
# if neither of the above work, mas_path produces a "sensible default value".
Directories are cached after the first look-up.

A fibre card number (ignored if not-running [[Multicard MAS]]), an alternate [[mas.cfg]] file (only used if [[mas_var]] is run) and an alternate [[mas_var]] program can be passed to mas_path:

from auto_setup.util import mas_path
mp = mas_path(fibre_card=1, mas_cfg="/etc/mce/mas-alternate.cfg", mas_var="/some/other/mas_var")
print mp.data_dir()

If no fibre_card is specified, the value of $MAS_MCE_DEV is used, if it exists, otherwise zero is used as a default fibre card number. If mas_var is not specified, the value of $MAS_VAR is tried, if it exists, otherwise the default path "/usr/mce/bin/mas_var" is tried. If mas_var can't be found, the first of the three tests is simply skipped without error.

The following methods are defined in this class:

* <code>bin_dir()</code>: returns the location of the MAS binaries (ie. $MAS_BIN, if defined); "/usr/mce/bin" is the default.
* <code>config_dir()</code>: returns the location of the MCE script configuration (ie. $MAS_CONFIG, if defined); "/usr/mce/config" is the default.
* <code>data_root()</code>: returns the root data directory ($MAS_DATA_ROOT, if defined); the default is "/data/mce''N''" where ''N'' is the fibre card number. However, for backwards compatibility, if the "/data/mce''N''" directory doesn't exist, "/data/cryo" will be returned instead.
* <code>data_dir()</code>: returns the current data directory ($MAS_DATA, if defined); the default is the value returned by <code>data_root()</code> with "/current_data" appended.
* <code>etc_dir()</code>: returns the location of the MAS configuration files ($MAS_ETC, if defined); "/etc/mce" is the default.
* <code>experiment_file()</code>: returns the location of the experiment config file (no corresponding environmental variable); the default is the value returned by <code>data_dir()</code> with "/experiment.cfg" appended.
* <code>hardware_file()</code>: returns the location of the hardware config file (no corresponding environmental variable); the default is the value returned by <code>etc_dir()</code> with "/mce''N''.cfg" appended, where ''N'' is the fibre card number. However, for backwards compatibility, if the "mce''N''.cfg" file doesn't exist, plain "mce.cfg" will be used instead.
* <code>mas_prefix()</code>: returns the location of the installed MAS tree (ie. $MAS_PREFIX, if defined); "/usr/mce" is the default.
* <code>temp_dir()</code>: returns the location of the MAS/MCE script temp directory ($MAS_TEMP, if defined); "/tmp" is the default.

* <code>mas_root()</code>: returns the location of the MCE script tree (ie. $MAS_ROOT, if defined); "/usr/mce/mce_script" is the default.
* <code>idl_dir()</code>: returns the location of the MCE script IDL directory (ie. $MAS_IDL, if defined); the default is the value returned by <code>mas_root()</code> with "/idl_pro" appended.
* <code>python_dir()</code>: returns the location of the MCE script Python directory (ie. $MAS_PYTHON, if defined); the default is the value returned by <code>mas_root()</code> with "/python" appended.
* <code>script_dir()</code>: returns the location of the MCE script shell script directory (ie. $MAS_SCRIPT, if defined); the default is the value returned by <code>mas_root()</code> with "/script" appended.
* <code>template_dir()</code>: returns the location of the MCE script template directory (ie. $MAS_TEMPLATE, if defined); the default is the value returned by <code>mas_root()</code> with "/template" appended.
* <code>test_suite_dir()</code>: returns the location of the MCE script test suite directory (ie. $MAS_TEST_SUITE, if defined); the default is the value returned by <code>mas_root()</code> with "/test_suite" appended.

These functions are all implemented through calls to the low-level method:

__get_path__(name, env, default)

where:
* <code>name</code> is the name of a [[mas_var]] parameter to check, excluding the initial "--", or None
* <code>env</code> is the name of an environmental variable to check, or None
* <code>default</code> is the default value to return if other look-up methods fail.
Ie., the <code>mas_path().bin_dir()</code> method is implemented using the call:

mas_path().__get_path__('bin-dir', 'MAS_BIN', '/usr/mce/bin')

== class SARamp ==
== class SQ2Servo==
== class SQ1Servo ==
== class SQ1Ramp ==

== class RCData ==

This class stores time-ordered data for some set of detectors. Tuning data sets can be quite complex (consider a multi-bias, all-row SQ1 Servo for example) and so a certain convention has been adopted to indicate different structuring of the data. In all cases, the data themselves are stored in a 2-d numpy array, with the second index representing the time index and the first index encapsulating all other degrees of freedom (row, column, bias index,...). The underlying data shape is contained in the attribute '''data_shape'''. This is not to be confused with '''data.shape''', which is the actual numpy dimensionality of the '''data''' array.

{| class="wikitable"
! Form of data
! data_shape
! data.shape
! gridded
! rows
! cols
|-
| One time-stream per channel
| (n_row, n_col, n_time)
| (n_row*n_col, n_time)
| True
| list of rows (size n_row)
| list of columns (size n_col)
|-
| Multi-bias data; n_bias time-stream per channel
| (n_bias, n_row, n_col, n_time)
| (n_bias*n_row*n_col, n_time)
| True
| list of rows (size n_chan)
| list of columns (size n_chan)
|-
| One time stream for some set of row, column pairs
| (1, n_chan, n_time)
| (n_chan, n_time)
| False
| list of rows (size n_chan)
| list of columns (size n_chan)
|-
| Multi-bias data; for some set of row, column pairs
| (n_bias, 1, n_chan, n_time)
| (n_bias*n_chan, n_time)
| False
| list of rows (size n_chan)
| list of columns (size n_chan)
|-
|}

== class config.configFile ==

This is a class for reading and modifying simple libconfig configuration files, such as [[experiment.cfg]]. The class extends the python "dict" class; keys from the configuration file become the keys of the dictionary. The class calls [[mas_param]] to decode the specified config file, including type information. Array data are stored as numpy arrays.

Typical usage in a script, to obtain access to experiment.cfg parameters, is done like this:
from auto_setup.config import configFile
cfg = configFile('/data/cryo/current_data/experiment.cfg')

print cfg['default_num_rows']
print cfg['sa_bias']

Output:
33
[42000 15000 16500 15000 15000 15000 15000 15000 0 0
0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0
0 0]

=== Updating values ===

There are two ways to update values in the target configuration file. The first is to use "set_param":

cfg.set_param('sa_bias', [65535] * 32) # write 65535 to all 32 entries of SA bias

This will immediately update the target configuration file, with a single call to mas_param to set the 'sa_bias' key.

The second way may be more convenient when modifying a large number of parameters. One updates the dict with new values and then calls the .write() method:
cfg['sa_bias'] = [65535] * 32
cfg['sa_offset'] = [1000] * 32
cfg['sq2_bias'] = [0] * 32
cfg.write()

Note that cfg.write() will rewrite *all* of the keys, not just the ones you have changed. This will make it somewhat slower and potentially more confusing than using cfg.set_param. So you might just want to stick with set_param.

[[Category:Tuning| ]]
[[Category:Python]]

Sync Box firmware

2021-11-17T02:18:31Z

Dvw:

{{Related|Sync Box Firmware}}
There is an Altera CPLD (EPM570T144C3) and an Atmel micro-controller (AT89C51) on in the [[Sync Box]].
* SyncBox CPLD Firmware Description [[http://www.phas.ubc.ca/~mce/mcedocs/hardware/Firmware_block_spec/SyncBox/SyncBox_FwDescr_S589_201.pdf PDF]] (SC2-ELE-S589-201)
* SyncBox Microcontroller Software Description [[http://www.phas.ubc.ca/~mce/mcedocs/hardware/Firmware_block_spec/SyncBox/SyncBox_SWDescr_S589_202.pdf PDF]] (SC2-ELE-S589-202)

Consequently, there are two sets of firmware:
*firmware for the CPLD part (*.pof file)
*firmware for the microcontroller (*.hex file)

== Firmware Upgrade Instructions ==
=== Downloads ===

Firmware is available from the MCE firmware repository:

* http://e-mode.phas.ubc.ca/mce_firmware/sync_box

To upgrade the Sync Box firmware, ''most times'' both the microcontroller and the CPLD firmware need to be reprogrammed.

=== CPLD programming (<tt>.pof</tt> file) ===
The CPLD firmware can be loaded using the Altera USB-Blaster that connects to the on-board P23 JTAG header, and Quartus Programmer software. A <tt>.pof</tt> file needs to be loaded. The P23 connector is not wired out to the sync box enclosure. To access it, remove the sync box cover plate.

=== Microcontroller programming (<tt>.hex</tt> file) ===
The microcontroller program is loaded over a USB cable that connects your computer to the on-board J1 (USB-B) connector. This connector is not wired out to the sync box enclosure: to access it, remove the top cover. In the past we used Atmel's [http://www.atmel.com/tools/FLIP.aspx Flip Programmer]. Now we recommend running <tt>dfu-programmer</tt> on linux. See:
* [[Sync Box Firmware Upgrade using dfu-programmer]].

==== Enabling reprogramming over USB ====
Regardless of what you use to program the sync box, you need to get the sync box bootloader to restart in reprogramming mode. To do this, the procedure is:
# Start with the sync box powered off and disconnected from USB
# Depress ''both'' the on-board RESET switch and the PS_EN switch. The PS_EN switch may be labeled as PRG_EN. Both switches are located next to the USB J1 connector on the board. '''NB''': This is ''not'' the reset switch on the outside of the sync box enclosure.
# Power on the sync box.
# Release the RESET switch
# Release the PS_EN switch
# Plug in the USB cable
If this procedure is successfully performed, the sync box will present itself as a USB device to your computer. Your computer should now detect the sync box as an Atmel AT89C5131 device. If the sync box isn't accepting USB protocol commands, turn it off and try the procedure again.

== Releases ==

=== Firmware set Rev. 31 ===
; Filename
: sync_box_v31_21Jun2016.hex
: sync_box_v31_21Jun2016.pof

; Features
: The two banks of Manchester outputs can now be configured independently. This permits up to 4 MCEs to share one timing configuration, while up to 4 other MCEs share a second timing configuration.
: The microprocessor's on-board EEPROM can be used to load and save configurations. A preferred configuration can be loaded "on startup", so there is no need for per-experiment defaults.

; Notes
: The firmware version is not reported by the serial interface. Subsequent versions will report the version, so if you see the "eeprom" menu but no version number then you're probably looking at v31!

=== Firmware set Rev. 30 ===

; Features
: The microprocessor code has been ported to the sdcc compiler. There are no changes in behaviour. This code should continue to work with CPLD code from version 1f.

=== Firmware set Rev. 22 ===
; Filename
: sync_box_v22_26sep2014.hex
: no change to cpld code

; Features
: Sync Box default values are set for ACT values: fr=38, num_rows=33, row_len=50

=== Firmware set Rev. 21 ===
; Filename
: sync_box_v21_02sep2014.pof
: no change to microcontroller code or *.hex file

; Features
: DV_FTS and DV_POL are now duplicate copies of DV_SPARE1 and DV_SPARE2, respectively. See [http://e-mode.phas.ubc.ca/mcewiki/index.php/Sync_Box_AC-in_Rack_Mount_io IO for rackmount AC-in Sync Box]

=== Firmware set Rev. 20 ===
; Filename
: sync_box_v20_22aug2013.hex

; Features
: hard-coded Spider values of fr=120, num_rows=33, row_len=53 (which translates to row_len=106 on mce front)
: firmware revision on rs232 interface now shows 20
=== Firmware set Rev. 1f ===
; Filename
: sync_box_v1f_25feb2010.pof
: sync_box_v1f_25feb2010.hex

; Features
: adds a ckd command to the rs232 interface to adjust the frequency of DV_Spare1 and DV_Spare2 by setting a 50MHz divisor through the command.
: when you turn on the sync box, the firmware revision 1f appears on the rs232 terminal

=== Firmware set Rev. 1e (6e?) ===
; Filename
: sync_box_v6e_11aug2008.pof
: sync_box_v1c_17nov2006.hex

; Features
: added a 50MHz clock on SMA output of the Sync box

; Note
: Since the microcontroller code is still 1c and that is what is reported in rs232 terminal, there is no way to identify this set from a 1c set.

=== Firmware set Rev. 1c ===
; Filename
: sync_box_v6c_19oct2006.pof
: sync_box_v1c_17nov2006.hex

; Features
original firmware

== Source code ==
The sync box source (both CPLD and Atmel code) is available in the <tt>sync_box</tt> project in the [[Code repositories|Multi-Channel Electronics GitHub project]]. So, something like this might work:

git clone https://github.com/multi-channel-electronics/sync_box.git

=== Building the code ===
The CPLD code needs to be rebuilt using Quartus. The Atmel code is compiled with <tt>[http://sdcc.sourceforge.net/ sdcc]</tt>, which is available in many Linux distributions. In Ubuntu:
sudo apt-get install sdcc

[[Category:Sync Box Firmware| ]]

MCE script

2021-11-17T02:17:13Z

Dvw:

{{Related|MCE Script}}
The '''MCE script''' project is a collection of array setup tools and other utilities, built on top of [[MAS]], useful for running experiments. MCE script is housed in a SVN repository at UBC. See [[Code repositories]] for details on downloading MCE script.

= Tutorials =

* [[ Basic mce_script configuration ]]
* [[ Series array setup ]]

= Tool descriptions =
* Auto-tuning system
** [[ Auto-setup (python) ]] - an integrated tool set for dealing with SQUID data.
** [[ auto_setup_squids.pro | Auto-setup (IDL) ]] - IDL-based auto-tuning code (obsolete)
** [[ experiment.cfg ]] - array and auto-setup configuration data.
** [[ mce_config_template system ]]
* Other scripts
** [[MCE Test Scripts]]
** [[MCE script utilities]]
** [[ place_sq1.pro ]] for row selection for the purposes of sq1servo
** [[ IV curves ]] - acquire and analyze TES IV curves
** [[ special_ops.py ]]
** [[ measure_quanta.py ]] - Analyzes tuning data to determine SQUID phi0.
* Scripting tools
** [[ mce_internal_ramp ]] - configure and run MCE internal command ramps
** [[Environmental variables]]

= Other resources =

* Educational tools
** [[ Media:MAS_auto-tuning_20090529.pdf ]] - Some quick graphical depictions of auto-tuning. (Not a stand-alone presentation!)
** Characterization and Locking SQUIDs with Multi-Channel Electronics [[http://www.phas.ubc.ca/%7Emce/mcedocs/software/locking_squids.pdf PDF]] (Jun. 07, 2005)

* Sample auto-tune plots:
** [http://www.phas.ubc.ca/%7Emce/mcedocs/auto_tune_results/biasing_ac_sq2fb_switching biasing ac sq2fb switching]
** [http://www.phas.ubc.ca/%7Emce/mcedocs/auto_tune_results/biasing_ac_not_switching biasing ac not switching]
[[Category:MCE Script| ]]

Main Page

2021-11-17T02:16:07Z

Dvw:

This Wiki is for users of UBC's '''Multi-Channel Electronics''' (MCE), including the '''MCE Acquisition Software''' (MAS).
__NOTOC__
== MCE Overview ==
The MCE described here borrows heavily from the designs used at [http://www.nist.gov/pml/ NIST]. Changes have been made to upgrade components, achieve higher integration, and match to the specific experimental configurations.

In basic operation, one MCE [[subrack]] controls the SQUID amplifiers and multiplexer, and reads signals from one 32×41 pixel or 16×41 pixel sub-array. The system hardware is completely modular at the sub-array level. Each sub-array is connected via woven cryogenic cables to a single MCE subrack through 3 or 5 MDM connectors. Each MCE subrack is, in turn, connected by an optical fibre to a single data-acquisition PC running Linux and data-acquisition software ([[MAS]]) developed at UBC.

Each MCE consists of hybrid analog/digital hardware and firmware developed for [https://www.altera.com/ Altera] [https://www.altera.com/products/fpga/stratix-series.html Stratix FPGAs]. A subrack has up to nine cards: including 2 or 4 [[Readout card]]s each of which reads 8 output columns through 14-bit 50MHz ADCs; 1 [[address card]] to multiplex the first-stage SQUIDs biases at around 20kHz; 1 [[clock card]] to interpret commands and to synchronize all the cards using a 25MHz clock; 2 or 3 [[bias card]]s to control the SQUID series-array feedback, the second-stage SQUID bias and feedback as well as the bolometer bias and heater. During [[auto_setup|detector setup]], the MCE is used to calculate the optimal operating points for the bolometers and the SQUID amplifiers by measuring their characteristics using open and closed feedback loops. During observation, MCE uses a running PID-calculation to determine the first-stage SQUID feedback necessary to keep the whole amplification chain in a linear regime.

In conjunction with the MCEs, a [[Sync Box]] supplies data-valid pulses with serial numbers to all MCE subracks and to the telescope pointing system. This allows synchronization between the data acquisition, the pointing system, and the telescope housekeeping.

== Documentation ==

* [[ MCE hardware | MCE Hardware ]] - information on MCE hardware (and accessories)
* [[ MCE firmware | MCE Firmware ]] - firmware versions, features, and tools (including sync box and PCI card firmware)
* [[ MAS ]] - the MCE Acquisition Software - kernel driver and low-level tools
* [[ MCE script ]] - SQUID array setup programs
* [[ MCE usage ]] - practical usage and reference documents
* [[Publications]] - technical publications relating to the Multi-Channel Electronics

== Source code ==

All MCE code is available on GitHub:
:https://github.com/multi-channel-electronics

== Contact Info ==

The '''<code>[[mce-announce]]</code>''' e-mail list is used to communicate important firmware and software updates to the MCE user community. See the [[mce-announce]] page for details on how to subscribe.

MCE Lab: 604-822-2585
Halpern's Lab: 604-822-6709

Hardware: mandana at phas.ubc.ca, halpern at phas.ubc.ca
Firmware: mandana at phas.ubc.ca
Software: mhasselfield at flatironinstitute.org, dvw at phas.ubc.ca

Department of Physics & Astronomy
University of British Columbia
6224 Agricultural Rd, Room 204
Vancouver, BC V6T 1Z1
Canada

MAS svn repository

2021-11-17T02:14:51Z

Dvw: Redirected page to Code repositories

#REDIRECT [[Code repositories]]

Code repositories

2021-11-17T02:14:24Z

Dvw: Dvw moved page UBC SVN repository to Code repositories

The MCE software is available on GitHub in several repositories:

:https://github.com/multi-channel-electronics

The most common things you'll need are:
* the [[MAS]] code here: https://github.com/multi-channel-electronics/mas
** MAS uses the GNU autotools for a bit of configuration work.
* the [[MCE script]]s here: https://github.com/multi-channel-electronics/mce_script
See [[MAS OS setup]] for information on how to build and install these packages.

Also available:
* [[Sync box firmware]]: https://github.com/multi-channel-electronics/sync_box
** both CPLD and Atmel code are available
* [[PCI card firmware]]: https://github.com/multi-channel-electronics/arc_pci

[[Category:MAS]]
[[Category:MCE Script]]
[[Category:Sync Box Firmware]]

UBC SVN repository

2021-11-17T02:14:24Z

Dvw: Dvw moved page UBC SVN repository to Code repositories

#REDIRECT [[Code repositories]]

Code repositories

2021-11-17T02:14:11Z

Dvw:

The MCE software is available on GitHub in several repositories:

:https://github.com/multi-channel-electronics

The most common things you'll need are:
* the [[MAS]] code here: https://github.com/multi-channel-electronics/mas
** MAS uses the GNU autotools for a bit of configuration work.
* the [[MCE script]]s here: https://github.com/multi-channel-electronics/mce_script
See [[MAS OS setup]] for information on how to build and install these packages.

Also available:
* [[Sync box firmware]]: https://github.com/multi-channel-electronics/sync_box
** both CPLD and Atmel code are available
* [[PCI card firmware]]: https://github.com/multi-channel-electronics/arc_pci

[[Category:MAS]]
[[Category:MCE Script]]
[[Category:Sync Box Firmware]]

MAS OS setup

2019-09-26T22:05:40Z

Dvw:

{{Related|MAS}}
= Supported operating systems =

We use Ubuntu.

* We only support LTS releases. Currently, we support:
** 18.04
** 16.04
** 14.04

= Ubuntu 16.04 and later =

The removal of the bigphysarea requirement from the kernel module means it's much easier to install MAS now. Because you don't need to rebuild your kernel, it should be possible to simply checkout the MAS trunk. Start by skipping down to the [[#Download (checkout) MAS and mce_script|Download (checkout) MAS and mce_script]] step, and then continue with installing MAS and MCE script.

= Ubuntu 14.04 =

The automated installation package is tested, but as Ubuntu tweaks its packages the install script may fall slightly out of sync. It's worth a shot though.

After installing Ubuntu 14.04, get the install tarball:

wget http://e-mode.phas.ubc.ca/mce/pc_install/install_tools/mce_install_ubuntu_14.04.tar.gz
tar -xzf ubuntu_14.04_install.tar.gz
cd install/

== Install additional ubuntu packages ==

From that install folder, run
bash install.bash

It can't hurt to run this a couple of times to make sure all dependencies are resolved.

== Bigphysarea kernel patch ==

You can either download the compiled kernels or build them from scratch.

From install folder, run EITHER
bash kernel_download.bash
or
bash kernel_build.bash

Compiled kernels currently exist for the x64 architecture.

Then when one or the other of those has succeeded, install them:
bash kernel_install.bash

You can now proceed to the section below titled "[[#Configure_the_system_for_MCE_users|Configure the system for MCE users]]".

= Ubuntu 12.04 and earlier =

See [[MAS OS setup on obsolete systems]]

= Configure the system for MCE users =

== Setup environment for MCE user ==

We tend to assume that a single user and group will have dominion over the MCE software, scripts, and data. We often assume that this user will be called "mce". But it doesn't need to be. Even if multiple users are running things through their own accounts it is likely useful to have a single group that can be used to manage access to the data.

Anyway, to set up a reasonable MCE user, see [[MAS user setup]].

All users using the MCE will need to define some environment variables to use the scripts. See the above link for lines to add to your '''.bashrc'''.

== System umask ==

You may want to set the system umask to make for a system where it's easier to share
Set the umask for all users to give write access for their group by default.

Edit /etc/profile and change the "umask 022" line to
umask 002

Edit /etc/login.defs and find the line that start "# UMASK" and change it to
UMASK 002

== Folders ==

mce_script assumes that /data/cryo/ exists and can be manipulated. To create something reasonable:

MCE_USER=mce
MCE_GROUP=mce
sudo mkdir /data
sudo chown $MCE_USER:$MCE_GROUP /data
sudo chmod g+ws /data
mkdir /data/cryo/

= Download (checkout) MAS and mce_script =

See [[MAS svn repository]].

= Compile and install MAS =

The following procedure outlines the default situation, where MAS is being installed on a computer containing only one fibre card. For information on running MAS with multiple fibre cards in one computer, see [[Multicard MAS]].

== Makefile.svn ==

MAS uses autoconf for some basic configuration stuff. After checking out MAS from the SVN repository the ''first'' time, you need to bootstrap the autoconf process. To simplify this, the Makefile.svn file will automate the process. From the MAS source folder run

make -f Makefile.svn

If successful, this will create the "./configure" script. This step is only required on fresh check-outs of the repository. If you already have a ./configure script, even if it's out of date, you can skip this step. (After having been bootstrapped the
first time, the build system is smart enough to know when it needs to regenerate itself.)

Note: this procedure requires autoconf. If it's not installed, install it with:

sudo apt-get install autoconf

== ./configure ==

Once the configure script exists, run it to generate the build system (ie. the Makefiles). The biggest thing you usually need to tell it is what the basic username and group should be for mce data. Also, there are a few options for the driver and some stupid python stuff.

From the MAS source folder, run

./configure

Some useful options:
--disable-driver suppress driver compilation/installation
--disable-bigphysarea compile driver without bigphysarea support
--disable-config2 suppress mas.cfg and mce.cfg generation/installation
--enable-multicard build a version of MAS which can drive multiple fibre cards. (See [[Multicard MAS]] for specifics.)
--with-user=USER set default MCE user
--with-group=GROUP set default MCE group
--with-kernel-dir=DIR set kernel build directory (typically automatically determined)

Run

./configure --help

for a full list. When running, configure will complain if it cannot find something, and even suggest what package you need to install.

== mce.cfg ==

After running configure, but before running make, you must specify a template file (mce.cin) which will be used to generate the hardware configuration file (mce.cfg). Full details of this procedure are given in the [[mce.cfg]] page, but briefly:

# copy an appropriate template from <code>config2/templates</code> to <code>config2/mce.cin</code>
# edit the <code>config2/mce.cin</code> file to describe your MCE.

The configuration file will be installed automatically when <code>make install</code> is run below. This entire step can be skipped if you passed --disable-config2 to configure above, but note that MAS will not function without mce.cfg and mas.cfg installed.

== make ==

This often works.

make clean; make

=== Troubleshooting ===
Sometimes after doing an SVN update <code>make</code> doesn't work but instead returns the cryptic message:

*** No rule to make target `defaults/masdefault.m4', needed by `aclocal.m4'.

In this case, it's necessary to force a rebuild of the build system manually by running

make -f Makefile.svn
./configure

See the [[#Makefile.svn|Makefile.svn section]] above for further details.

== Test the driver ==

It is wise to test that the driver does not kill your machine before installing it to load on boot. After compiling do:

cd driver
sudo ./reload

This will load the driver, which should then try to talk to the SDSU PCI card if it is installed. Note that since "reload" first unloads the driver if it is present, and then loads the driver from the current folder, it may report an "ERROR" message if the first step fails, even though the driver is successfully loaded. The definitive way to check that the driver is loaded is
cat [[/proc/mce_dsp]]

If this file does not exist, the driver isn't loaded. If the cat prints out a bunch of low-level driver information, you're in good shape.

== sudo make install ==

If you're satisfied that the driver works, install the whole thing. Go back up to the MAS base folder and run

sudo make install

This will do the following:

*install the kernel driver, <code>driver/mce_dsp.ko</code>, into <code>/lib/modules/$(uname -r)/kernel/drivers/misc/</code>, and re-scan the module dependencies.
*install the MAS binaries from <code>applications/</code> and the scripts from <code>script/</code> into <code>/usr/mce/bin</code>
*install the MAS udev ruleset <code>scripts/91-mas.rules</code> into <code>/etc/udev/rules.d/</code>. These udev rules will ensure that the mce_dsp module is loaded and the MAS device nodes are created at boot time. You can get udev to run these rules immediately, which will result in /dev being populated with the mce devices, by running:

sudo udevadm trigger

:or, else, you can make the nodes yourself by running mas_mknodes.
*install the mas logging daemon script <code>/etc/init.d/mas</code> init script. The driver can then be started/restarted as desired through this script:

/etc/init.d/mas restart

:The driver will automatically be set to load on boot. To disable this, remove the symbolic link "/etc/rc2.d/S99mas".
*install the hardware configuration file, <code>config2/mce.cfg</code>, and the MAS configuration file, <code>config2/mas.cfg</code> to <code>/etc/mce/</code>, assuming there aren't versions already there.

= Install mce_script =

Users have the option of running the MCE scripts from an svn working copy, or of running the MCE scripts from an "installed" copy. Talk to your MAS technician about which option is best for you.

== Running from an svn working copy ==

Checkout the tree directly into /usr/mce:

cd /usr/mce
svn checkout svn://e-mode.phas.ubc.ca/mce_script/trunk mce_script

== Running from an installed copy ==

Checkout the tree into your code folder; then make and install:

cd code
svn checkout svn://e-mode.phas.ubc.ca/mce_script/trunk mce_script
make
sudo make install

== .bashrc ==

Add a few lines to .bashrc to update your PATH, PYTHONPATH, and to define the MAS_* variables. The new way, using [[mas_var]], is:
eval `/usr/mce/bin/mas_var -e -s`

The old way, which will probably still work for a while:

export MAS_ROOT=/usr/mce/mce_script/
source $MAS_ROOT/template/mas_env.bash
export IDL_PATH="<IDL_DEFAULT>:$MAS_IDL/mas"

== Configuration data ==

Example configuration files (especially [[experiment.cfg]]) are kept in mce_script/template. MAS, by default, expects user configuration data to be in /usr/mce/config. Users should copy the template/ files to /usr/mce/config/, and then make configuration adjustments. After install mce_script, you can copy the template config from it with:

sudo cp -r /usr/mce/mce_script/template /usr/mce/config
sudo chown -R mce /usr/mce/config

[[Category:MAS]]

MAS OS setup on obsolete systems

2019-09-26T20:09:34Z

Dvw:

{{obsolete|MAS OS setup}}
This page describes the parts of the OS setup procedure for MAS specific to Ubuntu 6.06, 7.10, 8.04, 8.10, 9.04, 9.10, 10.04, and 12.04. For the general OS setup procedure, see: [[MAS OS setup]].

Users are strongly encouraged to run MAS under Ubuntu 14.04 LTS or 16.04 LTS, when possible. See the [[MAS OS setup]] for full instructions.

= Ubuntu 12.04 =
Follow instructions for Ubuntu 14.04, but use install tools package:

wget http://e-mode.phas.ubc.ca/mce/pc_install/install_tools/mce_install_ubuntu_12.04.tar.gz

= Ubuntu 10.04 =

The automated installation package is tested, but as Ubuntu tweaks its packages the install script may fall slightly out of sync. It's worth a shot though.

After installing Ubuntu 10.04 (desktop), get the install tarball:

cd ~
wget http://e-mode.phas.ubc.ca/mce/pc_install/install_tools/ubuntu_10.04_install.tar.gz
tar -xzf ubuntu_10.04_install.tar.gz
cd install/

== Install additional ubuntu packages ==

From that install folder, run
bash install.bash

(Under 10.04, the vanilla kernel 2.6.38.8 is also supported. To use it, copy ./alternatives/sources.2.6.38.8.bash to ./sources.bash before running install.bash and kernel_build.bash .)

== Bigphysarea kernel patch ==

You can either download the compiled kernels or build them from scratch.

From install folder, run EITHER
bash kernel_download.bash
or
bash kernel_build.bash

Then when one or the other of those has succeeded, install them:
bash kernel_install.bash

You can now proceed to the section below titled "[[#Configure_the_system_for_MCE_users|Configure the system for MCE users]]".

= Ubuntu 9.10 =

Starting with Ubuntu 9.10, some effort has been made to automate the installation. After installing Ubuntu 9.10 (desktop), get the install tarball:

cd ~
wget http://e-mode.phas.ubc.ca/mce/pc_install/install_tools/ubuntu_09.10_install.tar.gz
tar -xzf install.tar.gz
cd install/

== Install additional ubuntu packages ==

From that install folder, run
bash install.bash

== Bigphysarea kernel patch ==

You can either download the compiled kernels or build them from scratch.

From install folder, run EITHER
bash kernel_download.bash
or
bash kernel_build.bash

Then when one or the other of those has succeeded, install them:
bash kernel_install.bash

You can now proceed to the section titled "[[MAS OS setup#Configure_the_system_for_MCE_users|Configure the system for MCE users]]".

= Ubuntu 9.04 and earlier =
== Disable CDROM seeking ==

The package manager knows that you have the Ubuntu disk and will say things like
Media change: please insert the disc labeled
'Ubuntu-Server 6.06.1 _Dapper Drake_ - Release i386 (20060807.1)'

To disable this (and download packages from the internet instead), open /etc/apt/sources.list
sudo pico /etc/apt/sources.list
and remove (comment) the line
deb cdrom:[Ubuntu-Server 6.06.1 _Dapper Drake_ - Release i386 (20060807.1)]/ dapper main restricted

== Install required packages ==

sudo apt-get update
sudo apt-get install build-essential subversion emacs21 libreadline5-dev

== Enable universe repository and install GGV ==

Uncomment the line in /etc/apt/sources.list so it says
deb http://us.archive.ubuntu.com/ubuntu/ dapper universe

Then run
sudo apt-get update
sudo apt-get install gnome-gv

gnome-gv doesn't exist on 7.10, you'll have to settle for
sudo apt-get install gv

== Install packages that you shouldn't even want to install (soon to be optional) ==
sudo apt-get install tcsh

== Install desktop manager (optional) ==
sudo apt-get install ubuntu-desktop gdm

== Install python stuff ==

The 'pyth' branch MAS has experimental support for python using wx and matplotlib:
sudo apt-get install python-dev python-wxglade python-matplotlib python-numarray-ext swig

=== numpy and scipy ===

For loading / plotting MCE data in python using [[Python data and runfile modules | mce_data.py]], you will want numpy / scipy. The Ubuntu packages can be a bit out of date, but should be enough for basic data manipulation and plotting. Just run:
sudo apt-get install python-numpy python-scipy

For Ubuntu 6.06, numpy and scipy can be obtained following instructions from this page:
http://debs.astraw.com/dapper/

There are some very useful numpy features that are not available on older Ubuntu default packages. To access such features it is not too hard to install more recent versions of numpy (and scipy) from sourceforge:

1. Remove Ubuntu numpy and scipy packages; install dependencies for the source.
sudo apt-get remove python-numpy python-scipy
sudo apt-get install libblas-dev lapack-dev
2. Get source tarballs from links below... unzip the contents.
http://sourceforge.net/projects/numpy
http://sourceforge.net/projects/scipy
3. Compile the source packages. That means that in each folder you have to do:
./setup.py config
./setup.py build
sudo ./setup.py install

The config step complains a fair bit, but it's really obvious when there is an error rather than a warning. The scipy package takes a long time to compile.

== Install libconfig ==

MAS uses [[libconfig]] to manage its configuration files. The webpage is here: http://www.hyperrealm.com/libconfig/. To install libconfig run the commands below. The active version of libconfig changes a lot; go to the hyperrealm link to see what the latest version is; it's probably compatible.

wget http://www.hyperrealm.com/libconfig/libconfig-1.3.2.tar.gz
tar -xzf libconfig-1.3.2.tar.gz
cd libconfig-1.3.2
./configure
make
sudo make install

To make the system aware of this library, add "/usr/local/lib" to /etc/ld.so.conf and run "sudo ldconfig". i.e.
echo /usr/local/lib | sudo tee -a /etc/ld.so.conf
sudo ldconfig

On newer systems (Ubuntu 7.10) you can do this instead:
echo /usr/local/include | sudo tee /etc/ld.so.conf.d/libconfig.conf
sudo ldconfig

== Download and install MAS kernel patch ==

=== Download ===

If you're not compiling the kernel from scratch, download the binary packages from UBC:
wget http://e-mode.phas.ubc.ca/~mhasse/mce/kernel-headers-2.6.15.7-bigphys_10.00.Custom_i386.deb
wget http://e-mode.phas.ubc.ca/~mhasse/mce/kernel-image-2.6.15.7-bigphys_10.00.Custom_i386.deb
wget http://e-mode.phas.ubc.ca/~mhasse/mce/extras.patch

For '''Ubuntu 7.10''', get these instead:
wget http://e-mode.phas.ubc.ca/~mhasse/mce/linux-headers-2.6.22.9-bigphys_10.00.Custom_i386.deb
wget http://e-mode.phas.ubc.ca/~mhasse/mce/linux-image-2.6.22.9-bigphys_10.00.Custom_i386.deb

On '''Ubuntu 7.10''' machines '''without PAE''' hardware (i.e. a maximum of 4G of system memory) use:
wget http://e-mode.phas.ubc.ca/~mhasse/mce/linux-headers-2.6.22.14-bigphys_2.6.22.14-bigphys-10.00.Custom_i386.deb
wget http://e-mode.phas.ubc.ca/~mhasse/mce/linux-image-2.6.22.14-bigphys_2.6.22.14-bigphys-10.00.Custom_i386.deb

=== Install ===

Then, install the packages using dpkg:
sudo dpkg -i kernel-headers-2.6.15.7-bigphys_10.00.Custom_i386.deb
sudo dpkg -i kernel-image-2.6.15.7-bigphys_10.00.Custom_i386.deb
The "image" file might complain about symbolic links, no big deal.

On '''Ubuntu 7.10''', instead install these:
sudo dpkg -i linux-headers-2.6.22.9-bigphys_10.00.Custom_i386.deb
sudo dpkg -i linux-image-2.6.22.9-bigphys_10.00.Custom_i386.deb

Why are these ones called "linux" instead of "kernel"? I think it's because I got them from Ubuntu repositories instead of kernel.org.

On '''Ubuntu 7.10''' machines '''without PAE''' install these:
sudo dpkg -i linux-headers-2.6.22.14-bigphys_2.6.22.14-bigphys-10.00.Custom_i386.deb
sudo dpkg -i linux-image-2.6.22.14-bigphys_2.6.22.14-bigphys-10.00.Custom_i386.deb

The '''Ubuntu 8.04''' kernel has a sound-card driver that lays claim to the Motorola DSP on the PCI card. We have to blacklist this module to prevent it from trying to configure the card as a sound card. Add the following to the bottom of /etc/modprobe.d/blacklist :
# Conflicts with Astro-cam PCI card!!
blacklist snd_asihpi

=== Patch ===

This makes it possible to compile against the kernel package as though it had been locally compiled originally.
cd /usr/src/kernel-headers-2.6.15.7-bigphys/
sudo patch -p1 < ~/extras.patch

This step is not necessary for Ubuntu 7.10. It may be necessary to link the kernel headers into /lib/modules:
sudo ln -s /usr/src/linux-headers-2.6.22.9-bigphys/ /lib/modules/2.6.22.9-bigphys/build

=== Boot menu ===

We need to add the kernel option that causes bigphys to allocate boot memory for our driver. In older versions of MAS (especially ACT's stable release) we also need to disable "acpi". It's a good idea to not run any DSP/MCE commands until all of your kernel options are in place.

Having installed the kernel "image" package, the kernel should show up in the boot loader (grub)'s kernel list.

=== Editing the kernel list ===
As root (or using sudo), edit the file /boot/grub/menu.lst .
sudo pico /boot/grub/menu.lst
Go to the list of kernels, below the line "## ## End Default Options ##", and find the new kernel entry. On Ubuntu 6.06, it should be the third block (index 2), and look like this:

title Ubuntu, kernel 2.6.15.7-bigphys
root (hd0,0)
kernel /vmlinuz-2.6.15.7-bigphys root=/dev/sda3 ro quiet splash
initrd /initrd.img-2.6.15.7-bigphys
savedefault
boot

Add the kernel options to the "kernel" line, producing either this (recent MAS):
kernel /vmlinuz-2.6.15.7-bigphys root=/dev/sda3 ro quiet splash bigphysarea=8192
or this (old MAS, esp. ACT):
kernel /vmlinuz-2.6.15.7-bigphys root=/dev/sda3 ro quiet splash bigphysarea=8192 acpi=off

Save and close the file, and reboot to test this kernel. If the kernel "works", you can edit menu.lst again and change the value of the "default" option to point to this kernel:
default 2

'''Ubuntu 7.10 and later''': the kernel packages install a bit differently so the block will likely be the first one in the list. The 'kernel' line must change from something like
kernel /boot/vmlinuz-2.6.22.9-bigphys root=UUID=1b6e7b54-894d-4571-9f0a-527fe0103975 ro quiet splash
to
kernel /boot/vmlinuz-2.6.22.9-bigphys root=UUID=1b6e7b54-894d-4571-9f0a-527fe0103975 ro quiet splash bigphysarea=8192
Note that the long hexadecimal serial numbers are system specifc and yours are probably different than these ones. Leave them as they are and just add the new kernel options. The "default" option will probably be
default 0
but it's a good idea to count these things out for yourself.

You can now proceed to the section titled "[[MAS OS setup#Configure_the_system_for_MCE_users|Configure the system for MCE users]]".

[[Category:MAS]]