MCEWiki - User contributions [en]

Clock Card firmware

2011-07-12T18:58:25Z

Bburger: /* Revision 5.0.8 */

* Recommended Firmware Revisions [http://e-mode.phas.ubc.ca/mcewiki/index.php/Compatible_Versions_(CC,RC,BC,AC) here]

* Clock Card firmware revisions may implement different data packet header formats. All of the different formats are documented [http://www.phas.ubc.ca/%7Emce/mcedocs/Software/SC2_ELE_S580_526_mce_file_format.pdf here].

== Revision 5.0.8 (Ethernet in progress) ==
* '''Filename:''' cc_v05000008_12jul2011.sof

* '''To Do:'''

* '''Features:'''
** This tag is a place holder for the final version of Clock Cards with Ethernet (CCwE). This tag currently references unfinished code in CVS. The Quartus project file in this tag is designed for the Altera Stratix I Development Board.
** Header Version 6
** Based on 5.0.7
** Compatible with MCE Jam Player -- SVN revision 16 (~/jp_25/mce_jam/trunk)

* '''Details:'''

* '''Bugs:'''
** config_app command is broken, it works in 5.0.3, but not in this version. to be investigated.

* '''FPGA Resource Usage''' (clk_card.fit.rpt):

* '''Timing Analyzer Summary''' (clk_card.tan.rpt):

== Revision 5.0.7 ==
* '''Filename:''' cc_v05000007_14may2010.sof

* '''To Do:'''

* '''Features:'''
** Header Version 6
** Based on 5.0.6
** Compatible with MCE Jam Player -- SVN revision 16 (~/jp_25/mce_jam/trunk)
** Simulation compatible with firmware v5.0.0 for the other cards.
** Fixed a bug that caused a Clock Card with version 5.x.x firmware installed to return stale data for cards that had version 4.x.x. firmware installed on them.
** Fixed a bug that caused a Clock Card to return stale data if a card was not present, or not configured. Now the Clock Card returns 0x00000000.

* '''Details:'''

* '''Bugs:'''
** config_app command is broken, it works in 5.0.3, but not in this version. to be investigated.

* '''FPGA Resource Usage''' (clk_card.fit.rpt):
; Total logic elements ; 18,745 / 32,470 ( 58 % ) ;
; Total pins ; 243 / 598 ( 41 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 957,952 / 3,317,184 ( 29 % ) ;
; DSP block 9-bit elements ; 10 / 96 ( 10 % ) ;
; Total PLLs ; 2 / 6 ( 33 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;

* '''Timing Analyzer Summary''' (clk_card.tan.rpt):
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk1' ; 0.279 ns ;
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk0' ; 0.437 ns ;
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk2' ; 3.224 ns ;

== Revision 5.0.6 (buggy) ==
* '''Filename:''' cc_v05000006_21apr2010.sof

* '''To Do:'''

* '''Features:'''
** Header Version 6
** Based on 5.0.5
** Fixed a bug that prevented the Clock Card from loading firmware from its Factory Configuration Device when sw1:p1 is set to open (to enable remote configuration).
** This version of firmware works in conjunction with modified Jam Player code that was recently committed to SVN tag: '''~/jp_25/mce_jam/trunk : revision 16.'''

* '''Details:'''
** To learn how to use remote configuration: [[Remote Firmware Update]].
** For .jam file conversions, see: [[MCE Programming File Conversions]].
** Removed crc_error functionality for now. It will get added back in when it is working. It was found to conflict with the Remote Configuration functionality by preventing the Clock Card from configuring from its Factory Configuration Device.

* '''Bugs:'''
** Has a bug that causes the Clock Card with version 5.x.x firmware installed to return stale data for cards that have version 4.x.x. firmware installed on them.
** Has a bug that causes the Clock Card to return stale data if a card is not present, or not configured.

* '''FPGA Resource Usage''' (clk_card.fit.rpt):
; Total logic elements ; 18,652 / 32,470 ( 57 % ) ;
; Total pins ; 243 / 598 ( 41 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 957,952 / 3,317,184 ( 29 % ) ;
; DSP block 9-bit elements ; 10 / 96 ( 10 % ) ;
; Total PLLs ; 2 / 6 ( 33 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;

* '''Timing Analyzer Summary''' (clk_card.tan.rpt):
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk0' ; 0.590 ns
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk1' ; 1.683 ns
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk2' ; 3.277 ns

== Revision 5.0.5 (buggy) ==
* '''Filename:''' cc_v05000005_05mar2010.sof

* '''To Do:'''

* '''Features:'''
** Header Version 6
** Based on 5.0.4
** Implemented unpacking logic for TMS and TDI signals, and inferring logic for TCK. This is the solution to the JTAG packing problem.
** This version of firmware works in conjunction with modified Jam Player code that was recently committed to SVN tag: '''~/jp_25/mce_jam/trunk : revision 8.'''

* '''Details:'''
** Added the following commands: TMS_TDI, TDO, TDO_SAMPLE_DLY, TCK_HALF_PERIOD
** This firmware solves the TMS and TDI packing problem such that a "wb cc tms_tdi" command contains the following:
*** Word 0: total number of valid bits contained in words 1-n
*** Word 1-n: (tms,tdi) pairs starting from word 1 (bits 1,0), word 1 (bits 3,2), etc.
** The TDO packing is done differently: the tdo bits are captured by a shift register, and shifted from LSB to MSB, up to a maximum of 16 TDO bits per 32-bit fibre word.

* '''Bugs:'''
** Does not configure from its Factory Configuration Device upon power-up
** (non-critical) when a card does not return a valid reply, the clock card does not send an error reply back to the PC. Instead, it fills the data with whatever it had in its buffer from previous command and sends it to mas.

* '''FPGA Resource Usage''' (clk_card.fit.rpt):
; Total logic elements ; 18,699 / 32,470 ( 58 % ) ;
; Total pins ; 261 / 598 ( 44 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 957,952 / 3,317,184 ( 29 % ) ;
; DSP block 9-bit elements ; 10 / 96 ( 10 % ) ;
; Total PLLs ; 2 / 6 ( 33 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;

* '''Timing Analyzer Summary''' (clk_card.tan.rpt):
** Note that the clock slack on clk0 has diminished significantly over the past few revisions. However, on this version, it increased again to a reasonable level.
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk1' ; 1.164 ns ;
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk0' ; 1.276 ns ;
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk2' ; 3.299 ns ;

== Revision 5.0.4 (buggy) ==
* '''Filename:''' cc_v05000004_26feb2010.sof

* '''To Do:'''

* '''Features:'''
** Header Version 6
** Based on 5.0.3
** Added JTAG control registers that emulated a parallel port to allow Jam Player software to write to the MCE from a MAS PC and configure devices via JTAG.
*** JTAG0 -- Output data
*** JTAG1 -- Input data
*** JTAG2 -- JTAG Chain control

* '''Details:'''
** This version of firmware is compatible with ported JAM Player software that has been temporarily committed to CVS under \\mce\cards\clk_card\config_fpga\source\unix_code.

* '''Bugs:'''
** Does not configure from its Factory Configuration Device upon power-up
** (non-critical) when a card does not return a valid reply, the clock card does not send an error reply back to the PC. Instead, it fills the data with whatever it had in its buffer from previous command and sends it to mas.

* '''FPGA Resource Usage''' (clk_card.fit.rpt):
; Total logic elements ; 17,827 / 32,470 ( 55 % ) ;
; Total pins ; 261 / 598 ( 44 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 949,760 / 3,317,184 ( 29 % ) ;
; DSP block 9-bit elements ; 10 / 96 ( 10 % ) ;
; Total PLLs ; 2 / 6 ( 33 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;
; M512s ; 66 / 295 ( 22 % )
; M4Ks ; 171 / 171 ( 100 % )
; M-RAMs ; 3 / 4 ( 75 % )

* '''Timing Analyzer Summary''' (clk_card.tan.rpt):
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk0' ; 0.771 ns ;
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk1' ; 1.576 ns ;
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk2' ; 2.859 ns ;

== Revision 5.0.3 (tested) ==
* '''Filename:''' cc_v05000003_13jan2010.sof

* '''To Do:'''
** ---

* '''Features:'''
** Header Version 6
** Based on 5.0.2
** Added a Stratix I generic parameter for synthesis-time library selection.
** Made a top-level modification that makes the interface compatible with the LM95235, while maintaining backwards compatibility.
** Added the following commands for applying maximum-length sequences to MCE outputs: AWG_SEQUENCE_LEN, AWG_DATA, AWG_ADDR. See [[ Maximum Length Sequence Commands | Arbitrary Waveform Generator ]].

* '''Details:'''
** [[ Arbitrary Waveform Generator ]] (i.e. Maximum Length Sequences for Complex Impedance Measurements)

* '''Bugs:'''
** (non-critical) when a card does not return a valid reply, the clock card does not send an error reply back to the PC. Instead, it fills the data with whatever it had in its buffer from previous command and sends it to mas.

* '''FPGA Resource Usage''' (clk_card.fit.rpt):
; Total logic elements ; 18,095 / 32,470 ( 56 % ) ;
; Total pins ; 255 / 598 ( 43 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 949,760 / 3,317,184 ( 29 % ) ;
; DSP block 9-bit elements ; 10 / 96 ( 10 % ) ;
; Total PLLs ; 2 / 6 ( 33 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;

* '''Timing Analyzer Summary''' (clk_card.tan.rpt):
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk0' ; 1.547 ns ;
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk2' ; 1.985 ns ;
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk1' ; 2.067 ns ;

== Revision 5.0.2 ==
* '''Filename:''' cc_v05000002_test00_tagged.sof

* '''To Do:'''
** ---

* '''Features:'''
** Header Version 6
** Based off of 5.0.1 and in parallel with 4.0.c (equivalent version)
** The Sync Box PLL was re-instated to the top level and routed to dv_rx. It was mistakenly removed after v4.0.9, which means that the sync box sequence number decoding has not worked since then! When collecting data while triggering off the Sync Box DV, the Clock Card would also sporadically trigger in between data frames.
** Fixed a bug in ret_dat_wbs that did not handle wb num_rows_reported and wb num_cols_reported commands correctly.

* '''Details:'''

* '''Bugs:'''
** (non-critical) when a card does not return a valid reply, the clock card does not send an error reply back to the PC. Instead, it fills the data with whatever it had in its buffer from previous command and sends it to mas.

* '''FPGA Resource Usage''' (clk_card.fit.rpt):
; Total logic elements ; 17,598 / 32,470 ( 54 % ) ;
; Total pins ; 254 / 598 ( 42 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 818,688 / 3,317,184 ( 25 % ) ;
; DSP block 9-bit elements ; 10 / 96 ( 10 % ) ;
; Total PLLs ; 2 / 6 ( 33 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;

* '''Timing Analyzer Summary''' (clk_card.tan.rpt):
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk0' ; 1.965 ns ;
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk1' ; 2.041 ns ;
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk2' ; 3.548 ns ;

== Revision 5.0.1 (buggy) ==
* '''Filename:''' cc_v05000001_12may2009.sof

* '''To Do:'''
** ---

* '''Features:'''
** Based on 5.0.0 and in parallel with 4.0.b (equivalent version)
** Header Version 6
** STOP commands are meant to work in this revision. The successful execution of STOP commands through the system depends also on the PCI card firmware, and PCI driver. Modifications have been made to these, and their version numbers have been bumped to...

* '''Details:'''
** [[ The STOP Command ]]

* '''Bugs:'''
** There may be a problem with decoding sync numbers from the sync box.

* '''FPGA Resource Usage''' (clk_card.fit.rpt):
; Total logic elements ; 18,286 / 32,470 ( 56 % ) ;
; Total pins ; 259 / 598 ( 43 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 1,537,536 / 3,317,184 ( 46 % ) ;
; DSP block 9-bit elements ; 10 / 96 ( 10 % ) ;
; Total PLLs ; 1 / 6 ( 17 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;

* '''Timing Analyzer Summary''' (clk_card.tan.rpt):
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk0' ; 1.995 ns ;
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk2' ; 3.585 ns ;
; Clock Setup: 'altera_internal_jtag~TCKUTAP' ; 5.644 ns ;

== Revision 5.0.0 (buggy) ==
* '''Filename:''' cc_v05000000_22dec2008.sof (tagged as sys_v05000000_22dec2008)

* '''To Do:'''
** ---

* '''Features:'''
** Header Version 6
** IMPORTANT: Must be used in conjunction with firmware v05000000 of all other cards!!!
** This version is based on 4.0.a. That is, it includes all of the features that were under development in 4.0.a, even though 4.0.a was not released for telescope use.
** Added the ability to read out a single column of data continuously from one Readout Card
** New commands include: readout_col_index, readout_priority, num_cols_reported
** To allow enough data bandwidth, the spare LVDS line from each card to the Clock Card is now used

* '''Details:'''

* '''Bugs:'''
** There may be a problem with decoding sync numbers from the sync box.

* '''FPGA Resource Usage''' (clk_card.fit.rpt):
; Total logic elements ; 26,607 / 41,250 ( 65 % ) ;
; Total pins ; 358 / 616 ( 58 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 406,016 / 3,423,744 ( 12 % ) ;
; DSP block 9-bit elements ; 76 / 112 ( 68 % ) ;
; Total PLLs ; 1 / 6 ( 17 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;

* '''Timing Analyzer Summary''' (clk_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.558 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.892 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.987 ns ;

== Revision 4.0.c ==
* '''Filename:''' cc_v0400000c_24aug2009.sof

* '''To Do:'''
** ---

* '''Features:'''
** Header Version 6
** Based on v4.0.b and in parallel with 5.0.2 (equivalent version)
** The Sync Box PLL was re-instated to the top level and routed to dv_rx. It was mistakenly removed after v4.0.9, which means that the sync box sequence number decoding has not worked since then! When collecting data while triggering off the Sync Box DV, the Clock Card would also sporadically trigger in between data frames.

* '''Details:'''
** clk_card.vhd: re-instantiated the manchester PLL, and routed the manch_clk to dv_rx.

* '''Bugs:'''
** None yet.

* '''FPGA Resource Usage''' (clk_card.fit.rpt):
; Total logic elements ; 14,965 / 32,470 ( 46 % ) ;
; Total pins ; 254 / 598 ( 42 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 812,544 / 3,317,184 ( 24 % ) ;
; DSP block 9-bit elements ; 10 / 96 ( 10 % ) ;
; Total PLLs ; 2 / 6 ( 33 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;

* '''Timing Analyzer Summary''' (clk_card.tan.rpt):
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk0' ; 1.646 ns ;
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk1' ; 2.167 ns ;
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk2' ; 2.919 ns ;

== Revision 4.0.b (buggy) ==
* '''Filename:''' cc_v0400000b_03jun2009.sof

* '''To Do:'''
** ---

* '''Features:'''
** Header Version 6
** Based on v4.0.a and in parallel with 5.0.1 (equivalent version, but without the dual-LVDS feature).
** STOP commands are meant to work in this revision. The successful execution of STOP commands through the system depends also on the PCI card firmware, and PCI driver. Modifications have been made to these, and their version numbers have been bumped to...
** This firmware is a hybrid version that implements a single LVDS line, but has STOP and On-The-Fly capabilities built in. The purpose of this firmware is to give SCUBA-2 these features without forcing them to upgrade the firmware on all their other cards.

* '''Details:'''
** [[VHDL changes from v4.0.a and v4.0.b]]

* '''Bugs:'''
** There may be a problem with decoding sync numbers from the sync box.

* '''FPGA Resource Usage''' (clk_card.fit.rpt):
; Total logic elements ; 15,023 / 32,470 ( 46 % ) ;
; Total pins ; 254 / 598 ( 42 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 812,544 / 3,317,184 ( 24 % ) ;
; DSP block 9-bit elements ; 10 / 96 ( 10 % ) ;
; Total PLLs ; 1 / 6 ( 17 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;

* '''Timing Analyzer Summary''' (clk_card.tan.rpt):
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk1' ; 1.328 ns ;
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk0' ; 1.442 ns ;
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk2' ; 3.383 ns ;

== Revision 4.0.a (UBC only) ==
* '''Filename:''' cc_v0400000a_16oct2008

* '''To Do:'''
** Make sure that the errno word, and the cards to report word in the data frame header agree with cards_to_report

* '''Features:'''
** Header Version 6
** Based on 4.0.9
** Added stop_dly, rcs_to_report_data, and cards_to_report commands
** Added support for commands to the MCE during data acquisition

* '''Details:'''
** '''clk_card.vhd:''' incremented the firmware version number, and added cards_to_report interface signals; added support for the stop_dly, rcs_to_report_data, and cards_to_report commands; Removed the Manchester PLL because the only way to ensure that packets are received without trouble is for the main PLL to be locked on the Manchester clock. The Manchester PLL was a failed attempted around this.
** '''clock_card_pack.vhd:''' added support for the stop_dly, rcs_to_report_data, and cards_to_report commands
** '''issue_reply.vhd:''' added support for the stop_dly, rcs_to_report_data, and cards_to_report commands
** '''cmd_translator.vhd:''' split up command registers so that it can handle WB/RB/RS commands while acquiring data based on a GO command.
** '''issue_reply_pack.vhd:''' added indexing constants.
** '''reply_queue.vhd:''' modified the logic for calculating the reply data size, in response to the addition of the rcs_to_report_data, and cards_to_report commands
** '''reply_queue_sequencer.vhd:''' modified the logic for reading the data from the reply queues; modified the logic for determining when to stop readout from a card queue to ease timing constraints. Changed to logic for multiplexing the data buses from the reply queues to combinatorial logic to ease timing constraints.
** '''reply_translator.vhd:''' added a stop_delay counter for delaying the replies to 'stop ret_dat' commands; added the QUICK_REPLY and QUICK_REPLY_PAUSE states to pause the return of replies to stop commands; added extra handling to the LD_STATUS state to avoid mixing stop replies, and replies to data or simple commands; added stop reply pause logic to DONE state
** '''ret_dat_wbs.vhd:''' added the stop_delay_o, rcs_to_report_data, and cards_to_report_o interfaces; implemented a custom register from cards_to_report and stop_delay; removed the register for ret_dat_card_addr which was a special case of cards_to_report.
** '''ret_dat_wbs_pack:''' added the constant DEFAULT_CARDS_TO_REPORT

* '''Bugs:'''
** Reading back rcs_to_report_data returns zero (fixed)
** Can't issue simple commands during data taking
** Can't read from RC4 (fixed)
** There may be a problem with decoding sync numbers from the sync box.

* '''FPGA Resource Usage''' (clk_card.fit.rpt):
; Total logic elements ; 14,542 / 32,470 ( 45 % ) ;
; Total pins ; 254 / 598 ( 42 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 812,544 / 3,317,184 ( 24 % ) ;
; DSP block 9-bit elements ; 8 / 96 ( 8 % ) ;
; Total PLLs ; 1 / 6 ( 17 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;

* '''Timing Analyzer Summary''' (clk_card.tan.rpt):
; Clock Setup: 'clk_switchover:t|_clk0' ; 1.712 ns ;
; Clock Setup: 'clk_switchover:t|_clk1' ; 2.632 ns ;
; Clock Setup: 'clk_switchover:t|_clk2' ; 3.884 ns ;

== Revision 4.0.9 ==
* '''Filename:''' cc_v04000009

* '''Features:'''
** Header Version 6
** Integrated a bug fix for the sram_ctrl block
** Integrated new all_cards block of code which was causing a synthesis warning in ModelSim
** Two new commands added: card_type, scratch.

* '''Bugs:'''
** None to report so far

* '''FPGA Resource Usage''' (clk_card.fit.rpt):
; Total logic elements ; 14,144 / 32,470 ( 44 % ) ;
; Total pins ; 254 / 598 ( 42 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 812,544 / 3,317,184 ( 24 % ) ;
; DSP block 9-bit elements ; 8 / 96 ( 8 % ) ;
; Total PLLs ; 2 / 6 ( 33 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;

* '''Timing Analyzer Summary''' (clk_card.tan.rpt):
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk1' ; 0.294 ns ;
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk0' ; 2.091 ns ;
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk2' ; 2.711 ns ;

= Firmware Links =
* [http://www.phas.ubc.ca/~mce/mcedocs/firmware/cc_fpga_programming_file_catalogue.pdf Clock Card Firmware Catalog]
* [http://www.phas.ubc.ca/~mce/mcedocs/firmware/ Firmware Downloads]

= Wiki Links =
* [http://e-mode.phas.ubc.ca/mcewiki/index.php/MCE_firmware MCE Firmware Page]
* [http://e-mode.phas.ubc.ca/mcewiki/index.php/Main_Page MCE Main Page]

Clock Card firmware

2011-07-12T18:56:24Z

Bburger: /* Revision 5.0.8 */

* Recommended Firmware Revisions [http://e-mode.phas.ubc.ca/mcewiki/index.php/Compatible_Versions_(CC,RC,BC,AC) here]

* Clock Card firmware revisions may implement different data packet header formats. All of the different formats are documented [http://www.phas.ubc.ca/%7Emce/mcedocs/Software/SC2_ELE_S580_526_mce_file_format.pdf here].

== Revision 5.0.8 ==
* '''Filename:''' cc_v05000008_12jul2011.sof

* '''To Do:'''

* '''Features:'''
** This tag is a place holder for the final version of Clock Cards with Ethernet (CCwE). This tag currently references unfinished code in CVS. The Quartus project file in this tag is designed for the Altera Stratix I Development Board.
** Header Version 6
** Based on 5.0.7
** Compatible with MCE Jam Player -- SVN revision 16 (~/jp_25/mce_jam/trunk)

* '''Details:'''

* '''Bugs:'''
** config_app command is broken, it works in 5.0.3, but not in this version. to be investigated.

* '''FPGA Resource Usage''' (clk_card.fit.rpt):

* '''Timing Analyzer Summary''' (clk_card.tan.rpt):

== Revision 5.0.7 ==
* '''Filename:''' cc_v05000007_14may2010.sof

* '''To Do:'''

* '''Features:'''
** Header Version 6
** Based on 5.0.6
** Compatible with MCE Jam Player -- SVN revision 16 (~/jp_25/mce_jam/trunk)
** Simulation compatible with firmware v5.0.0 for the other cards.
** Fixed a bug that caused a Clock Card with version 5.x.x firmware installed to return stale data for cards that had version 4.x.x. firmware installed on them.
** Fixed a bug that caused a Clock Card to return stale data if a card was not present, or not configured. Now the Clock Card returns 0x00000000.

* '''Details:'''

* '''Bugs:'''
** config_app command is broken, it works in 5.0.3, but not in this version. to be investigated.

* '''FPGA Resource Usage''' (clk_card.fit.rpt):
; Total logic elements ; 18,745 / 32,470 ( 58 % ) ;
; Total pins ; 243 / 598 ( 41 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 957,952 / 3,317,184 ( 29 % ) ;
; DSP block 9-bit elements ; 10 / 96 ( 10 % ) ;
; Total PLLs ; 2 / 6 ( 33 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;

* '''Timing Analyzer Summary''' (clk_card.tan.rpt):
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk1' ; 0.279 ns ;
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk0' ; 0.437 ns ;
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk2' ; 3.224 ns ;

== Revision 5.0.6 (buggy) ==
* '''Filename:''' cc_v05000006_21apr2010.sof

* '''To Do:'''

* '''Features:'''
** Header Version 6
** Based on 5.0.5
** Fixed a bug that prevented the Clock Card from loading firmware from its Factory Configuration Device when sw1:p1 is set to open (to enable remote configuration).
** This version of firmware works in conjunction with modified Jam Player code that was recently committed to SVN tag: '''~/jp_25/mce_jam/trunk : revision 16.'''

* '''Details:'''
** To learn how to use remote configuration: [[Remote Firmware Update]].
** For .jam file conversions, see: [[MCE Programming File Conversions]].
** Removed crc_error functionality for now. It will get added back in when it is working. It was found to conflict with the Remote Configuration functionality by preventing the Clock Card from configuring from its Factory Configuration Device.

* '''Bugs:'''
** Has a bug that causes the Clock Card with version 5.x.x firmware installed to return stale data for cards that have version 4.x.x. firmware installed on them.
** Has a bug that causes the Clock Card to return stale data if a card is not present, or not configured.

* '''FPGA Resource Usage''' (clk_card.fit.rpt):
; Total logic elements ; 18,652 / 32,470 ( 57 % ) ;
; Total pins ; 243 / 598 ( 41 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 957,952 / 3,317,184 ( 29 % ) ;
; DSP block 9-bit elements ; 10 / 96 ( 10 % ) ;
; Total PLLs ; 2 / 6 ( 33 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;

* '''Timing Analyzer Summary''' (clk_card.tan.rpt):
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk0' ; 0.590 ns
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk1' ; 1.683 ns
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk2' ; 3.277 ns

== Revision 5.0.5 (buggy) ==
* '''Filename:''' cc_v05000005_05mar2010.sof

* '''To Do:'''

* '''Features:'''
** Header Version 6
** Based on 5.0.4
** Implemented unpacking logic for TMS and TDI signals, and inferring logic for TCK. This is the solution to the JTAG packing problem.
** This version of firmware works in conjunction with modified Jam Player code that was recently committed to SVN tag: '''~/jp_25/mce_jam/trunk : revision 8.'''

* '''Details:'''
** Added the following commands: TMS_TDI, TDO, TDO_SAMPLE_DLY, TCK_HALF_PERIOD
** This firmware solves the TMS and TDI packing problem such that a "wb cc tms_tdi" command contains the following:
*** Word 0: total number of valid bits contained in words 1-n
*** Word 1-n: (tms,tdi) pairs starting from word 1 (bits 1,0), word 1 (bits 3,2), etc.
** The TDO packing is done differently: the tdo bits are captured by a shift register, and shifted from LSB to MSB, up to a maximum of 16 TDO bits per 32-bit fibre word.

* '''Bugs:'''
** Does not configure from its Factory Configuration Device upon power-up
** (non-critical) when a card does not return a valid reply, the clock card does not send an error reply back to the PC. Instead, it fills the data with whatever it had in its buffer from previous command and sends it to mas.

* '''FPGA Resource Usage''' (clk_card.fit.rpt):
; Total logic elements ; 18,699 / 32,470 ( 58 % ) ;
; Total pins ; 261 / 598 ( 44 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 957,952 / 3,317,184 ( 29 % ) ;
; DSP block 9-bit elements ; 10 / 96 ( 10 % ) ;
; Total PLLs ; 2 / 6 ( 33 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;

* '''Timing Analyzer Summary''' (clk_card.tan.rpt):
** Note that the clock slack on clk0 has diminished significantly over the past few revisions. However, on this version, it increased again to a reasonable level.
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk1' ; 1.164 ns ;
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk0' ; 1.276 ns ;
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk2' ; 3.299 ns ;

== Revision 5.0.4 (buggy) ==
* '''Filename:''' cc_v05000004_26feb2010.sof

* '''To Do:'''

* '''Features:'''
** Header Version 6
** Based on 5.0.3
** Added JTAG control registers that emulated a parallel port to allow Jam Player software to write to the MCE from a MAS PC and configure devices via JTAG.
*** JTAG0 -- Output data
*** JTAG1 -- Input data
*** JTAG2 -- JTAG Chain control

* '''Details:'''
** This version of firmware is compatible with ported JAM Player software that has been temporarily committed to CVS under \\mce\cards\clk_card\config_fpga\source\unix_code.

* '''Bugs:'''
** Does not configure from its Factory Configuration Device upon power-up
** (non-critical) when a card does not return a valid reply, the clock card does not send an error reply back to the PC. Instead, it fills the data with whatever it had in its buffer from previous command and sends it to mas.

* '''FPGA Resource Usage''' (clk_card.fit.rpt):
; Total logic elements ; 17,827 / 32,470 ( 55 % ) ;
; Total pins ; 261 / 598 ( 44 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 949,760 / 3,317,184 ( 29 % ) ;
; DSP block 9-bit elements ; 10 / 96 ( 10 % ) ;
; Total PLLs ; 2 / 6 ( 33 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;
; M512s ; 66 / 295 ( 22 % )
; M4Ks ; 171 / 171 ( 100 % )
; M-RAMs ; 3 / 4 ( 75 % )

* '''Timing Analyzer Summary''' (clk_card.tan.rpt):
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk0' ; 0.771 ns ;
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk1' ; 1.576 ns ;
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk2' ; 2.859 ns ;

== Revision 5.0.3 (tested) ==
* '''Filename:''' cc_v05000003_13jan2010.sof

* '''To Do:'''
** ---

* '''Features:'''
** Header Version 6
** Based on 5.0.2
** Added a Stratix I generic parameter for synthesis-time library selection.
** Made a top-level modification that makes the interface compatible with the LM95235, while maintaining backwards compatibility.
** Added the following commands for applying maximum-length sequences to MCE outputs: AWG_SEQUENCE_LEN, AWG_DATA, AWG_ADDR. See [[ Maximum Length Sequence Commands | Arbitrary Waveform Generator ]].

* '''Details:'''
** [[ Arbitrary Waveform Generator ]] (i.e. Maximum Length Sequences for Complex Impedance Measurements)

* '''Bugs:'''
** (non-critical) when a card does not return a valid reply, the clock card does not send an error reply back to the PC. Instead, it fills the data with whatever it had in its buffer from previous command and sends it to mas.

* '''FPGA Resource Usage''' (clk_card.fit.rpt):
; Total logic elements ; 18,095 / 32,470 ( 56 % ) ;
; Total pins ; 255 / 598 ( 43 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 949,760 / 3,317,184 ( 29 % ) ;
; DSP block 9-bit elements ; 10 / 96 ( 10 % ) ;
; Total PLLs ; 2 / 6 ( 33 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;

* '''Timing Analyzer Summary''' (clk_card.tan.rpt):
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk0' ; 1.547 ns ;
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk2' ; 1.985 ns ;
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk1' ; 2.067 ns ;

== Revision 5.0.2 ==
* '''Filename:''' cc_v05000002_test00_tagged.sof

* '''To Do:'''
** ---

* '''Features:'''
** Header Version 6
** Based off of 5.0.1 and in parallel with 4.0.c (equivalent version)
** The Sync Box PLL was re-instated to the top level and routed to dv_rx. It was mistakenly removed after v4.0.9, which means that the sync box sequence number decoding has not worked since then! When collecting data while triggering off the Sync Box DV, the Clock Card would also sporadically trigger in between data frames.
** Fixed a bug in ret_dat_wbs that did not handle wb num_rows_reported and wb num_cols_reported commands correctly.

* '''Details:'''

* '''Bugs:'''
** (non-critical) when a card does not return a valid reply, the clock card does not send an error reply back to the PC. Instead, it fills the data with whatever it had in its buffer from previous command and sends it to mas.

* '''FPGA Resource Usage''' (clk_card.fit.rpt):
; Total logic elements ; 17,598 / 32,470 ( 54 % ) ;
; Total pins ; 254 / 598 ( 42 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 818,688 / 3,317,184 ( 25 % ) ;
; DSP block 9-bit elements ; 10 / 96 ( 10 % ) ;
; Total PLLs ; 2 / 6 ( 33 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;

* '''Timing Analyzer Summary''' (clk_card.tan.rpt):
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk0' ; 1.965 ns ;
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk1' ; 2.041 ns ;
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk2' ; 3.548 ns ;

== Revision 5.0.1 (buggy) ==
* '''Filename:''' cc_v05000001_12may2009.sof

* '''To Do:'''
** ---

* '''Features:'''
** Based on 5.0.0 and in parallel with 4.0.b (equivalent version)
** Header Version 6
** STOP commands are meant to work in this revision. The successful execution of STOP commands through the system depends also on the PCI card firmware, and PCI driver. Modifications have been made to these, and their version numbers have been bumped to...

* '''Details:'''
** [[ The STOP Command ]]

* '''Bugs:'''
** There may be a problem with decoding sync numbers from the sync box.

* '''FPGA Resource Usage''' (clk_card.fit.rpt):
; Total logic elements ; 18,286 / 32,470 ( 56 % ) ;
; Total pins ; 259 / 598 ( 43 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 1,537,536 / 3,317,184 ( 46 % ) ;
; DSP block 9-bit elements ; 10 / 96 ( 10 % ) ;
; Total PLLs ; 1 / 6 ( 17 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;

* '''Timing Analyzer Summary''' (clk_card.tan.rpt):
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk0' ; 1.995 ns ;
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk2' ; 3.585 ns ;
; Clock Setup: 'altera_internal_jtag~TCKUTAP' ; 5.644 ns ;

== Revision 5.0.0 (buggy) ==
* '''Filename:''' cc_v05000000_22dec2008.sof (tagged as sys_v05000000_22dec2008)

* '''To Do:'''
** ---

* '''Features:'''
** Header Version 6
** IMPORTANT: Must be used in conjunction with firmware v05000000 of all other cards!!!
** This version is based on 4.0.a. That is, it includes all of the features that were under development in 4.0.a, even though 4.0.a was not released for telescope use.
** Added the ability to read out a single column of data continuously from one Readout Card
** New commands include: readout_col_index, readout_priority, num_cols_reported
** To allow enough data bandwidth, the spare LVDS line from each card to the Clock Card is now used

* '''Details:'''

* '''Bugs:'''
** There may be a problem with decoding sync numbers from the sync box.

* '''FPGA Resource Usage''' (clk_card.fit.rpt):
; Total logic elements ; 26,607 / 41,250 ( 65 % ) ;
; Total pins ; 358 / 616 ( 58 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 406,016 / 3,423,744 ( 12 % ) ;
; DSP block 9-bit elements ; 76 / 112 ( 68 % ) ;
; Total PLLs ; 1 / 6 ( 17 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;

* '''Timing Analyzer Summary''' (clk_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.558 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.892 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.987 ns ;

== Revision 4.0.c ==
* '''Filename:''' cc_v0400000c_24aug2009.sof

* '''To Do:'''
** ---

* '''Features:'''
** Header Version 6
** Based on v4.0.b and in parallel with 5.0.2 (equivalent version)
** The Sync Box PLL was re-instated to the top level and routed to dv_rx. It was mistakenly removed after v4.0.9, which means that the sync box sequence number decoding has not worked since then! When collecting data while triggering off the Sync Box DV, the Clock Card would also sporadically trigger in between data frames.

* '''Details:'''
** clk_card.vhd: re-instantiated the manchester PLL, and routed the manch_clk to dv_rx.

* '''Bugs:'''
** None yet.

* '''FPGA Resource Usage''' (clk_card.fit.rpt):
; Total logic elements ; 14,965 / 32,470 ( 46 % ) ;
; Total pins ; 254 / 598 ( 42 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 812,544 / 3,317,184 ( 24 % ) ;
; DSP block 9-bit elements ; 10 / 96 ( 10 % ) ;
; Total PLLs ; 2 / 6 ( 33 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;

* '''Timing Analyzer Summary''' (clk_card.tan.rpt):
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk0' ; 1.646 ns ;
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk1' ; 2.167 ns ;
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk2' ; 2.919 ns ;

== Revision 4.0.b (buggy) ==
* '''Filename:''' cc_v0400000b_03jun2009.sof

* '''To Do:'''
** ---

* '''Features:'''
** Header Version 6
** Based on v4.0.a and in parallel with 5.0.1 (equivalent version, but without the dual-LVDS feature).
** STOP commands are meant to work in this revision. The successful execution of STOP commands through the system depends also on the PCI card firmware, and PCI driver. Modifications have been made to these, and their version numbers have been bumped to...
** This firmware is a hybrid version that implements a single LVDS line, but has STOP and On-The-Fly capabilities built in. The purpose of this firmware is to give SCUBA-2 these features without forcing them to upgrade the firmware on all their other cards.

* '''Details:'''
** [[VHDL changes from v4.0.a and v4.0.b]]

* '''Bugs:'''
** There may be a problem with decoding sync numbers from the sync box.

* '''FPGA Resource Usage''' (clk_card.fit.rpt):
; Total logic elements ; 15,023 / 32,470 ( 46 % ) ;
; Total pins ; 254 / 598 ( 42 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 812,544 / 3,317,184 ( 24 % ) ;
; DSP block 9-bit elements ; 10 / 96 ( 10 % ) ;
; Total PLLs ; 1 / 6 ( 17 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;

* '''Timing Analyzer Summary''' (clk_card.tan.rpt):
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk1' ; 1.328 ns ;
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk0' ; 1.442 ns ;
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk2' ; 3.383 ns ;

== Revision 4.0.a (UBC only) ==
* '''Filename:''' cc_v0400000a_16oct2008

* '''To Do:'''
** Make sure that the errno word, and the cards to report word in the data frame header agree with cards_to_report

* '''Features:'''
** Header Version 6
** Based on 4.0.9
** Added stop_dly, rcs_to_report_data, and cards_to_report commands
** Added support for commands to the MCE during data acquisition

* '''Details:'''
** '''clk_card.vhd:''' incremented the firmware version number, and added cards_to_report interface signals; added support for the stop_dly, rcs_to_report_data, and cards_to_report commands; Removed the Manchester PLL because the only way to ensure that packets are received without trouble is for the main PLL to be locked on the Manchester clock. The Manchester PLL was a failed attempted around this.
** '''clock_card_pack.vhd:''' added support for the stop_dly, rcs_to_report_data, and cards_to_report commands
** '''issue_reply.vhd:''' added support for the stop_dly, rcs_to_report_data, and cards_to_report commands
** '''cmd_translator.vhd:''' split up command registers so that it can handle WB/RB/RS commands while acquiring data based on a GO command.
** '''issue_reply_pack.vhd:''' added indexing constants.
** '''reply_queue.vhd:''' modified the logic for calculating the reply data size, in response to the addition of the rcs_to_report_data, and cards_to_report commands
** '''reply_queue_sequencer.vhd:''' modified the logic for reading the data from the reply queues; modified the logic for determining when to stop readout from a card queue to ease timing constraints. Changed to logic for multiplexing the data buses from the reply queues to combinatorial logic to ease timing constraints.
** '''reply_translator.vhd:''' added a stop_delay counter for delaying the replies to 'stop ret_dat' commands; added the QUICK_REPLY and QUICK_REPLY_PAUSE states to pause the return of replies to stop commands; added extra handling to the LD_STATUS state to avoid mixing stop replies, and replies to data or simple commands; added stop reply pause logic to DONE state
** '''ret_dat_wbs.vhd:''' added the stop_delay_o, rcs_to_report_data, and cards_to_report_o interfaces; implemented a custom register from cards_to_report and stop_delay; removed the register for ret_dat_card_addr which was a special case of cards_to_report.
** '''ret_dat_wbs_pack:''' added the constant DEFAULT_CARDS_TO_REPORT

* '''Bugs:'''
** Reading back rcs_to_report_data returns zero (fixed)
** Can't issue simple commands during data taking
** Can't read from RC4 (fixed)
** There may be a problem with decoding sync numbers from the sync box.

* '''FPGA Resource Usage''' (clk_card.fit.rpt):
; Total logic elements ; 14,542 / 32,470 ( 45 % ) ;
; Total pins ; 254 / 598 ( 42 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 812,544 / 3,317,184 ( 24 % ) ;
; DSP block 9-bit elements ; 8 / 96 ( 8 % ) ;
; Total PLLs ; 1 / 6 ( 17 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;

* '''Timing Analyzer Summary''' (clk_card.tan.rpt):
; Clock Setup: 'clk_switchover:t|_clk0' ; 1.712 ns ;
; Clock Setup: 'clk_switchover:t|_clk1' ; 2.632 ns ;
; Clock Setup: 'clk_switchover:t|_clk2' ; 3.884 ns ;

== Revision 4.0.9 ==
* '''Filename:''' cc_v04000009

* '''Features:'''
** Header Version 6
** Integrated a bug fix for the sram_ctrl block
** Integrated new all_cards block of code which was causing a synthesis warning in ModelSim
** Two new commands added: card_type, scratch.

* '''Bugs:'''
** None to report so far

* '''FPGA Resource Usage''' (clk_card.fit.rpt):
; Total logic elements ; 14,144 / 32,470 ( 44 % ) ;
; Total pins ; 254 / 598 ( 42 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 812,544 / 3,317,184 ( 24 % ) ;
; DSP block 9-bit elements ; 8 / 96 ( 8 % ) ;
; Total PLLs ; 2 / 6 ( 33 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;

* '''Timing Analyzer Summary''' (clk_card.tan.rpt):
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk1' ; 0.294 ns ;
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk0' ; 2.091 ns ;
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk2' ; 2.711 ns ;

= Firmware Links =
* [http://www.phas.ubc.ca/~mce/mcedocs/firmware/cc_fpga_programming_file_catalogue.pdf Clock Card Firmware Catalog]
* [http://www.phas.ubc.ca/~mce/mcedocs/firmware/ Firmware Downloads]

= Wiki Links =
* [http://e-mode.phas.ubc.ca/mcewiki/index.php/MCE_firmware MCE Firmware Page]
* [http://e-mode.phas.ubc.ca/mcewiki/index.php/Main_Page MCE Main Page]

Clock Card firmware

2011-07-12T18:53:25Z

Bburger: /* Revision 5.0.8 */

* Recommended Firmware Revisions [http://e-mode.phas.ubc.ca/mcewiki/index.php/Compatible_Versions_(CC,RC,BC,AC) here]

* Clock Card firmware revisions may implement different data packet header formats. All of the different formats are documented [http://www.phas.ubc.ca/%7Emce/mcedocs/Software/SC2_ELE_S580_526_mce_file_format.pdf here].

== Revision 5.0.8 ==
* '''Filename:''' cc_v05000008_12jul2011.sof

* '''To Do:'''

* '''Features:'''
** This tag is a place holder for the final version of Clock Cards with Ethernet (CCwE). This tag currently references unfinished code in CVS.
** Header Version 6
** Based on 5.0.7
** Compatible with MCE Jam Player -- SVN revision 16 (~/jp_25/mce_jam/trunk)

* '''Details:'''

* '''Bugs:'''
** config_app command is broken, it works in 5.0.3, but not in this version. to be investigated.

* '''FPGA Resource Usage''' (clk_card.fit.rpt):

* '''Timing Analyzer Summary''' (clk_card.tan.rpt):

== Revision 5.0.7 ==
* '''Filename:''' cc_v05000007_14may2010.sof

* '''To Do:'''

* '''Features:'''
** Header Version 6
** Based on 5.0.6
** Compatible with MCE Jam Player -- SVN revision 16 (~/jp_25/mce_jam/trunk)
** Simulation compatible with firmware v5.0.0 for the other cards.
** Fixed a bug that caused a Clock Card with version 5.x.x firmware installed to return stale data for cards that had version 4.x.x. firmware installed on them.
** Fixed a bug that caused a Clock Card to return stale data if a card was not present, or not configured. Now the Clock Card returns 0x00000000.

* '''Details:'''

* '''Bugs:'''
** config_app command is broken, it works in 5.0.3, but not in this version. to be investigated.

* '''FPGA Resource Usage''' (clk_card.fit.rpt):
; Total logic elements ; 18,745 / 32,470 ( 58 % ) ;
; Total pins ; 243 / 598 ( 41 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 957,952 / 3,317,184 ( 29 % ) ;
; DSP block 9-bit elements ; 10 / 96 ( 10 % ) ;
; Total PLLs ; 2 / 6 ( 33 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;

* '''Timing Analyzer Summary''' (clk_card.tan.rpt):
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk1' ; 0.279 ns ;
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk0' ; 0.437 ns ;
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk2' ; 3.224 ns ;

== Revision 5.0.6 (buggy) ==
* '''Filename:''' cc_v05000006_21apr2010.sof

* '''To Do:'''

* '''Features:'''
** Header Version 6
** Based on 5.0.5
** Fixed a bug that prevented the Clock Card from loading firmware from its Factory Configuration Device when sw1:p1 is set to open (to enable remote configuration).
** This version of firmware works in conjunction with modified Jam Player code that was recently committed to SVN tag: '''~/jp_25/mce_jam/trunk : revision 16.'''

* '''Details:'''
** To learn how to use remote configuration: [[Remote Firmware Update]].
** For .jam file conversions, see: [[MCE Programming File Conversions]].
** Removed crc_error functionality for now. It will get added back in when it is working. It was found to conflict with the Remote Configuration functionality by preventing the Clock Card from configuring from its Factory Configuration Device.

* '''Bugs:'''
** Has a bug that causes the Clock Card with version 5.x.x firmware installed to return stale data for cards that have version 4.x.x. firmware installed on them.
** Has a bug that causes the Clock Card to return stale data if a card is not present, or not configured.

* '''FPGA Resource Usage''' (clk_card.fit.rpt):
; Total logic elements ; 18,652 / 32,470 ( 57 % ) ;
; Total pins ; 243 / 598 ( 41 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 957,952 / 3,317,184 ( 29 % ) ;
; DSP block 9-bit elements ; 10 / 96 ( 10 % ) ;
; Total PLLs ; 2 / 6 ( 33 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;

* '''Timing Analyzer Summary''' (clk_card.tan.rpt):
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk0' ; 0.590 ns
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk1' ; 1.683 ns
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk2' ; 3.277 ns

== Revision 5.0.5 (buggy) ==
* '''Filename:''' cc_v05000005_05mar2010.sof

* '''To Do:'''

* '''Features:'''
** Header Version 6
** Based on 5.0.4
** Implemented unpacking logic for TMS and TDI signals, and inferring logic for TCK. This is the solution to the JTAG packing problem.
** This version of firmware works in conjunction with modified Jam Player code that was recently committed to SVN tag: '''~/jp_25/mce_jam/trunk : revision 8.'''

* '''Details:'''
** Added the following commands: TMS_TDI, TDO, TDO_SAMPLE_DLY, TCK_HALF_PERIOD
** This firmware solves the TMS and TDI packing problem such that a "wb cc tms_tdi" command contains the following:
*** Word 0: total number of valid bits contained in words 1-n
*** Word 1-n: (tms,tdi) pairs starting from word 1 (bits 1,0), word 1 (bits 3,2), etc.
** The TDO packing is done differently: the tdo bits are captured by a shift register, and shifted from LSB to MSB, up to a maximum of 16 TDO bits per 32-bit fibre word.

* '''Bugs:'''
** Does not configure from its Factory Configuration Device upon power-up
** (non-critical) when a card does not return a valid reply, the clock card does not send an error reply back to the PC. Instead, it fills the data with whatever it had in its buffer from previous command and sends it to mas.

* '''FPGA Resource Usage''' (clk_card.fit.rpt):
; Total logic elements ; 18,699 / 32,470 ( 58 % ) ;
; Total pins ; 261 / 598 ( 44 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 957,952 / 3,317,184 ( 29 % ) ;
; DSP block 9-bit elements ; 10 / 96 ( 10 % ) ;
; Total PLLs ; 2 / 6 ( 33 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;

* '''Timing Analyzer Summary''' (clk_card.tan.rpt):
** Note that the clock slack on clk0 has diminished significantly over the past few revisions. However, on this version, it increased again to a reasonable level.
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk1' ; 1.164 ns ;
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk0' ; 1.276 ns ;
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk2' ; 3.299 ns ;

== Revision 5.0.4 (buggy) ==
* '''Filename:''' cc_v05000004_26feb2010.sof

* '''To Do:'''

* '''Features:'''
** Header Version 6
** Based on 5.0.3
** Added JTAG control registers that emulated a parallel port to allow Jam Player software to write to the MCE from a MAS PC and configure devices via JTAG.
*** JTAG0 -- Output data
*** JTAG1 -- Input data
*** JTAG2 -- JTAG Chain control

* '''Details:'''
** This version of firmware is compatible with ported JAM Player software that has been temporarily committed to CVS under \\mce\cards\clk_card\config_fpga\source\unix_code.

* '''Bugs:'''
** Does not configure from its Factory Configuration Device upon power-up
** (non-critical) when a card does not return a valid reply, the clock card does not send an error reply back to the PC. Instead, it fills the data with whatever it had in its buffer from previous command and sends it to mas.

* '''FPGA Resource Usage''' (clk_card.fit.rpt):
; Total logic elements ; 17,827 / 32,470 ( 55 % ) ;
; Total pins ; 261 / 598 ( 44 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 949,760 / 3,317,184 ( 29 % ) ;
; DSP block 9-bit elements ; 10 / 96 ( 10 % ) ;
; Total PLLs ; 2 / 6 ( 33 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;
; M512s ; 66 / 295 ( 22 % )
; M4Ks ; 171 / 171 ( 100 % )
; M-RAMs ; 3 / 4 ( 75 % )

* '''Timing Analyzer Summary''' (clk_card.tan.rpt):
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk0' ; 0.771 ns ;
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk1' ; 1.576 ns ;
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk2' ; 2.859 ns ;

== Revision 5.0.3 (tested) ==
* '''Filename:''' cc_v05000003_13jan2010.sof

* '''To Do:'''
** ---

* '''Features:'''
** Header Version 6
** Based on 5.0.2
** Added a Stratix I generic parameter for synthesis-time library selection.
** Made a top-level modification that makes the interface compatible with the LM95235, while maintaining backwards compatibility.
** Added the following commands for applying maximum-length sequences to MCE outputs: AWG_SEQUENCE_LEN, AWG_DATA, AWG_ADDR. See [[ Maximum Length Sequence Commands | Arbitrary Waveform Generator ]].

* '''Details:'''
** [[ Arbitrary Waveform Generator ]] (i.e. Maximum Length Sequences for Complex Impedance Measurements)

* '''Bugs:'''
** (non-critical) when a card does not return a valid reply, the clock card does not send an error reply back to the PC. Instead, it fills the data with whatever it had in its buffer from previous command and sends it to mas.

* '''FPGA Resource Usage''' (clk_card.fit.rpt):
; Total logic elements ; 18,095 / 32,470 ( 56 % ) ;
; Total pins ; 255 / 598 ( 43 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 949,760 / 3,317,184 ( 29 % ) ;
; DSP block 9-bit elements ; 10 / 96 ( 10 % ) ;
; Total PLLs ; 2 / 6 ( 33 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;

* '''Timing Analyzer Summary''' (clk_card.tan.rpt):
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk0' ; 1.547 ns ;
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk2' ; 1.985 ns ;
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk1' ; 2.067 ns ;

== Revision 5.0.2 ==
* '''Filename:''' cc_v05000002_test00_tagged.sof

* '''To Do:'''
** ---

* '''Features:'''
** Header Version 6
** Based off of 5.0.1 and in parallel with 4.0.c (equivalent version)
** The Sync Box PLL was re-instated to the top level and routed to dv_rx. It was mistakenly removed after v4.0.9, which means that the sync box sequence number decoding has not worked since then! When collecting data while triggering off the Sync Box DV, the Clock Card would also sporadically trigger in between data frames.
** Fixed a bug in ret_dat_wbs that did not handle wb num_rows_reported and wb num_cols_reported commands correctly.

* '''Details:'''

* '''Bugs:'''
** (non-critical) when a card does not return a valid reply, the clock card does not send an error reply back to the PC. Instead, it fills the data with whatever it had in its buffer from previous command and sends it to mas.

* '''FPGA Resource Usage''' (clk_card.fit.rpt):
; Total logic elements ; 17,598 / 32,470 ( 54 % ) ;
; Total pins ; 254 / 598 ( 42 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 818,688 / 3,317,184 ( 25 % ) ;
; DSP block 9-bit elements ; 10 / 96 ( 10 % ) ;
; Total PLLs ; 2 / 6 ( 33 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;

* '''Timing Analyzer Summary''' (clk_card.tan.rpt):
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk0' ; 1.965 ns ;
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk1' ; 2.041 ns ;
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk2' ; 3.548 ns ;

== Revision 5.0.1 (buggy) ==
* '''Filename:''' cc_v05000001_12may2009.sof

* '''To Do:'''
** ---

* '''Features:'''
** Based on 5.0.0 and in parallel with 4.0.b (equivalent version)
** Header Version 6
** STOP commands are meant to work in this revision. The successful execution of STOP commands through the system depends also on the PCI card firmware, and PCI driver. Modifications have been made to these, and their version numbers have been bumped to...

* '''Details:'''
** [[ The STOP Command ]]

* '''Bugs:'''
** There may be a problem with decoding sync numbers from the sync box.

* '''FPGA Resource Usage''' (clk_card.fit.rpt):
; Total logic elements ; 18,286 / 32,470 ( 56 % ) ;
; Total pins ; 259 / 598 ( 43 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 1,537,536 / 3,317,184 ( 46 % ) ;
; DSP block 9-bit elements ; 10 / 96 ( 10 % ) ;
; Total PLLs ; 1 / 6 ( 17 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;

* '''Timing Analyzer Summary''' (clk_card.tan.rpt):
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk0' ; 1.995 ns ;
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk2' ; 3.585 ns ;
; Clock Setup: 'altera_internal_jtag~TCKUTAP' ; 5.644 ns ;

== Revision 5.0.0 (buggy) ==
* '''Filename:''' cc_v05000000_22dec2008.sof (tagged as sys_v05000000_22dec2008)

* '''To Do:'''
** ---

* '''Features:'''
** Header Version 6
** IMPORTANT: Must be used in conjunction with firmware v05000000 of all other cards!!!
** This version is based on 4.0.a. That is, it includes all of the features that were under development in 4.0.a, even though 4.0.a was not released for telescope use.
** Added the ability to read out a single column of data continuously from one Readout Card
** New commands include: readout_col_index, readout_priority, num_cols_reported
** To allow enough data bandwidth, the spare LVDS line from each card to the Clock Card is now used

* '''Details:'''

* '''Bugs:'''
** There may be a problem with decoding sync numbers from the sync box.

* '''FPGA Resource Usage''' (clk_card.fit.rpt):
; Total logic elements ; 26,607 / 41,250 ( 65 % ) ;
; Total pins ; 358 / 616 ( 58 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 406,016 / 3,423,744 ( 12 % ) ;
; DSP block 9-bit elements ; 76 / 112 ( 68 % ) ;
; Total PLLs ; 1 / 6 ( 17 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;

* '''Timing Analyzer Summary''' (clk_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.558 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.892 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.987 ns ;

== Revision 4.0.c ==
* '''Filename:''' cc_v0400000c_24aug2009.sof

* '''To Do:'''
** ---

* '''Features:'''
** Header Version 6
** Based on v4.0.b and in parallel with 5.0.2 (equivalent version)
** The Sync Box PLL was re-instated to the top level and routed to dv_rx. It was mistakenly removed after v4.0.9, which means that the sync box sequence number decoding has not worked since then! When collecting data while triggering off the Sync Box DV, the Clock Card would also sporadically trigger in between data frames.

* '''Details:'''
** clk_card.vhd: re-instantiated the manchester PLL, and routed the manch_clk to dv_rx.

* '''Bugs:'''
** None yet.

* '''FPGA Resource Usage''' (clk_card.fit.rpt):
; Total logic elements ; 14,965 / 32,470 ( 46 % ) ;
; Total pins ; 254 / 598 ( 42 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 812,544 / 3,317,184 ( 24 % ) ;
; DSP block 9-bit elements ; 10 / 96 ( 10 % ) ;
; Total PLLs ; 2 / 6 ( 33 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;

* '''Timing Analyzer Summary''' (clk_card.tan.rpt):
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk0' ; 1.646 ns ;
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk1' ; 2.167 ns ;
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk2' ; 2.919 ns ;

== Revision 4.0.b (buggy) ==
* '''Filename:''' cc_v0400000b_03jun2009.sof

* '''To Do:'''
** ---

* '''Features:'''
** Header Version 6
** Based on v4.0.a and in parallel with 5.0.1 (equivalent version, but without the dual-LVDS feature).
** STOP commands are meant to work in this revision. The successful execution of STOP commands through the system depends also on the PCI card firmware, and PCI driver. Modifications have been made to these, and their version numbers have been bumped to...
** This firmware is a hybrid version that implements a single LVDS line, but has STOP and On-The-Fly capabilities built in. The purpose of this firmware is to give SCUBA-2 these features without forcing them to upgrade the firmware on all their other cards.

* '''Details:'''
** [[VHDL changes from v4.0.a and v4.0.b]]

* '''Bugs:'''
** There may be a problem with decoding sync numbers from the sync box.

* '''FPGA Resource Usage''' (clk_card.fit.rpt):
; Total logic elements ; 15,023 / 32,470 ( 46 % ) ;
; Total pins ; 254 / 598 ( 42 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 812,544 / 3,317,184 ( 24 % ) ;
; DSP block 9-bit elements ; 10 / 96 ( 10 % ) ;
; Total PLLs ; 1 / 6 ( 17 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;

* '''Timing Analyzer Summary''' (clk_card.tan.rpt):
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk1' ; 1.328 ns ;
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk0' ; 1.442 ns ;
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk2' ; 3.383 ns ;

== Revision 4.0.a (UBC only) ==
* '''Filename:''' cc_v0400000a_16oct2008

* '''To Do:'''
** Make sure that the errno word, and the cards to report word in the data frame header agree with cards_to_report

* '''Features:'''
** Header Version 6
** Based on 4.0.9
** Added stop_dly, rcs_to_report_data, and cards_to_report commands
** Added support for commands to the MCE during data acquisition

* '''Details:'''
** '''clk_card.vhd:''' incremented the firmware version number, and added cards_to_report interface signals; added support for the stop_dly, rcs_to_report_data, and cards_to_report commands; Removed the Manchester PLL because the only way to ensure that packets are received without trouble is for the main PLL to be locked on the Manchester clock. The Manchester PLL was a failed attempted around this.
** '''clock_card_pack.vhd:''' added support for the stop_dly, rcs_to_report_data, and cards_to_report commands
** '''issue_reply.vhd:''' added support for the stop_dly, rcs_to_report_data, and cards_to_report commands
** '''cmd_translator.vhd:''' split up command registers so that it can handle WB/RB/RS commands while acquiring data based on a GO command.
** '''issue_reply_pack.vhd:''' added indexing constants.
** '''reply_queue.vhd:''' modified the logic for calculating the reply data size, in response to the addition of the rcs_to_report_data, and cards_to_report commands
** '''reply_queue_sequencer.vhd:''' modified the logic for reading the data from the reply queues; modified the logic for determining when to stop readout from a card queue to ease timing constraints. Changed to logic for multiplexing the data buses from the reply queues to combinatorial logic to ease timing constraints.
** '''reply_translator.vhd:''' added a stop_delay counter for delaying the replies to 'stop ret_dat' commands; added the QUICK_REPLY and QUICK_REPLY_PAUSE states to pause the return of replies to stop commands; added extra handling to the LD_STATUS state to avoid mixing stop replies, and replies to data or simple commands; added stop reply pause logic to DONE state
** '''ret_dat_wbs.vhd:''' added the stop_delay_o, rcs_to_report_data, and cards_to_report_o interfaces; implemented a custom register from cards_to_report and stop_delay; removed the register for ret_dat_card_addr which was a special case of cards_to_report.
** '''ret_dat_wbs_pack:''' added the constant DEFAULT_CARDS_TO_REPORT

* '''Bugs:'''
** Reading back rcs_to_report_data returns zero (fixed)
** Can't issue simple commands during data taking
** Can't read from RC4 (fixed)
** There may be a problem with decoding sync numbers from the sync box.

* '''FPGA Resource Usage''' (clk_card.fit.rpt):
; Total logic elements ; 14,542 / 32,470 ( 45 % ) ;
; Total pins ; 254 / 598 ( 42 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 812,544 / 3,317,184 ( 24 % ) ;
; DSP block 9-bit elements ; 8 / 96 ( 8 % ) ;
; Total PLLs ; 1 / 6 ( 17 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;

* '''Timing Analyzer Summary''' (clk_card.tan.rpt):
; Clock Setup: 'clk_switchover:t|_clk0' ; 1.712 ns ;
; Clock Setup: 'clk_switchover:t|_clk1' ; 2.632 ns ;
; Clock Setup: 'clk_switchover:t|_clk2' ; 3.884 ns ;

== Revision 4.0.9 ==
* '''Filename:''' cc_v04000009

* '''Features:'''
** Header Version 6
** Integrated a bug fix for the sram_ctrl block
** Integrated new all_cards block of code which was causing a synthesis warning in ModelSim
** Two new commands added: card_type, scratch.

* '''Bugs:'''
** None to report so far

* '''FPGA Resource Usage''' (clk_card.fit.rpt):
; Total logic elements ; 14,144 / 32,470 ( 44 % ) ;
; Total pins ; 254 / 598 ( 42 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 812,544 / 3,317,184 ( 24 % ) ;
; DSP block 9-bit elements ; 8 / 96 ( 8 % ) ;
; Total PLLs ; 2 / 6 ( 33 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;

* '''Timing Analyzer Summary''' (clk_card.tan.rpt):
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk1' ; 0.294 ns ;
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk0' ; 2.091 ns ;
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk2' ; 2.711 ns ;

= Firmware Links =
* [http://www.phas.ubc.ca/~mce/mcedocs/firmware/cc_fpga_programming_file_catalogue.pdf Clock Card Firmware Catalog]
* [http://www.phas.ubc.ca/~mce/mcedocs/firmware/ Firmware Downloads]

= Wiki Links =
* [http://e-mode.phas.ubc.ca/mcewiki/index.php/MCE_firmware MCE Firmware Page]
* [http://e-mode.phas.ubc.ca/mcewiki/index.php/Main_Page MCE Main Page]

Clock Card firmware

2011-07-12T18:52:39Z

Bburger:

* Recommended Firmware Revisions [http://e-mode.phas.ubc.ca/mcewiki/index.php/Compatible_Versions_(CC,RC,BC,AC) here]

* Clock Card firmware revisions may implement different data packet header formats. All of the different formats are documented [http://www.phas.ubc.ca/%7Emce/mcedocs/Software/SC2_ELE_S580_526_mce_file_format.pdf here].

== Revision 5.0.8 ==
* '''Filename:''' cc_v05000008_12jul2011.sof

* '''To Do:'''

* '''Features:'''
** This tag is a place holder for the final version of Ethernet Clock Cards. This tag currently references unfinished code in CVS.
** Header Version 6
** Based on 5.0.7
** Compatible with MCE Jam Player -- SVN revision 16 (~/jp_25/mce_jam/trunk)

* '''Details:'''

* '''Bugs:'''
** config_app command is broken, it works in 5.0.3, but not in this version. to be investigated.

* '''FPGA Resource Usage''' (clk_card.fit.rpt):

* '''Timing Analyzer Summary''' (clk_card.tan.rpt):

== Revision 5.0.7 ==
* '''Filename:''' cc_v05000007_14may2010.sof

* '''To Do:'''

* '''Features:'''
** Header Version 6
** Based on 5.0.6
** Compatible with MCE Jam Player -- SVN revision 16 (~/jp_25/mce_jam/trunk)
** Simulation compatible with firmware v5.0.0 for the other cards.
** Fixed a bug that caused a Clock Card with version 5.x.x firmware installed to return stale data for cards that had version 4.x.x. firmware installed on them.
** Fixed a bug that caused a Clock Card to return stale data if a card was not present, or not configured. Now the Clock Card returns 0x00000000.

* '''Details:'''

* '''Bugs:'''
** config_app command is broken, it works in 5.0.3, but not in this version. to be investigated.

* '''FPGA Resource Usage''' (clk_card.fit.rpt):
; Total logic elements ; 18,745 / 32,470 ( 58 % ) ;
; Total pins ; 243 / 598 ( 41 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 957,952 / 3,317,184 ( 29 % ) ;
; DSP block 9-bit elements ; 10 / 96 ( 10 % ) ;
; Total PLLs ; 2 / 6 ( 33 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;

* '''Timing Analyzer Summary''' (clk_card.tan.rpt):
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk1' ; 0.279 ns ;
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk0' ; 0.437 ns ;
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk2' ; 3.224 ns ;

== Revision 5.0.6 (buggy) ==
* '''Filename:''' cc_v05000006_21apr2010.sof

* '''To Do:'''

* '''Features:'''
** Header Version 6
** Based on 5.0.5
** Fixed a bug that prevented the Clock Card from loading firmware from its Factory Configuration Device when sw1:p1 is set to open (to enable remote configuration).
** This version of firmware works in conjunction with modified Jam Player code that was recently committed to SVN tag: '''~/jp_25/mce_jam/trunk : revision 16.'''

* '''Details:'''
** To learn how to use remote configuration: [[Remote Firmware Update]].
** For .jam file conversions, see: [[MCE Programming File Conversions]].
** Removed crc_error functionality for now. It will get added back in when it is working. It was found to conflict with the Remote Configuration functionality by preventing the Clock Card from configuring from its Factory Configuration Device.

* '''Bugs:'''
** Has a bug that causes the Clock Card with version 5.x.x firmware installed to return stale data for cards that have version 4.x.x. firmware installed on them.
** Has a bug that causes the Clock Card to return stale data if a card is not present, or not configured.

* '''FPGA Resource Usage''' (clk_card.fit.rpt):
; Total logic elements ; 18,652 / 32,470 ( 57 % ) ;
; Total pins ; 243 / 598 ( 41 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 957,952 / 3,317,184 ( 29 % ) ;
; DSP block 9-bit elements ; 10 / 96 ( 10 % ) ;
; Total PLLs ; 2 / 6 ( 33 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;

* '''Timing Analyzer Summary''' (clk_card.tan.rpt):
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk0' ; 0.590 ns
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk1' ; 1.683 ns
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk2' ; 3.277 ns

== Revision 5.0.5 (buggy) ==
* '''Filename:''' cc_v05000005_05mar2010.sof

* '''To Do:'''

* '''Features:'''
** Header Version 6
** Based on 5.0.4
** Implemented unpacking logic for TMS and TDI signals, and inferring logic for TCK. This is the solution to the JTAG packing problem.
** This version of firmware works in conjunction with modified Jam Player code that was recently committed to SVN tag: '''~/jp_25/mce_jam/trunk : revision 8.'''

* '''Details:'''
** Added the following commands: TMS_TDI, TDO, TDO_SAMPLE_DLY, TCK_HALF_PERIOD
** This firmware solves the TMS and TDI packing problem such that a "wb cc tms_tdi" command contains the following:
*** Word 0: total number of valid bits contained in words 1-n
*** Word 1-n: (tms,tdi) pairs starting from word 1 (bits 1,0), word 1 (bits 3,2), etc.
** The TDO packing is done differently: the tdo bits are captured by a shift register, and shifted from LSB to MSB, up to a maximum of 16 TDO bits per 32-bit fibre word.

* '''Bugs:'''
** Does not configure from its Factory Configuration Device upon power-up
** (non-critical) when a card does not return a valid reply, the clock card does not send an error reply back to the PC. Instead, it fills the data with whatever it had in its buffer from previous command and sends it to mas.

* '''FPGA Resource Usage''' (clk_card.fit.rpt):
; Total logic elements ; 18,699 / 32,470 ( 58 % ) ;
; Total pins ; 261 / 598 ( 44 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 957,952 / 3,317,184 ( 29 % ) ;
; DSP block 9-bit elements ; 10 / 96 ( 10 % ) ;
; Total PLLs ; 2 / 6 ( 33 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;

* '''Timing Analyzer Summary''' (clk_card.tan.rpt):
** Note that the clock slack on clk0 has diminished significantly over the past few revisions. However, on this version, it increased again to a reasonable level.
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk1' ; 1.164 ns ;
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk0' ; 1.276 ns ;
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk2' ; 3.299 ns ;

== Revision 5.0.4 (buggy) ==
* '''Filename:''' cc_v05000004_26feb2010.sof

* '''To Do:'''

* '''Features:'''
** Header Version 6
** Based on 5.0.3
** Added JTAG control registers that emulated a parallel port to allow Jam Player software to write to the MCE from a MAS PC and configure devices via JTAG.
*** JTAG0 -- Output data
*** JTAG1 -- Input data
*** JTAG2 -- JTAG Chain control

* '''Details:'''
** This version of firmware is compatible with ported JAM Player software that has been temporarily committed to CVS under \\mce\cards\clk_card\config_fpga\source\unix_code.

* '''Bugs:'''
** Does not configure from its Factory Configuration Device upon power-up
** (non-critical) when a card does not return a valid reply, the clock card does not send an error reply back to the PC. Instead, it fills the data with whatever it had in its buffer from previous command and sends it to mas.

* '''FPGA Resource Usage''' (clk_card.fit.rpt):
; Total logic elements ; 17,827 / 32,470 ( 55 % ) ;
; Total pins ; 261 / 598 ( 44 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 949,760 / 3,317,184 ( 29 % ) ;
; DSP block 9-bit elements ; 10 / 96 ( 10 % ) ;
; Total PLLs ; 2 / 6 ( 33 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;
; M512s ; 66 / 295 ( 22 % )
; M4Ks ; 171 / 171 ( 100 % )
; M-RAMs ; 3 / 4 ( 75 % )

* '''Timing Analyzer Summary''' (clk_card.tan.rpt):
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk0' ; 0.771 ns ;
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk1' ; 1.576 ns ;
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk2' ; 2.859 ns ;

== Revision 5.0.3 (tested) ==
* '''Filename:''' cc_v05000003_13jan2010.sof

* '''To Do:'''
** ---

* '''Features:'''
** Header Version 6
** Based on 5.0.2
** Added a Stratix I generic parameter for synthesis-time library selection.
** Made a top-level modification that makes the interface compatible with the LM95235, while maintaining backwards compatibility.
** Added the following commands for applying maximum-length sequences to MCE outputs: AWG_SEQUENCE_LEN, AWG_DATA, AWG_ADDR. See [[ Maximum Length Sequence Commands | Arbitrary Waveform Generator ]].

* '''Details:'''
** [[ Arbitrary Waveform Generator ]] (i.e. Maximum Length Sequences for Complex Impedance Measurements)

* '''Bugs:'''
** (non-critical) when a card does not return a valid reply, the clock card does not send an error reply back to the PC. Instead, it fills the data with whatever it had in its buffer from previous command and sends it to mas.

* '''FPGA Resource Usage''' (clk_card.fit.rpt):
; Total logic elements ; 18,095 / 32,470 ( 56 % ) ;
; Total pins ; 255 / 598 ( 43 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 949,760 / 3,317,184 ( 29 % ) ;
; DSP block 9-bit elements ; 10 / 96 ( 10 % ) ;
; Total PLLs ; 2 / 6 ( 33 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;

* '''Timing Analyzer Summary''' (clk_card.tan.rpt):
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk0' ; 1.547 ns ;
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk2' ; 1.985 ns ;
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk1' ; 2.067 ns ;

== Revision 5.0.2 ==
* '''Filename:''' cc_v05000002_test00_tagged.sof

* '''To Do:'''
** ---

* '''Features:'''
** Header Version 6
** Based off of 5.0.1 and in parallel with 4.0.c (equivalent version)
** The Sync Box PLL was re-instated to the top level and routed to dv_rx. It was mistakenly removed after v4.0.9, which means that the sync box sequence number decoding has not worked since then! When collecting data while triggering off the Sync Box DV, the Clock Card would also sporadically trigger in between data frames.
** Fixed a bug in ret_dat_wbs that did not handle wb num_rows_reported and wb num_cols_reported commands correctly.

* '''Details:'''

* '''Bugs:'''
** (non-critical) when a card does not return a valid reply, the clock card does not send an error reply back to the PC. Instead, it fills the data with whatever it had in its buffer from previous command and sends it to mas.

* '''FPGA Resource Usage''' (clk_card.fit.rpt):
; Total logic elements ; 17,598 / 32,470 ( 54 % ) ;
; Total pins ; 254 / 598 ( 42 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 818,688 / 3,317,184 ( 25 % ) ;
; DSP block 9-bit elements ; 10 / 96 ( 10 % ) ;
; Total PLLs ; 2 / 6 ( 33 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;

* '''Timing Analyzer Summary''' (clk_card.tan.rpt):
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk0' ; 1.965 ns ;
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk1' ; 2.041 ns ;
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk2' ; 3.548 ns ;

== Revision 5.0.1 (buggy) ==
* '''Filename:''' cc_v05000001_12may2009.sof

* '''To Do:'''
** ---

* '''Features:'''
** Based on 5.0.0 and in parallel with 4.0.b (equivalent version)
** Header Version 6
** STOP commands are meant to work in this revision. The successful execution of STOP commands through the system depends also on the PCI card firmware, and PCI driver. Modifications have been made to these, and their version numbers have been bumped to...

* '''Details:'''
** [[ The STOP Command ]]

* '''Bugs:'''
** There may be a problem with decoding sync numbers from the sync box.

* '''FPGA Resource Usage''' (clk_card.fit.rpt):
; Total logic elements ; 18,286 / 32,470 ( 56 % ) ;
; Total pins ; 259 / 598 ( 43 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 1,537,536 / 3,317,184 ( 46 % ) ;
; DSP block 9-bit elements ; 10 / 96 ( 10 % ) ;
; Total PLLs ; 1 / 6 ( 17 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;

* '''Timing Analyzer Summary''' (clk_card.tan.rpt):
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk0' ; 1.995 ns ;
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk2' ; 3.585 ns ;
; Clock Setup: 'altera_internal_jtag~TCKUTAP' ; 5.644 ns ;

== Revision 5.0.0 (buggy) ==
* '''Filename:''' cc_v05000000_22dec2008.sof (tagged as sys_v05000000_22dec2008)

* '''To Do:'''
** ---

* '''Features:'''
** Header Version 6
** IMPORTANT: Must be used in conjunction with firmware v05000000 of all other cards!!!
** This version is based on 4.0.a. That is, it includes all of the features that were under development in 4.0.a, even though 4.0.a was not released for telescope use.
** Added the ability to read out a single column of data continuously from one Readout Card
** New commands include: readout_col_index, readout_priority, num_cols_reported
** To allow enough data bandwidth, the spare LVDS line from each card to the Clock Card is now used

* '''Details:'''

* '''Bugs:'''
** There may be a problem with decoding sync numbers from the sync box.

* '''FPGA Resource Usage''' (clk_card.fit.rpt):
; Total logic elements ; 26,607 / 41,250 ( 65 % ) ;
; Total pins ; 358 / 616 ( 58 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 406,016 / 3,423,744 ( 12 % ) ;
; DSP block 9-bit elements ; 76 / 112 ( 68 % ) ;
; Total PLLs ; 1 / 6 ( 17 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;

* '''Timing Analyzer Summary''' (clk_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.558 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.892 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.987 ns ;

== Revision 4.0.c ==
* '''Filename:''' cc_v0400000c_24aug2009.sof

* '''To Do:'''
** ---

* '''Features:'''
** Header Version 6
** Based on v4.0.b and in parallel with 5.0.2 (equivalent version)
** The Sync Box PLL was re-instated to the top level and routed to dv_rx. It was mistakenly removed after v4.0.9, which means that the sync box sequence number decoding has not worked since then! When collecting data while triggering off the Sync Box DV, the Clock Card would also sporadically trigger in between data frames.

* '''Details:'''
** clk_card.vhd: re-instantiated the manchester PLL, and routed the manch_clk to dv_rx.

* '''Bugs:'''
** None yet.

* '''FPGA Resource Usage''' (clk_card.fit.rpt):
; Total logic elements ; 14,965 / 32,470 ( 46 % ) ;
; Total pins ; 254 / 598 ( 42 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 812,544 / 3,317,184 ( 24 % ) ;
; DSP block 9-bit elements ; 10 / 96 ( 10 % ) ;
; Total PLLs ; 2 / 6 ( 33 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;

* '''Timing Analyzer Summary''' (clk_card.tan.rpt):
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk0' ; 1.646 ns ;
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk1' ; 2.167 ns ;
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk2' ; 2.919 ns ;

== Revision 4.0.b (buggy) ==
* '''Filename:''' cc_v0400000b_03jun2009.sof

* '''To Do:'''
** ---

* '''Features:'''
** Header Version 6
** Based on v4.0.a and in parallel with 5.0.1 (equivalent version, but without the dual-LVDS feature).
** STOP commands are meant to work in this revision. The successful execution of STOP commands through the system depends also on the PCI card firmware, and PCI driver. Modifications have been made to these, and their version numbers have been bumped to...
** This firmware is a hybrid version that implements a single LVDS line, but has STOP and On-The-Fly capabilities built in. The purpose of this firmware is to give SCUBA-2 these features without forcing them to upgrade the firmware on all their other cards.

* '''Details:'''
** [[VHDL changes from v4.0.a and v4.0.b]]

* '''Bugs:'''
** There may be a problem with decoding sync numbers from the sync box.

* '''FPGA Resource Usage''' (clk_card.fit.rpt):
; Total logic elements ; 15,023 / 32,470 ( 46 % ) ;
; Total pins ; 254 / 598 ( 42 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 812,544 / 3,317,184 ( 24 % ) ;
; DSP block 9-bit elements ; 10 / 96 ( 10 % ) ;
; Total PLLs ; 1 / 6 ( 17 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;

* '''Timing Analyzer Summary''' (clk_card.tan.rpt):
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk1' ; 1.328 ns ;
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk0' ; 1.442 ns ;
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk2' ; 3.383 ns ;

== Revision 4.0.a (UBC only) ==
* '''Filename:''' cc_v0400000a_16oct2008

* '''To Do:'''
** Make sure that the errno word, and the cards to report word in the data frame header agree with cards_to_report

* '''Features:'''
** Header Version 6
** Based on 4.0.9
** Added stop_dly, rcs_to_report_data, and cards_to_report commands
** Added support for commands to the MCE during data acquisition

* '''Details:'''
** '''clk_card.vhd:''' incremented the firmware version number, and added cards_to_report interface signals; added support for the stop_dly, rcs_to_report_data, and cards_to_report commands; Removed the Manchester PLL because the only way to ensure that packets are received without trouble is for the main PLL to be locked on the Manchester clock. The Manchester PLL was a failed attempted around this.
** '''clock_card_pack.vhd:''' added support for the stop_dly, rcs_to_report_data, and cards_to_report commands
** '''issue_reply.vhd:''' added support for the stop_dly, rcs_to_report_data, and cards_to_report commands
** '''cmd_translator.vhd:''' split up command registers so that it can handle WB/RB/RS commands while acquiring data based on a GO command.
** '''issue_reply_pack.vhd:''' added indexing constants.
** '''reply_queue.vhd:''' modified the logic for calculating the reply data size, in response to the addition of the rcs_to_report_data, and cards_to_report commands
** '''reply_queue_sequencer.vhd:''' modified the logic for reading the data from the reply queues; modified the logic for determining when to stop readout from a card queue to ease timing constraints. Changed to logic for multiplexing the data buses from the reply queues to combinatorial logic to ease timing constraints.
** '''reply_translator.vhd:''' added a stop_delay counter for delaying the replies to 'stop ret_dat' commands; added the QUICK_REPLY and QUICK_REPLY_PAUSE states to pause the return of replies to stop commands; added extra handling to the LD_STATUS state to avoid mixing stop replies, and replies to data or simple commands; added stop reply pause logic to DONE state
** '''ret_dat_wbs.vhd:''' added the stop_delay_o, rcs_to_report_data, and cards_to_report_o interfaces; implemented a custom register from cards_to_report and stop_delay; removed the register for ret_dat_card_addr which was a special case of cards_to_report.
** '''ret_dat_wbs_pack:''' added the constant DEFAULT_CARDS_TO_REPORT

* '''Bugs:'''
** Reading back rcs_to_report_data returns zero (fixed)
** Can't issue simple commands during data taking
** Can't read from RC4 (fixed)
** There may be a problem with decoding sync numbers from the sync box.

* '''FPGA Resource Usage''' (clk_card.fit.rpt):
; Total logic elements ; 14,542 / 32,470 ( 45 % ) ;
; Total pins ; 254 / 598 ( 42 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 812,544 / 3,317,184 ( 24 % ) ;
; DSP block 9-bit elements ; 8 / 96 ( 8 % ) ;
; Total PLLs ; 1 / 6 ( 17 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;

* '''Timing Analyzer Summary''' (clk_card.tan.rpt):
; Clock Setup: 'clk_switchover:t|_clk0' ; 1.712 ns ;
; Clock Setup: 'clk_switchover:t|_clk1' ; 2.632 ns ;
; Clock Setup: 'clk_switchover:t|_clk2' ; 3.884 ns ;

== Revision 4.0.9 ==
* '''Filename:''' cc_v04000009

* '''Features:'''
** Header Version 6
** Integrated a bug fix for the sram_ctrl block
** Integrated new all_cards block of code which was causing a synthesis warning in ModelSim
** Two new commands added: card_type, scratch.

* '''Bugs:'''
** None to report so far

* '''FPGA Resource Usage''' (clk_card.fit.rpt):
; Total logic elements ; 14,144 / 32,470 ( 44 % ) ;
; Total pins ; 254 / 598 ( 42 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 812,544 / 3,317,184 ( 24 % ) ;
; DSP block 9-bit elements ; 8 / 96 ( 8 % ) ;
; Total PLLs ; 2 / 6 ( 33 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;

* '''Timing Analyzer Summary''' (clk_card.tan.rpt):
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk1' ; 0.294 ns ;
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk0' ; 2.091 ns ;
; Clock Setup: 'clk_switchover:clk_switchover_slave|cc_pll:pll0|altpll:altpll_component|_clk2' ; 2.711 ns ;

= Firmware Links =
* [http://www.phas.ubc.ca/~mce/mcedocs/firmware/cc_fpga_programming_file_catalogue.pdf Clock Card Firmware Catalog]
* [http://www.phas.ubc.ca/~mce/mcedocs/firmware/ Firmware Downloads]

= Wiki Links =
* [http://e-mode.phas.ubc.ca/mcewiki/index.php/MCE_firmware MCE Firmware Page]
* [http://e-mode.phas.ubc.ca/mcewiki/index.php/Main_Page MCE Main Page]

Quartus II Installation

2011-05-20T18:28:50Z

Bburger: /* Quartus II for Windows (For Synthesizing MCE Firmware) */

= Quartus II Programmer for Windows (For Programming the MCE) =
* If you are planning to use Altera-supplied hardware (e.g. USB-Blaster) to upgrade the MCE firmware, you need to install "'''Quartus Programmer'''" on either a Windows or Linux PC.
* See the OS requirements here: http://www.altera.com/download/os-support/oss-index.html 
* Download Quartus here: https://www.altera.com/download/programming/quartus2/pq2-index.jsp
* Note that the installer needs direct access to Quartus website. In case you are behind a firewall, you may need to setup a proxy server.
* The installation is straight forward. After installation is complete, plug in the USB-Blaster and the driver is typically found under altera/10.0/quartus/driver.

= Quartus II for Windows (For Synthesizing MCE Firmware) =
* In a web browser, browse to ftp://ftp.altera.com/outgoing/release/, or https://www.altera.com/download/dnl-index.jsp
* Filenames to look for are of the form "91sp1_quartus_free.exe" if you don't have a license, or "91sp1_quartus_windows.exe" if you have a license.
* Download the appropriate file.
* Double click on 'XX_quartus_windows.exe' and follow the extraction and installation instructions.

= Quartus II for Linux =
As usual, only RedHat and Seuse are officially supported and you are on your own if you install it on any other Linux distribution.

== Troubleshooting Ubuntu Installation ==
Quartus 10.0 installed fine on Ubuntu and no tweaking was needed.

However, when installing Quartus 9.1 the installer couldn't find a few commands that typically exist on Fedora systems, notably ''arch'' and ''rpm''. You can create a fake version of these and copy them under /usr/bin.
* Create a script called ''arch'' that contains:
uname -m
* Create a script called ''rpm'' that contains:
#!/bin/bash
OUT=/home/mce/rpm_cmd.txt
date >> $OUT
echo $@ >> $OUT
Make sure the permissions are set to executable.

More tips here: http://fpga4u.epfl.ch/wiki/Install_Quartus_II#On_Linux

== Launching Quartus ==
After installation is complete, add the Quartus path to $PATH (probably in .bashrc), e.g.:
PATH=$PATH:/opt/usr/local/lib/altera/10.0/quartus/bin
export PATH

== License Manager ==
If you have only installed '''Quartus Programmer or Quartus II web edition''', the following section '''does NOT''' apply to you. However, if you have installed the "Quartus Subscription Edition", then continue reading.

You need to have a license file from Altera. The license file needs to be modified as follows. Change the top few lines from:
SERVER <hostname> 001e90151053 <port number>
VENDOR alterad <path to daemon executable>
VENDOR mgcld <path to daemon executable>
USE_SERVER
to
SERVER mce-ubc-2 001e90151053 1700
DAEMON alterad /opt/altera91/quartus/linux64/alterad
DAEMON mgcld /opt/altera91/modelsim_ase/linux/mgls/lib/mgcld
USE_SERVER

Copy the license file in /opt/licenses/quartus_001e90151053.dat

The license manager can be invoked by:
sudo /opt/altera10.0sp1/quartus/linux/lmgrd -c /opt/licenses/quartus_001e90151053.dat

You can add this line (without the sudo) into /etc/rc.local to get it to start whenever the computer boots.

When this works, it should spit out messages like this:
8:38:25 (lmgrd) Started alterad (internet tcp_port 52255 pid 28888)
8:38:25 (lmgrd) Started mgcld (internet tcp_port 54712 pid 28889)
8:38:25 (alterad) FLEXlm version 9.50
8:38:25 (alterad) lmgrd version 11.4, alterad version 9.5

8:38:25 (mgcld) FLEXnet Licensing version v10.8.5.0 build 31891 i86_r6
8:38:25 (mgcld) lmgrd version 11.4, mgcld version 10.8

8:38:25 (mgcld) Server started on mce-ubc-2 for: alteramtivsim
8:38:25 (mgcld)
8:38:25 (mgcld) Licenses are case sensitive for mgcld
8:38:25 (mgcld)
8:38:25 (mgcld) EXTERNAL FILTERS are OFF
8:38:25 (lmgrd) mgcld using TCP-port 54712
8:38:25 (alterad) Server started on mce-ubc-2 for: maxplus2
8:38:25 (alterad) quartus 6AF7_0012 6AF7_0014
8:38:25 (alterad) 6AF7_0055 6AF7_00A7 6AF7_00A8
8:38:25 (alterad) 6AF7_00A4 6AF7_0034 6AF7_00AC
8:38:25 (alterad) 6AF7_00AD 6AF7_00BE 6AF7_00BF
8:38:25 (alterad) 6AF7_00C2 maxplus2verilog maxplus2vhdl
8:38:25 (alterad) altera_mainwin_lnx altera_mainwin 6AF8_00A2
8:38:25 (alterad) 6AF7_00A2

Quartus II Installation

2011-05-20T18:28:37Z

Bburger: /* Quartus II for Windows (For Synthesizing MCE Firmware) */

= Quartus II Programmer for Windows (For Programming the MCE) =
* If you are planning to use Altera-supplied hardware (e.g. USB-Blaster) to upgrade the MCE firmware, you need to install "'''Quartus Programmer'''" on either a Windows or Linux PC.
* See the OS requirements here: http://www.altera.com/download/os-support/oss-index.html 
* Download Quartus here: https://www.altera.com/download/programming/quartus2/pq2-index.jsp
* Note that the installer needs direct access to Quartus website. In case you are behind a firewall, you may need to setup a proxy server.
* The installation is straight forward. After installation is complete, plug in the USB-Blaster and the driver is typically found under altera/10.0/quartus/driver.

= Quartus II for Windows (For Synthesizing MCE Firmware) =
* In a web browser, browse to ftp://ftp.altera.com/outgoing/release/
* Or: https://www.altera.com/download/dnl-index.jsp
* Filenames to look for are of the form "91sp1_quartus_free.exe" if you don't have a license, or "91sp1_quartus_windows.exe" if you have a license.
* Download the appropriate file.
* Double click on 'XX_quartus_windows.exe' and follow the extraction and installation instructions.

= Quartus II for Linux =
As usual, only RedHat and Seuse are officially supported and you are on your own if you install it on any other Linux distribution.

== Troubleshooting Ubuntu Installation ==
Quartus 10.0 installed fine on Ubuntu and no tweaking was needed.

However, when installing Quartus 9.1 the installer couldn't find a few commands that typically exist on Fedora systems, notably ''arch'' and ''rpm''. You can create a fake version of these and copy them under /usr/bin.
* Create a script called ''arch'' that contains:
uname -m
* Create a script called ''rpm'' that contains:
#!/bin/bash
OUT=/home/mce/rpm_cmd.txt
date >> $OUT
echo $@ >> $OUT
Make sure the permissions are set to executable.

More tips here: http://fpga4u.epfl.ch/wiki/Install_Quartus_II#On_Linux

== Launching Quartus ==
After installation is complete, add the Quartus path to $PATH (probably in .bashrc), e.g.:
PATH=$PATH:/opt/usr/local/lib/altera/10.0/quartus/bin
export PATH

== License Manager ==
If you have only installed '''Quartus Programmer or Quartus II web edition''', the following section '''does NOT''' apply to you. However, if you have installed the "Quartus Subscription Edition", then continue reading.

You need to have a license file from Altera. The license file needs to be modified as follows. Change the top few lines from:
SERVER <hostname> 001e90151053 <port number>
VENDOR alterad <path to daemon executable>
VENDOR mgcld <path to daemon executable>
USE_SERVER
to
SERVER mce-ubc-2 001e90151053 1700
DAEMON alterad /opt/altera91/quartus/linux64/alterad
DAEMON mgcld /opt/altera91/modelsim_ase/linux/mgls/lib/mgcld
USE_SERVER

Copy the license file in /opt/licenses/quartus_001e90151053.dat

The license manager can be invoked by:
sudo /opt/altera10.0sp1/quartus/linux/lmgrd -c /opt/licenses/quartus_001e90151053.dat

You can add this line (without the sudo) into /etc/rc.local to get it to start whenever the computer boots.

When this works, it should spit out messages like this:
8:38:25 (lmgrd) Started alterad (internet tcp_port 52255 pid 28888)
8:38:25 (lmgrd) Started mgcld (internet tcp_port 54712 pid 28889)
8:38:25 (alterad) FLEXlm version 9.50
8:38:25 (alterad) lmgrd version 11.4, alterad version 9.5

8:38:25 (mgcld) FLEXnet Licensing version v10.8.5.0 build 31891 i86_r6
8:38:25 (mgcld) lmgrd version 11.4, mgcld version 10.8

8:38:25 (mgcld) Server started on mce-ubc-2 for: alteramtivsim
8:38:25 (mgcld)
8:38:25 (mgcld) Licenses are case sensitive for mgcld
8:38:25 (mgcld)
8:38:25 (mgcld) EXTERNAL FILTERS are OFF
8:38:25 (lmgrd) mgcld using TCP-port 54712
8:38:25 (alterad) Server started on mce-ubc-2 for: maxplus2
8:38:25 (alterad) quartus 6AF7_0012 6AF7_0014
8:38:25 (alterad) 6AF7_0055 6AF7_00A7 6AF7_00A8
8:38:25 (alterad) 6AF7_00A4 6AF7_0034 6AF7_00AC
8:38:25 (alterad) 6AF7_00AD 6AF7_00BE 6AF7_00BF
8:38:25 (alterad) 6AF7_00C2 maxplus2verilog maxplus2vhdl
8:38:25 (alterad) altera_mainwin_lnx altera_mainwin 6AF8_00A2
8:38:25 (alterad) 6AF7_00A2

Bias Card firmware

2011-05-12T21:51:02Z

Bburger: /* Revision 5.0.5 (recommended) */

* Recommended Firmware Revisions [http://e-mode.phas.ubc.ca/mcewiki/index.php/Compatible_Versions_(CC,RC,BC,AC) here]

== Revision 5.0.6 (under test) ==
* '''Filename:''' bc_v05000006_11may2011.sof

* '''To Do:'''
* '''Features:'''
** Changes the timing of loading the FB_COLxx values from 32 clock cycles before the start of a new frame, to the start of a new frame. This firmware was generated to find the reason for the downturns in raw data at the end of rows, as seen by Jeffrey Flilippini:
** See details here: http://spiderwiki.princeton.edu/spider/AnalysisLogbook/TestCryostat/20110427_muxing/index.html

* '''Details:'''

* '''Bugs:'''
** None yet reported

* '''FPGA Resource Usage''' (bias_card.fit.rpt):
; Total logic elements ; 6,278 / 10,570 ( 59 % ) ;
; Total pins ; 209 / 427 ( 49 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 133,120 / 920,448 ( 14 % ) ;
; DSP block 9-bit elements ; 8 / 48 ( 17 % ) ;

* '''Timing Analyzer Summary''' (bias_card.tan.rpt):
; Fast Model Clock Setup: 'bc_pll:pll0|altpll:altpll_component|_clk0' ; 6.930 ns
; Fast Model Clock Setup: 'bc_pll:pll0|altpll:altpll_component|_clk1' ; 6.980 ns
; Fast Model Clock Setup: 'bc_pll:pll0|altpll:altpll_component|_clk3' ; 16.383 ns

== Revision 5.0.5 (recommended) ==
; Filename
: bc_v05000005_20jul2010.sof
; Features
: based on 5.0.4, but updated for Rev. F/D hardware pinout.
: card_type parameter now includes the pcb-revision information as well as the card_type. card_type is specified as 0x01 as the lower byte (same as before). Reading back card_type parameter returns: 0x0F01 in Rev. D cards, and 0x0601 in Rev. F cards. (Previously, reading back card_type parameter only returned 0x01).

; Details
: When using tes_bias lines, make sure the count is 12 for bias parameter in mce.cfg file.
: When installed on Rev. D file, tes_mapping has to have offset =11 in mce.cfg.

; To do
:none
; Bugs
: none
; FPGA Resource Usage
: Total logic elements ; 60%
: M512s ; 49%
: M4Ks ; 100%
: M-RAMs ; 100%

== Revision 5.0.4 (lab use) ==
; Filename
: bc_v05000004_20may2010.sof
; Features
: build based on 5.0.3 for Rev. E cards
: Biases are refreshed 1 clock cycles after the start of a new row, regardless of whether they are running in multiplex mode or not and whether it is a regular bias line or low-noise bias line.
; Details
: '''NOTE''' If this firmware is loaded on a Rev. D card, it's harmless. The only functionality loss is that the '''bias''' command will not work as unfortunately DAC CS and CLK pins are swapped for the bias DAC between the two revisions of the card.
; To do
:none
; Bugs
: none
; FPGA Resource Usage
: Total logic elements ; 60%
: M512s ; 49%
: M4Ks ; 100%
: M-RAMs ; 100%

== Revision 5.0.3 (lab use) ==
; Filename
: bc_v05000003_12may2010.sof
; Features
: build based on 5.0.2 for Rev. E cards
: added '''fb_col0 to fb_col31''' and '''enbl_mux''' commands to accommodate row-based sq2fb switching. When enbl_mux is asserted for a column, then the DAC is refreshed on every row visit with the value specified by fb_col command.
; Details
: The original Bias Card design has a buffer after the DAC that is too slow followed by kHz range RC filters, so in order to enable the multiplexing feature, one has to make sure that the BC hardware is modified as per ECO-xxx (to be added here).
: card_type returns 5 (indicating a Rev. E)
: If this firmware is loaded on a Rev. D card, it's harmless. The only functionality loss is that the bias command will not work as unfortunately DAC CS and CLK pins are swapped for the bias DAC between the two revisions of the card.
: combinational loops present in previous versions are removed now
: There is 9+16*2=41 clock cycle (820ns) delay for the bias to be applied after the start of a new row. This combined with another 400ns delay due to inherent DAC delay is about 60 clock-cycle delay.
; To do
: The excessive 41 clock cycle delay to apply a new bias has to be reduced. It is conceivable to preload the DACs and reduce this delay to 1 to 2 clock cycles.
; Bugs
: none
; FPGA Resource Usage
: Total logic elements ; 6,140 / 10,570 ( 58 % ) ;
: Total memory bits ; 133,120 / 920,448 ( 14 % ) ;
: M512s ; 48 / 94 ( 51 % ) ;
: M4Ks ; 60 / 60 ( 100 % ) ;
: M-RAMs ; 0 / 1 ( 0 % ) ;

== Revision 5.0.2 (lab use) ==
; Filename
: bc_v05000002_xxjan2010.sof
; Features
: build based on 5.0.1 for Rev. E cards
: Independent control for ln_bias lines 0 to 11
; Details
: If this firmware is loaded on a Rev. D card, it's harmless. The only functionality loss is that the bias command will not work as unfortunately DAC CS and CLK pins are swapped for the bias DAC between the two revisions of the card.
; To do
: fix combinational loops on read-ram register

; Bugs

== Revision 5.0.1 (lab use) ==
; Filename
: bc_v05000001_19jan2010.sof
; Features
: supports the new low-noise bias lines (total of 12) introduced in Bias Card Rev. E
: card_type parameter is set to 5 (bias-card Rev. E)
: All DACs are loaded at once as oppose to previous revisions that loaded them one after next.
: DAC clock is now 25MHz and generated by PLL, previous firmware had 12.5MHz clock generated by dividing down.
; Details
: If this firmware is loaded on a Rev. D card, it's harmless. The only functionality loss is that the bias command will not work as unfortunately DAC CS and CLK pins are swapped for the bias DAC between the two revisions of the card.
; To do
: All ln_bias lines are controlled at once and this should be modified to independent control.
; Bugs
ln_bias_0 doesn't work, because the data line for ln_bias_0 is not connected in firmware.

== Revision 5.0.0 ==
* '''Filename:''' bc_v05000000_22dec2008.sof (tagged as sys_v05000000_22dec2008)

* '''To Do:'''
* '''Features:'''
** IMPORTANT: Must be used in conjunction with firmware v05000000 of all other cards!!!
** To allow enough data bandwidth, the spare LVDS line from each card to the Clock Card is now used

* '''Details:'''

* '''Bugs:'''
** None yet reported

* '''FPGA Resource Usage''' (bias_card.fit.rpt):
; Fitter Status ; Successful - Wed Jan 14 11:19:37 2009 ;
; Quartus II Version ; 8.1 Build 163 10/28/2008 SJ Full Version ;
; Device ; EP1S10F780C5 ;
; Total logic elements ; 3,356 / 10,570 ( 32 % ) ;
; Total pins ; 187 / 427 ( 44 % ) ;
; Total memory bits ; 70,144 / 920,448 ( 8 % ) ;

* '''Timing Analyzer Summary''' (bias_card.tan.rpt):
; Fast Model Clock Setup: 'bc_pll:pll0|altpll:altpll_component|_clk1' ; 7.060 ns ;
; Fast Model Clock Setup: 'bc_pll:pll0|altpll:altpll_component|_clk0' ; 7.125 ns ;
; Fast Model Clock Hold: 'bc_pll:pll0|altpll:altpll_component|_clk0' ; 0.383 ns ;
; Fast Model Clock Hold: 'bc_pll:pll0|altpll:altpll_component|_clk1' ; 0.384 ns ;
; Fast Model Recovery: 'bc_pll:pll0|altpll:altpll_component|_clk0' ; 16.037 ns ;
; Fast Model Removal: 'bc_pll:pll0|altpll:altpll_component|_clk0' ; 0.575 ns ;
; Total number of failed paths ; ;

== Revision 1.4.2 ==
* bc_v01040002_15jul2008.sof
Features:
* Added the tga_i signal to the sensitivity list for the bc_dac_ctrl FSM
* potential bug may have been introduced with resetting the DAC counter due to inadvertently using the wrong bc_dac_ctrl_core.vhd version.

== Revision 1.4.1 ==
* bc_v01040001_25jan2008.sof

Features:
* Added card_type and scratch commands
* Integrated fw_rev and slot_id as part of all_cards
* Added provisions for safe state machines to fix the reset problem.
* Added lvds_tx = 0 so clock-card can check whether the card is plugged in using this spare lvds line.
Bugs: None so far

= Firmware Links =
* [http://www.phas.ubc.ca/~mce/mcedocs/firmware/ Firmware .sof & .pof Downloads]
* [http://www.phas.ubc.ca/~mce/mcedocs/firmware/bc_fpga_programming_file_catalogue.pdf Bias Card Firmware Catalog]

= Wiki Links =
* [http://e-mode.phas.ubc.ca/mcewiki/index.php/MCE_firmware MCE Firmware Page]
* [http://e-mode.phas.ubc.ca/mcewiki/index.php/Main_Page MCE Main Page]

Bias Card firmware

2011-05-12T19:17:23Z

Bburger: /* Revision 5.0.6 (under test) */

Bias Card firmware

2011-05-12T19:12:03Z

Bburger: /* Revision 5.0.6 (under test) */

* Recommended Firmware Revisions [http://e-mode.phas.ubc.ca/mcewiki/index.php/Compatible_Versions_(CC,RC,BC,AC) here]

== Revision 5.0.6 (under test) ==
* '''Filename:''' bc_v05000006_11may2011.sof

* '''To Do:'''
* '''Features:'''
** Changes the timing of loading the FB_COLxx values from 32 clock cycles before the start of a new frame, to the start of a new frame. This firmware was generated to find the reason for the downturns in raw data at the end of rows, as seen by Jeffrey Flilippini:
** See details here: http://spiderwiki.princeton.edu/spider/AnalysisLogbook/TestCryostat/20110427_muxing/index.html

* '''Details:'''

* '''Bugs:'''
** None yet reported

* '''FPGA Resource Usage''' (bias_card.fit.rpt):

* '''Timing Analyzer Summary''' (bias_card.tan.rpt):

== Revision 5.0.5 (recommended) ==
; Filename
: bc_v05000005_20jul2010.sof
; Features
: based on 5.0.4, but updated for Rev. F/D hardware pinout.
: card_type parameter now includes the pcb-revision information as well as the card_type. card_type is specified as 0x01 as the lower byte (same as before). Reading back card_type parameter returns: 0x0F01 in Rev. D cards, and 0x0601 in Rev. F cards. (Previously, reading back card_type parameter only returned 0x01).

; Details
: When using tes_bias lines, make sure the count is 12 for bias parameter in mce.cfg file.
: When installed on Rev. D file, tes_mapping has to have offset =11 in mce.cfg.

; To do
:none
; Bugs
: none
; FPGA Resource Usage
: Total logic elements ; 60%
: M512s ; 49%
: M4Ks ; 100%
: M-RAMs ; 100%

== Revision 5.0.4 (lab use) ==
; Filename
: bc_v05000004_20may2010.sof
; Features
: build based on 5.0.3 for Rev. E cards
: Biases are refreshed 1 clock cycles after the start of a new row, regardless of whether they are running in multiplex mode or not and whether it is a regular bias line or low-noise bias line.
; Details
: '''NOTE''' If this firmware is loaded on a Rev. D card, it's harmless. The only functionality loss is that the '''bias''' command will not work as unfortunately DAC CS and CLK pins are swapped for the bias DAC between the two revisions of the card.
; To do
:none
; Bugs
: none
; FPGA Resource Usage
: Total logic elements ; 60%
: M512s ; 49%
: M4Ks ; 100%
: M-RAMs ; 100%

== Revision 5.0.3 (lab use) ==
; Filename
: bc_v05000003_12may2010.sof
; Features
: build based on 5.0.2 for Rev. E cards
: added '''fb_col0 to fb_col31''' and '''enbl_mux''' commands to accommodate row-based sq2fb switching. When enbl_mux is asserted for a column, then the DAC is refreshed on every row visit with the value specified by fb_col command.
; Details
: The original Bias Card design has a buffer after the DAC that is too slow followed by kHz range RC filters, so in order to enable the multiplexing feature, one has to make sure that the BC hardware is modified as per ECO-xxx (to be added here).
: card_type returns 5 (indicating a Rev. E)
: If this firmware is loaded on a Rev. D card, it's harmless. The only functionality loss is that the bias command will not work as unfortunately DAC CS and CLK pins are swapped for the bias DAC between the two revisions of the card.
: combinational loops present in previous versions are removed now
: There is 9+16*2=41 clock cycle (820ns) delay for the bias to be applied after the start of a new row. This combined with another 400ns delay due to inherent DAC delay is about 60 clock-cycle delay.
; To do
: The excessive 41 clock cycle delay to apply a new bias has to be reduced. It is conceivable to preload the DACs and reduce this delay to 1 to 2 clock cycles.
; Bugs
: none
; FPGA Resource Usage
: Total logic elements ; 6,140 / 10,570 ( 58 % ) ;
: Total memory bits ; 133,120 / 920,448 ( 14 % ) ;
: M512s ; 48 / 94 ( 51 % ) ;
: M4Ks ; 60 / 60 ( 100 % ) ;
: M-RAMs ; 0 / 1 ( 0 % ) ;

== Revision 5.0.2 (lab use) ==
; Filename
: bc_v05000002_xxjan2010.sof
; Features
: build based on 5.0.1 for Rev. E cards
: Independent control for ln_bias lines 0 to 11
; Details
: If this firmware is loaded on a Rev. D card, it's harmless. The only functionality loss is that the bias command will not work as unfortunately DAC CS and CLK pins are swapped for the bias DAC between the two revisions of the card.
; To do
: fix combinational loops on read-ram register

; Bugs

== Revision 5.0.1 (lab use) ==
; Filename
: bc_v05000001_19jan2010.sof
; Features
: supports the new low-noise bias lines (total of 12) introduced in Bias Card Rev. E
: card_type parameter is set to 5 (bias-card Rev. E)
: All DACs are loaded at once as oppose to previous revisions that loaded them one after next.
: DAC clock is now 25MHz and generated by PLL, previous firmware had 12.5MHz clock generated by dividing down.
; Details
: If this firmware is loaded on a Rev. D card, it's harmless. The only functionality loss is that the bias command will not work as unfortunately DAC CS and CLK pins are swapped for the bias DAC between the two revisions of the card.
; To do
: All ln_bias lines are controlled at once and this should be modified to independent control.
; Bugs
ln_bias_0 doesn't work, because the data line for ln_bias_0 is not connected in firmware.

== Revision 5.0.0 ==
* '''Filename:''' bc_v05000000_22dec2008.sof (tagged as sys_v05000000_22dec2008)

* '''To Do:'''
* '''Features:'''
** IMPORTANT: Must be used in conjunction with firmware v05000000 of all other cards!!!
** To allow enough data bandwidth, the spare LVDS line from each card to the Clock Card is now used

* '''Details:'''

* '''Bugs:'''
** None yet reported

* '''FPGA Resource Usage''' (bias_card.fit.rpt):
; Fitter Status ; Successful - Wed Jan 14 11:19:37 2009 ;
; Quartus II Version ; 8.1 Build 163 10/28/2008 SJ Full Version ;
; Device ; EP1S10F780C5 ;
; Total logic elements ; 3,356 / 10,570 ( 32 % ) ;
; Total pins ; 187 / 427 ( 44 % ) ;
; Total memory bits ; 70,144 / 920,448 ( 8 % ) ;

* '''Timing Analyzer Summary''' (bias_card.tan.rpt):
; Fast Model Clock Setup: 'bc_pll:pll0|altpll:altpll_component|_clk1' ; 7.060 ns ;
; Fast Model Clock Setup: 'bc_pll:pll0|altpll:altpll_component|_clk0' ; 7.125 ns ;
; Fast Model Clock Hold: 'bc_pll:pll0|altpll:altpll_component|_clk0' ; 0.383 ns ;
; Fast Model Clock Hold: 'bc_pll:pll0|altpll:altpll_component|_clk1' ; 0.384 ns ;
; Fast Model Recovery: 'bc_pll:pll0|altpll:altpll_component|_clk0' ; 16.037 ns ;
; Fast Model Removal: 'bc_pll:pll0|altpll:altpll_component|_clk0' ; 0.575 ns ;
; Total number of failed paths ; ;

== Revision 1.4.2 ==
* bc_v01040002_15jul2008.sof
Features:
* Added the tga_i signal to the sensitivity list for the bc_dac_ctrl FSM
* potential bug may have been introduced with resetting the DAC counter due to inadvertently using the wrong bc_dac_ctrl_core.vhd version.

== Revision 1.4.1 ==
* bc_v01040001_25jan2008.sof

Features:
* Added card_type and scratch commands
* Integrated fw_rev and slot_id as part of all_cards
* Added provisions for safe state machines to fix the reset problem.
* Added lvds_tx = 0 so clock-card can check whether the card is plugged in using this spare lvds line.
Bugs: None so far

= Firmware Links =
* [http://www.phas.ubc.ca/~mce/mcedocs/firmware/ Firmware .sof & .pof Downloads]
* [http://www.phas.ubc.ca/~mce/mcedocs/firmware/bc_fpga_programming_file_catalogue.pdf Bias Card Firmware Catalog]

= Wiki Links =
* [http://e-mode.phas.ubc.ca/mcewiki/index.php/MCE_firmware MCE Firmware Page]
* [http://e-mode.phas.ubc.ca/mcewiki/index.php/Main_Page MCE Main Page]

Bias Card firmware

2011-05-12T18:28:32Z

Bburger: /* Revision 5.0.6 */

* Recommended Firmware Revisions [http://e-mode.phas.ubc.ca/mcewiki/index.php/Compatible_Versions_(CC,RC,BC,AC) here]

== Revision 5.0.6 (under test) ==
* '''Filename:''' bc_v05000006_11may2011.sof

* '''To Do:'''
* '''Features:'''
** Changes the timing of loading the FB_COLxx values from 32 clock cycles before the start of a new frame, to at the beginning of a new frame. This firmware was generated to find the reason for the downturn in raw data at the end of rows, as seen by Jeffrey Flilippini:
** See details here: http://spiderwiki.princeton.edu/spider/AnalysisLogbook/TestCryostat/20110427_muxing/index.html

* '''Details:'''

* '''Bugs:'''
** None yet reported

* '''FPGA Resource Usage''' (bias_card.fit.rpt):

* '''Timing Analyzer Summary''' (bias_card.tan.rpt):

== Revision 5.0.5 (recommended) ==
; Filename
: bc_v05000005_20jul2010.sof
; Features
: based on 5.0.4, but updated for Rev. F/D hardware pinout.
: card_type parameter now includes the pcb-revision information as well as the card_type. card_type is specified as 0x01 as the lower byte (same as before). Reading back card_type parameter returns: 0x0F01 in Rev. D cards, and 0x0601 in Rev. F cards. (Previously, reading back card_type parameter only returned 0x01).

; Details
: When using tes_bias lines, make sure the count is 12 for bias parameter in mce.cfg file.
: When installed on Rev. D file, tes_mapping has to have offset =11 in mce.cfg.

; To do
:none
; Bugs
: none
; FPGA Resource Usage
: Total logic elements ; 60%
: M512s ; 49%
: M4Ks ; 100%
: M-RAMs ; 100%

== Revision 5.0.4 (lab use) ==
; Filename
: bc_v05000004_20may2010.sof
; Features
: build based on 5.0.3 for Rev. E cards
: Biases are refreshed 1 clock cycles after the start of a new row, regardless of whether they are running in multiplex mode or not and whether it is a regular bias line or low-noise bias line.
; Details
: '''NOTE''' If this firmware is loaded on a Rev. D card, it's harmless. The only functionality loss is that the '''bias''' command will not work as unfortunately DAC CS and CLK pins are swapped for the bias DAC between the two revisions of the card.
; To do
:none
; Bugs
: none
; FPGA Resource Usage
: Total logic elements ; 60%
: M512s ; 49%
: M4Ks ; 100%
: M-RAMs ; 100%

== Revision 5.0.3 (lab use) ==
; Filename
: bc_v05000003_12may2010.sof
; Features
: build based on 5.0.2 for Rev. E cards
: added '''fb_col0 to fb_col31''' and '''enbl_mux''' commands to accommodate row-based sq2fb switching. When enbl_mux is asserted for a column, then the DAC is refreshed on every row visit with the value specified by fb_col command.
; Details
: The original Bias Card design has a buffer after the DAC that is too slow followed by kHz range RC filters, so in order to enable the multiplexing feature, one has to make sure that the BC hardware is modified as per ECO-xxx (to be added here).
: card_type returns 5 (indicating a Rev. E)
: If this firmware is loaded on a Rev. D card, it's harmless. The only functionality loss is that the bias command will not work as unfortunately DAC CS and CLK pins are swapped for the bias DAC between the two revisions of the card.
: combinational loops present in previous versions are removed now
: There is 9+16*2=41 clock cycle (820ns) delay for the bias to be applied after the start of a new row. This combined with another 400ns delay due to inherent DAC delay is about 60 clock-cycle delay.
; To do
: The excessive 41 clock cycle delay to apply a new bias has to be reduced. It is conceivable to preload the DACs and reduce this delay to 1 to 2 clock cycles.
; Bugs
: none
; FPGA Resource Usage
: Total logic elements ; 6,140 / 10,570 ( 58 % ) ;
: Total memory bits ; 133,120 / 920,448 ( 14 % ) ;
: M512s ; 48 / 94 ( 51 % ) ;
: M4Ks ; 60 / 60 ( 100 % ) ;
: M-RAMs ; 0 / 1 ( 0 % ) ;

== Revision 5.0.2 (lab use) ==
; Filename
: bc_v05000002_xxjan2010.sof
; Features
: build based on 5.0.1 for Rev. E cards
: Independent control for ln_bias lines 0 to 11
; Details
: If this firmware is loaded on a Rev. D card, it's harmless. The only functionality loss is that the bias command will not work as unfortunately DAC CS and CLK pins are swapped for the bias DAC between the two revisions of the card.
; To do
: fix combinational loops on read-ram register

; Bugs

== Revision 5.0.1 (lab use) ==
; Filename
: bc_v05000001_19jan2010.sof
; Features
: supports the new low-noise bias lines (total of 12) introduced in Bias Card Rev. E
: card_type parameter is set to 5 (bias-card Rev. E)
: All DACs are loaded at once as oppose to previous revisions that loaded them one after next.
: DAC clock is now 25MHz and generated by PLL, previous firmware had 12.5MHz clock generated by dividing down.
; Details
: If this firmware is loaded on a Rev. D card, it's harmless. The only functionality loss is that the bias command will not work as unfortunately DAC CS and CLK pins are swapped for the bias DAC between the two revisions of the card.
; To do
: All ln_bias lines are controlled at once and this should be modified to independent control.
; Bugs
ln_bias_0 doesn't work, because the data line for ln_bias_0 is not connected in firmware.

== Revision 5.0.0 ==
* '''Filename:''' bc_v05000000_22dec2008.sof (tagged as sys_v05000000_22dec2008)

* '''To Do:'''
* '''Features:'''
** IMPORTANT: Must be used in conjunction with firmware v05000000 of all other cards!!!
** To allow enough data bandwidth, the spare LVDS line from each card to the Clock Card is now used

* '''Details:'''

* '''Bugs:'''
** None yet reported

* '''FPGA Resource Usage''' (bias_card.fit.rpt):
; Fitter Status ; Successful - Wed Jan 14 11:19:37 2009 ;
; Quartus II Version ; 8.1 Build 163 10/28/2008 SJ Full Version ;
; Device ; EP1S10F780C5 ;
; Total logic elements ; 3,356 / 10,570 ( 32 % ) ;
; Total pins ; 187 / 427 ( 44 % ) ;
; Total memory bits ; 70,144 / 920,448 ( 8 % ) ;

* '''Timing Analyzer Summary''' (bias_card.tan.rpt):
; Fast Model Clock Setup: 'bc_pll:pll0|altpll:altpll_component|_clk1' ; 7.060 ns ;
; Fast Model Clock Setup: 'bc_pll:pll0|altpll:altpll_component|_clk0' ; 7.125 ns ;
; Fast Model Clock Hold: 'bc_pll:pll0|altpll:altpll_component|_clk0' ; 0.383 ns ;
; Fast Model Clock Hold: 'bc_pll:pll0|altpll:altpll_component|_clk1' ; 0.384 ns ;
; Fast Model Recovery: 'bc_pll:pll0|altpll:altpll_component|_clk0' ; 16.037 ns ;
; Fast Model Removal: 'bc_pll:pll0|altpll:altpll_component|_clk0' ; 0.575 ns ;
; Total number of failed paths ; ;

== Revision 1.4.2 ==
* bc_v01040002_15jul2008.sof
Features:
* Added the tga_i signal to the sensitivity list for the bc_dac_ctrl FSM
* potential bug may have been introduced with resetting the DAC counter due to inadvertently using the wrong bc_dac_ctrl_core.vhd version.

== Revision 1.4.1 ==
* bc_v01040001_25jan2008.sof

Features:
* Added card_type and scratch commands
* Integrated fw_rev and slot_id as part of all_cards
* Added provisions for safe state machines to fix the reset problem.
* Added lvds_tx = 0 so clock-card can check whether the card is plugged in using this spare lvds line.
Bugs: None so far

= Firmware Links =
* [http://www.phas.ubc.ca/~mce/mcedocs/firmware/ Firmware .sof & .pof Downloads]
* [http://www.phas.ubc.ca/~mce/mcedocs/firmware/bc_fpga_programming_file_catalogue.pdf Bias Card Firmware Catalog]

= Wiki Links =
* [http://e-mode.phas.ubc.ca/mcewiki/index.php/MCE_firmware MCE Firmware Page]
* [http://e-mode.phas.ubc.ca/mcewiki/index.php/Main_Page MCE Main Page]

Bias Card firmware

2011-05-12T18:28:12Z

Bburger: /* Revision 5.0.6 */

* Recommended Firmware Revisions [http://e-mode.phas.ubc.ca/mcewiki/index.php/Compatible_Versions_(CC,RC,BC,AC) here]

== Revision 5.0.6 ==
* '''Filename:''' bc_v05000006_11may2011.sof

* '''To Do:'''
* '''Features:'''
** Changes the timing of loading the FB_COLxx values from 32 clock cycles before the start of a new frame, to at the beginning of a new frame. This firmware was generated to find the reason for the downturn in raw data at the end of rows, as seen by Jeffrey Flilippini:
** See details here: http://spiderwiki.princeton.edu/spider/AnalysisLogbook/TestCryostat/20110427_muxing/index.html

* '''Details:'''

* '''Bugs:'''
** None yet reported

* '''FPGA Resource Usage''' (bias_card.fit.rpt):

* '''Timing Analyzer Summary''' (bias_card.tan.rpt):

== Revision 5.0.5 (recommended) ==
; Filename
: bc_v05000005_20jul2010.sof
; Features
: based on 5.0.4, but updated for Rev. F/D hardware pinout.
: card_type parameter now includes the pcb-revision information as well as the card_type. card_type is specified as 0x01 as the lower byte (same as before). Reading back card_type parameter returns: 0x0F01 in Rev. D cards, and 0x0601 in Rev. F cards. (Previously, reading back card_type parameter only returned 0x01).

; Details
: When using tes_bias lines, make sure the count is 12 for bias parameter in mce.cfg file.
: When installed on Rev. D file, tes_mapping has to have offset =11 in mce.cfg.

; To do
:none
; Bugs
: none
; FPGA Resource Usage
: Total logic elements ; 60%
: M512s ; 49%
: M4Ks ; 100%
: M-RAMs ; 100%

== Revision 5.0.4 (lab use) ==
; Filename
: bc_v05000004_20may2010.sof
; Features
: build based on 5.0.3 for Rev. E cards
: Biases are refreshed 1 clock cycles after the start of a new row, regardless of whether they are running in multiplex mode or not and whether it is a regular bias line or low-noise bias line.
; Details
: '''NOTE''' If this firmware is loaded on a Rev. D card, it's harmless. The only functionality loss is that the '''bias''' command will not work as unfortunately DAC CS and CLK pins are swapped for the bias DAC between the two revisions of the card.
; To do
:none
; Bugs
: none
; FPGA Resource Usage
: Total logic elements ; 60%
: M512s ; 49%
: M4Ks ; 100%
: M-RAMs ; 100%

== Revision 5.0.3 (lab use) ==
; Filename
: bc_v05000003_12may2010.sof
; Features
: build based on 5.0.2 for Rev. E cards
: added '''fb_col0 to fb_col31''' and '''enbl_mux''' commands to accommodate row-based sq2fb switching. When enbl_mux is asserted for a column, then the DAC is refreshed on every row visit with the value specified by fb_col command.
; Details
: The original Bias Card design has a buffer after the DAC that is too slow followed by kHz range RC filters, so in order to enable the multiplexing feature, one has to make sure that the BC hardware is modified as per ECO-xxx (to be added here).
: card_type returns 5 (indicating a Rev. E)
: If this firmware is loaded on a Rev. D card, it's harmless. The only functionality loss is that the bias command will not work as unfortunately DAC CS and CLK pins are swapped for the bias DAC between the two revisions of the card.
: combinational loops present in previous versions are removed now
: There is 9+16*2=41 clock cycle (820ns) delay for the bias to be applied after the start of a new row. This combined with another 400ns delay due to inherent DAC delay is about 60 clock-cycle delay.
; To do
: The excessive 41 clock cycle delay to apply a new bias has to be reduced. It is conceivable to preload the DACs and reduce this delay to 1 to 2 clock cycles.
; Bugs
: none
; FPGA Resource Usage
: Total logic elements ; 6,140 / 10,570 ( 58 % ) ;
: Total memory bits ; 133,120 / 920,448 ( 14 % ) ;
: M512s ; 48 / 94 ( 51 % ) ;
: M4Ks ; 60 / 60 ( 100 % ) ;
: M-RAMs ; 0 / 1 ( 0 % ) ;

== Revision 5.0.2 (lab use) ==
; Filename
: bc_v05000002_xxjan2010.sof
; Features
: build based on 5.0.1 for Rev. E cards
: Independent control for ln_bias lines 0 to 11
; Details
: If this firmware is loaded on a Rev. D card, it's harmless. The only functionality loss is that the bias command will not work as unfortunately DAC CS and CLK pins are swapped for the bias DAC between the two revisions of the card.
; To do
: fix combinational loops on read-ram register

; Bugs

== Revision 5.0.1 (lab use) ==
; Filename
: bc_v05000001_19jan2010.sof
; Features
: supports the new low-noise bias lines (total of 12) introduced in Bias Card Rev. E
: card_type parameter is set to 5 (bias-card Rev. E)
: All DACs are loaded at once as oppose to previous revisions that loaded them one after next.
: DAC clock is now 25MHz and generated by PLL, previous firmware had 12.5MHz clock generated by dividing down.
; Details
: If this firmware is loaded on a Rev. D card, it's harmless. The only functionality loss is that the bias command will not work as unfortunately DAC CS and CLK pins are swapped for the bias DAC between the two revisions of the card.
; To do
: All ln_bias lines are controlled at once and this should be modified to independent control.
; Bugs
ln_bias_0 doesn't work, because the data line for ln_bias_0 is not connected in firmware.

== Revision 5.0.0 ==
* '''Filename:''' bc_v05000000_22dec2008.sof (tagged as sys_v05000000_22dec2008)

* '''To Do:'''
* '''Features:'''
** IMPORTANT: Must be used in conjunction with firmware v05000000 of all other cards!!!
** To allow enough data bandwidth, the spare LVDS line from each card to the Clock Card is now used

* '''Details:'''

* '''Bugs:'''
** None yet reported

* '''FPGA Resource Usage''' (bias_card.fit.rpt):
; Fitter Status ; Successful - Wed Jan 14 11:19:37 2009 ;
; Quartus II Version ; 8.1 Build 163 10/28/2008 SJ Full Version ;
; Device ; EP1S10F780C5 ;
; Total logic elements ; 3,356 / 10,570 ( 32 % ) ;
; Total pins ; 187 / 427 ( 44 % ) ;
; Total memory bits ; 70,144 / 920,448 ( 8 % ) ;

* '''Timing Analyzer Summary''' (bias_card.tan.rpt):
; Fast Model Clock Setup: 'bc_pll:pll0|altpll:altpll_component|_clk1' ; 7.060 ns ;
; Fast Model Clock Setup: 'bc_pll:pll0|altpll:altpll_component|_clk0' ; 7.125 ns ;
; Fast Model Clock Hold: 'bc_pll:pll0|altpll:altpll_component|_clk0' ; 0.383 ns ;
; Fast Model Clock Hold: 'bc_pll:pll0|altpll:altpll_component|_clk1' ; 0.384 ns ;
; Fast Model Recovery: 'bc_pll:pll0|altpll:altpll_component|_clk0' ; 16.037 ns ;
; Fast Model Removal: 'bc_pll:pll0|altpll:altpll_component|_clk0' ; 0.575 ns ;
; Total number of failed paths ; ;

== Revision 1.4.2 ==
* bc_v01040002_15jul2008.sof
Features:
* Added the tga_i signal to the sensitivity list for the bc_dac_ctrl FSM
* potential bug may have been introduced with resetting the DAC counter due to inadvertently using the wrong bc_dac_ctrl_core.vhd version.

== Revision 1.4.1 ==
* bc_v01040001_25jan2008.sof

Features:
* Added card_type and scratch commands
* Integrated fw_rev and slot_id as part of all_cards
* Added provisions for safe state machines to fix the reset problem.
* Added lvds_tx = 0 so clock-card can check whether the card is plugged in using this spare lvds line.
Bugs: None so far

= Firmware Links =
* [http://www.phas.ubc.ca/~mce/mcedocs/firmware/ Firmware .sof & .pof Downloads]
* [http://www.phas.ubc.ca/~mce/mcedocs/firmware/bc_fpga_programming_file_catalogue.pdf Bias Card Firmware Catalog]

= Wiki Links =
* [http://e-mode.phas.ubc.ca/mcewiki/index.php/MCE_firmware MCE Firmware Page]
* [http://e-mode.phas.ubc.ca/mcewiki/index.php/Main_Page MCE Main Page]

Bias Card firmware

2011-05-12T18:27:50Z

Bburger: /* Revision 5.0.0 */

* Recommended Firmware Revisions [http://e-mode.phas.ubc.ca/mcewiki/index.php/Compatible_Versions_(CC,RC,BC,AC) here]

== Revision 5.0.6 ==
* '''Filename:''' bc_v05000006_11may2011.sof

* '''To Do:'''
* '''Features:'''
** Changes the timing of loading the FB_COLxx values from 32 clock cycles before the start of a new frame, to at the beginning of a new frame. This firmware was generated to find the reason for the downturn in raw data at the end of rows, as seen by Jeffrey Flilippini: http://spiderwiki.princeton.edu/spider/AnalysisLogbook/TestCryostat/20110427_muxing/index.html

* '''Details:'''

* '''Bugs:'''
** None yet reported

* '''FPGA Resource Usage''' (bias_card.fit.rpt):

* '''Timing Analyzer Summary''' (bias_card.tan.rpt):

== Revision 5.0.5 (recommended) ==
; Filename
: bc_v05000005_20jul2010.sof
; Features
: based on 5.0.4, but updated for Rev. F/D hardware pinout.
: card_type parameter now includes the pcb-revision information as well as the card_type. card_type is specified as 0x01 as the lower byte (same as before). Reading back card_type parameter returns: 0x0F01 in Rev. D cards, and 0x0601 in Rev. F cards. (Previously, reading back card_type parameter only returned 0x01).

; Details
: When using tes_bias lines, make sure the count is 12 for bias parameter in mce.cfg file.
: When installed on Rev. D file, tes_mapping has to have offset =11 in mce.cfg.

; To do
:none
; Bugs
: none
; FPGA Resource Usage
: Total logic elements ; 60%
: M512s ; 49%
: M4Ks ; 100%
: M-RAMs ; 100%

== Revision 5.0.4 (lab use) ==
; Filename
: bc_v05000004_20may2010.sof
; Features
: build based on 5.0.3 for Rev. E cards
: Biases are refreshed 1 clock cycles after the start of a new row, regardless of whether they are running in multiplex mode or not and whether it is a regular bias line or low-noise bias line.
; Details
: '''NOTE''' If this firmware is loaded on a Rev. D card, it's harmless. The only functionality loss is that the '''bias''' command will not work as unfortunately DAC CS and CLK pins are swapped for the bias DAC between the two revisions of the card.
; To do
:none
; Bugs
: none
; FPGA Resource Usage
: Total logic elements ; 60%
: M512s ; 49%
: M4Ks ; 100%
: M-RAMs ; 100%

== Revision 5.0.3 (lab use) ==
; Filename
: bc_v05000003_12may2010.sof
; Features
: build based on 5.0.2 for Rev. E cards
: added '''fb_col0 to fb_col31''' and '''enbl_mux''' commands to accommodate row-based sq2fb switching. When enbl_mux is asserted for a column, then the DAC is refreshed on every row visit with the value specified by fb_col command.
; Details
: The original Bias Card design has a buffer after the DAC that is too slow followed by kHz range RC filters, so in order to enable the multiplexing feature, one has to make sure that the BC hardware is modified as per ECO-xxx (to be added here).
: card_type returns 5 (indicating a Rev. E)
: If this firmware is loaded on a Rev. D card, it's harmless. The only functionality loss is that the bias command will not work as unfortunately DAC CS and CLK pins are swapped for the bias DAC between the two revisions of the card.
: combinational loops present in previous versions are removed now
: There is 9+16*2=41 clock cycle (820ns) delay for the bias to be applied after the start of a new row. This combined with another 400ns delay due to inherent DAC delay is about 60 clock-cycle delay.
; To do
: The excessive 41 clock cycle delay to apply a new bias has to be reduced. It is conceivable to preload the DACs and reduce this delay to 1 to 2 clock cycles.
; Bugs
: none
; FPGA Resource Usage
: Total logic elements ; 6,140 / 10,570 ( 58 % ) ;
: Total memory bits ; 133,120 / 920,448 ( 14 % ) ;
: M512s ; 48 / 94 ( 51 % ) ;
: M4Ks ; 60 / 60 ( 100 % ) ;
: M-RAMs ; 0 / 1 ( 0 % ) ;

== Revision 5.0.2 (lab use) ==
; Filename
: bc_v05000002_xxjan2010.sof
; Features
: build based on 5.0.1 for Rev. E cards
: Independent control for ln_bias lines 0 to 11
; Details
: If this firmware is loaded on a Rev. D card, it's harmless. The only functionality loss is that the bias command will not work as unfortunately DAC CS and CLK pins are swapped for the bias DAC between the two revisions of the card.
; To do
: fix combinational loops on read-ram register

; Bugs

== Revision 5.0.1 (lab use) ==
; Filename
: bc_v05000001_19jan2010.sof
; Features
: supports the new low-noise bias lines (total of 12) introduced in Bias Card Rev. E
: card_type parameter is set to 5 (bias-card Rev. E)
: All DACs are loaded at once as oppose to previous revisions that loaded them one after next.
: DAC clock is now 25MHz and generated by PLL, previous firmware had 12.5MHz clock generated by dividing down.
; Details
: If this firmware is loaded on a Rev. D card, it's harmless. The only functionality loss is that the bias command will not work as unfortunately DAC CS and CLK pins are swapped for the bias DAC between the two revisions of the card.
; To do
: All ln_bias lines are controlled at once and this should be modified to independent control.
; Bugs
ln_bias_0 doesn't work, because the data line for ln_bias_0 is not connected in firmware.

== Revision 5.0.0 ==
* '''Filename:''' bc_v05000000_22dec2008.sof (tagged as sys_v05000000_22dec2008)

* '''To Do:'''
* '''Features:'''
** IMPORTANT: Must be used in conjunction with firmware v05000000 of all other cards!!!
** To allow enough data bandwidth, the spare LVDS line from each card to the Clock Card is now used

* '''Details:'''

* '''Bugs:'''
** None yet reported

* '''FPGA Resource Usage''' (bias_card.fit.rpt):
; Fitter Status ; Successful - Wed Jan 14 11:19:37 2009 ;
; Quartus II Version ; 8.1 Build 163 10/28/2008 SJ Full Version ;
; Device ; EP1S10F780C5 ;
; Total logic elements ; 3,356 / 10,570 ( 32 % ) ;
; Total pins ; 187 / 427 ( 44 % ) ;
; Total memory bits ; 70,144 / 920,448 ( 8 % ) ;

* '''Timing Analyzer Summary''' (bias_card.tan.rpt):
; Fast Model Clock Setup: 'bc_pll:pll0|altpll:altpll_component|_clk1' ; 7.060 ns ;
; Fast Model Clock Setup: 'bc_pll:pll0|altpll:altpll_component|_clk0' ; 7.125 ns ;
; Fast Model Clock Hold: 'bc_pll:pll0|altpll:altpll_component|_clk0' ; 0.383 ns ;
; Fast Model Clock Hold: 'bc_pll:pll0|altpll:altpll_component|_clk1' ; 0.384 ns ;
; Fast Model Recovery: 'bc_pll:pll0|altpll:altpll_component|_clk0' ; 16.037 ns ;
; Fast Model Removal: 'bc_pll:pll0|altpll:altpll_component|_clk0' ; 0.575 ns ;
; Total number of failed paths ; ;

== Revision 1.4.2 ==
* bc_v01040002_15jul2008.sof
Features:
* Added the tga_i signal to the sensitivity list for the bc_dac_ctrl FSM
* potential bug may have been introduced with resetting the DAC counter due to inadvertently using the wrong bc_dac_ctrl_core.vhd version.

== Revision 1.4.1 ==
* bc_v01040001_25jan2008.sof

Features:
* Added card_type and scratch commands
* Integrated fw_rev and slot_id as part of all_cards
* Added provisions for safe state machines to fix the reset problem.
* Added lvds_tx = 0 so clock-card can check whether the card is plugged in using this spare lvds line.
Bugs: None so far

= Firmware Links =
* [http://www.phas.ubc.ca/~mce/mcedocs/firmware/ Firmware .sof & .pof Downloads]
* [http://www.phas.ubc.ca/~mce/mcedocs/firmware/bc_fpga_programming_file_catalogue.pdf Bias Card Firmware Catalog]

= Wiki Links =
* [http://e-mode.phas.ubc.ca/mcewiki/index.php/MCE_firmware MCE Firmware Page]
* [http://e-mode.phas.ubc.ca/mcewiki/index.php/Main_Page MCE Main Page]

Bias Card firmware

2011-05-12T18:25:34Z

Bburger: /* Revision 5.0.5 (recommended) */

* Recommended Firmware Revisions [http://e-mode.phas.ubc.ca/mcewiki/index.php/Compatible_Versions_(CC,RC,BC,AC) here]

== Revision 5.0.0 ==
* '''Filename:''' bc_v05000006_11may2011.sof

* '''To Do:'''
* '''Features:'''

* '''Details:'''

* '''Bugs:'''
** None yet reported

* '''FPGA Resource Usage''' (bias_card.fit.rpt):

* '''Timing Analyzer Summary''' (bias_card.tan.rpt):

== Revision 5.0.5 (recommended) ==
; Filename
: bc_v05000005_20jul2010.sof
; Features
: based on 5.0.4, but updated for Rev. F/D hardware pinout.
: card_type parameter now includes the pcb-revision information as well as the card_type. card_type is specified as 0x01 as the lower byte (same as before). Reading back card_type parameter returns: 0x0F01 in Rev. D cards, and 0x0601 in Rev. F cards. (Previously, reading back card_type parameter only returned 0x01).

; Details
: When using tes_bias lines, make sure the count is 12 for bias parameter in mce.cfg file.
: When installed on Rev. D file, tes_mapping has to have offset =11 in mce.cfg.

; To do
:none
; Bugs
: none
; FPGA Resource Usage
: Total logic elements ; 60%
: M512s ; 49%
: M4Ks ; 100%
: M-RAMs ; 100%

== Revision 5.0.4 (lab use) ==
; Filename
: bc_v05000004_20may2010.sof
; Features
: build based on 5.0.3 for Rev. E cards
: Biases are refreshed 1 clock cycles after the start of a new row, regardless of whether they are running in multiplex mode or not and whether it is a regular bias line or low-noise bias line.
; Details
: '''NOTE''' If this firmware is loaded on a Rev. D card, it's harmless. The only functionality loss is that the '''bias''' command will not work as unfortunately DAC CS and CLK pins are swapped for the bias DAC between the two revisions of the card.
; To do
:none
; Bugs
: none
; FPGA Resource Usage
: Total logic elements ; 60%
: M512s ; 49%
: M4Ks ; 100%
: M-RAMs ; 100%

== Revision 5.0.3 (lab use) ==
; Filename
: bc_v05000003_12may2010.sof
; Features
: build based on 5.0.2 for Rev. E cards
: added '''fb_col0 to fb_col31''' and '''enbl_mux''' commands to accommodate row-based sq2fb switching. When enbl_mux is asserted for a column, then the DAC is refreshed on every row visit with the value specified by fb_col command.
; Details
: The original Bias Card design has a buffer after the DAC that is too slow followed by kHz range RC filters, so in order to enable the multiplexing feature, one has to make sure that the BC hardware is modified as per ECO-xxx (to be added here).
: card_type returns 5 (indicating a Rev. E)
: If this firmware is loaded on a Rev. D card, it's harmless. The only functionality loss is that the bias command will not work as unfortunately DAC CS and CLK pins are swapped for the bias DAC between the two revisions of the card.
: combinational loops present in previous versions are removed now
: There is 9+16*2=41 clock cycle (820ns) delay for the bias to be applied after the start of a new row. This combined with another 400ns delay due to inherent DAC delay is about 60 clock-cycle delay.
; To do
: The excessive 41 clock cycle delay to apply a new bias has to be reduced. It is conceivable to preload the DACs and reduce this delay to 1 to 2 clock cycles.
; Bugs
: none
; FPGA Resource Usage
: Total logic elements ; 6,140 / 10,570 ( 58 % ) ;
: Total memory bits ; 133,120 / 920,448 ( 14 % ) ;
: M512s ; 48 / 94 ( 51 % ) ;
: M4Ks ; 60 / 60 ( 100 % ) ;
: M-RAMs ; 0 / 1 ( 0 % ) ;

== Revision 5.0.2 (lab use) ==
; Filename
: bc_v05000002_xxjan2010.sof
; Features
: build based on 5.0.1 for Rev. E cards
: Independent control for ln_bias lines 0 to 11
; Details
: If this firmware is loaded on a Rev. D card, it's harmless. The only functionality loss is that the bias command will not work as unfortunately DAC CS and CLK pins are swapped for the bias DAC between the two revisions of the card.
; To do
: fix combinational loops on read-ram register

; Bugs

== Revision 5.0.1 (lab use) ==
; Filename
: bc_v05000001_19jan2010.sof
; Features
: supports the new low-noise bias lines (total of 12) introduced in Bias Card Rev. E
: card_type parameter is set to 5 (bias-card Rev. E)
: All DACs are loaded at once as oppose to previous revisions that loaded them one after next.
: DAC clock is now 25MHz and generated by PLL, previous firmware had 12.5MHz clock generated by dividing down.
; Details
: If this firmware is loaded on a Rev. D card, it's harmless. The only functionality loss is that the bias command will not work as unfortunately DAC CS and CLK pins are swapped for the bias DAC between the two revisions of the card.
; To do
: All ln_bias lines are controlled at once and this should be modified to independent control.
; Bugs
ln_bias_0 doesn't work, because the data line for ln_bias_0 is not connected in firmware.

== Revision 5.0.0 ==
* '''Filename:''' bc_v05000000_22dec2008.sof (tagged as sys_v05000000_22dec2008)

* '''To Do:'''
* '''Features:'''
** IMPORTANT: Must be used in conjunction with firmware v05000000 of all other cards!!!
** To allow enough data bandwidth, the spare LVDS line from each card to the Clock Card is now used

* '''Details:'''

* '''Bugs:'''
** None yet reported

* '''FPGA Resource Usage''' (bias_card.fit.rpt):
; Fitter Status ; Successful - Wed Jan 14 11:19:37 2009 ;
; Quartus II Version ; 8.1 Build 163 10/28/2008 SJ Full Version ;
; Device ; EP1S10F780C5 ;
; Total logic elements ; 3,356 / 10,570 ( 32 % ) ;
; Total pins ; 187 / 427 ( 44 % ) ;
; Total memory bits ; 70,144 / 920,448 ( 8 % ) ;

* '''Timing Analyzer Summary''' (bias_card.tan.rpt):
; Fast Model Clock Setup: 'bc_pll:pll0|altpll:altpll_component|_clk1' ; 7.060 ns ;
; Fast Model Clock Setup: 'bc_pll:pll0|altpll:altpll_component|_clk0' ; 7.125 ns ;
; Fast Model Clock Hold: 'bc_pll:pll0|altpll:altpll_component|_clk0' ; 0.383 ns ;
; Fast Model Clock Hold: 'bc_pll:pll0|altpll:altpll_component|_clk1' ; 0.384 ns ;
; Fast Model Recovery: 'bc_pll:pll0|altpll:altpll_component|_clk0' ; 16.037 ns ;
; Fast Model Removal: 'bc_pll:pll0|altpll:altpll_component|_clk0' ; 0.575 ns ;
; Total number of failed paths ; ;

== Revision 1.4.2 ==
* bc_v01040002_15jul2008.sof
Features:
* Added the tga_i signal to the sensitivity list for the bc_dac_ctrl FSM
* potential bug may have been introduced with resetting the DAC counter due to inadvertently using the wrong bc_dac_ctrl_core.vhd version.

== Revision 1.4.1 ==
* bc_v01040001_25jan2008.sof

Features:
* Added card_type and scratch commands
* Integrated fw_rev and slot_id as part of all_cards
* Added provisions for safe state machines to fix the reset problem.
* Added lvds_tx = 0 so clock-card can check whether the card is plugged in using this spare lvds line.
Bugs: None so far

= Firmware Links =
* [http://www.phas.ubc.ca/~mce/mcedocs/firmware/ Firmware .sof & .pof Downloads]
* [http://www.phas.ubc.ca/~mce/mcedocs/firmware/bc_fpga_programming_file_catalogue.pdf Bias Card Firmware Catalog]

= Wiki Links =
* [http://e-mode.phas.ubc.ca/mcewiki/index.php/MCE_firmware MCE Firmware Page]
* [http://e-mode.phas.ubc.ca/mcewiki/index.php/Main_Page MCE Main Page]

Quartus II Installation

2011-05-09T20:30:27Z

Bburger:

= Quartus II Programmer for Windows (For Programming the MCE) =
* If you are planning to use Altera-supplied hardware (e.g. USB-Blaster) to upgrade the MCE firmware, you need to install "'''Quartus Programmer'''" on either a Windows or Linux PC.
* See the OS requirements here: http://www.altera.com/download/os-support/oss-index.html 
* Download Quartus here: https://www.altera.com/download/programming/quartus2/pq2-index.jsp
* Note that the installer needs direct access to Quartus website. In case you are behind a firewall, you may need to setup a proxy server.
* The installation is straight forward. After installation is complete, plug in the USB-Blaster and the driver is typically found under altera/10.0/quartus/driver.

= Quartus II for Windows (For Synthesizing MCE Firmware) =
* In a web browser, browse to ftp://ftp.altera.com/outgoing/release/
* Filenames to look for are of the form "91sp1_quartus_free.exe" if you don't have a license, or "91sp1_quartus_windows.exe" if you have a license.
* Download the appropriate file.
* Double click on 'XX_quartus_windows.exe' and follow the extraction and installation instructions.

= Quartus II for Linux =
As usual, only RedHat and Seuse are officially supported and you are on your own if you install it on any other Linux distribution.

== Troubleshooting Ubuntu Installation ==
Quartus 10.0 installed fine on Ubuntu and no tweaking was needed.

However, when installing Quartus 9.1 the installer couldn't find a few commands that typically exist on Fedora systems, notably ''arch'' and ''rpm''. You can create a fake version of these and copy them under /usr/bin.
* Create a script called ''arch'' that contains:
uname -m
* Create a script called ''rpm'' that contains:
#!/bin/bash
OUT=/home/mce/rpm_cmd.txt
date >> $OUT
echo $@ >> $OUT
Make sure the permissions are set to executable.

More tips here: http://fpga4u.epfl.ch/wiki/Install_Quartus_II#On_Linux

== Launching Quartus ==
After installation is complete, add the Quartus path to $PATH (probably in .bashrc), e.g.:
PATH=$PATH:/opt/usr/local/lib/altera/10.0/quartus/bin
export PATH

== License Manager ==
If you have only installed '''Quartus Programmer or Quartus II web edition''', the following section '''does NOT''' apply to you. However, if you have installed the "Quartus Subscription Edition", then continue reading.

You need to have a license file from Altera. The license file needs to be modified as follows. Change the top few lines from:
SERVER <hostname> 001e90151053 <port number>
VENDOR alterad <path to daemon executable>
VENDOR mgcld <path to daemon executable>
USE_SERVER
to
SERVER mce-ubc-2 001e90151053 1700
DAEMON alterad /opt/altera91/quartus/linux64/alterad
DAEMON mgcld /opt/altera91/modelsim_ase/linux/mgls/lib/mgcld
USE_SERVER

Copy the license file in /opt/licenses/quartus_001e90151053.dat

The license manager can be invoked by:
sudo /opt/altera10.0sp1/quartus/linux/lmgrd -c /opt/licenses/quartus_001e90151053.dat

You can add this line (without the sudo) into /etc/rc.local to get it to start whenever the computer boots.

When this works, it should spit out messages like this:
8:38:25 (lmgrd) Started alterad (internet tcp_port 52255 pid 28888)
8:38:25 (lmgrd) Started mgcld (internet tcp_port 54712 pid 28889)
8:38:25 (alterad) FLEXlm version 9.50
8:38:25 (alterad) lmgrd version 11.4, alterad version 9.5

8:38:25 (mgcld) FLEXnet Licensing version v10.8.5.0 build 31891 i86_r6
8:38:25 (mgcld) lmgrd version 11.4, mgcld version 10.8

8:38:25 (mgcld) Server started on mce-ubc-2 for: alteramtivsim
8:38:25 (mgcld)
8:38:25 (mgcld) Licenses are case sensitive for mgcld
8:38:25 (mgcld)
8:38:25 (mgcld) EXTERNAL FILTERS are OFF
8:38:25 (lmgrd) mgcld using TCP-port 54712
8:38:25 (alterad) Server started on mce-ubc-2 for: maxplus2
8:38:25 (alterad) quartus 6AF7_0012 6AF7_0014
8:38:25 (alterad) 6AF7_0055 6AF7_00A7 6AF7_00A8
8:38:25 (alterad) 6AF7_00A4 6AF7_0034 6AF7_00AC
8:38:25 (alterad) 6AF7_00AD 6AF7_00BE 6AF7_00BF
8:38:25 (alterad) 6AF7_00C2 maxplus2verilog maxplus2vhdl
8:38:25 (alterad) altera_mainwin_lnx altera_mainwin 6AF8_00A2
8:38:25 (alterad) 6AF7_00A2

Quartus II Installation

2011-05-09T19:50:15Z

Bburger: /* Quartus II for Windows (For Synthesizing MCE Firmware) */

= Quartus II Programmer for Windows (For Loading MCE Firmware) =
* If you are planning to use Altera-supplied hardware (e.g. USB-Blaster) to upgrade the MCE firmware, you need to install "'''Quartus Programmer'''" on either a Windows or Linux PC.
* See the OS requirements here: http://www.altera.com/download/os-support/oss-index.html 
* Download Quartus here: https://www.altera.com/download/programming/quartus2/pq2-index.jsp
* Note that the installer needs direct access to Quartus website. In case you are behind a firewall, you may need to setup a proxy server.
* The installation is straight forward. After installation is complete, plug in the USB-Blaster and the driver is typically found under altera/10.0/quartus/driver.

= Quartus II for Windows (For Synthesizing MCE Firmware) =
* In a web browser, browse to ftp://ftp.altera.com/outgoing/release/
* Filenames to look for are of the form "91sp1_quartus_free.exe" if you don't have a license, or "91sp1_quartus_windows.exe" if you have a license.
* Download the appropriate file.
* Double click on 'XX_quartus_windows.exe' and follow the extraction and installation instructions.

= Quartus II for Linux =
As usual, only RedHat and Seuse are officially supported and you are on your own if you install it on any other Linux distribution.

== Troubleshooting Ubuntu Installation ==
Quartus 10.0 installed fine on Ubuntu and no tweaking was needed.

However, when installing Quartus 9.1 the installer couldn't find a few commands that typically exist on Fedora systems, notably ''arch'' and ''rpm''. You can create a fake version of these and copy them under /usr/bin.
* Create a script called ''arch'' that contains:
uname -m
* Create a script called ''rpm'' that contains:
#!/bin/bash
OUT=/home/mce/rpm_cmd.txt
date >> $OUT
echo $@ >> $OUT
Make sure the permissions are set to executable.

More tips here: http://fpga4u.epfl.ch/wiki/Install_Quartus_II#On_Linux

== Launching Quartus ==
After installation is complete, add the Quartus path to $PATH (probably in .bashrc), e.g.:
PATH=$PATH:/opt/usr/local/lib/altera/10.0/quartus/bin
export PATH

== License Manager ==
If you have only installed '''Quartus Programmer or Quartus II web edition''', the following section '''does NOT''' apply to you. However, if you have installed the "Quartus Subscription Edition", then continue reading.

You need to have a license file from Altera. The license file needs to be modified as follows. Change the top few lines from:
SERVER <hostname> 001e90151053 <port number>
VENDOR alterad <path to daemon executable>
VENDOR mgcld <path to daemon executable>
USE_SERVER
to
SERVER mce-ubc-2 001e90151053 1700
DAEMON alterad /opt/altera91/quartus/linux64/alterad
DAEMON mgcld /opt/altera91/modelsim_ase/linux/mgls/lib/mgcld
USE_SERVER

Copy the license file in /opt/licenses/quartus_001e90151053.dat

The license manager can be invoked by:
sudo /opt/altera10.0sp1/quartus/linux/lmgrd -c /opt/licenses/quartus_001e90151053.dat

You can add this line (without the sudo) into /etc/rc.local to get it to start whenever the computer boots.

When this works, it should spit out messages like this:
8:38:25 (lmgrd) Started alterad (internet tcp_port 52255 pid 28888)
8:38:25 (lmgrd) Started mgcld (internet tcp_port 54712 pid 28889)
8:38:25 (alterad) FLEXlm version 9.50
8:38:25 (alterad) lmgrd version 11.4, alterad version 9.5

8:38:25 (mgcld) FLEXnet Licensing version v10.8.5.0 build 31891 i86_r6
8:38:25 (mgcld) lmgrd version 11.4, mgcld version 10.8

8:38:25 (mgcld) Server started on mce-ubc-2 for: alteramtivsim
8:38:25 (mgcld)
8:38:25 (mgcld) Licenses are case sensitive for mgcld
8:38:25 (mgcld)
8:38:25 (mgcld) EXTERNAL FILTERS are OFF
8:38:25 (lmgrd) mgcld using TCP-port 54712
8:38:25 (alterad) Server started on mce-ubc-2 for: maxplus2
8:38:25 (alterad) quartus 6AF7_0012 6AF7_0014
8:38:25 (alterad) 6AF7_0055 6AF7_00A7 6AF7_00A8
8:38:25 (alterad) 6AF7_00A4 6AF7_0034 6AF7_00AC
8:38:25 (alterad) 6AF7_00AD 6AF7_00BE 6AF7_00BF
8:38:25 (alterad) 6AF7_00C2 maxplus2verilog maxplus2vhdl
8:38:25 (alterad) altera_mainwin_lnx altera_mainwin 6AF8_00A2
8:38:25 (alterad) 6AF7_00A2

Quartus II Installation

2011-05-09T19:49:09Z

Bburger: /* Quartus II for Windows */

= Quartus II Programmer for Windows (For Loading MCE Firmware) =
* If you are planning to use Altera-supplied hardware (e.g. USB-Blaster) to upgrade the MCE firmware, you need to install "'''Quartus Programmer'''" on either a Windows or Linux PC.
* See the OS requirements here: http://www.altera.com/download/os-support/oss-index.html 
* Download Quartus here: https://www.altera.com/download/programming/quartus2/pq2-index.jsp
* Note that the installer needs direct access to Quartus website. In case you are behind a firewall, you may need to setup a proxy server.
* The installation is straight forward. After installation is complete, plug in the USB-Blaster and the driver is typically found under altera/10.0/quartus/driver.

= Quartus II for Windows (For Synthesizing MCE Firmware) =
* In a web browser, browse to ftp://ftp.altera.com/outgoing/release/
* Filenames to look for are of the form "91sp1_quartus_free.exe" if you don't have a license, or "91sp1_quartus_windows.exe" if you have a license.
* Double click on 'XX_quartus_windows.exe' and follow the extraction and installation instructions.

= Quartus II for Linux =
As usual, only RedHat and Seuse are officially supported and you are on your own if you install it on any other Linux distribution.

== Troubleshooting Ubuntu Installation ==
Quartus 10.0 installed fine on Ubuntu and no tweaking was needed.

However, when installing Quartus 9.1 the installer couldn't find a few commands that typically exist on Fedora systems, notably ''arch'' and ''rpm''. You can create a fake version of these and copy them under /usr/bin.
* Create a script called ''arch'' that contains:
uname -m
* Create a script called ''rpm'' that contains:
#!/bin/bash
OUT=/home/mce/rpm_cmd.txt
date >> $OUT
echo $@ >> $OUT
Make sure the permissions are set to executable.

More tips here: http://fpga4u.epfl.ch/wiki/Install_Quartus_II#On_Linux

== Launching Quartus ==
After installation is complete, add the Quartus path to $PATH (probably in .bashrc), e.g.:
PATH=$PATH:/opt/usr/local/lib/altera/10.0/quartus/bin
export PATH

== License Manager ==
If you have only installed '''Quartus Programmer or Quartus II web edition''', the following section '''does NOT''' apply to you. However, if you have installed the "Quartus Subscription Edition", then continue reading.

You need to have a license file from Altera. The license file needs to be modified as follows. Change the top few lines from:
SERVER <hostname> 001e90151053 <port number>
VENDOR alterad <path to daemon executable>
VENDOR mgcld <path to daemon executable>
USE_SERVER
to
SERVER mce-ubc-2 001e90151053 1700
DAEMON alterad /opt/altera91/quartus/linux64/alterad
DAEMON mgcld /opt/altera91/modelsim_ase/linux/mgls/lib/mgcld
USE_SERVER

Copy the license file in /opt/licenses/quartus_001e90151053.dat

The license manager can be invoked by:
sudo /opt/altera10.0sp1/quartus/linux/lmgrd -c /opt/licenses/quartus_001e90151053.dat

You can add this line (without the sudo) into /etc/rc.local to get it to start whenever the computer boots.

When this works, it should spit out messages like this:
8:38:25 (lmgrd) Started alterad (internet tcp_port 52255 pid 28888)
8:38:25 (lmgrd) Started mgcld (internet tcp_port 54712 pid 28889)
8:38:25 (alterad) FLEXlm version 9.50
8:38:25 (alterad) lmgrd version 11.4, alterad version 9.5

8:38:25 (mgcld) FLEXnet Licensing version v10.8.5.0 build 31891 i86_r6
8:38:25 (mgcld) lmgrd version 11.4, mgcld version 10.8

8:38:25 (mgcld) Server started on mce-ubc-2 for: alteramtivsim
8:38:25 (mgcld)
8:38:25 (mgcld) Licenses are case sensitive for mgcld
8:38:25 (mgcld)
8:38:25 (mgcld) EXTERNAL FILTERS are OFF
8:38:25 (lmgrd) mgcld using TCP-port 54712
8:38:25 (alterad) Server started on mce-ubc-2 for: maxplus2
8:38:25 (alterad) quartus 6AF7_0012 6AF7_0014
8:38:25 (alterad) 6AF7_0055 6AF7_00A7 6AF7_00A8
8:38:25 (alterad) 6AF7_00A4 6AF7_0034 6AF7_00AC
8:38:25 (alterad) 6AF7_00AD 6AF7_00BE 6AF7_00BF
8:38:25 (alterad) 6AF7_00C2 maxplus2verilog maxplus2vhdl
8:38:25 (alterad) altera_mainwin_lnx altera_mainwin 6AF8_00A2
8:38:25 (alterad) 6AF7_00A2

Quartus II Installation

2011-05-09T19:48:52Z

Bburger: /* Quartus II Programmer for Windows */

= Quartus II Programmer for Windows (For Loading MCE Firmware) =
* If you are planning to use Altera-supplied hardware (e.g. USB-Blaster) to upgrade the MCE firmware, you need to install "'''Quartus Programmer'''" on either a Windows or Linux PC.
* See the OS requirements here: http://www.altera.com/download/os-support/oss-index.html 
* Download Quartus here: https://www.altera.com/download/programming/quartus2/pq2-index.jsp
* Note that the installer needs direct access to Quartus website. In case you are behind a firewall, you may need to setup a proxy server.
* The installation is straight forward. After installation is complete, plug in the USB-Blaster and the driver is typically found under altera/10.0/quartus/driver.

= Quartus II for Windows =
* In a web browser, browse to ftp://ftp.altera.com/outgoing/release/
* Filenames to look for are of the form "91sp1_quartus_free.exe" if you don't have a license, or "91sp1_quartus_windows.exe" if you have a license.
* Double click on 'XX_quartus_windows.exe' and follow the extraction and installation instructions.

= Quartus II for Linux =
As usual, only RedHat and Seuse are officially supported and you are on your own if you install it on any other Linux distribution.

== Troubleshooting Ubuntu Installation ==
Quartus 10.0 installed fine on Ubuntu and no tweaking was needed.

However, when installing Quartus 9.1 the installer couldn't find a few commands that typically exist on Fedora systems, notably ''arch'' and ''rpm''. You can create a fake version of these and copy them under /usr/bin.
* Create a script called ''arch'' that contains:
uname -m
* Create a script called ''rpm'' that contains:
#!/bin/bash
OUT=/home/mce/rpm_cmd.txt
date >> $OUT
echo $@ >> $OUT
Make sure the permissions are set to executable.

More tips here: http://fpga4u.epfl.ch/wiki/Install_Quartus_II#On_Linux

== Launching Quartus ==
After installation is complete, add the Quartus path to $PATH (probably in .bashrc), e.g.:
PATH=$PATH:/opt/usr/local/lib/altera/10.0/quartus/bin
export PATH

== License Manager ==
If you have only installed '''Quartus Programmer or Quartus II web edition''', the following section '''does NOT''' apply to you. However, if you have installed the "Quartus Subscription Edition", then continue reading.

You need to have a license file from Altera. The license file needs to be modified as follows. Change the top few lines from:
SERVER <hostname> 001e90151053 <port number>
VENDOR alterad <path to daemon executable>
VENDOR mgcld <path to daemon executable>
USE_SERVER
to
SERVER mce-ubc-2 001e90151053 1700
DAEMON alterad /opt/altera91/quartus/linux64/alterad
DAEMON mgcld /opt/altera91/modelsim_ase/linux/mgls/lib/mgcld
USE_SERVER

Copy the license file in /opt/licenses/quartus_001e90151053.dat

The license manager can be invoked by:
sudo /opt/altera10.0sp1/quartus/linux/lmgrd -c /opt/licenses/quartus_001e90151053.dat

You can add this line (without the sudo) into /etc/rc.local to get it to start whenever the computer boots.

When this works, it should spit out messages like this:
8:38:25 (lmgrd) Started alterad (internet tcp_port 52255 pid 28888)
8:38:25 (lmgrd) Started mgcld (internet tcp_port 54712 pid 28889)
8:38:25 (alterad) FLEXlm version 9.50
8:38:25 (alterad) lmgrd version 11.4, alterad version 9.5

8:38:25 (mgcld) FLEXnet Licensing version v10.8.5.0 build 31891 i86_r6
8:38:25 (mgcld) lmgrd version 11.4, mgcld version 10.8

8:38:25 (mgcld) Server started on mce-ubc-2 for: alteramtivsim
8:38:25 (mgcld)
8:38:25 (mgcld) Licenses are case sensitive for mgcld
8:38:25 (mgcld)
8:38:25 (mgcld) EXTERNAL FILTERS are OFF
8:38:25 (lmgrd) mgcld using TCP-port 54712
8:38:25 (alterad) Server started on mce-ubc-2 for: maxplus2
8:38:25 (alterad) quartus 6AF7_0012 6AF7_0014
8:38:25 (alterad) 6AF7_0055 6AF7_00A7 6AF7_00A8
8:38:25 (alterad) 6AF7_00A4 6AF7_0034 6AF7_00AC
8:38:25 (alterad) 6AF7_00AD 6AF7_00BE 6AF7_00BF
8:38:25 (alterad) 6AF7_00C2 maxplus2verilog maxplus2vhdl
8:38:25 (alterad) altera_mainwin_lnx altera_mainwin 6AF8_00A2
8:38:25 (alterad) 6AF7_00A2

Quartus II Installation

2011-05-09T19:47:46Z

Bburger:

= Quartus II Programmer for Windows =
* If you are planning to use Altera-supplied hardware (e.g. USB-Blaster) to upgrade the MCE firmware, you need to install "'''Quartus Programmer'''" on either a Windows or Linux PC.
* See the OS requirements here: http://www.altera.com/download/os-support/oss-index.html 
* Download Quartus here: https://www.altera.com/download/programming/quartus2/pq2-index.jsp
* Note that the installer needs direct access to Quartus website. In case you are behind a firewall, you may need to setup a proxy server.
* The installation is straight forward. After installation is complete, plug in the USB-Blaster and the driver is typically found under altera/10.0/quartus/driver.

= Quartus II for Windows =
* In a web browser, browse to ftp://ftp.altera.com/outgoing/release/
* Filenames to look for are of the form "91sp1_quartus_free.exe" if you don't have a license, or "91sp1_quartus_windows.exe" if you have a license.
* Double click on 'XX_quartus_windows.exe' and follow the extraction and installation instructions.

= Quartus II for Linux =
As usual, only RedHat and Seuse are officially supported and you are on your own if you install it on any other Linux distribution.

== Troubleshooting Ubuntu Installation ==
Quartus 10.0 installed fine on Ubuntu and no tweaking was needed.

However, when installing Quartus 9.1 the installer couldn't find a few commands that typically exist on Fedora systems, notably ''arch'' and ''rpm''. You can create a fake version of these and copy them under /usr/bin.
* Create a script called ''arch'' that contains:
uname -m
* Create a script called ''rpm'' that contains:
#!/bin/bash
OUT=/home/mce/rpm_cmd.txt
date >> $OUT
echo $@ >> $OUT
Make sure the permissions are set to executable.

More tips here: http://fpga4u.epfl.ch/wiki/Install_Quartus_II#On_Linux

== Launching Quartus ==
After installation is complete, add the Quartus path to $PATH (probably in .bashrc), e.g.:
PATH=$PATH:/opt/usr/local/lib/altera/10.0/quartus/bin
export PATH

== License Manager ==
If you have only installed '''Quartus Programmer or Quartus II web edition''', the following section '''does NOT''' apply to you. However, if you have installed the "Quartus Subscription Edition", then continue reading.

You need to have a license file from Altera. The license file needs to be modified as follows. Change the top few lines from:
SERVER <hostname> 001e90151053 <port number>
VENDOR alterad <path to daemon executable>
VENDOR mgcld <path to daemon executable>
USE_SERVER
to
SERVER mce-ubc-2 001e90151053 1700
DAEMON alterad /opt/altera91/quartus/linux64/alterad
DAEMON mgcld /opt/altera91/modelsim_ase/linux/mgls/lib/mgcld
USE_SERVER

Copy the license file in /opt/licenses/quartus_001e90151053.dat

The license manager can be invoked by:
sudo /opt/altera10.0sp1/quartus/linux/lmgrd -c /opt/licenses/quartus_001e90151053.dat

You can add this line (without the sudo) into /etc/rc.local to get it to start whenever the computer boots.

When this works, it should spit out messages like this:
8:38:25 (lmgrd) Started alterad (internet tcp_port 52255 pid 28888)
8:38:25 (lmgrd) Started mgcld (internet tcp_port 54712 pid 28889)
8:38:25 (alterad) FLEXlm version 9.50
8:38:25 (alterad) lmgrd version 11.4, alterad version 9.5

8:38:25 (mgcld) FLEXnet Licensing version v10.8.5.0 build 31891 i86_r6
8:38:25 (mgcld) lmgrd version 11.4, mgcld version 10.8

8:38:25 (mgcld) Server started on mce-ubc-2 for: alteramtivsim
8:38:25 (mgcld)
8:38:25 (mgcld) Licenses are case sensitive for mgcld
8:38:25 (mgcld)
8:38:25 (mgcld) EXTERNAL FILTERS are OFF
8:38:25 (lmgrd) mgcld using TCP-port 54712
8:38:25 (alterad) Server started on mce-ubc-2 for: maxplus2
8:38:25 (alterad) quartus 6AF7_0012 6AF7_0014
8:38:25 (alterad) 6AF7_0055 6AF7_00A7 6AF7_00A8
8:38:25 (alterad) 6AF7_00A4 6AF7_0034 6AF7_00AC
8:38:25 (alterad) 6AF7_00AD 6AF7_00BE 6AF7_00BF
8:38:25 (alterad) 6AF7_00C2 maxplus2verilog maxplus2vhdl
8:38:25 (alterad) altera_mainwin_lnx altera_mainwin 6AF8_00A2
8:38:25 (alterad) 6AF7_00A2

Quartus II Installation

2011-05-09T19:47:30Z

Bburger:

= Quartus II Programmer for Windows =
* If you are planning to use Altera-supplied hardware (e.g. USB-Blaster) to upgrade the MCE firmware, you need to install "'''Quartus Programmer'''" on either a Windows or Linux PC.
* See the OS requirements here: http://www.altera.com/download/os-support/oss-index.html 
Download Quartus here: https://www.altera.com/download/programming/quartus2/pq2-index.jsp
* Note that the installer needs direct access to Quartus website. In case you are behind a firewall, you may need to setup a proxy server.
* The installation is straight forward. After installation is complete, plug in the USB-Blaster and the driver is typically found under altera/10.0/quartus/driver.

= Quartus II for Windows =
* In a web browser, browse to ftp://ftp.altera.com/outgoing/release/
* Filenames to look for are of the form "91sp1_quartus_free.exe" if you don't have a license, or "91sp1_quartus_windows.exe" if you have a license.
* Double click on 'XX_quartus_windows.exe' and follow the extraction and installation instructions.

= Quartus II for Linux =
As usual, only RedHat and Seuse are officially supported and you are on your own if you install it on any other Linux distribution.

== Troubleshooting Ubuntu Installation ==
Quartus 10.0 installed fine on Ubuntu and no tweaking was needed.

However, when installing Quartus 9.1 the installer couldn't find a few commands that typically exist on Fedora systems, notably ''arch'' and ''rpm''. You can create a fake version of these and copy them under /usr/bin.
* Create a script called ''arch'' that contains:
uname -m
* Create a script called ''rpm'' that contains:
#!/bin/bash
OUT=/home/mce/rpm_cmd.txt
date >> $OUT
echo $@ >> $OUT
Make sure the permissions are set to executable.

More tips here: http://fpga4u.epfl.ch/wiki/Install_Quartus_II#On_Linux

== Launching Quartus ==
After installation is complete, add the Quartus path to $PATH (probably in .bashrc), e.g.:
PATH=$PATH:/opt/usr/local/lib/altera/10.0/quartus/bin
export PATH

== License Manager ==
If you have only installed '''Quartus Programmer or Quartus II web edition''', the following section '''does NOT''' apply to you. However, if you have installed the "Quartus Subscription Edition", then continue reading.

You need to have a license file from Altera. The license file needs to be modified as follows. Change the top few lines from:
SERVER <hostname> 001e90151053 <port number>
VENDOR alterad <path to daemon executable>
VENDOR mgcld <path to daemon executable>
USE_SERVER
to
SERVER mce-ubc-2 001e90151053 1700
DAEMON alterad /opt/altera91/quartus/linux64/alterad
DAEMON mgcld /opt/altera91/modelsim_ase/linux/mgls/lib/mgcld
USE_SERVER

Copy the license file in /opt/licenses/quartus_001e90151053.dat

The license manager can be invoked by:
sudo /opt/altera10.0sp1/quartus/linux/lmgrd -c /opt/licenses/quartus_001e90151053.dat

You can add this line (without the sudo) into /etc/rc.local to get it to start whenever the computer boots.

When this works, it should spit out messages like this:
8:38:25 (lmgrd) Started alterad (internet tcp_port 52255 pid 28888)
8:38:25 (lmgrd) Started mgcld (internet tcp_port 54712 pid 28889)
8:38:25 (alterad) FLEXlm version 9.50
8:38:25 (alterad) lmgrd version 11.4, alterad version 9.5

8:38:25 (mgcld) FLEXnet Licensing version v10.8.5.0 build 31891 i86_r6
8:38:25 (mgcld) lmgrd version 11.4, mgcld version 10.8

8:38:25 (mgcld) Server started on mce-ubc-2 for: alteramtivsim
8:38:25 (mgcld)
8:38:25 (mgcld) Licenses are case sensitive for mgcld
8:38:25 (mgcld)
8:38:25 (mgcld) EXTERNAL FILTERS are OFF
8:38:25 (lmgrd) mgcld using TCP-port 54712
8:38:25 (alterad) Server started on mce-ubc-2 for: maxplus2
8:38:25 (alterad) quartus 6AF7_0012 6AF7_0014
8:38:25 (alterad) 6AF7_0055 6AF7_00A7 6AF7_00A8
8:38:25 (alterad) 6AF7_00A4 6AF7_0034 6AF7_00AC
8:38:25 (alterad) 6AF7_00AD 6AF7_00BE 6AF7_00BF
8:38:25 (alterad) 6AF7_00C2 maxplus2verilog maxplus2vhdl
8:38:25 (alterad) altera_mainwin_lnx altera_mainwin 6AF8_00A2
8:38:25 (alterad) 6AF7_00A2

Readout Card firmware

2011-05-04T22:04:41Z

Bburger: /* Revision 5.0.c (not recommended) */

* Synthesis Reminders (for firmware developers)
** quartus.ini is not needed anymore (Fixed as of Q7, Altera SR10783580 2010-10-24)
** Remember that readout_card/fsfb_clac/source/rtl/ram_40x64.vhd must be initialized with the ram_40x64.hex file in the same directory.
= Revision 5.1.2 =
* '''Filename:'''
** rc_stratix3_v05010002_18jan2011.sof (for Rev. E cards)
** rc_stratix3_v05010002_18jan2011.jic (for Rev. E cards)
** rc_v05010002_03feb2011.sof (for Rev. B cards)
** rc_v05010002_03feb2011.pof (for Rev. B cards)

* '''Features:'''
** based on 5.1.1 with k1 and k2 (filter params) limited to k1<16 and k2<32 in order to resolve the timing when compiling for smaller Stratix FPGA on RC Rev. B.

* '''Bug fix:'''
** the 2-rows-off filtered data readout introduced with configurable filter in rev. 5.1.0 and 5.1.1 is fixed now.

* '''Bugs:'''
** none so far.

* '''FPGA Resource Usage''' (readout_card.fit.rpt, rev. B)
; Total logic elements ; 33,285 / 41,250 ( 81 % ) ;
; Total pins ; 358 / 616 ( 58 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt, rev. B)
; Fast Model Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 6.591 ns
; Fast Model Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 7.206 ns
; Fast Model Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 18.299 ns

== Revision 5.1.1 (not recommended) ==
* '''Filename:'''
** rc_v05010001_01dec2010.sof (for Rev. B cards)

* '''Features:'''
** based on 5.1.0, but k1 and k2 (filter params) are now limited to k1<16 and k2<32 in order to resolve the timing failures of compiling 5.1.0 for smaller Stratix FPGA on RC Rev. B.

* '''Bugs:'''
** filter mode data is off by 2 rows.

== Revision 5.1.0 (not recommended) ==
* '''Filename:'''
** rc_stratix3_v05010000_01nov2010.sof (for Rev. E cards)
** rc_v05010000_01nov2010.sof (for Rev. B cards) has timing failures '''do not use!!!'''

* '''Features:'''
** added configurable filter parameters specified by ''fltr_coeff'', default is the fcutoff/fsampl=122Hz/15kHz. see [[ Digital 4-pole Butterworth Low-pass filter ]].
** ''fltr_type'' is set to 255 to indicate configurable filter parameters.
** see [http://www.phas.ubc.ca/~mce/mcedocs/software/SC2_ELE_S580_515_mce_command_description.pdf MCE command description]
* '''Details'''
** It is built on Quartus10.1.
** tcl files had to be updated as cmp syntax is not supported in Q10 anymore.
** Rev. E cards now can be identified by reading back pcb_rev as part of card_type, therefore both stratix I and III sof/pof/jic are generated from the same source.

* '''Bugs:'''
** rc_v05010000_01nov2010.sof has timing failures that were overlooked, do not use this firmware for Rev.B cards.
** '''filter mode data is off by 2 rows.'''

* '''FPGA Resource Usage and Timing Report''' (readout_card.fit.rpt and readout_card.tan.rpt): logic usage is upto 85% from 66% in 5.0.d/e/f

= Revision 5.0.f =
* '''Filename:'''
** rc_v0500000f_22oct2010.sof (for Rev. B cards)
** rc_stratix3_v0500000f_22oct2010.sof (for Rev. E cards)

* '''Features:'''
** Bugfix: integral clamp should work now. only positive integral_clamp values are valid!

* '''Details:''':
** SQ1FB is applied 18 clock cycles after start of a row visit (SQ1_Bias being applied) regardless of flux-jump being enabled or not. In pre-5.0.b firmware SQ1FB was being applied after 7 clock cycles when flux-jump was disabled and after 18 clock cycles when flux-jump was enabled.
** available for both Rev. E and Rev. B cards, the upper byte of card_type parameter now reports the pcb revision.
** development note: It is built on Quartus10.1.

* '''Bugs:'''
**none yet!

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 27,377 / 41,250 ( 66 % ) ;
; Total pins ; 358 / 616 ( 58 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.652 ns
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.385 ns
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.860 ns

== Revision 5.0.e (not recommended) ==
* '''Filename:'''
** rc_v0500000e_06oct2010.sof

* '''Details:'''
** an unsuccessful attempt to fix integral_clamp, but changed the functionality so that it clamps at the value, but it doesn't hold the clamp. i.e., if the calculated sq1fb becomes less than the specified clamp value, the sq1fb is not clamped anymore. This is not a desired functionality!

== Revision 5.0.d (not recommended) ==
* '''Filename:'''
** rc_v0500000d_04aug2010.sof

* '''Features:'''
** Bugfix: To fix the bug associated with negative flux-jumps, reverted to signed multiplier and hence, incremented the width of the flux-quanta multiplier input by 1.

* '''Details:''':
** SQ1FB is applied 18 clock cycles after start of a row visit (SQ1_Bias being applied) regardless of flux-jump being enabled or not. In pre-5.0.b firmware SQ1FB was being applied after 7 clock cycles when flux-jump was disabled and after 18 clock cycles when flux-jump was enabled.

* '''Bugs:'''
** '''integral_clamping is broken'''. To test the clamping, a servo-locked ramp was initiated on the sq1fb and then flux-jumping was turned on and observed by attaching a scope to the SQ1FB output. With integral_clamp=80000000, flux_quanta=8000, gaini=1, flux-jump enabled, we see [[http://e-mode.phas.ubc.ca/mcewiki/index.php/Image:Clamp_unstable.png scope snapshot]] used slow_fb_ramp.py script for testing.

* '''FPGA Resource Usage and Timing Report''' (readout_card.fit.rpt and readout_card.tan.rpt): no change compared to 5.0.a/b/c

== Revision 5.0.c (not recommended) ==
* '''Filename:'''
** rc_v0500000c_16jun2010.sof

* '''Features:'''
** Based on rev. 5.0.b
** Re-introduced flux-jump counter clamping to maintain continuity in behavior from past versions of firmware in the field.
** '''Important''': SQ1FB is applied 18 clock cycles after start of a row visit (SQ1_Bias being applied) regardless of flux-jump being enabled or not. In pre-5.0.b firmware SQ1FB was being applied after 7 clock cycles when flux-jump was disabled and after 18 clock cycles when flux-jump was enabled.

* '''Details:'''
* '''Bugs:'''
** '''flux-jump is broken'''. flux-jumping block misbehaves at the first jump in the negative range.

* '''FPGA Resource Usage''' (readout_card.fit.rpt): [[rc_5.0.c_fit_rpt]]
; Total logic elements ; 26,800 / 41,250 ( 65 % ) ;
; Total pins ; 358 / 616 ( 58 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt): [[rc_5.0.c_tan_rpt]]
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.964 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 4.382 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 15.924 ns ;

== Revision 5.0.b (not recommended) ==
* '''Filename:'''
** rc_v0500000b_03jun2010.sof

* '''Features:'''
** Based on rev. 5.0.a
** A bug that caused jumps in first-stage feedback, and detected as spikes in the raw data of pixels that were in servo_mode=0,1,2 was fixed. The jumps in FSFB were due to flux-jumping being enabled on live pixes with non-zero flx_quanta, and being disabled on the fly on dead pixels with flx_quanta=0. Flux-jumping is now disabled on a column-by-column basis if a column is in servo_mode = 0,1,2.
** Ineffective clamping was removed from the flux-jumping block (as per 5.0.9), as it is now replaced by the clamping that was perfected in rev. 5.0.10
** A sticky bit that only affected servo_mode=0,1,2 was also removed from the flux-jumping block.
** flx_lp_init commands now also clear the flux-jumping block as well.
** The 11-clock-cycle delay (in applying SQ1_FB) that in previous firmware only occurred when flux-jumping was enabled, now (in this version) is in effect all the time. Due to the bug-fix above, flux-jumping can be disabled on a column-by-column basis by setting servo_mode=0,1,2 when en_fb_jump=1. Before the change, this meant that constant values could be applied with or without the 11-cycle delay if en_fb_jump=1 or 0. To make the delay consistent, it is now always 11 cycles. As background, the flux-jumping block is pipelined, meaning that it does calculations for all 8 channels serially. The serialization is because of DSP-block limitations in the Readout Card FPGA that prevent us from doing all 8 channels in parallel. The reason that it takes 11 cycles to complete the flux-jumping calculations is because the values are computed for the eight channels in three ALU stages: 8 + 3 = 11 cycles. Adding 11 cycles to the 7 cycles of latency from other stages in the system results in: 11 + 7 = 18 cycles of latency from the start of a row dwell period before the first-stage feedback is applied. In rc_v5.0.c, I enforce the 18-cycle delay even when flux-jumping is not enabled to maintain uniformity across all eight channels, because flux-jumping is enabled/disabled on a per-channel basis. In other words, if I hadn't enforced the 18-cycle delay, some channels could have their feedback applied after 7 cycles, while others could have it applied after 18 cycles. I wasn't a fan of this non-uniformity. I realize that 18 cycles is a long time. In fact, so is 7. In the last few months, we have been discussing how to reduce these times to 1 cycle, because every experiment out there wants to multiplex as fast as possible, and the 7/18-delay is a rate limiting step.
** The flux-jumping code was re-arranged in the flux-jumping block to reflect the flow of data through the pipeline and make it easier to understand.

* '''Details:'''

* '''Bugs:'''
** flux-jump does not work when jumping to negative values.

* '''FPGA Resource Usage''' (readout_card.fit.rpt): [[rc_5.0.b_fit_rpt]]
; Total logic elements ; 26,745 / 41,250 ( 65 % ) ;
; Total pins ; 358 / 616 ( 58 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;
; DSP block 9-bit elements ; 76 / 112 ( 68 % ) ;
; Total PLLs ; 1 / 6 ( 17 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;
* '''FPGA Timing Analysis''' (readout_card.tan.rpt): [[rc_5.0.b_tan_rpt]]
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.459 ns
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.895 ns
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 15.956 ns

== Revision 5.0.a (not recommended) ==
* '''Filename:'''
** rc_v0500000a_12mar2010.sof

* '''Features:'''
** Based on the merger of rev. 5.0.8 and 5.0.9.
** '''integral_clamp''' command is added where a clamp value is set for the integral term and once the integral term hits that value, the integral-term is clamped to that value and p-term and d-term are clamped to zero. When integral_term=0 then no clamping is in effect, similar to previous releases of firmware.
** The low pass filter has 20-bit input and f_3dB/f_samp = 122Hz/15kHz .
** The flux-jump clamping that was removed in 5.0.9 is included once again here, as we decided this is safer for now.

* '''Details:'''
** "lock_dat_left" parameter that was removed in 5.0.9 is now implemented as "lock_dat_lsb"

* '''Bugs:'''
** flx_lp_init does not reinitialize the flux-jump block

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis
** tag name: rc_v0500000a_12mar2009! years were mixed up!

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
* '''FPGA Timing Analysis''' (readout_card.tan.rpt):

== Revision 5.0.9 (buggy) ==
* '''Filename:'''
** rc_v05000009_13nov2009.sof

* '''Features:'''
** Based on rev. 5.0.4
** Removes a sticky bit in pid calculation result storage -- in fsfb_processor.
** Adds a command to clamp the growth of the I-term to prevent wrapping and track down the source of Caltech's FSFB jumps.
** Removed the unused lock_dat_left parameter. The ability to shift left was moved to the fsfb_corr block some time ago.
** Fixed a sign extension bug acting on the flux quanta, which limited the value to 8191. Changed the extension from signed to unsigned.
** Removed ineffective clamping in the flux-jump calculation block.
** IMPORTANT: Must be used in conjunction with firmware rev. 5.0.0+ of all other cards.

* '''Details:'''

* '''Bugs:'''
** integral_clamp read/write command does not work.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 27,960 / 41,250 ( 68 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.825 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.878 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 14.397 ns ;

== Revision 5.0.8 (UBC only) ==
* '''Filename:'''
** rc_v05000008_09oct2009.sof

* '''Features:'''
** Based on rev. 5.0.4
** type 1 low-pass filter: f3dB=122Hz for fsample=15kHz
** Filter-input-width changed from 18b to 20b with no sticky bits!
** removed sticky bits in internal arithmetic of the filter.

= Revision 5.0.7 (type-2 filter) =
* '''Filename:'''
** rc_v05000007_09oct2009.sof

* '''Features:'''
** Based on rev. 5.0.4
** type-2 low-pass-filter: f3dB=75Hz for fsample=30000.
** Filter-input-width changed from 18b to 20b with no sticky bits!
** inter-biquad-gain-scaling for the filter is 2^14
** filter results are scaled down by 2^3 in the output of the filter.
** removed sticky bits in internal arithmetics
** _correction_ disabled in fsfb_proc_pidz

* '''Details:'''
** quartus.ini file was '''not''' present in synth directory.

* '''Bugs:'''
** none to report

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
== Revision 5.0.6 (UBC only) ==
* '''Filename:'''
** rc_stratix3_v05000006_15sep2009.sof

* '''Features:'''
** Only Valid for Rev. C/D Cards
** Based on rev. 5.0.3
** tcl file updated for Rev. D and aligned with top-level and qsf (project file).
** flux loop commented, just to try sampling the ADC.
** compiled with Q9.1

== Revision 5.0.5 (UBC only) ==
* '''Filename:'''
** rc_v05000005_04sep2009.sof

* '''Features:'''
** Based on rev. 5.0.2
** changed the low-pass-filter to f(3db)=75Hz for f(sample)=30000.

* '''Details:'''
** quartus.ini file was '''not''' present in synth directory.

* '''Bugs:'''
** negative inputs to the filter cause filter to have a non-flat pass-band region. may have to do with sign-handling...

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
* '''FPGA Timing Analysis''' (readout_card.tan.rpt):

= Revision 5.0.4 =
* '''Filename:'''
** rc_v05000004_28aug2009.sof

* '''Features:'''
** Based on rev. 5.0.2
** BUG Fix: handles 14-bit flux quanta (changed the multiplier to unsigned)
** BUG Fix: changed standard logic vector extension from signed to unsigned in flux-jumping slave.
** IMPORTANT: Must be used in conjunction with firmware rev. 5.0.0+ of all other cards.

* '''Details:'''

* '''Bugs:'''
** None so far.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,170 / 41,250 ( 63 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.541 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.612 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 15.398 ns ;

= Revision 5.0.3 =
* '''Filename:'''
** rc_stratix3_v05000003_21aug2009.sof

* '''Features:'''
** ONLY valid REV C/D RC Cards
** Based on rev. 5.0.2
** flux loop commented, just to try sampling the ADC.
** updated tcl file, but still need to rely on project file as well as qsf file.
** changed default level of adc_sclk to '1'
** dac_clr_n was changed from an output to an input.
** added 'locked' interface to rc_pll_stratix_iii
** renamed the adc_pll clock signals to more explanitory names
** added the FPGA_DEVICE_FAMILY generic to the dispatch interace for synthesis of the dc_fifo in lvds_rx
** uncommented DDR interface to force the syntesizer to use correct left and right PLLs (in conjunction with ADC and DDR PLLs)
** added test signals to test_status to see clocks on the scope.
== Revision 5.0.2 (buggy) ==
* '''Filename:'''
** rc_v05000002_test00_tagged.sof

* '''Features:'''
** Based on rev. 5.0.1
** Fixed a bug in wbs_frame_data that stored data incorrectly if reporting 1 or 2 pixels only.
** IMPORTANT: Must be used in conjunction with firmware rev. 5.0.0+ of all other cards.

* '''Details:'''

* '''Bugs:'''
** None so far.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,186 / 41,250 ( 63 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.755 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.979 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.067 ns ;

== Revision 5.0.1 (buggy) (Filter + Raw + Rectangle, 2 LVDS) ==
* '''Filename:'''
** rc_v05000001_26may2009.sof

* '''Features:'''
** Combines features in rev. 5.0.0 (2 LVDS Lines) and rev. 4.0.e (Filtered + Raw), with the NEW rectangle mode.
** IMPORTANT: Must be used in conjunction with firmware rev. 5.0.0+ of all other cards.

* '''Details:'''
** [[CVS Diff Between sys_v05000000 and rc_v05000001]]

* '''Bugs:'''
** Has a bug in wbs_frame_data that stored data incorrectly if reporting 1 or 2 pixels only.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,565 / 41,250 ( 64 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.656 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.861 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 14.167 ns ;

== Revision 5.0.0 (Filter Only, 2 LVDS) ==
* '''Filename:'''
** rc_v05000000_22dec2008.sof (tagged as sys_v05000000_22dec2008)

* '''Features:'''
** IMPORTANT: Must be used in conjunction with firmware v05000000+ of all other cards!!!
** Adds the ability to read out one column of data continuously from readout cards
** Adds data mode 11, which is an engineering mode. Data points are 32-bits, and bits [9..3]=row_index, [2..0]=column_index. This mode is useful for determining which pixels one is reading out in the array, in column mode for example.

* '''Details:'''
** [[CVS Diff Between rc_v0400000c and sys_v05000000]]

* '''Bugs:'''
** None so far.

* '''Synthesis Notes:'''
** The quartus.ini file was not present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,607 / 41,250 ( 65 % ) ;
; Total memory bits ; 406,016 / 3,423,744 ( 12 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.558 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.892 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.987 ns ;

== Revision 4.0.f (Filter + Raw, 1 LVDS) ==
* '''Filename:'''
** rc_v0400000f_12feb2010.sof

* '''Features:'''
** Based on 4.0.e and in parallel with 5.0.9 (equivalent version, clamping is not included)
** Incorporates fixes that were done to flux-jumping between 5.0.2 - 5.0.4 - 5.0.9. Namely:
*** Changes a multiplier from signed to unsigned (in fsfb_corr_multplier.vhd).
*** Changes sign extension from signed to unsigned (in flux_quanta_ram_admin.vhd).

* '''Details:'''

* '''Bugs:'''
** None reported yet.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,773 / 41,250 ( 65 % ) ;
; Total memory bits ; 1,321,984 / 3,423,744 ( 39 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.539 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 4.118 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 17.318 ns ;

== Revision 4.0.e (Filter + Raw, 1 LVDS) ==
* '''Filename:'''
** rc_v0400000e_27apr2009.sof

* '''Features:'''
** Based on 4.0.d
** Combines both raw- and filtered-data modes.
** fpga_temp, card_temp, card_id commands are disabled.
** Tested by Matt Hasselfield.

* '''Details:'''

* '''Bugs:'''
** fpga_temp, card_temp, card_id commands are disabled.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 27,048 / 41,250 ( 66 % ) ;
; Total memory bits ; 1,321,984 / 3,423,744 ( 39 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.675 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.907 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.728 ns ;

== Revision 4.0.d (Raw Only, 1 LVDS) ==
* '''Filename:''' rc_v0400000d_20090417.sof

* '''Features:'''
** Based on v4.0.c, but has the filter removed, and implements a single 65536-index RAM block for storing 50 MHz raw-data samples.
** The firmware takes a new command called readout_col_index which specifies which column to capture raw data from.
** Other than readout_col_index, the firmware functions the same as previous raw-data firmware, including then need to issue a capture_raw command.
** For more information on raw-data, see: http://e-mode.phas.ubc.ca/mcewiki/index.php/Raw-mode_readout
** This firmware also integrates some of the improvements that were implemented in 4.4.0, like the removal of the tga_o signal from an FSM in dispatch_wishbone.vhd.

* '''Details:'''
** Differences between 4.0.c and 4.0.d
U system/test/source/tb/tb_cc_rcs_bcs_ac.vhd
U all_cards/dispatch/source/rtl/dispatch_wishbone.vhd
U library/sys_param/source/rtl/wishbone_pack.vhd
U readout_card/adc_sample_coadd/source/rtl/adc_sample_coadd.vhd
U readout_card/adc_sample_coadd/source/rtl/adc_sample_coadd_pack.vhd
U readout_card/flux_loop/source/rtl/flux_loop.vhd
U readout_card/flux_loop/source/rtl/flux_loop_pack.vhd
U readout_card/flux_loop_ctrl/source/rtl/flux_loop_ctrl.vhd
U readout_card/flux_loop_ctrl/source/rtl/flux_loop_ctrl_pack.vhd
U readout_card/flux_loop_ctrl/source/tb/tb1_flux_loop_ctrl.vhd
U readout_card/flux_loop_ctrl/source/tb/tb2_flux_loop_ctrl.vhd
U readout_card/fsfb_calc/source/rtl/fsfb_fltr_regs.vhd
U readout_card/fsfb_corr/source/rtl/fsfb_corr.vhd
U readout_card/readout_card/source/rtl/readout_card.vhd
U readout_card/readout_card/source/rtl/readout_card_pack.vhd
U readout_card/wbs_frame_data/source/rtl/wbs_frame_data.vhd
U readout_card/wbs_frame_data/source/rtl/wbs_frame_data_pack.vhd

* '''Bugs:'''
** None so far.
** fpga_temp, card_temp, card_id commands are not supported.

* '''Synthesis Notes:'''
** The quartus.ini file was present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 24,554 / 41,250 ( 60 % ) ;
; Total memory bits ; 1,262,592 / 3,423,744 ( 37 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.991 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.864 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 17.052 ns ;

== Revision 4.4.1 ==
* '''Filename:''' rc_v04040001_21nov2008

* '''Features:'''
** Fixes a bug that froze up the firmware if any of the following commands were issued: CARD_ID_ADDR, CARD_TEMP_ADDR, FPGA_TEMP_ADDR in 4.4.0 only.

* '''Details:'''
** The bug fix include adding more logic to the wishbone ack path (readout_card.vhd), which subsequently decreased the minimum clock setup time to 1.588ns. The new logic will catch errors that the old logic wouldn't have, and is now consistent with the firmware on all the other cards. However, if timing becomes an issue, the logic may have to revert back to that which was in version 4.0.c.

* '''Bugs:'''
** None so far.

* '''Synthesis Notes:'''
** The quartus.ini file was not present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 27,241 / 41,250 ( 66 % ) ;
; Total memory bits ; 405,504 / 3,423,744 ( 12 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.588 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.585 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 17.057 ns ;

== Revision 4.4.0 (buggy) ==
* '''Filename:''' rc_v04040000_02oct2008
* '''Features:'''
** Reinstated the data modes in wbs_frame_data.vhd that were removed in 4.0.c. This firmware has the following modes: '''0, 1, 2, 4, 5, 7, 10'''. The modes that are not present are: '''3''' (raw data), '''6''' (replaced by data_mode = 7), '''8''' (replaced by data_mode = 10), '''9''' (replaced by data_mode = 10). For more information on data modes, see [[Data mode]].
** Re-integrated the id_thermo and fpga_thermo block in the readout_card.vhd top level that was removed in 4.0.c.
** Removed the sticky bit in fsfb_corr.vhd, which was enabled when flux-jumping was turned on. Because the feedback is signed, the sticky bit would usually reflect the value of the 14th bit, except in situations when the number of flux quanta to jump was greater than 1 (i.e. cosmic rays, IV-curves, etc). Flux jumps are made at a maximum rate of one per frame period, so that if the First-Stage Feedback increased past the 13th bit, it would not be reflected in the feedback applied. Now it is.
* '''Details:'''
** Simplified the FSM logic in wbs_frame_data.vhd that determines when to transition from IDLE to WSS1. This was done to lower the number of gates in that path, and ease the timing.
** Removed the z_dat_i port in fsfb_processor.vhd and fsfb_calc_pack.vhd to the fsfb_proc_pidz block, in an effort to make it clearer within that block that the z-term is always = 0.
** Removed the z-term sign extension in fsfb_proc_pidz.vhd, and the [d-term + z-term] adder to free up DSP resources since the z-term is always = 0.
** Adjusted the indentation in fsfb_io_controller.vhd to make the file more readable.
** Moved the tga_o signal out of the dispatch_wishbone.vhd FSM, and made it a continuous assignment. This signal had one of the highest fan-out counts in the RTL design, and actually was impossible to route in Stratix III chips in its previous configuration because of the number of gates on the fan-out. As a consequence of making it a continuous assignment, the Stratix III fitter was able to succeed, and the Stratix I timing characteristics were greatly improved. This is the most significant change in this revision. This change single-handedly increased the minimum slack from 1.282 ns in v0400000c to 2.372 ns (or 56.7 MHz max) in this revision.
* '''Bugs:'''
** The following commands lock up the Readout Card firmware: CARD_ID_ADDR, CARD_TEMP_ADDR, FPGA_TEMP_ADDR.
** fb_const0 commands to channel 0 do not work. The value is stored in the register, but not applied to the DAC. Thus, read-back returns the correct value, but the DAC does not
* '''Synthesis Notes:'''
** The quartus.ini file was not present in the synth directory during synthesis.
* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 27,099 / 41,250 ( 66 % ) ;
; Total memory bits ; 406,016 / 3,423,744 ( 12 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.372 ns ;
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 4.052 ns ;
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.066 ns ;

== Revision 4.0.c ==
* '''Filename:''' rc_v0400000c_15aug2008.sof
* '''Features:'''
** Only has data modes 0, 1, 4, and 10.
** Fixed the bug that exists in 4.0.b, 4.0.a, and 4.0.9 that prevented the fb_const value from being applied to channel zero (wbs_fb_data.vhd).
* '''Details:'''
** Changed a counter in the dispatch block to ease timing constraints in synthesis (dispatch_wishbone.vhd)
** Updated the tagged versions of dispatch.vhd , dispatch_cmd_receive.vhd, and dispatch_reply_transmit.vhd to the version that is used by all the other cards.
** '''Removed''' the fpga_termo (command: '''fpga_temp''') and id_thermo (commands: '''card_temp, card_id''') to ease timing constraints in synthesis (readout_card.vhd)
** Updated the tagged version of fpga_termo.vhd to include the new 'stale bit' feature
** Updated the tagged version of frame_timing_core.vhd to include the new 'err_o' interface
* '''Bugs:'''
** None reported yet
* '''Synthesis Notes:'''
** The quartus.ini file was not present in the synth directory during synthesis.
* '''FPGA Resource Usage:'''
Total logic elements : 25,058 / 41,250 ( 61 % )
Total memory bits : 400,896 / 3,423,744 ( 12 % )

* '''Timing Analysis''' (readout_card.tan.rpt):
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.282 ns ;
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.736 ns ;
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.665 ns ;

== Revision 4.0.b (buggy) ==
Note: This revision is on a watch list, after the bug detected 15 July 2008. See the bug section for more details.
* '''Filename''' : rc_v0400000b_04aug2008.sof
* '''Features'''
** data_mode 10 is added to provide more filtfb bits (compared to data mode 9) for planet observations. filtered_dat(27 downto 3) & flux_cnt_dat(6 downto 0)

* '''Bugs'''
** An unexplained bug that appeared in 4.0.a and may still be present in 4.0.b is a problem with the readout of channels being clipped out of data reporting. [[Bug 1 Notes]]

* ''' Synthesis note '''
** Quartus.ini removed.

== Revision 4.0.a (buggy) ==
Note: This revision is on a watch list, after the bug detected 15 July 2008. See the bug section for more details.
* '''Filename''' : rc_v0400000a_07jul2008.sof
* '''Bug Fix'''
** mce_status and adc_offset/flx_quanta commands do not fail after power up.
* ''' Synthesis note '''
** Quartus.ini removed.

* '''Bugs'''
** Seems to clip out channel 0 from data reporting.

== Revision 4.0.9 (buggy) ==
* '''Filename''' : rc_v04000009_26jun2008.sof
* '''Features'''
** sa_bias and offset DACs only refreshed when new values are written. (in previous versions, DACs were refreshed every frame)
* '''Bugs'''
** fb_const0 commands to channel 0 do not work. The value is stored in the register, but not applied to the DAC. Thus, read-back returns the correct value, but the DAC does not.
** reading flx_quanta and adc_offset right after power up hangs the reply datapath to CC. resetmce clears this error as temporary solution. the problem is caused by first read ack of the wishbone slave.

== Revision 4.0.8 ==
* '''Filename''' : rc_v04000008_26jun2008.sof
* '''Features'''
** The gaini, gainp, gaind resolution increased to 12-bit, i.e. -2048 to 2047 (formerly 10-bit).

* '''Bug fix'''
** the bug associated with gainpid read before mce_reset is fixed.

* ''' Synthesis note '''
** Quartus.ini removed.

== Revision 4.3.7 ==
* '''Filename''' : rc_v04030007_26may2008_raw.sof
* '''Features'''
** 14-bit raw mode enabled to buffer a snapshot of 50MHz samples for 2 frames of row_len * num_rows samples.
** In order to extend the raw-mode to 14-bit, an assumption is made that the raw buffer is not written to while being read. Therefore, make sure there is at least 2*row_len*num_rows*20ns between issuing captr_raw command and reading back the raw data.
** In order to save RAM for raw mode, two memory-intensive features are disabled:
*** low-pass filter disabled ( mixed filtfb data modes 6, 7, 9 are also disabled)
*** PID (gainp0, gaini0, gaind0) readback disabled. one can still set PID values and run servo, but can not read back the values.

== Revision 4.2.7 ==
* '''Filename''' : rc_v04020007_24may2008_raw.sof
* '''Features'''
** raw mode enabled to buffer a snapshot of 50MHz samples for 2 frames of row_len * num_rows samples.
** In order to save RAM for raw mode, two memory-intensive features are disabled:
*** low-pass filter disabled ( mixed filtfb data modes 6, 7, 9 are also disabled)
*** PID (gainp0, gaini0, gaind0) readback disabled. one can still set PID values and run servo, but can not read back the values.
* '''Bug fix'''
** the bug associated with reading from raw-buffer is fixed.

== Revision 4.1.7 ==
* '''Filename''' : rc_v04010007_25apr2008_raw.sof
* '''Features'''
** raw mode enabled to buffer a snapshot of 50MHz samples for 2 frames of row_len * num_rows samples.
** In order to save RAM for raw mode, two memory-intensive features are disabled:
*** low-pass filter disabled ( mixed filtfb data modes 6, 7, 9 are also disabled)
*** PID (gainp0, gaini0, gaind0) readback disabled. one can still set PID values and run servo, but can not read back the values.
* '''Bugs'''
** after each readout frame, raw-buffer readout counter falls behind by 3 and this causes skipping 3 50MHz samples in the data stream and column-data being messed up in subsequent frames. Data can be rearranged by post processing.

== Revision 4.0.6 (buggy) ==
* '''Filename''' : rc_v04000006_15feb2008.sof or .pof
* '''Features'''
** '''bugfix''': unreliable reset due to unsafe and incomplete state machines is fixed.
** '''bugfix''': flux_jump sign problem fixed, so far proved in const_mode, to be tested in servo_mode with cold setup.
** servo_mode=2 or ramp previously only went from 0 to ramp_amp, but now goes from -8192 to -8192+ramp_amp
** new commands are added: ''scratch'' and ''card_type''. Scratch takes 8 values and can be used by software to detect reset.
** slot_id and fw_rev are now integrated as part of all_cards.vhd
** lvds_tx_b=0, This will allow Clock Card to use the secondary backplane lvds line and check whether RC is plugged in.
** filter_coeff in misc_banks_admin commented as it is not implemented and causes timing problems.

* '''Bugs'''
** reading gainp/gaini/gaind right after power up hangs the reply datapath to CC. resetmce clears this error as temporary solution. the problem is caused by first read ack of pid_ram_admin.
** slot_id is only set after a resetmce is issued. (using the latest all_cards in the next revision will fix this)
** has spurious spikes on channel 7 data, which max out the integral, and cause the detectors to come unlocked. This firmware officially meets timing requirements, but the bug could be due to marginal timing on the longest data paths, i.e. ~0.1 ns in some cases.

== Revision 4.0.5 ==
* '''Filename''' : rc_v04000005_01nov2007.sof or .pof
* '''Features'''
** data mode 9 (mixed filt + flux jump) with windowing readjusted compared to data mode 8

* '''Bugs'''
** unreliable resetmce. Sometimes, firmware waked up non-responsive on lvds lines.
** In data mode 5 and 9, flux-jump counter is not reported properly due to a sign error. However, flux jumping works fine.

== Revision 3.0.19 ==
* '''Filename''' : rc_v03000019_16feb2007_raw.sof (no pof as one is not likely to run with this as regular firmware)
* '''Features'''
** data mode 3 is enabled.
** filter is disabled as a compromise to fit the raw-mode buffer.

* '''Bugs'''
** unreliable resetmce. Sometimes, firmware waked up non-responsive on lvds lines.

== Old Firmware Revisions ==
* '''4.0.4''': rc_v04000004_11oct2007.sof data mode 8 added (mixed filt + flux jump)
* '''4.0.3''': rc_v04000003_19sep2007.sof data mode 7 bit split readjusted to 10b error being bit 4 to 14
* '''4.0.2''': rc_v04000002_11sep2007.sof pid resolution increased to 10b, data mode 7 added
* '''4.0.1''': rc_v04000001_06sep2007.sof
* '''4.0.0''': rc_v04000000_29aug2007.sof supports readout_row_index * [[ bugs ]]

= To-Do List =
* the starting point for the servo is currently zero and it would be nice to have it programmable.

= RC Synthesis Notes =
# The following note applies when using Quartus versions earlier than Q7: Quartus.ini file had to exist in synth directory up to revision 4.0.a due to a bug that started in Quartus 6.1 and would synthesize away arbitrary parts of readout card. We contacted Altera at the time and they provided us the ini file.
# Timing: There is no "lock region" defined for readout card. Timing on readout card is tight and since version 3 or so any new feature would initially fail timing till some synthesis options were tweaked. One path that remains to be consistently marginal is from addr_gen counter (i.e. tga_o counter) in dispatch_wishbone.vhd to wishbone slaves particularly misc_banks_admin.vhd. Modules that are rewritten to address timing concerns are fsfb_corr, all_cards, misc_banks_admin, and finally instantiating an lpm counter instead of a counter from components library. Surprisingly, the lpm counter reduced 87 failures to 37, although looking at the technology map viewer, it seemed that they were both synthesized the same.
# Compile time: This was at some point 4.5 hours, after going to dual core PC, this was reduced to 35 minutes. After extending pid gains to 12b and fixing offset/sa_bias update code, the compile time increased to 1.5hr again with utilization up to ~70%.
# wbs_fb_storage, ram_8x64, pid_ram had to be regenerated using latest (Q7.2) MegaWizard to get rid of the bug associated with failure to read after power up until a reset was issued.
# During simulations, the initialization of RAM block with .hex files needs to be disabled. This is done by commenting out the following lines from the MegaWizard generated Megafunction files (remember to un-comment them before synthesizing the code):
lpm_file => "C:/scuba2_repository/cards/readout_card/fsfb_calc/source/rtl/ram_40x64.hex", and
lpm_file : STRING;
#Starting Q10.0 use TimeQuest timing analyzer as oppose to the classic one. The classic one is being phased out by Altera. In order to use TimeQuest, you need to have an sdc file present in your project directory.
----
[http://e-mode.phas.ubc.ca/mcewiki/index.php/Main_Page MCE Main Page]

Readout Card firmware

2011-05-04T22:02:19Z

Bburger: /* Revision 5.0.f */

* Synthesis Reminders (for firmware developers)
** quartus.ini is not needed anymore (Fixed as of Q7, Altera SR10783580 2010-10-24)
** Remember that readout_card/fsfb_clac/source/rtl/ram_40x64.vhd must be initialized with the ram_40x64.hex file in the same directory.
= Revision 5.1.2 =
* '''Filename:'''
** rc_stratix3_v05010002_18jan2011.sof (for Rev. E cards)
** rc_stratix3_v05010002_18jan2011.jic (for Rev. E cards)
** rc_v05010002_03feb2011.sof (for Rev. B cards)
** rc_v05010002_03feb2011.pof (for Rev. B cards)

* '''Features:'''
** based on 5.1.1 with k1 and k2 (filter params) limited to k1<16 and k2<32 in order to resolve the timing when compiling for smaller Stratix FPGA on RC Rev. B.

* '''Bug fix:'''
** the 2-rows-off filtered data readout introduced with configurable filter in rev. 5.1.0 and 5.1.1 is fixed now.

* '''Bugs:'''
** none so far.

* '''FPGA Resource Usage''' (readout_card.fit.rpt, rev. B)
; Total logic elements ; 33,285 / 41,250 ( 81 % ) ;
; Total pins ; 358 / 616 ( 58 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt, rev. B)
; Fast Model Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 6.591 ns
; Fast Model Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 7.206 ns
; Fast Model Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 18.299 ns

== Revision 5.1.1 (not recommended) ==
* '''Filename:'''
** rc_v05010001_01dec2010.sof (for Rev. B cards)

* '''Features:'''
** based on 5.1.0, but k1 and k2 (filter params) are now limited to k1<16 and k2<32 in order to resolve the timing failures of compiling 5.1.0 for smaller Stratix FPGA on RC Rev. B.

* '''Bugs:'''
** filter mode data is off by 2 rows.

== Revision 5.1.0 (not recommended) ==
* '''Filename:'''
** rc_stratix3_v05010000_01nov2010.sof (for Rev. E cards)
** rc_v05010000_01nov2010.sof (for Rev. B cards) has timing failures '''do not use!!!'''

* '''Features:'''
** added configurable filter parameters specified by ''fltr_coeff'', default is the fcutoff/fsampl=122Hz/15kHz. see [[ Digital 4-pole Butterworth Low-pass filter ]].
** ''fltr_type'' is set to 255 to indicate configurable filter parameters.
** see [http://www.phas.ubc.ca/~mce/mcedocs/software/SC2_ELE_S580_515_mce_command_description.pdf MCE command description]
* '''Details'''
** It is built on Quartus10.1.
** tcl files had to be updated as cmp syntax is not supported in Q10 anymore.
** Rev. E cards now can be identified by reading back pcb_rev as part of card_type, therefore both stratix I and III sof/pof/jic are generated from the same source.

* '''Bugs:'''
** rc_v05010000_01nov2010.sof has timing failures that were overlooked, do not use this firmware for Rev.B cards.
** '''filter mode data is off by 2 rows.'''

* '''FPGA Resource Usage and Timing Report''' (readout_card.fit.rpt and readout_card.tan.rpt): logic usage is upto 85% from 66% in 5.0.d/e/f

= Revision 5.0.f =
* '''Filename:'''
** rc_v0500000f_22oct2010.sof (for Rev. B cards)
** rc_stratix3_v0500000f_22oct2010.sof (for Rev. E cards)

* '''Features:'''
** Bugfix: integral clamp should work now. only positive integral_clamp values are valid!

* '''Details:''':
** SQ1FB is applied 18 clock cycles after start of a row visit (SQ1_Bias being applied) regardless of flux-jump being enabled or not. In pre-5.0.b firmware SQ1FB was being applied after 7 clock cycles when flux-jump was disabled and after 18 clock cycles when flux-jump was enabled.
** available for both Rev. E and Rev. B cards, the upper byte of card_type parameter now reports the pcb revision.
** development note: It is built on Quartus10.1.

* '''Bugs:'''
**none yet!

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 27,377 / 41,250 ( 66 % ) ;
; Total pins ; 358 / 616 ( 58 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.652 ns
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.385 ns
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.860 ns

== Revision 5.0.e (not recommended) ==
* '''Filename:'''
** rc_v0500000e_06oct2010.sof

* '''Details:'''
** an unsuccessful attempt to fix integral_clamp, but changed the functionality so that it clamps at the value, but it doesn't hold the clamp. i.e., if the calculated sq1fb becomes less than the specified clamp value, the sq1fb is not clamped anymore. This is not a desired functionality!

== Revision 5.0.d (not recommended) ==
* '''Filename:'''
** rc_v0500000d_04aug2010.sof

* '''Features:'''
** Bugfix: To fix the bug associated with negative flux-jumps, reverted to signed multiplier and hence, incremented the width of the flux-quanta multiplier input by 1.

* '''Details:''':
** SQ1FB is applied 18 clock cycles after start of a row visit (SQ1_Bias being applied) regardless of flux-jump being enabled or not. In pre-5.0.b firmware SQ1FB was being applied after 7 clock cycles when flux-jump was disabled and after 18 clock cycles when flux-jump was enabled.

* '''Bugs:'''
** '''integral_clamping is broken'''. To test the clamping, a servo-locked ramp was initiated on the sq1fb and then flux-jumping was turned on and observed by attaching a scope to the SQ1FB output. With integral_clamp=80000000, flux_quanta=8000, gaini=1, flux-jump enabled, we see [[http://e-mode.phas.ubc.ca/mcewiki/index.php/Image:Clamp_unstable.png scope snapshot]] used slow_fb_ramp.py script for testing.

* '''FPGA Resource Usage and Timing Report''' (readout_card.fit.rpt and readout_card.tan.rpt): no change compared to 5.0.a/b/c

== Revision 5.0.c (not recommended) ==
* '''Filename:'''
** rc_v0500000c_16jun2010.sof

* '''Features:'''
** Based on rev. 5.0.b
** Re-introduced flux-jump counter clamping to maintain continuity in behavior from past versions of firmware in the field.
** '''Important''': SQ1FB is applied 18 clock cycles after start of a row visit (SQ1_Bias being applied) regardless of flux-jump being enabled or not. In pre-5.0.b firmware SQ1FB was being applied after 7 clock cycles when flux-jump was disabled and after 18 clock cycles when flux-jump was enabled.

* '''Details:'''
* '''Bugs:'''
** '''flux-jump is broken'''. flux-jumping block misbehaves at the first jump in the negative range.

* '''FPGA Resource Usage''' (readout_card.fit.rpt): [[rc_5.0.c_fit_rpt]]
; Total logic elements ; 26,800 / 41,250 ( 65 % ) ;
; Total pins ; 358 / 616 ( 58 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;
; DSP block 9-bit elements ; 76 / 112 ( 68 % ) ;
; Total PLLs ; 1 / 6 ( 17 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt): [[rc_5.0.c_tan_rpt]]
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.964 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 4.382 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 15.924 ns ;

== Revision 5.0.b (not recommended) ==
* '''Filename:'''
** rc_v0500000b_03jun2010.sof

* '''Features:'''
** Based on rev. 5.0.a
** A bug that caused jumps in first-stage feedback, and detected as spikes in the raw data of pixels that were in servo_mode=0,1,2 was fixed. The jumps in FSFB were due to flux-jumping being enabled on live pixes with non-zero flx_quanta, and being disabled on the fly on dead pixels with flx_quanta=0. Flux-jumping is now disabled on a column-by-column basis if a column is in servo_mode = 0,1,2.
** Ineffective clamping was removed from the flux-jumping block (as per 5.0.9), as it is now replaced by the clamping that was perfected in rev. 5.0.10
** A sticky bit that only affected servo_mode=0,1,2 was also removed from the flux-jumping block.
** flx_lp_init commands now also clear the flux-jumping block as well.
** The 11-clock-cycle delay (in applying SQ1_FB) that in previous firmware only occurred when flux-jumping was enabled, now (in this version) is in effect all the time. Due to the bug-fix above, flux-jumping can be disabled on a column-by-column basis by setting servo_mode=0,1,2 when en_fb_jump=1. Before the change, this meant that constant values could be applied with or without the 11-cycle delay if en_fb_jump=1 or 0. To make the delay consistent, it is now always 11 cycles. As background, the flux-jumping block is pipelined, meaning that it does calculations for all 8 channels serially. The serialization is because of DSP-block limitations in the Readout Card FPGA that prevent us from doing all 8 channels in parallel. The reason that it takes 11 cycles to complete the flux-jumping calculations is because the values are computed for the eight channels in three ALU stages: 8 + 3 = 11 cycles. Adding 11 cycles to the 7 cycles of latency from other stages in the system results in: 11 + 7 = 18 cycles of latency from the start of a row dwell period before the first-stage feedback is applied. In rc_v5.0.c, I enforce the 18-cycle delay even when flux-jumping is not enabled to maintain uniformity across all eight channels, because flux-jumping is enabled/disabled on a per-channel basis. In other words, if I hadn't enforced the 18-cycle delay, some channels could have their feedback applied after 7 cycles, while others could have it applied after 18 cycles. I wasn't a fan of this non-uniformity. I realize that 18 cycles is a long time. In fact, so is 7. In the last few months, we have been discussing how to reduce these times to 1 cycle, because every experiment out there wants to multiplex as fast as possible, and the 7/18-delay is a rate limiting step.
** The flux-jumping code was re-arranged in the flux-jumping block to reflect the flow of data through the pipeline and make it easier to understand.

* '''Details:'''

* '''Bugs:'''
** flux-jump does not work when jumping to negative values.

* '''FPGA Resource Usage''' (readout_card.fit.rpt): [[rc_5.0.b_fit_rpt]]
; Total logic elements ; 26,745 / 41,250 ( 65 % ) ;
; Total pins ; 358 / 616 ( 58 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;
; DSP block 9-bit elements ; 76 / 112 ( 68 % ) ;
; Total PLLs ; 1 / 6 ( 17 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;
* '''FPGA Timing Analysis''' (readout_card.tan.rpt): [[rc_5.0.b_tan_rpt]]
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.459 ns
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.895 ns
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 15.956 ns

== Revision 5.0.a (not recommended) ==
* '''Filename:'''
** rc_v0500000a_12mar2010.sof

* '''Features:'''
** Based on the merger of rev. 5.0.8 and 5.0.9.
** '''integral_clamp''' command is added where a clamp value is set for the integral term and once the integral term hits that value, the integral-term is clamped to that value and p-term and d-term are clamped to zero. When integral_term=0 then no clamping is in effect, similar to previous releases of firmware.
** The low pass filter has 20-bit input and f_3dB/f_samp = 122Hz/15kHz .
** The flux-jump clamping that was removed in 5.0.9 is included once again here, as we decided this is safer for now.

* '''Details:'''
** "lock_dat_left" parameter that was removed in 5.0.9 is now implemented as "lock_dat_lsb"

* '''Bugs:'''
** flx_lp_init does not reinitialize the flux-jump block

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis
** tag name: rc_v0500000a_12mar2009! years were mixed up!

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
* '''FPGA Timing Analysis''' (readout_card.tan.rpt):

== Revision 5.0.9 (buggy) ==
* '''Filename:'''
** rc_v05000009_13nov2009.sof

* '''Features:'''
** Based on rev. 5.0.4
** Removes a sticky bit in pid calculation result storage -- in fsfb_processor.
** Adds a command to clamp the growth of the I-term to prevent wrapping and track down the source of Caltech's FSFB jumps.
** Removed the unused lock_dat_left parameter. The ability to shift left was moved to the fsfb_corr block some time ago.
** Fixed a sign extension bug acting on the flux quanta, which limited the value to 8191. Changed the extension from signed to unsigned.
** Removed ineffective clamping in the flux-jump calculation block.
** IMPORTANT: Must be used in conjunction with firmware rev. 5.0.0+ of all other cards.

* '''Details:'''

* '''Bugs:'''
** integral_clamp read/write command does not work.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 27,960 / 41,250 ( 68 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.825 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.878 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 14.397 ns ;

== Revision 5.0.8 (UBC only) ==
* '''Filename:'''
** rc_v05000008_09oct2009.sof

* '''Features:'''
** Based on rev. 5.0.4
** type 1 low-pass filter: f3dB=122Hz for fsample=15kHz
** Filter-input-width changed from 18b to 20b with no sticky bits!
** removed sticky bits in internal arithmetic of the filter.

= Revision 5.0.7 (type-2 filter) =
* '''Filename:'''
** rc_v05000007_09oct2009.sof

* '''Features:'''
** Based on rev. 5.0.4
** type-2 low-pass-filter: f3dB=75Hz for fsample=30000.
** Filter-input-width changed from 18b to 20b with no sticky bits!
** inter-biquad-gain-scaling for the filter is 2^14
** filter results are scaled down by 2^3 in the output of the filter.
** removed sticky bits in internal arithmetics
** _correction_ disabled in fsfb_proc_pidz

* '''Details:'''
** quartus.ini file was '''not''' present in synth directory.

* '''Bugs:'''
** none to report

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
== Revision 5.0.6 (UBC only) ==
* '''Filename:'''
** rc_stratix3_v05000006_15sep2009.sof

* '''Features:'''
** Only Valid for Rev. C/D Cards
** Based on rev. 5.0.3
** tcl file updated for Rev. D and aligned with top-level and qsf (project file).
** flux loop commented, just to try sampling the ADC.
** compiled with Q9.1

== Revision 5.0.5 (UBC only) ==
* '''Filename:'''
** rc_v05000005_04sep2009.sof

* '''Features:'''
** Based on rev. 5.0.2
** changed the low-pass-filter to f(3db)=75Hz for f(sample)=30000.

* '''Details:'''
** quartus.ini file was '''not''' present in synth directory.

* '''Bugs:'''
** negative inputs to the filter cause filter to have a non-flat pass-band region. may have to do with sign-handling...

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
* '''FPGA Timing Analysis''' (readout_card.tan.rpt):

= Revision 5.0.4 =
* '''Filename:'''
** rc_v05000004_28aug2009.sof

* '''Features:'''
** Based on rev. 5.0.2
** BUG Fix: handles 14-bit flux quanta (changed the multiplier to unsigned)
** BUG Fix: changed standard logic vector extension from signed to unsigned in flux-jumping slave.
** IMPORTANT: Must be used in conjunction with firmware rev. 5.0.0+ of all other cards.

* '''Details:'''

* '''Bugs:'''
** None so far.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,170 / 41,250 ( 63 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.541 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.612 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 15.398 ns ;

= Revision 5.0.3 =
* '''Filename:'''
** rc_stratix3_v05000003_21aug2009.sof

* '''Features:'''
** ONLY valid REV C/D RC Cards
** Based on rev. 5.0.2
** flux loop commented, just to try sampling the ADC.
** updated tcl file, but still need to rely on project file as well as qsf file.
** changed default level of adc_sclk to '1'
** dac_clr_n was changed from an output to an input.
** added 'locked' interface to rc_pll_stratix_iii
** renamed the adc_pll clock signals to more explanitory names
** added the FPGA_DEVICE_FAMILY generic to the dispatch interace for synthesis of the dc_fifo in lvds_rx
** uncommented DDR interface to force the syntesizer to use correct left and right PLLs (in conjunction with ADC and DDR PLLs)
** added test signals to test_status to see clocks on the scope.
== Revision 5.0.2 (buggy) ==
* '''Filename:'''
** rc_v05000002_test00_tagged.sof

* '''Features:'''
** Based on rev. 5.0.1
** Fixed a bug in wbs_frame_data that stored data incorrectly if reporting 1 or 2 pixels only.
** IMPORTANT: Must be used in conjunction with firmware rev. 5.0.0+ of all other cards.

* '''Details:'''

* '''Bugs:'''
** None so far.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,186 / 41,250 ( 63 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.755 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.979 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.067 ns ;

== Revision 5.0.1 (buggy) (Filter + Raw + Rectangle, 2 LVDS) ==
* '''Filename:'''
** rc_v05000001_26may2009.sof

* '''Features:'''
** Combines features in rev. 5.0.0 (2 LVDS Lines) and rev. 4.0.e (Filtered + Raw), with the NEW rectangle mode.
** IMPORTANT: Must be used in conjunction with firmware rev. 5.0.0+ of all other cards.

* '''Details:'''
** [[CVS Diff Between sys_v05000000 and rc_v05000001]]

* '''Bugs:'''
** Has a bug in wbs_frame_data that stored data incorrectly if reporting 1 or 2 pixels only.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,565 / 41,250 ( 64 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.656 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.861 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 14.167 ns ;

== Revision 5.0.0 (Filter Only, 2 LVDS) ==
* '''Filename:'''
** rc_v05000000_22dec2008.sof (tagged as sys_v05000000_22dec2008)

* '''Features:'''
** IMPORTANT: Must be used in conjunction with firmware v05000000+ of all other cards!!!
** Adds the ability to read out one column of data continuously from readout cards
** Adds data mode 11, which is an engineering mode. Data points are 32-bits, and bits [9..3]=row_index, [2..0]=column_index. This mode is useful for determining which pixels one is reading out in the array, in column mode for example.

* '''Details:'''
** [[CVS Diff Between rc_v0400000c and sys_v05000000]]

* '''Bugs:'''
** None so far.

* '''Synthesis Notes:'''
** The quartus.ini file was not present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,607 / 41,250 ( 65 % ) ;
; Total memory bits ; 406,016 / 3,423,744 ( 12 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.558 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.892 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.987 ns ;

== Revision 4.0.f (Filter + Raw, 1 LVDS) ==
* '''Filename:'''
** rc_v0400000f_12feb2010.sof

* '''Features:'''
** Based on 4.0.e and in parallel with 5.0.9 (equivalent version, clamping is not included)
** Incorporates fixes that were done to flux-jumping between 5.0.2 - 5.0.4 - 5.0.9. Namely:
*** Changes a multiplier from signed to unsigned (in fsfb_corr_multplier.vhd).
*** Changes sign extension from signed to unsigned (in flux_quanta_ram_admin.vhd).

* '''Details:'''

* '''Bugs:'''
** None reported yet.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,773 / 41,250 ( 65 % ) ;
; Total memory bits ; 1,321,984 / 3,423,744 ( 39 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.539 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 4.118 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 17.318 ns ;

== Revision 4.0.e (Filter + Raw, 1 LVDS) ==
* '''Filename:'''
** rc_v0400000e_27apr2009.sof

* '''Features:'''
** Based on 4.0.d
** Combines both raw- and filtered-data modes.
** fpga_temp, card_temp, card_id commands are disabled.
** Tested by Matt Hasselfield.

* '''Details:'''

* '''Bugs:'''
** fpga_temp, card_temp, card_id commands are disabled.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 27,048 / 41,250 ( 66 % ) ;
; Total memory bits ; 1,321,984 / 3,423,744 ( 39 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.675 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.907 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.728 ns ;

== Revision 4.0.d (Raw Only, 1 LVDS) ==
* '''Filename:''' rc_v0400000d_20090417.sof

* '''Features:'''
** Based on v4.0.c, but has the filter removed, and implements a single 65536-index RAM block for storing 50 MHz raw-data samples.
** The firmware takes a new command called readout_col_index which specifies which column to capture raw data from.
** Other than readout_col_index, the firmware functions the same as previous raw-data firmware, including then need to issue a capture_raw command.
** For more information on raw-data, see: http://e-mode.phas.ubc.ca/mcewiki/index.php/Raw-mode_readout
** This firmware also integrates some of the improvements that were implemented in 4.4.0, like the removal of the tga_o signal from an FSM in dispatch_wishbone.vhd.

* '''Details:'''
** Differences between 4.0.c and 4.0.d
U system/test/source/tb/tb_cc_rcs_bcs_ac.vhd
U all_cards/dispatch/source/rtl/dispatch_wishbone.vhd
U library/sys_param/source/rtl/wishbone_pack.vhd
U readout_card/adc_sample_coadd/source/rtl/adc_sample_coadd.vhd
U readout_card/adc_sample_coadd/source/rtl/adc_sample_coadd_pack.vhd
U readout_card/flux_loop/source/rtl/flux_loop.vhd
U readout_card/flux_loop/source/rtl/flux_loop_pack.vhd
U readout_card/flux_loop_ctrl/source/rtl/flux_loop_ctrl.vhd
U readout_card/flux_loop_ctrl/source/rtl/flux_loop_ctrl_pack.vhd
U readout_card/flux_loop_ctrl/source/tb/tb1_flux_loop_ctrl.vhd
U readout_card/flux_loop_ctrl/source/tb/tb2_flux_loop_ctrl.vhd
U readout_card/fsfb_calc/source/rtl/fsfb_fltr_regs.vhd
U readout_card/fsfb_corr/source/rtl/fsfb_corr.vhd
U readout_card/readout_card/source/rtl/readout_card.vhd
U readout_card/readout_card/source/rtl/readout_card_pack.vhd
U readout_card/wbs_frame_data/source/rtl/wbs_frame_data.vhd
U readout_card/wbs_frame_data/source/rtl/wbs_frame_data_pack.vhd

* '''Bugs:'''
** None so far.
** fpga_temp, card_temp, card_id commands are not supported.

* '''Synthesis Notes:'''
** The quartus.ini file was present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 24,554 / 41,250 ( 60 % ) ;
; Total memory bits ; 1,262,592 / 3,423,744 ( 37 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.991 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.864 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 17.052 ns ;

== Revision 4.4.1 ==
* '''Filename:''' rc_v04040001_21nov2008

* '''Features:'''
** Fixes a bug that froze up the firmware if any of the following commands were issued: CARD_ID_ADDR, CARD_TEMP_ADDR, FPGA_TEMP_ADDR in 4.4.0 only.

* '''Details:'''
** The bug fix include adding more logic to the wishbone ack path (readout_card.vhd), which subsequently decreased the minimum clock setup time to 1.588ns. The new logic will catch errors that the old logic wouldn't have, and is now consistent with the firmware on all the other cards. However, if timing becomes an issue, the logic may have to revert back to that which was in version 4.0.c.

* '''Bugs:'''
** None so far.

* '''Synthesis Notes:'''
** The quartus.ini file was not present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 27,241 / 41,250 ( 66 % ) ;
; Total memory bits ; 405,504 / 3,423,744 ( 12 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.588 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.585 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 17.057 ns ;

== Revision 4.4.0 (buggy) ==
* '''Filename:''' rc_v04040000_02oct2008
* '''Features:'''
** Reinstated the data modes in wbs_frame_data.vhd that were removed in 4.0.c. This firmware has the following modes: '''0, 1, 2, 4, 5, 7, 10'''. The modes that are not present are: '''3''' (raw data), '''6''' (replaced by data_mode = 7), '''8''' (replaced by data_mode = 10), '''9''' (replaced by data_mode = 10). For more information on data modes, see [[Data mode]].
** Re-integrated the id_thermo and fpga_thermo block in the readout_card.vhd top level that was removed in 4.0.c.
** Removed the sticky bit in fsfb_corr.vhd, which was enabled when flux-jumping was turned on. Because the feedback is signed, the sticky bit would usually reflect the value of the 14th bit, except in situations when the number of flux quanta to jump was greater than 1 (i.e. cosmic rays, IV-curves, etc). Flux jumps are made at a maximum rate of one per frame period, so that if the First-Stage Feedback increased past the 13th bit, it would not be reflected in the feedback applied. Now it is.
* '''Details:'''
** Simplified the FSM logic in wbs_frame_data.vhd that determines when to transition from IDLE to WSS1. This was done to lower the number of gates in that path, and ease the timing.
** Removed the z_dat_i port in fsfb_processor.vhd and fsfb_calc_pack.vhd to the fsfb_proc_pidz block, in an effort to make it clearer within that block that the z-term is always = 0.
** Removed the z-term sign extension in fsfb_proc_pidz.vhd, and the [d-term + z-term] adder to free up DSP resources since the z-term is always = 0.
** Adjusted the indentation in fsfb_io_controller.vhd to make the file more readable.
** Moved the tga_o signal out of the dispatch_wishbone.vhd FSM, and made it a continuous assignment. This signal had one of the highest fan-out counts in the RTL design, and actually was impossible to route in Stratix III chips in its previous configuration because of the number of gates on the fan-out. As a consequence of making it a continuous assignment, the Stratix III fitter was able to succeed, and the Stratix I timing characteristics were greatly improved. This is the most significant change in this revision. This change single-handedly increased the minimum slack from 1.282 ns in v0400000c to 2.372 ns (or 56.7 MHz max) in this revision.
* '''Bugs:'''
** The following commands lock up the Readout Card firmware: CARD_ID_ADDR, CARD_TEMP_ADDR, FPGA_TEMP_ADDR.
** fb_const0 commands to channel 0 do not work. The value is stored in the register, but not applied to the DAC. Thus, read-back returns the correct value, but the DAC does not
* '''Synthesis Notes:'''
** The quartus.ini file was not present in the synth directory during synthesis.
* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 27,099 / 41,250 ( 66 % ) ;
; Total memory bits ; 406,016 / 3,423,744 ( 12 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.372 ns ;
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 4.052 ns ;
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.066 ns ;

== Revision 4.0.c ==
* '''Filename:''' rc_v0400000c_15aug2008.sof
* '''Features:'''
** Only has data modes 0, 1, 4, and 10.
** Fixed the bug that exists in 4.0.b, 4.0.a, and 4.0.9 that prevented the fb_const value from being applied to channel zero (wbs_fb_data.vhd).
* '''Details:'''
** Changed a counter in the dispatch block to ease timing constraints in synthesis (dispatch_wishbone.vhd)
** Updated the tagged versions of dispatch.vhd , dispatch_cmd_receive.vhd, and dispatch_reply_transmit.vhd to the version that is used by all the other cards.
** '''Removed''' the fpga_termo (command: '''fpga_temp''') and id_thermo (commands: '''card_temp, card_id''') to ease timing constraints in synthesis (readout_card.vhd)
** Updated the tagged version of fpga_termo.vhd to include the new 'stale bit' feature
** Updated the tagged version of frame_timing_core.vhd to include the new 'err_o' interface
* '''Bugs:'''
** None reported yet
* '''Synthesis Notes:'''
** The quartus.ini file was not present in the synth directory during synthesis.
* '''FPGA Resource Usage:'''
Total logic elements : 25,058 / 41,250 ( 61 % )
Total memory bits : 400,896 / 3,423,744 ( 12 % )

* '''Timing Analysis''' (readout_card.tan.rpt):
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.282 ns ;
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.736 ns ;
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.665 ns ;

== Revision 4.0.b (buggy) ==
Note: This revision is on a watch list, after the bug detected 15 July 2008. See the bug section for more details.
* '''Filename''' : rc_v0400000b_04aug2008.sof
* '''Features'''
** data_mode 10 is added to provide more filtfb bits (compared to data mode 9) for planet observations. filtered_dat(27 downto 3) & flux_cnt_dat(6 downto 0)

* '''Bugs'''
** An unexplained bug that appeared in 4.0.a and may still be present in 4.0.b is a problem with the readout of channels being clipped out of data reporting. [[Bug 1 Notes]]

* ''' Synthesis note '''
** Quartus.ini removed.

== Revision 4.0.a (buggy) ==
Note: This revision is on a watch list, after the bug detected 15 July 2008. See the bug section for more details.
* '''Filename''' : rc_v0400000a_07jul2008.sof
* '''Bug Fix'''
** mce_status and adc_offset/flx_quanta commands do not fail after power up.
* ''' Synthesis note '''
** Quartus.ini removed.

* '''Bugs'''
** Seems to clip out channel 0 from data reporting.

== Revision 4.0.9 (buggy) ==
* '''Filename''' : rc_v04000009_26jun2008.sof
* '''Features'''
** sa_bias and offset DACs only refreshed when new values are written. (in previous versions, DACs were refreshed every frame)
* '''Bugs'''
** fb_const0 commands to channel 0 do not work. The value is stored in the register, but not applied to the DAC. Thus, read-back returns the correct value, but the DAC does not.
** reading flx_quanta and adc_offset right after power up hangs the reply datapath to CC. resetmce clears this error as temporary solution. the problem is caused by first read ack of the wishbone slave.

== Revision 4.0.8 ==
* '''Filename''' : rc_v04000008_26jun2008.sof
* '''Features'''
** The gaini, gainp, gaind resolution increased to 12-bit, i.e. -2048 to 2047 (formerly 10-bit).

* '''Bug fix'''
** the bug associated with gainpid read before mce_reset is fixed.

* ''' Synthesis note '''
** Quartus.ini removed.

== Revision 4.3.7 ==
* '''Filename''' : rc_v04030007_26may2008_raw.sof
* '''Features'''
** 14-bit raw mode enabled to buffer a snapshot of 50MHz samples for 2 frames of row_len * num_rows samples.
** In order to extend the raw-mode to 14-bit, an assumption is made that the raw buffer is not written to while being read. Therefore, make sure there is at least 2*row_len*num_rows*20ns between issuing captr_raw command and reading back the raw data.
** In order to save RAM for raw mode, two memory-intensive features are disabled:
*** low-pass filter disabled ( mixed filtfb data modes 6, 7, 9 are also disabled)
*** PID (gainp0, gaini0, gaind0) readback disabled. one can still set PID values and run servo, but can not read back the values.

== Revision 4.2.7 ==
* '''Filename''' : rc_v04020007_24may2008_raw.sof
* '''Features'''
** raw mode enabled to buffer a snapshot of 50MHz samples for 2 frames of row_len * num_rows samples.
** In order to save RAM for raw mode, two memory-intensive features are disabled:
*** low-pass filter disabled ( mixed filtfb data modes 6, 7, 9 are also disabled)
*** PID (gainp0, gaini0, gaind0) readback disabled. one can still set PID values and run servo, but can not read back the values.
* '''Bug fix'''
** the bug associated with reading from raw-buffer is fixed.

== Revision 4.1.7 ==
* '''Filename''' : rc_v04010007_25apr2008_raw.sof
* '''Features'''
** raw mode enabled to buffer a snapshot of 50MHz samples for 2 frames of row_len * num_rows samples.
** In order to save RAM for raw mode, two memory-intensive features are disabled:
*** low-pass filter disabled ( mixed filtfb data modes 6, 7, 9 are also disabled)
*** PID (gainp0, gaini0, gaind0) readback disabled. one can still set PID values and run servo, but can not read back the values.
* '''Bugs'''
** after each readout frame, raw-buffer readout counter falls behind by 3 and this causes skipping 3 50MHz samples in the data stream and column-data being messed up in subsequent frames. Data can be rearranged by post processing.

== Revision 4.0.6 (buggy) ==
* '''Filename''' : rc_v04000006_15feb2008.sof or .pof
* '''Features'''
** '''bugfix''': unreliable reset due to unsafe and incomplete state machines is fixed.
** '''bugfix''': flux_jump sign problem fixed, so far proved in const_mode, to be tested in servo_mode with cold setup.
** servo_mode=2 or ramp previously only went from 0 to ramp_amp, but now goes from -8192 to -8192+ramp_amp
** new commands are added: ''scratch'' and ''card_type''. Scratch takes 8 values and can be used by software to detect reset.
** slot_id and fw_rev are now integrated as part of all_cards.vhd
** lvds_tx_b=0, This will allow Clock Card to use the secondary backplane lvds line and check whether RC is plugged in.
** filter_coeff in misc_banks_admin commented as it is not implemented and causes timing problems.

* '''Bugs'''
** reading gainp/gaini/gaind right after power up hangs the reply datapath to CC. resetmce clears this error as temporary solution. the problem is caused by first read ack of pid_ram_admin.
** slot_id is only set after a resetmce is issued. (using the latest all_cards in the next revision will fix this)
** has spurious spikes on channel 7 data, which max out the integral, and cause the detectors to come unlocked. This firmware officially meets timing requirements, but the bug could be due to marginal timing on the longest data paths, i.e. ~0.1 ns in some cases.

== Revision 4.0.5 ==
* '''Filename''' : rc_v04000005_01nov2007.sof or .pof
* '''Features'''
** data mode 9 (mixed filt + flux jump) with windowing readjusted compared to data mode 8

* '''Bugs'''
** unreliable resetmce. Sometimes, firmware waked up non-responsive on lvds lines.
** In data mode 5 and 9, flux-jump counter is not reported properly due to a sign error. However, flux jumping works fine.

== Revision 3.0.19 ==
* '''Filename''' : rc_v03000019_16feb2007_raw.sof (no pof as one is not likely to run with this as regular firmware)
* '''Features'''
** data mode 3 is enabled.
** filter is disabled as a compromise to fit the raw-mode buffer.

* '''Bugs'''
** unreliable resetmce. Sometimes, firmware waked up non-responsive on lvds lines.

== Old Firmware Revisions ==
* '''4.0.4''': rc_v04000004_11oct2007.sof data mode 8 added (mixed filt + flux jump)
* '''4.0.3''': rc_v04000003_19sep2007.sof data mode 7 bit split readjusted to 10b error being bit 4 to 14
* '''4.0.2''': rc_v04000002_11sep2007.sof pid resolution increased to 10b, data mode 7 added
* '''4.0.1''': rc_v04000001_06sep2007.sof
* '''4.0.0''': rc_v04000000_29aug2007.sof supports readout_row_index * [[ bugs ]]

= To-Do List =
* the starting point for the servo is currently zero and it would be nice to have it programmable.

= RC Synthesis Notes =
# The following note applies when using Quartus versions earlier than Q7: Quartus.ini file had to exist in synth directory up to revision 4.0.a due to a bug that started in Quartus 6.1 and would synthesize away arbitrary parts of readout card. We contacted Altera at the time and they provided us the ini file.
# Timing: There is no "lock region" defined for readout card. Timing on readout card is tight and since version 3 or so any new feature would initially fail timing till some synthesis options were tweaked. One path that remains to be consistently marginal is from addr_gen counter (i.e. tga_o counter) in dispatch_wishbone.vhd to wishbone slaves particularly misc_banks_admin.vhd. Modules that are rewritten to address timing concerns are fsfb_corr, all_cards, misc_banks_admin, and finally instantiating an lpm counter instead of a counter from components library. Surprisingly, the lpm counter reduced 87 failures to 37, although looking at the technology map viewer, it seemed that they were both synthesized the same.
# Compile time: This was at some point 4.5 hours, after going to dual core PC, this was reduced to 35 minutes. After extending pid gains to 12b and fixing offset/sa_bias update code, the compile time increased to 1.5hr again with utilization up to ~70%.
# wbs_fb_storage, ram_8x64, pid_ram had to be regenerated using latest (Q7.2) MegaWizard to get rid of the bug associated with failure to read after power up until a reset was issued.
# During simulations, the initialization of RAM block with .hex files needs to be disabled. This is done by commenting out the following lines from the MegaWizard generated Megafunction files (remember to un-comment them before synthesizing the code):
lpm_file => "C:/scuba2_repository/cards/readout_card/fsfb_calc/source/rtl/ram_40x64.hex", and
lpm_file : STRING;
#Starting Q10.0 use TimeQuest timing analyzer as oppose to the classic one. The classic one is being phased out by Altera. In order to use TimeQuest, you need to have an sdc file present in your project directory.
----
[http://e-mode.phas.ubc.ca/mcewiki/index.php/Main_Page MCE Main Page]

Readout Card firmware

2011-05-04T22:01:27Z

Bburger: /* Revision 5.0.f */

* Synthesis Reminders (for firmware developers)
** quartus.ini is not needed anymore (Fixed as of Q7, Altera SR10783580 2010-10-24)
** Remember that readout_card/fsfb_clac/source/rtl/ram_40x64.vhd must be initialized with the ram_40x64.hex file in the same directory.
= Revision 5.1.2 =
* '''Filename:'''
** rc_stratix3_v05010002_18jan2011.sof (for Rev. E cards)
** rc_stratix3_v05010002_18jan2011.jic (for Rev. E cards)
** rc_v05010002_03feb2011.sof (for Rev. B cards)
** rc_v05010002_03feb2011.pof (for Rev. B cards)

* '''Features:'''
** based on 5.1.1 with k1 and k2 (filter params) limited to k1<16 and k2<32 in order to resolve the timing when compiling for smaller Stratix FPGA on RC Rev. B.

* '''Bug fix:'''
** the 2-rows-off filtered data readout introduced with configurable filter in rev. 5.1.0 and 5.1.1 is fixed now.

* '''Bugs:'''
** none so far.

* '''FPGA Resource Usage''' (readout_card.fit.rpt, rev. B)
; Total logic elements ; 33,285 / 41,250 ( 81 % ) ;
; Total pins ; 358 / 616 ( 58 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt, rev. B)
; Fast Model Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 6.591 ns
; Fast Model Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 7.206 ns
; Fast Model Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 18.299 ns

== Revision 5.1.1 (not recommended) ==
* '''Filename:'''
** rc_v05010001_01dec2010.sof (for Rev. B cards)

* '''Features:'''
** based on 5.1.0, but k1 and k2 (filter params) are now limited to k1<16 and k2<32 in order to resolve the timing failures of compiling 5.1.0 for smaller Stratix FPGA on RC Rev. B.

* '''Bugs:'''
** filter mode data is off by 2 rows.

== Revision 5.1.0 (not recommended) ==
* '''Filename:'''
** rc_stratix3_v05010000_01nov2010.sof (for Rev. E cards)
** rc_v05010000_01nov2010.sof (for Rev. B cards) has timing failures '''do not use!!!'''

* '''Features:'''
** added configurable filter parameters specified by ''fltr_coeff'', default is the fcutoff/fsampl=122Hz/15kHz. see [[ Digital 4-pole Butterworth Low-pass filter ]].
** ''fltr_type'' is set to 255 to indicate configurable filter parameters.
** see [http://www.phas.ubc.ca/~mce/mcedocs/software/SC2_ELE_S580_515_mce_command_description.pdf MCE command description]
* '''Details'''
** It is built on Quartus10.1.
** tcl files had to be updated as cmp syntax is not supported in Q10 anymore.
** Rev. E cards now can be identified by reading back pcb_rev as part of card_type, therefore both stratix I and III sof/pof/jic are generated from the same source.

* '''Bugs:'''
** rc_v05010000_01nov2010.sof has timing failures that were overlooked, do not use this firmware for Rev.B cards.
** '''filter mode data is off by 2 rows.'''

* '''FPGA Resource Usage and Timing Report''' (readout_card.fit.rpt and readout_card.tan.rpt): logic usage is upto 85% from 66% in 5.0.d/e/f

= Revision 5.0.f =
* '''Filename:'''
** rc_v0500000f_22oct2010.sof (for Rev. B cards)
** rc_stratix3_v0500000f_22oct2010.sof (for Rev. E cards)

* '''Features:'''
** Bugfix: integral clamp should work now. only positive integral_clamp values are valid!

* '''Details:''':
** SQ1FB is applied 18 clock cycles after start of a row visit (SQ1_Bias being applied) regardless of flux-jump being enabled or not. In pre-5.0.b firmware SQ1FB was being applied after 7 clock cycles when flux-jump was disabled and after 18 clock cycles when flux-jump was enabled.
** available for both Rev. E and Rev. B cards, the upper byte of card_type parameter now reports the pcb revision.
** development note: It is built on Quartus10.1.

* '''Bugs:'''
**none yet!

* '''FPGA Resource Usage and Timing Report''' (readout_card.fit.rpt and readout_card.tan.rpt): no change compared to 5.0.a/b/c/d

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 27,377 / 41,250 ( 66 % ) ;
; Total pins ; 358 / 616 ( 58 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.652 ns
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.385 ns
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.860 ns

== Revision 5.0.e (not recommended) ==
* '''Filename:'''
** rc_v0500000e_06oct2010.sof

* '''Details:'''
** an unsuccessful attempt to fix integral_clamp, but changed the functionality so that it clamps at the value, but it doesn't hold the clamp. i.e., if the calculated sq1fb becomes less than the specified clamp value, the sq1fb is not clamped anymore. This is not a desired functionality!

== Revision 5.0.d (not recommended) ==
* '''Filename:'''
** rc_v0500000d_04aug2010.sof

* '''Features:'''
** Bugfix: To fix the bug associated with negative flux-jumps, reverted to signed multiplier and hence, incremented the width of the flux-quanta multiplier input by 1.

* '''Details:''':
** SQ1FB is applied 18 clock cycles after start of a row visit (SQ1_Bias being applied) regardless of flux-jump being enabled or not. In pre-5.0.b firmware SQ1FB was being applied after 7 clock cycles when flux-jump was disabled and after 18 clock cycles when flux-jump was enabled.

* '''Bugs:'''
** '''integral_clamping is broken'''. To test the clamping, a servo-locked ramp was initiated on the sq1fb and then flux-jumping was turned on and observed by attaching a scope to the SQ1FB output. With integral_clamp=80000000, flux_quanta=8000, gaini=1, flux-jump enabled, we see [[http://e-mode.phas.ubc.ca/mcewiki/index.php/Image:Clamp_unstable.png scope snapshot]] used slow_fb_ramp.py script for testing.

* '''FPGA Resource Usage and Timing Report''' (readout_card.fit.rpt and readout_card.tan.rpt): no change compared to 5.0.a/b/c

== Revision 5.0.c (not recommended) ==
* '''Filename:'''
** rc_v0500000c_16jun2010.sof

* '''Features:'''
** Based on rev. 5.0.b
** Re-introduced flux-jump counter clamping to maintain continuity in behavior from past versions of firmware in the field.
** '''Important''': SQ1FB is applied 18 clock cycles after start of a row visit (SQ1_Bias being applied) regardless of flux-jump being enabled or not. In pre-5.0.b firmware SQ1FB was being applied after 7 clock cycles when flux-jump was disabled and after 18 clock cycles when flux-jump was enabled.

* '''Details:'''
* '''Bugs:'''
** '''flux-jump is broken'''. flux-jumping block misbehaves at the first jump in the negative range.

* '''FPGA Resource Usage''' (readout_card.fit.rpt): [[rc_5.0.c_fit_rpt]]
; Total logic elements ; 26,800 / 41,250 ( 65 % ) ;
; Total pins ; 358 / 616 ( 58 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;
; DSP block 9-bit elements ; 76 / 112 ( 68 % ) ;
; Total PLLs ; 1 / 6 ( 17 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt): [[rc_5.0.c_tan_rpt]]
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.964 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 4.382 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 15.924 ns ;

== Revision 5.0.b (not recommended) ==
* '''Filename:'''
** rc_v0500000b_03jun2010.sof

* '''Features:'''
** Based on rev. 5.0.a
** A bug that caused jumps in first-stage feedback, and detected as spikes in the raw data of pixels that were in servo_mode=0,1,2 was fixed. The jumps in FSFB were due to flux-jumping being enabled on live pixes with non-zero flx_quanta, and being disabled on the fly on dead pixels with flx_quanta=0. Flux-jumping is now disabled on a column-by-column basis if a column is in servo_mode = 0,1,2.
** Ineffective clamping was removed from the flux-jumping block (as per 5.0.9), as it is now replaced by the clamping that was perfected in rev. 5.0.10
** A sticky bit that only affected servo_mode=0,1,2 was also removed from the flux-jumping block.
** flx_lp_init commands now also clear the flux-jumping block as well.
** The 11-clock-cycle delay (in applying SQ1_FB) that in previous firmware only occurred when flux-jumping was enabled, now (in this version) is in effect all the time. Due to the bug-fix above, flux-jumping can be disabled on a column-by-column basis by setting servo_mode=0,1,2 when en_fb_jump=1. Before the change, this meant that constant values could be applied with or without the 11-cycle delay if en_fb_jump=1 or 0. To make the delay consistent, it is now always 11 cycles. As background, the flux-jumping block is pipelined, meaning that it does calculations for all 8 channels serially. The serialization is because of DSP-block limitations in the Readout Card FPGA that prevent us from doing all 8 channels in parallel. The reason that it takes 11 cycles to complete the flux-jumping calculations is because the values are computed for the eight channels in three ALU stages: 8 + 3 = 11 cycles. Adding 11 cycles to the 7 cycles of latency from other stages in the system results in: 11 + 7 = 18 cycles of latency from the start of a row dwell period before the first-stage feedback is applied. In rc_v5.0.c, I enforce the 18-cycle delay even when flux-jumping is not enabled to maintain uniformity across all eight channels, because flux-jumping is enabled/disabled on a per-channel basis. In other words, if I hadn't enforced the 18-cycle delay, some channels could have their feedback applied after 7 cycles, while others could have it applied after 18 cycles. I wasn't a fan of this non-uniformity. I realize that 18 cycles is a long time. In fact, so is 7. In the last few months, we have been discussing how to reduce these times to 1 cycle, because every experiment out there wants to multiplex as fast as possible, and the 7/18-delay is a rate limiting step.
** The flux-jumping code was re-arranged in the flux-jumping block to reflect the flow of data through the pipeline and make it easier to understand.

* '''Details:'''

* '''Bugs:'''
** flux-jump does not work when jumping to negative values.

* '''FPGA Resource Usage''' (readout_card.fit.rpt): [[rc_5.0.b_fit_rpt]]
; Total logic elements ; 26,745 / 41,250 ( 65 % ) ;
; Total pins ; 358 / 616 ( 58 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;
; DSP block 9-bit elements ; 76 / 112 ( 68 % ) ;
; Total PLLs ; 1 / 6 ( 17 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;
* '''FPGA Timing Analysis''' (readout_card.tan.rpt): [[rc_5.0.b_tan_rpt]]
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.459 ns
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.895 ns
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 15.956 ns

== Revision 5.0.a (not recommended) ==
* '''Filename:'''
** rc_v0500000a_12mar2010.sof

* '''Features:'''
** Based on the merger of rev. 5.0.8 and 5.0.9.
** '''integral_clamp''' command is added where a clamp value is set for the integral term and once the integral term hits that value, the integral-term is clamped to that value and p-term and d-term are clamped to zero. When integral_term=0 then no clamping is in effect, similar to previous releases of firmware.
** The low pass filter has 20-bit input and f_3dB/f_samp = 122Hz/15kHz .
** The flux-jump clamping that was removed in 5.0.9 is included once again here, as we decided this is safer for now.

* '''Details:'''
** "lock_dat_left" parameter that was removed in 5.0.9 is now implemented as "lock_dat_lsb"

* '''Bugs:'''
** flx_lp_init does not reinitialize the flux-jump block

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis
** tag name: rc_v0500000a_12mar2009! years were mixed up!

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
* '''FPGA Timing Analysis''' (readout_card.tan.rpt):

== Revision 5.0.9 (buggy) ==
* '''Filename:'''
** rc_v05000009_13nov2009.sof

* '''Features:'''
** Based on rev. 5.0.4
** Removes a sticky bit in pid calculation result storage -- in fsfb_processor.
** Adds a command to clamp the growth of the I-term to prevent wrapping and track down the source of Caltech's FSFB jumps.
** Removed the unused lock_dat_left parameter. The ability to shift left was moved to the fsfb_corr block some time ago.
** Fixed a sign extension bug acting on the flux quanta, which limited the value to 8191. Changed the extension from signed to unsigned.
** Removed ineffective clamping in the flux-jump calculation block.
** IMPORTANT: Must be used in conjunction with firmware rev. 5.0.0+ of all other cards.

* '''Details:'''

* '''Bugs:'''
** integral_clamp read/write command does not work.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 27,960 / 41,250 ( 68 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.825 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.878 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 14.397 ns ;

== Revision 5.0.8 (UBC only) ==
* '''Filename:'''
** rc_v05000008_09oct2009.sof

* '''Features:'''
** Based on rev. 5.0.4
** type 1 low-pass filter: f3dB=122Hz for fsample=15kHz
** Filter-input-width changed from 18b to 20b with no sticky bits!
** removed sticky bits in internal arithmetic of the filter.

= Revision 5.0.7 (type-2 filter) =
* '''Filename:'''
** rc_v05000007_09oct2009.sof

* '''Features:'''
** Based on rev. 5.0.4
** type-2 low-pass-filter: f3dB=75Hz for fsample=30000.
** Filter-input-width changed from 18b to 20b with no sticky bits!
** inter-biquad-gain-scaling for the filter is 2^14
** filter results are scaled down by 2^3 in the output of the filter.
** removed sticky bits in internal arithmetics
** _correction_ disabled in fsfb_proc_pidz

* '''Details:'''
** quartus.ini file was '''not''' present in synth directory.

* '''Bugs:'''
** none to report

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
== Revision 5.0.6 (UBC only) ==
* '''Filename:'''
** rc_stratix3_v05000006_15sep2009.sof

* '''Features:'''
** Only Valid for Rev. C/D Cards
** Based on rev. 5.0.3
** tcl file updated for Rev. D and aligned with top-level and qsf (project file).
** flux loop commented, just to try sampling the ADC.
** compiled with Q9.1

== Revision 5.0.5 (UBC only) ==
* '''Filename:'''
** rc_v05000005_04sep2009.sof

* '''Features:'''
** Based on rev. 5.0.2
** changed the low-pass-filter to f(3db)=75Hz for f(sample)=30000.

* '''Details:'''
** quartus.ini file was '''not''' present in synth directory.

* '''Bugs:'''
** negative inputs to the filter cause filter to have a non-flat pass-band region. may have to do with sign-handling...

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
* '''FPGA Timing Analysis''' (readout_card.tan.rpt):

= Revision 5.0.4 =
* '''Filename:'''
** rc_v05000004_28aug2009.sof

* '''Features:'''
** Based on rev. 5.0.2
** BUG Fix: handles 14-bit flux quanta (changed the multiplier to unsigned)
** BUG Fix: changed standard logic vector extension from signed to unsigned in flux-jumping slave.
** IMPORTANT: Must be used in conjunction with firmware rev. 5.0.0+ of all other cards.

* '''Details:'''

* '''Bugs:'''
** None so far.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,170 / 41,250 ( 63 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.541 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.612 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 15.398 ns ;

= Revision 5.0.3 =
* '''Filename:'''
** rc_stratix3_v05000003_21aug2009.sof

* '''Features:'''
** ONLY valid REV C/D RC Cards
** Based on rev. 5.0.2
** flux loop commented, just to try sampling the ADC.
** updated tcl file, but still need to rely on project file as well as qsf file.
** changed default level of adc_sclk to '1'
** dac_clr_n was changed from an output to an input.
** added 'locked' interface to rc_pll_stratix_iii
** renamed the adc_pll clock signals to more explanitory names
** added the FPGA_DEVICE_FAMILY generic to the dispatch interace for synthesis of the dc_fifo in lvds_rx
** uncommented DDR interface to force the syntesizer to use correct left and right PLLs (in conjunction with ADC and DDR PLLs)
** added test signals to test_status to see clocks on the scope.
== Revision 5.0.2 (buggy) ==
* '''Filename:'''
** rc_v05000002_test00_tagged.sof

* '''Features:'''
** Based on rev. 5.0.1
** Fixed a bug in wbs_frame_data that stored data incorrectly if reporting 1 or 2 pixels only.
** IMPORTANT: Must be used in conjunction with firmware rev. 5.0.0+ of all other cards.

* '''Details:'''

* '''Bugs:'''
** None so far.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,186 / 41,250 ( 63 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.755 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.979 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.067 ns ;

== Revision 5.0.1 (buggy) (Filter + Raw + Rectangle, 2 LVDS) ==
* '''Filename:'''
** rc_v05000001_26may2009.sof

* '''Features:'''
** Combines features in rev. 5.0.0 (2 LVDS Lines) and rev. 4.0.e (Filtered + Raw), with the NEW rectangle mode.
** IMPORTANT: Must be used in conjunction with firmware rev. 5.0.0+ of all other cards.

* '''Details:'''
** [[CVS Diff Between sys_v05000000 and rc_v05000001]]

* '''Bugs:'''
** Has a bug in wbs_frame_data that stored data incorrectly if reporting 1 or 2 pixels only.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,565 / 41,250 ( 64 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.656 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.861 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 14.167 ns ;

== Revision 5.0.0 (Filter Only, 2 LVDS) ==
* '''Filename:'''
** rc_v05000000_22dec2008.sof (tagged as sys_v05000000_22dec2008)

* '''Features:'''
** IMPORTANT: Must be used in conjunction with firmware v05000000+ of all other cards!!!
** Adds the ability to read out one column of data continuously from readout cards
** Adds data mode 11, which is an engineering mode. Data points are 32-bits, and bits [9..3]=row_index, [2..0]=column_index. This mode is useful for determining which pixels one is reading out in the array, in column mode for example.

* '''Details:'''
** [[CVS Diff Between rc_v0400000c and sys_v05000000]]

* '''Bugs:'''
** None so far.

* '''Synthesis Notes:'''
** The quartus.ini file was not present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,607 / 41,250 ( 65 % ) ;
; Total memory bits ; 406,016 / 3,423,744 ( 12 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.558 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.892 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.987 ns ;

== Revision 4.0.f (Filter + Raw, 1 LVDS) ==
* '''Filename:'''
** rc_v0400000f_12feb2010.sof

* '''Features:'''
** Based on 4.0.e and in parallel with 5.0.9 (equivalent version, clamping is not included)
** Incorporates fixes that were done to flux-jumping between 5.0.2 - 5.0.4 - 5.0.9. Namely:
*** Changes a multiplier from signed to unsigned (in fsfb_corr_multplier.vhd).
*** Changes sign extension from signed to unsigned (in flux_quanta_ram_admin.vhd).

* '''Details:'''

* '''Bugs:'''
** None reported yet.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,773 / 41,250 ( 65 % ) ;
; Total memory bits ; 1,321,984 / 3,423,744 ( 39 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.539 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 4.118 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 17.318 ns ;

== Revision 4.0.e (Filter + Raw, 1 LVDS) ==
* '''Filename:'''
** rc_v0400000e_27apr2009.sof

* '''Features:'''
** Based on 4.0.d
** Combines both raw- and filtered-data modes.
** fpga_temp, card_temp, card_id commands are disabled.
** Tested by Matt Hasselfield.

* '''Details:'''

* '''Bugs:'''
** fpga_temp, card_temp, card_id commands are disabled.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 27,048 / 41,250 ( 66 % ) ;
; Total memory bits ; 1,321,984 / 3,423,744 ( 39 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.675 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.907 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.728 ns ;

== Revision 4.0.d (Raw Only, 1 LVDS) ==
* '''Filename:''' rc_v0400000d_20090417.sof

* '''Features:'''
** Based on v4.0.c, but has the filter removed, and implements a single 65536-index RAM block for storing 50 MHz raw-data samples.
** The firmware takes a new command called readout_col_index which specifies which column to capture raw data from.
** Other than readout_col_index, the firmware functions the same as previous raw-data firmware, including then need to issue a capture_raw command.
** For more information on raw-data, see: http://e-mode.phas.ubc.ca/mcewiki/index.php/Raw-mode_readout
** This firmware also integrates some of the improvements that were implemented in 4.4.0, like the removal of the tga_o signal from an FSM in dispatch_wishbone.vhd.

* '''Details:'''
** Differences between 4.0.c and 4.0.d
U system/test/source/tb/tb_cc_rcs_bcs_ac.vhd
U all_cards/dispatch/source/rtl/dispatch_wishbone.vhd
U library/sys_param/source/rtl/wishbone_pack.vhd
U readout_card/adc_sample_coadd/source/rtl/adc_sample_coadd.vhd
U readout_card/adc_sample_coadd/source/rtl/adc_sample_coadd_pack.vhd
U readout_card/flux_loop/source/rtl/flux_loop.vhd
U readout_card/flux_loop/source/rtl/flux_loop_pack.vhd
U readout_card/flux_loop_ctrl/source/rtl/flux_loop_ctrl.vhd
U readout_card/flux_loop_ctrl/source/rtl/flux_loop_ctrl_pack.vhd
U readout_card/flux_loop_ctrl/source/tb/tb1_flux_loop_ctrl.vhd
U readout_card/flux_loop_ctrl/source/tb/tb2_flux_loop_ctrl.vhd
U readout_card/fsfb_calc/source/rtl/fsfb_fltr_regs.vhd
U readout_card/fsfb_corr/source/rtl/fsfb_corr.vhd
U readout_card/readout_card/source/rtl/readout_card.vhd
U readout_card/readout_card/source/rtl/readout_card_pack.vhd
U readout_card/wbs_frame_data/source/rtl/wbs_frame_data.vhd
U readout_card/wbs_frame_data/source/rtl/wbs_frame_data_pack.vhd

* '''Bugs:'''
** None so far.
** fpga_temp, card_temp, card_id commands are not supported.

* '''Synthesis Notes:'''
** The quartus.ini file was present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 24,554 / 41,250 ( 60 % ) ;
; Total memory bits ; 1,262,592 / 3,423,744 ( 37 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.991 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.864 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 17.052 ns ;

== Revision 4.4.1 ==
* '''Filename:''' rc_v04040001_21nov2008

* '''Features:'''
** Fixes a bug that froze up the firmware if any of the following commands were issued: CARD_ID_ADDR, CARD_TEMP_ADDR, FPGA_TEMP_ADDR in 4.4.0 only.

* '''Details:'''
** The bug fix include adding more logic to the wishbone ack path (readout_card.vhd), which subsequently decreased the minimum clock setup time to 1.588ns. The new logic will catch errors that the old logic wouldn't have, and is now consistent with the firmware on all the other cards. However, if timing becomes an issue, the logic may have to revert back to that which was in version 4.0.c.

* '''Bugs:'''
** None so far.

* '''Synthesis Notes:'''
** The quartus.ini file was not present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 27,241 / 41,250 ( 66 % ) ;
; Total memory bits ; 405,504 / 3,423,744 ( 12 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.588 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.585 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 17.057 ns ;

== Revision 4.4.0 (buggy) ==
* '''Filename:''' rc_v04040000_02oct2008
* '''Features:'''
** Reinstated the data modes in wbs_frame_data.vhd that were removed in 4.0.c. This firmware has the following modes: '''0, 1, 2, 4, 5, 7, 10'''. The modes that are not present are: '''3''' (raw data), '''6''' (replaced by data_mode = 7), '''8''' (replaced by data_mode = 10), '''9''' (replaced by data_mode = 10). For more information on data modes, see [[Data mode]].
** Re-integrated the id_thermo and fpga_thermo block in the readout_card.vhd top level that was removed in 4.0.c.
** Removed the sticky bit in fsfb_corr.vhd, which was enabled when flux-jumping was turned on. Because the feedback is signed, the sticky bit would usually reflect the value of the 14th bit, except in situations when the number of flux quanta to jump was greater than 1 (i.e. cosmic rays, IV-curves, etc). Flux jumps are made at a maximum rate of one per frame period, so that if the First-Stage Feedback increased past the 13th bit, it would not be reflected in the feedback applied. Now it is.
* '''Details:'''
** Simplified the FSM logic in wbs_frame_data.vhd that determines when to transition from IDLE to WSS1. This was done to lower the number of gates in that path, and ease the timing.
** Removed the z_dat_i port in fsfb_processor.vhd and fsfb_calc_pack.vhd to the fsfb_proc_pidz block, in an effort to make it clearer within that block that the z-term is always = 0.
** Removed the z-term sign extension in fsfb_proc_pidz.vhd, and the [d-term + z-term] adder to free up DSP resources since the z-term is always = 0.
** Adjusted the indentation in fsfb_io_controller.vhd to make the file more readable.
** Moved the tga_o signal out of the dispatch_wishbone.vhd FSM, and made it a continuous assignment. This signal had one of the highest fan-out counts in the RTL design, and actually was impossible to route in Stratix III chips in its previous configuration because of the number of gates on the fan-out. As a consequence of making it a continuous assignment, the Stratix III fitter was able to succeed, and the Stratix I timing characteristics were greatly improved. This is the most significant change in this revision. This change single-handedly increased the minimum slack from 1.282 ns in v0400000c to 2.372 ns (or 56.7 MHz max) in this revision.
* '''Bugs:'''
** The following commands lock up the Readout Card firmware: CARD_ID_ADDR, CARD_TEMP_ADDR, FPGA_TEMP_ADDR.
** fb_const0 commands to channel 0 do not work. The value is stored in the register, but not applied to the DAC. Thus, read-back returns the correct value, but the DAC does not
* '''Synthesis Notes:'''
** The quartus.ini file was not present in the synth directory during synthesis.
* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 27,099 / 41,250 ( 66 % ) ;
; Total memory bits ; 406,016 / 3,423,744 ( 12 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.372 ns ;
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 4.052 ns ;
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.066 ns ;

== Revision 4.0.c ==
* '''Filename:''' rc_v0400000c_15aug2008.sof
* '''Features:'''
** Only has data modes 0, 1, 4, and 10.
** Fixed the bug that exists in 4.0.b, 4.0.a, and 4.0.9 that prevented the fb_const value from being applied to channel zero (wbs_fb_data.vhd).
* '''Details:'''
** Changed a counter in the dispatch block to ease timing constraints in synthesis (dispatch_wishbone.vhd)
** Updated the tagged versions of dispatch.vhd , dispatch_cmd_receive.vhd, and dispatch_reply_transmit.vhd to the version that is used by all the other cards.
** '''Removed''' the fpga_termo (command: '''fpga_temp''') and id_thermo (commands: '''card_temp, card_id''') to ease timing constraints in synthesis (readout_card.vhd)
** Updated the tagged version of fpga_termo.vhd to include the new 'stale bit' feature
** Updated the tagged version of frame_timing_core.vhd to include the new 'err_o' interface
* '''Bugs:'''
** None reported yet
* '''Synthesis Notes:'''
** The quartus.ini file was not present in the synth directory during synthesis.
* '''FPGA Resource Usage:'''
Total logic elements : 25,058 / 41,250 ( 61 % )
Total memory bits : 400,896 / 3,423,744 ( 12 % )

* '''Timing Analysis''' (readout_card.tan.rpt):
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.282 ns ;
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.736 ns ;
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.665 ns ;

== Revision 4.0.b (buggy) ==
Note: This revision is on a watch list, after the bug detected 15 July 2008. See the bug section for more details.
* '''Filename''' : rc_v0400000b_04aug2008.sof
* '''Features'''
** data_mode 10 is added to provide more filtfb bits (compared to data mode 9) for planet observations. filtered_dat(27 downto 3) & flux_cnt_dat(6 downto 0)

* '''Bugs'''
** An unexplained bug that appeared in 4.0.a and may still be present in 4.0.b is a problem with the readout of channels being clipped out of data reporting. [[Bug 1 Notes]]

* ''' Synthesis note '''
** Quartus.ini removed.

== Revision 4.0.a (buggy) ==
Note: This revision is on a watch list, after the bug detected 15 July 2008. See the bug section for more details.
* '''Filename''' : rc_v0400000a_07jul2008.sof
* '''Bug Fix'''
** mce_status and adc_offset/flx_quanta commands do not fail after power up.
* ''' Synthesis note '''
** Quartus.ini removed.

* '''Bugs'''
** Seems to clip out channel 0 from data reporting.

== Revision 4.0.9 (buggy) ==
* '''Filename''' : rc_v04000009_26jun2008.sof
* '''Features'''
** sa_bias and offset DACs only refreshed when new values are written. (in previous versions, DACs were refreshed every frame)
* '''Bugs'''
** fb_const0 commands to channel 0 do not work. The value is stored in the register, but not applied to the DAC. Thus, read-back returns the correct value, but the DAC does not.
** reading flx_quanta and adc_offset right after power up hangs the reply datapath to CC. resetmce clears this error as temporary solution. the problem is caused by first read ack of the wishbone slave.

== Revision 4.0.8 ==
* '''Filename''' : rc_v04000008_26jun2008.sof
* '''Features'''
** The gaini, gainp, gaind resolution increased to 12-bit, i.e. -2048 to 2047 (formerly 10-bit).

* '''Bug fix'''
** the bug associated with gainpid read before mce_reset is fixed.

* ''' Synthesis note '''
** Quartus.ini removed.

== Revision 4.3.7 ==
* '''Filename''' : rc_v04030007_26may2008_raw.sof
* '''Features'''
** 14-bit raw mode enabled to buffer a snapshot of 50MHz samples for 2 frames of row_len * num_rows samples.
** In order to extend the raw-mode to 14-bit, an assumption is made that the raw buffer is not written to while being read. Therefore, make sure there is at least 2*row_len*num_rows*20ns between issuing captr_raw command and reading back the raw data.
** In order to save RAM for raw mode, two memory-intensive features are disabled:
*** low-pass filter disabled ( mixed filtfb data modes 6, 7, 9 are also disabled)
*** PID (gainp0, gaini0, gaind0) readback disabled. one can still set PID values and run servo, but can not read back the values.

== Revision 4.2.7 ==
* '''Filename''' : rc_v04020007_24may2008_raw.sof
* '''Features'''
** raw mode enabled to buffer a snapshot of 50MHz samples for 2 frames of row_len * num_rows samples.
** In order to save RAM for raw mode, two memory-intensive features are disabled:
*** low-pass filter disabled ( mixed filtfb data modes 6, 7, 9 are also disabled)
*** PID (gainp0, gaini0, gaind0) readback disabled. one can still set PID values and run servo, but can not read back the values.
* '''Bug fix'''
** the bug associated with reading from raw-buffer is fixed.

== Revision 4.1.7 ==
* '''Filename''' : rc_v04010007_25apr2008_raw.sof
* '''Features'''
** raw mode enabled to buffer a snapshot of 50MHz samples for 2 frames of row_len * num_rows samples.
** In order to save RAM for raw mode, two memory-intensive features are disabled:
*** low-pass filter disabled ( mixed filtfb data modes 6, 7, 9 are also disabled)
*** PID (gainp0, gaini0, gaind0) readback disabled. one can still set PID values and run servo, but can not read back the values.
* '''Bugs'''
** after each readout frame, raw-buffer readout counter falls behind by 3 and this causes skipping 3 50MHz samples in the data stream and column-data being messed up in subsequent frames. Data can be rearranged by post processing.

== Revision 4.0.6 (buggy) ==
* '''Filename''' : rc_v04000006_15feb2008.sof or .pof
* '''Features'''
** '''bugfix''': unreliable reset due to unsafe and incomplete state machines is fixed.
** '''bugfix''': flux_jump sign problem fixed, so far proved in const_mode, to be tested in servo_mode with cold setup.
** servo_mode=2 or ramp previously only went from 0 to ramp_amp, but now goes from -8192 to -8192+ramp_amp
** new commands are added: ''scratch'' and ''card_type''. Scratch takes 8 values and can be used by software to detect reset.
** slot_id and fw_rev are now integrated as part of all_cards.vhd
** lvds_tx_b=0, This will allow Clock Card to use the secondary backplane lvds line and check whether RC is plugged in.
** filter_coeff in misc_banks_admin commented as it is not implemented and causes timing problems.

* '''Bugs'''
** reading gainp/gaini/gaind right after power up hangs the reply datapath to CC. resetmce clears this error as temporary solution. the problem is caused by first read ack of pid_ram_admin.
** slot_id is only set after a resetmce is issued. (using the latest all_cards in the next revision will fix this)
** has spurious spikes on channel 7 data, which max out the integral, and cause the detectors to come unlocked. This firmware officially meets timing requirements, but the bug could be due to marginal timing on the longest data paths, i.e. ~0.1 ns in some cases.

== Revision 4.0.5 ==
* '''Filename''' : rc_v04000005_01nov2007.sof or .pof
* '''Features'''
** data mode 9 (mixed filt + flux jump) with windowing readjusted compared to data mode 8

* '''Bugs'''
** unreliable resetmce. Sometimes, firmware waked up non-responsive on lvds lines.
** In data mode 5 and 9, flux-jump counter is not reported properly due to a sign error. However, flux jumping works fine.

== Revision 3.0.19 ==
* '''Filename''' : rc_v03000019_16feb2007_raw.sof (no pof as one is not likely to run with this as regular firmware)
* '''Features'''
** data mode 3 is enabled.
** filter is disabled as a compromise to fit the raw-mode buffer.

* '''Bugs'''
** unreliable resetmce. Sometimes, firmware waked up non-responsive on lvds lines.

== Old Firmware Revisions ==
* '''4.0.4''': rc_v04000004_11oct2007.sof data mode 8 added (mixed filt + flux jump)
* '''4.0.3''': rc_v04000003_19sep2007.sof data mode 7 bit split readjusted to 10b error being bit 4 to 14
* '''4.0.2''': rc_v04000002_11sep2007.sof pid resolution increased to 10b, data mode 7 added
* '''4.0.1''': rc_v04000001_06sep2007.sof
* '''4.0.0''': rc_v04000000_29aug2007.sof supports readout_row_index * [[ bugs ]]

= To-Do List =
* the starting point for the servo is currently zero and it would be nice to have it programmable.

= RC Synthesis Notes =
# The following note applies when using Quartus versions earlier than Q7: Quartus.ini file had to exist in synth directory up to revision 4.0.a due to a bug that started in Quartus 6.1 and would synthesize away arbitrary parts of readout card. We contacted Altera at the time and they provided us the ini file.
# Timing: There is no "lock region" defined for readout card. Timing on readout card is tight and since version 3 or so any new feature would initially fail timing till some synthesis options were tweaked. One path that remains to be consistently marginal is from addr_gen counter (i.e. tga_o counter) in dispatch_wishbone.vhd to wishbone slaves particularly misc_banks_admin.vhd. Modules that are rewritten to address timing concerns are fsfb_corr, all_cards, misc_banks_admin, and finally instantiating an lpm counter instead of a counter from components library. Surprisingly, the lpm counter reduced 87 failures to 37, although looking at the technology map viewer, it seemed that they were both synthesized the same.
# Compile time: This was at some point 4.5 hours, after going to dual core PC, this was reduced to 35 minutes. After extending pid gains to 12b and fixing offset/sa_bias update code, the compile time increased to 1.5hr again with utilization up to ~70%.
# wbs_fb_storage, ram_8x64, pid_ram had to be regenerated using latest (Q7.2) MegaWizard to get rid of the bug associated with failure to read after power up until a reset was issued.
# During simulations, the initialization of RAM block with .hex files needs to be disabled. This is done by commenting out the following lines from the MegaWizard generated Megafunction files (remember to un-comment them before synthesizing the code):
lpm_file => "C:/scuba2_repository/cards/readout_card/fsfb_calc/source/rtl/ram_40x64.hex", and
lpm_file : STRING;
#Starting Q10.0 use TimeQuest timing analyzer as oppose to the classic one. The classic one is being phased out by Altera. In order to use TimeQuest, you need to have an sdc file present in your project directory.
----
[http://e-mode.phas.ubc.ca/mcewiki/index.php/Main_Page MCE Main Page]

Readout Card firmware

2011-05-04T21:57:36Z

Bburger: /* Revision 5.0.a */

* Synthesis Reminders (for firmware developers)
** quartus.ini is not needed anymore (Fixed as of Q7, Altera SR10783580 2010-10-24)
** Remember that readout_card/fsfb_clac/source/rtl/ram_40x64.vhd must be initialized with the ram_40x64.hex file in the same directory.
= Revision 5.1.2 =
* '''Filename:'''
** rc_stratix3_v05010002_18jan2011.sof (for Rev. E cards)
** rc_stratix3_v05010002_18jan2011.jic (for Rev. E cards)
** rc_v05010002_03feb2011.sof (for Rev. B cards)
** rc_v05010002_03feb2011.pof (for Rev. B cards)

* '''Features:'''
** based on 5.1.1 with k1 and k2 (filter params) limited to k1<16 and k2<32 in order to resolve the timing when compiling for smaller Stratix FPGA on RC Rev. B.

* '''Bug fix:'''
** the 2-rows-off filtered data readout introduced with configurable filter in rev. 5.1.0 and 5.1.1 is fixed now.

* '''Bugs:'''
** none so far.

* '''FPGA Resource Usage''' (readout_card.fit.rpt, rev. B)
; Total logic elements ; 33,285 / 41,250 ( 81 % ) ;
; Total pins ; 358 / 616 ( 58 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt, rev. B)
; Fast Model Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 6.591 ns
; Fast Model Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 7.206 ns
; Fast Model Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 18.299 ns

== Revision 5.1.1 (not recommended) ==
* '''Filename:'''
** rc_v05010001_01dec2010.sof (for Rev. B cards)

* '''Features:'''
** based on 5.1.0, but k1 and k2 (filter params) are now limited to k1<16 and k2<32 in order to resolve the timing failures of compiling 5.1.0 for smaller Stratix FPGA on RC Rev. B.

* '''Bugs:'''
** filter mode data is off by 2 rows.

== Revision 5.1.0 (not recommended) ==
* '''Filename:'''
** rc_stratix3_v05010000_01nov2010.sof (for Rev. E cards)
** rc_v05010000_01nov2010.sof (for Rev. B cards) has timing failures '''do not use!!!'''

* '''Features:'''
** added configurable filter parameters specified by ''fltr_coeff'', default is the fcutoff/fsampl=122Hz/15kHz. see [[ Digital 4-pole Butterworth Low-pass filter ]].
** ''fltr_type'' is set to 255 to indicate configurable filter parameters.
** see [http://www.phas.ubc.ca/~mce/mcedocs/software/SC2_ELE_S580_515_mce_command_description.pdf MCE command description]
* '''Details'''
** It is built on Quartus10.1.
** tcl files had to be updated as cmp syntax is not supported in Q10 anymore.
** Rev. E cards now can be identified by reading back pcb_rev as part of card_type, therefore both stratix I and III sof/pof/jic are generated from the same source.

* '''Bugs:'''
** rc_v05010000_01nov2010.sof has timing failures that were overlooked, do not use this firmware for Rev.B cards.
** '''filter mode data is off by 2 rows.'''

* '''FPGA Resource Usage and Timing Report''' (readout_card.fit.rpt and readout_card.tan.rpt): logic usage is upto 85% from 66% in 5.0.d/e/f

= Revision 5.0.f =
* '''Filename:'''
** rc_v0500000f_22oct2010.sof (for Rev. B cards)
** rc_stratix3_v0500000f_22oct2010.sof (for Rev. E cards)

* '''Features:'''
** Bugfix: integral clamp should work now. only positive integral_clamp values are valid!

* '''Details:''':
** SQ1FB is applied 18 clock cycles after start of a row visit (SQ1_Bias being applied) regardless of flux-jump being enabled or not. In pre-5.0.b firmware SQ1FB was being applied after 7 clock cycles when flux-jump was disabled and after 18 clock cycles when flux-jump was enabled.
** available for both Rev. E and Rev. B cards, the upper byte of card_type parameter now reports the pcb revision.
** development note: It is built on Quartus10.1.

* '''Bugs:'''
**none yet!

* '''FPGA Resource Usage and Timing Report''' (readout_card.fit.rpt and readout_card.tan.rpt): no change compared to 5.0.a/b/c/d

== Revision 5.0.e (not recommended) ==
* '''Filename:'''
** rc_v0500000e_06oct2010.sof

* '''Details:'''
** an unsuccessful attempt to fix integral_clamp, but changed the functionality so that it clamps at the value, but it doesn't hold the clamp. i.e., if the calculated sq1fb becomes less than the specified clamp value, the sq1fb is not clamped anymore. This is not a desired functionality!

== Revision 5.0.d (not recommended) ==
* '''Filename:'''
** rc_v0500000d_04aug2010.sof

* '''Features:'''
** Bugfix: To fix the bug associated with negative flux-jumps, reverted to signed multiplier and hence, incremented the width of the flux-quanta multiplier input by 1.

* '''Details:''':
** SQ1FB is applied 18 clock cycles after start of a row visit (SQ1_Bias being applied) regardless of flux-jump being enabled or not. In pre-5.0.b firmware SQ1FB was being applied after 7 clock cycles when flux-jump was disabled and after 18 clock cycles when flux-jump was enabled.

* '''Bugs:'''
** '''integral_clamping is broken'''. To test the clamping, a servo-locked ramp was initiated on the sq1fb and then flux-jumping was turned on and observed by attaching a scope to the SQ1FB output. With integral_clamp=80000000, flux_quanta=8000, gaini=1, flux-jump enabled, we see [[http://e-mode.phas.ubc.ca/mcewiki/index.php/Image:Clamp_unstable.png scope snapshot]] used slow_fb_ramp.py script for testing.

* '''FPGA Resource Usage and Timing Report''' (readout_card.fit.rpt and readout_card.tan.rpt): no change compared to 5.0.a/b/c

== Revision 5.0.c (not recommended) ==
* '''Filename:'''
** rc_v0500000c_16jun2010.sof

* '''Features:'''
** Based on rev. 5.0.b
** Re-introduced flux-jump counter clamping to maintain continuity in behavior from past versions of firmware in the field.
** '''Important''': SQ1FB is applied 18 clock cycles after start of a row visit (SQ1_Bias being applied) regardless of flux-jump being enabled or not. In pre-5.0.b firmware SQ1FB was being applied after 7 clock cycles when flux-jump was disabled and after 18 clock cycles when flux-jump was enabled.

* '''Details:'''
* '''Bugs:'''
** '''flux-jump is broken'''. flux-jumping block misbehaves at the first jump in the negative range.

* '''FPGA Resource Usage''' (readout_card.fit.rpt): [[rc_5.0.c_fit_rpt]]
; Total logic elements ; 26,800 / 41,250 ( 65 % ) ;
; Total pins ; 358 / 616 ( 58 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;
; DSP block 9-bit elements ; 76 / 112 ( 68 % ) ;
; Total PLLs ; 1 / 6 ( 17 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt): [[rc_5.0.c_tan_rpt]]
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.964 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 4.382 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 15.924 ns ;

== Revision 5.0.b (not recommended) ==
* '''Filename:'''
** rc_v0500000b_03jun2010.sof

* '''Features:'''
** Based on rev. 5.0.a
** A bug that caused jumps in first-stage feedback, and detected as spikes in the raw data of pixels that were in servo_mode=0,1,2 was fixed. The jumps in FSFB were due to flux-jumping being enabled on live pixes with non-zero flx_quanta, and being disabled on the fly on dead pixels with flx_quanta=0. Flux-jumping is now disabled on a column-by-column basis if a column is in servo_mode = 0,1,2.
** Ineffective clamping was removed from the flux-jumping block (as per 5.0.9), as it is now replaced by the clamping that was perfected in rev. 5.0.10
** A sticky bit that only affected servo_mode=0,1,2 was also removed from the flux-jumping block.
** flx_lp_init commands now also clear the flux-jumping block as well.
** The 11-clock-cycle delay (in applying SQ1_FB) that in previous firmware only occurred when flux-jumping was enabled, now (in this version) is in effect all the time. Due to the bug-fix above, flux-jumping can be disabled on a column-by-column basis by setting servo_mode=0,1,2 when en_fb_jump=1. Before the change, this meant that constant values could be applied with or without the 11-cycle delay if en_fb_jump=1 or 0. To make the delay consistent, it is now always 11 cycles. As background, the flux-jumping block is pipelined, meaning that it does calculations for all 8 channels serially. The serialization is because of DSP-block limitations in the Readout Card FPGA that prevent us from doing all 8 channels in parallel. The reason that it takes 11 cycles to complete the flux-jumping calculations is because the values are computed for the eight channels in three ALU stages: 8 + 3 = 11 cycles. Adding 11 cycles to the 7 cycles of latency from other stages in the system results in: 11 + 7 = 18 cycles of latency from the start of a row dwell period before the first-stage feedback is applied. In rc_v5.0.c, I enforce the 18-cycle delay even when flux-jumping is not enabled to maintain uniformity across all eight channels, because flux-jumping is enabled/disabled on a per-channel basis. In other words, if I hadn't enforced the 18-cycle delay, some channels could have their feedback applied after 7 cycles, while others could have it applied after 18 cycles. I wasn't a fan of this non-uniformity. I realize that 18 cycles is a long time. In fact, so is 7. In the last few months, we have been discussing how to reduce these times to 1 cycle, because every experiment out there wants to multiplex as fast as possible, and the 7/18-delay is a rate limiting step.
** The flux-jumping code was re-arranged in the flux-jumping block to reflect the flow of data through the pipeline and make it easier to understand.

* '''Details:'''

* '''Bugs:'''
** flux-jump does not work when jumping to negative values.

* '''FPGA Resource Usage''' (readout_card.fit.rpt): [[rc_5.0.b_fit_rpt]]
; Total logic elements ; 26,745 / 41,250 ( 65 % ) ;
; Total pins ; 358 / 616 ( 58 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;
; DSP block 9-bit elements ; 76 / 112 ( 68 % ) ;
; Total PLLs ; 1 / 6 ( 17 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;
* '''FPGA Timing Analysis''' (readout_card.tan.rpt): [[rc_5.0.b_tan_rpt]]
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.459 ns
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.895 ns
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 15.956 ns

== Revision 5.0.a (not recommended) ==
* '''Filename:'''
** rc_v0500000a_12mar2010.sof

* '''Features:'''
** Based on the merger of rev. 5.0.8 and 5.0.9.
** '''integral_clamp''' command is added where a clamp value is set for the integral term and once the integral term hits that value, the integral-term is clamped to that value and p-term and d-term are clamped to zero. When integral_term=0 then no clamping is in effect, similar to previous releases of firmware.
** The low pass filter has 20-bit input and f_3dB/f_samp = 122Hz/15kHz .
** The flux-jump clamping that was removed in 5.0.9 is included once again here, as we decided this is safer for now.

* '''Details:'''
** "lock_dat_left" parameter that was removed in 5.0.9 is now implemented as "lock_dat_lsb"

* '''Bugs:'''
** flx_lp_init does not reinitialize the flux-jump block

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis
** tag name: rc_v0500000a_12mar2009! years were mixed up!

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
* '''FPGA Timing Analysis''' (readout_card.tan.rpt):

== Revision 5.0.9 (buggy) ==
* '''Filename:'''
** rc_v05000009_13nov2009.sof

* '''Features:'''
** Based on rev. 5.0.4
** Removes a sticky bit in pid calculation result storage -- in fsfb_processor.
** Adds a command to clamp the growth of the I-term to prevent wrapping and track down the source of Caltech's FSFB jumps.
** Removed the unused lock_dat_left parameter. The ability to shift left was moved to the fsfb_corr block some time ago.
** Fixed a sign extension bug acting on the flux quanta, which limited the value to 8191. Changed the extension from signed to unsigned.
** Removed ineffective clamping in the flux-jump calculation block.
** IMPORTANT: Must be used in conjunction with firmware rev. 5.0.0+ of all other cards.

* '''Details:'''

* '''Bugs:'''
** integral_clamp read/write command does not work.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 27,960 / 41,250 ( 68 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.825 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.878 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 14.397 ns ;

== Revision 5.0.8 (UBC only) ==
* '''Filename:'''
** rc_v05000008_09oct2009.sof

* '''Features:'''
** Based on rev. 5.0.4
** type 1 low-pass filter: f3dB=122Hz for fsample=15kHz
** Filter-input-width changed from 18b to 20b with no sticky bits!
** removed sticky bits in internal arithmetic of the filter.

= Revision 5.0.7 (type-2 filter) =
* '''Filename:'''
** rc_v05000007_09oct2009.sof

* '''Features:'''
** Based on rev. 5.0.4
** type-2 low-pass-filter: f3dB=75Hz for fsample=30000.
** Filter-input-width changed from 18b to 20b with no sticky bits!
** inter-biquad-gain-scaling for the filter is 2^14
** filter results are scaled down by 2^3 in the output of the filter.
** removed sticky bits in internal arithmetics
** _correction_ disabled in fsfb_proc_pidz

* '''Details:'''
** quartus.ini file was '''not''' present in synth directory.

* '''Bugs:'''
** none to report

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
== Revision 5.0.6 (UBC only) ==
* '''Filename:'''
** rc_stratix3_v05000006_15sep2009.sof

* '''Features:'''
** Only Valid for Rev. C/D Cards
** Based on rev. 5.0.3
** tcl file updated for Rev. D and aligned with top-level and qsf (project file).
** flux loop commented, just to try sampling the ADC.
** compiled with Q9.1

== Revision 5.0.5 (UBC only) ==
* '''Filename:'''
** rc_v05000005_04sep2009.sof

* '''Features:'''
** Based on rev. 5.0.2
** changed the low-pass-filter to f(3db)=75Hz for f(sample)=30000.

* '''Details:'''
** quartus.ini file was '''not''' present in synth directory.

* '''Bugs:'''
** negative inputs to the filter cause filter to have a non-flat pass-band region. may have to do with sign-handling...

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
* '''FPGA Timing Analysis''' (readout_card.tan.rpt):

= Revision 5.0.4 =
* '''Filename:'''
** rc_v05000004_28aug2009.sof

* '''Features:'''
** Based on rev. 5.0.2
** BUG Fix: handles 14-bit flux quanta (changed the multiplier to unsigned)
** BUG Fix: changed standard logic vector extension from signed to unsigned in flux-jumping slave.
** IMPORTANT: Must be used in conjunction with firmware rev. 5.0.0+ of all other cards.

* '''Details:'''

* '''Bugs:'''
** None so far.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,170 / 41,250 ( 63 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.541 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.612 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 15.398 ns ;

= Revision 5.0.3 =
* '''Filename:'''
** rc_stratix3_v05000003_21aug2009.sof

* '''Features:'''
** ONLY valid REV C/D RC Cards
** Based on rev. 5.0.2
** flux loop commented, just to try sampling the ADC.
** updated tcl file, but still need to rely on project file as well as qsf file.
** changed default level of adc_sclk to '1'
** dac_clr_n was changed from an output to an input.
** added 'locked' interface to rc_pll_stratix_iii
** renamed the adc_pll clock signals to more explanitory names
** added the FPGA_DEVICE_FAMILY generic to the dispatch interace for synthesis of the dc_fifo in lvds_rx
** uncommented DDR interface to force the syntesizer to use correct left and right PLLs (in conjunction with ADC and DDR PLLs)
** added test signals to test_status to see clocks on the scope.
== Revision 5.0.2 (buggy) ==
* '''Filename:'''
** rc_v05000002_test00_tagged.sof

* '''Features:'''
** Based on rev. 5.0.1
** Fixed a bug in wbs_frame_data that stored data incorrectly if reporting 1 or 2 pixels only.
** IMPORTANT: Must be used in conjunction with firmware rev. 5.0.0+ of all other cards.

* '''Details:'''

* '''Bugs:'''
** None so far.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,186 / 41,250 ( 63 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.755 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.979 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.067 ns ;

== Revision 5.0.1 (buggy) (Filter + Raw + Rectangle, 2 LVDS) ==
* '''Filename:'''
** rc_v05000001_26may2009.sof

* '''Features:'''
** Combines features in rev. 5.0.0 (2 LVDS Lines) and rev. 4.0.e (Filtered + Raw), with the NEW rectangle mode.
** IMPORTANT: Must be used in conjunction with firmware rev. 5.0.0+ of all other cards.

* '''Details:'''
** [[CVS Diff Between sys_v05000000 and rc_v05000001]]

* '''Bugs:'''
** Has a bug in wbs_frame_data that stored data incorrectly if reporting 1 or 2 pixels only.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,565 / 41,250 ( 64 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.656 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.861 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 14.167 ns ;

== Revision 5.0.0 (Filter Only, 2 LVDS) ==
* '''Filename:'''
** rc_v05000000_22dec2008.sof (tagged as sys_v05000000_22dec2008)

* '''Features:'''
** IMPORTANT: Must be used in conjunction with firmware v05000000+ of all other cards!!!
** Adds the ability to read out one column of data continuously from readout cards
** Adds data mode 11, which is an engineering mode. Data points are 32-bits, and bits [9..3]=row_index, [2..0]=column_index. This mode is useful for determining which pixels one is reading out in the array, in column mode for example.

* '''Details:'''
** [[CVS Diff Between rc_v0400000c and sys_v05000000]]

* '''Bugs:'''
** None so far.

* '''Synthesis Notes:'''
** The quartus.ini file was not present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,607 / 41,250 ( 65 % ) ;
; Total memory bits ; 406,016 / 3,423,744 ( 12 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.558 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.892 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.987 ns ;

== Revision 4.0.f (Filter + Raw, 1 LVDS) ==
* '''Filename:'''
** rc_v0400000f_12feb2010.sof

* '''Features:'''
** Based on 4.0.e and in parallel with 5.0.9 (equivalent version, clamping is not included)
** Incorporates fixes that were done to flux-jumping between 5.0.2 - 5.0.4 - 5.0.9. Namely:
*** Changes a multiplier from signed to unsigned (in fsfb_corr_multplier.vhd).
*** Changes sign extension from signed to unsigned (in flux_quanta_ram_admin.vhd).

* '''Details:'''

* '''Bugs:'''
** None reported yet.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,773 / 41,250 ( 65 % ) ;
; Total memory bits ; 1,321,984 / 3,423,744 ( 39 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.539 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 4.118 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 17.318 ns ;

== Revision 4.0.e (Filter + Raw, 1 LVDS) ==
* '''Filename:'''
** rc_v0400000e_27apr2009.sof

* '''Features:'''
** Based on 4.0.d
** Combines both raw- and filtered-data modes.
** fpga_temp, card_temp, card_id commands are disabled.
** Tested by Matt Hasselfield.

* '''Details:'''

* '''Bugs:'''
** fpga_temp, card_temp, card_id commands are disabled.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 27,048 / 41,250 ( 66 % ) ;
; Total memory bits ; 1,321,984 / 3,423,744 ( 39 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.675 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.907 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.728 ns ;

== Revision 4.0.d (Raw Only, 1 LVDS) ==
* '''Filename:''' rc_v0400000d_20090417.sof

* '''Features:'''
** Based on v4.0.c, but has the filter removed, and implements a single 65536-index RAM block for storing 50 MHz raw-data samples.
** The firmware takes a new command called readout_col_index which specifies which column to capture raw data from.
** Other than readout_col_index, the firmware functions the same as previous raw-data firmware, including then need to issue a capture_raw command.
** For more information on raw-data, see: http://e-mode.phas.ubc.ca/mcewiki/index.php/Raw-mode_readout
** This firmware also integrates some of the improvements that were implemented in 4.4.0, like the removal of the tga_o signal from an FSM in dispatch_wishbone.vhd.

* '''Details:'''
** Differences between 4.0.c and 4.0.d
U system/test/source/tb/tb_cc_rcs_bcs_ac.vhd
U all_cards/dispatch/source/rtl/dispatch_wishbone.vhd
U library/sys_param/source/rtl/wishbone_pack.vhd
U readout_card/adc_sample_coadd/source/rtl/adc_sample_coadd.vhd
U readout_card/adc_sample_coadd/source/rtl/adc_sample_coadd_pack.vhd
U readout_card/flux_loop/source/rtl/flux_loop.vhd
U readout_card/flux_loop/source/rtl/flux_loop_pack.vhd
U readout_card/flux_loop_ctrl/source/rtl/flux_loop_ctrl.vhd
U readout_card/flux_loop_ctrl/source/rtl/flux_loop_ctrl_pack.vhd
U readout_card/flux_loop_ctrl/source/tb/tb1_flux_loop_ctrl.vhd
U readout_card/flux_loop_ctrl/source/tb/tb2_flux_loop_ctrl.vhd
U readout_card/fsfb_calc/source/rtl/fsfb_fltr_regs.vhd
U readout_card/fsfb_corr/source/rtl/fsfb_corr.vhd
U readout_card/readout_card/source/rtl/readout_card.vhd
U readout_card/readout_card/source/rtl/readout_card_pack.vhd
U readout_card/wbs_frame_data/source/rtl/wbs_frame_data.vhd
U readout_card/wbs_frame_data/source/rtl/wbs_frame_data_pack.vhd

* '''Bugs:'''
** None so far.
** fpga_temp, card_temp, card_id commands are not supported.

* '''Synthesis Notes:'''
** The quartus.ini file was present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 24,554 / 41,250 ( 60 % ) ;
; Total memory bits ; 1,262,592 / 3,423,744 ( 37 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.991 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.864 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 17.052 ns ;

== Revision 4.4.1 ==
* '''Filename:''' rc_v04040001_21nov2008

* '''Features:'''
** Fixes a bug that froze up the firmware if any of the following commands were issued: CARD_ID_ADDR, CARD_TEMP_ADDR, FPGA_TEMP_ADDR in 4.4.0 only.

* '''Details:'''
** The bug fix include adding more logic to the wishbone ack path (readout_card.vhd), which subsequently decreased the minimum clock setup time to 1.588ns. The new logic will catch errors that the old logic wouldn't have, and is now consistent with the firmware on all the other cards. However, if timing becomes an issue, the logic may have to revert back to that which was in version 4.0.c.

* '''Bugs:'''
** None so far.

* '''Synthesis Notes:'''
** The quartus.ini file was not present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 27,241 / 41,250 ( 66 % ) ;
; Total memory bits ; 405,504 / 3,423,744 ( 12 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.588 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.585 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 17.057 ns ;

== Revision 4.4.0 (buggy) ==
* '''Filename:''' rc_v04040000_02oct2008
* '''Features:'''
** Reinstated the data modes in wbs_frame_data.vhd that were removed in 4.0.c. This firmware has the following modes: '''0, 1, 2, 4, 5, 7, 10'''. The modes that are not present are: '''3''' (raw data), '''6''' (replaced by data_mode = 7), '''8''' (replaced by data_mode = 10), '''9''' (replaced by data_mode = 10). For more information on data modes, see [[Data mode]].
** Re-integrated the id_thermo and fpga_thermo block in the readout_card.vhd top level that was removed in 4.0.c.
** Removed the sticky bit in fsfb_corr.vhd, which was enabled when flux-jumping was turned on. Because the feedback is signed, the sticky bit would usually reflect the value of the 14th bit, except in situations when the number of flux quanta to jump was greater than 1 (i.e. cosmic rays, IV-curves, etc). Flux jumps are made at a maximum rate of one per frame period, so that if the First-Stage Feedback increased past the 13th bit, it would not be reflected in the feedback applied. Now it is.
* '''Details:'''
** Simplified the FSM logic in wbs_frame_data.vhd that determines when to transition from IDLE to WSS1. This was done to lower the number of gates in that path, and ease the timing.
** Removed the z_dat_i port in fsfb_processor.vhd and fsfb_calc_pack.vhd to the fsfb_proc_pidz block, in an effort to make it clearer within that block that the z-term is always = 0.
** Removed the z-term sign extension in fsfb_proc_pidz.vhd, and the [d-term + z-term] adder to free up DSP resources since the z-term is always = 0.
** Adjusted the indentation in fsfb_io_controller.vhd to make the file more readable.
** Moved the tga_o signal out of the dispatch_wishbone.vhd FSM, and made it a continuous assignment. This signal had one of the highest fan-out counts in the RTL design, and actually was impossible to route in Stratix III chips in its previous configuration because of the number of gates on the fan-out. As a consequence of making it a continuous assignment, the Stratix III fitter was able to succeed, and the Stratix I timing characteristics were greatly improved. This is the most significant change in this revision. This change single-handedly increased the minimum slack from 1.282 ns in v0400000c to 2.372 ns (or 56.7 MHz max) in this revision.
* '''Bugs:'''
** The following commands lock up the Readout Card firmware: CARD_ID_ADDR, CARD_TEMP_ADDR, FPGA_TEMP_ADDR.
** fb_const0 commands to channel 0 do not work. The value is stored in the register, but not applied to the DAC. Thus, read-back returns the correct value, but the DAC does not
* '''Synthesis Notes:'''
** The quartus.ini file was not present in the synth directory during synthesis.
* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 27,099 / 41,250 ( 66 % ) ;
; Total memory bits ; 406,016 / 3,423,744 ( 12 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.372 ns ;
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 4.052 ns ;
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.066 ns ;

== Revision 4.0.c ==
* '''Filename:''' rc_v0400000c_15aug2008.sof
* '''Features:'''
** Only has data modes 0, 1, 4, and 10.
** Fixed the bug that exists in 4.0.b, 4.0.a, and 4.0.9 that prevented the fb_const value from being applied to channel zero (wbs_fb_data.vhd).
* '''Details:'''
** Changed a counter in the dispatch block to ease timing constraints in synthesis (dispatch_wishbone.vhd)
** Updated the tagged versions of dispatch.vhd , dispatch_cmd_receive.vhd, and dispatch_reply_transmit.vhd to the version that is used by all the other cards.
** '''Removed''' the fpga_termo (command: '''fpga_temp''') and id_thermo (commands: '''card_temp, card_id''') to ease timing constraints in synthesis (readout_card.vhd)
** Updated the tagged version of fpga_termo.vhd to include the new 'stale bit' feature
** Updated the tagged version of frame_timing_core.vhd to include the new 'err_o' interface
* '''Bugs:'''
** None reported yet
* '''Synthesis Notes:'''
** The quartus.ini file was not present in the synth directory during synthesis.
* '''FPGA Resource Usage:'''
Total logic elements : 25,058 / 41,250 ( 61 % )
Total memory bits : 400,896 / 3,423,744 ( 12 % )

* '''Timing Analysis''' (readout_card.tan.rpt):
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.282 ns ;
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.736 ns ;
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.665 ns ;

== Revision 4.0.b (buggy) ==
Note: This revision is on a watch list, after the bug detected 15 July 2008. See the bug section for more details.
* '''Filename''' : rc_v0400000b_04aug2008.sof
* '''Features'''
** data_mode 10 is added to provide more filtfb bits (compared to data mode 9) for planet observations. filtered_dat(27 downto 3) & flux_cnt_dat(6 downto 0)

* '''Bugs'''
** An unexplained bug that appeared in 4.0.a and may still be present in 4.0.b is a problem with the readout of channels being clipped out of data reporting. [[Bug 1 Notes]]

* ''' Synthesis note '''
** Quartus.ini removed.

== Revision 4.0.a (buggy) ==
Note: This revision is on a watch list, after the bug detected 15 July 2008. See the bug section for more details.
* '''Filename''' : rc_v0400000a_07jul2008.sof
* '''Bug Fix'''
** mce_status and adc_offset/flx_quanta commands do not fail after power up.
* ''' Synthesis note '''
** Quartus.ini removed.

* '''Bugs'''
** Seems to clip out channel 0 from data reporting.

== Revision 4.0.9 (buggy) ==
* '''Filename''' : rc_v04000009_26jun2008.sof
* '''Features'''
** sa_bias and offset DACs only refreshed when new values are written. (in previous versions, DACs were refreshed every frame)
* '''Bugs'''
** fb_const0 commands to channel 0 do not work. The value is stored in the register, but not applied to the DAC. Thus, read-back returns the correct value, but the DAC does not.
** reading flx_quanta and adc_offset right after power up hangs the reply datapath to CC. resetmce clears this error as temporary solution. the problem is caused by first read ack of the wishbone slave.

== Revision 4.0.8 ==
* '''Filename''' : rc_v04000008_26jun2008.sof
* '''Features'''
** The gaini, gainp, gaind resolution increased to 12-bit, i.e. -2048 to 2047 (formerly 10-bit).

* '''Bug fix'''
** the bug associated with gainpid read before mce_reset is fixed.

* ''' Synthesis note '''
** Quartus.ini removed.

== Revision 4.3.7 ==
* '''Filename''' : rc_v04030007_26may2008_raw.sof
* '''Features'''
** 14-bit raw mode enabled to buffer a snapshot of 50MHz samples for 2 frames of row_len * num_rows samples.
** In order to extend the raw-mode to 14-bit, an assumption is made that the raw buffer is not written to while being read. Therefore, make sure there is at least 2*row_len*num_rows*20ns between issuing captr_raw command and reading back the raw data.
** In order to save RAM for raw mode, two memory-intensive features are disabled:
*** low-pass filter disabled ( mixed filtfb data modes 6, 7, 9 are also disabled)
*** PID (gainp0, gaini0, gaind0) readback disabled. one can still set PID values and run servo, but can not read back the values.

== Revision 4.2.7 ==
* '''Filename''' : rc_v04020007_24may2008_raw.sof
* '''Features'''
** raw mode enabled to buffer a snapshot of 50MHz samples for 2 frames of row_len * num_rows samples.
** In order to save RAM for raw mode, two memory-intensive features are disabled:
*** low-pass filter disabled ( mixed filtfb data modes 6, 7, 9 are also disabled)
*** PID (gainp0, gaini0, gaind0) readback disabled. one can still set PID values and run servo, but can not read back the values.
* '''Bug fix'''
** the bug associated with reading from raw-buffer is fixed.

== Revision 4.1.7 ==
* '''Filename''' : rc_v04010007_25apr2008_raw.sof
* '''Features'''
** raw mode enabled to buffer a snapshot of 50MHz samples for 2 frames of row_len * num_rows samples.
** In order to save RAM for raw mode, two memory-intensive features are disabled:
*** low-pass filter disabled ( mixed filtfb data modes 6, 7, 9 are also disabled)
*** PID (gainp0, gaini0, gaind0) readback disabled. one can still set PID values and run servo, but can not read back the values.
* '''Bugs'''
** after each readout frame, raw-buffer readout counter falls behind by 3 and this causes skipping 3 50MHz samples in the data stream and column-data being messed up in subsequent frames. Data can be rearranged by post processing.

== Revision 4.0.6 (buggy) ==
* '''Filename''' : rc_v04000006_15feb2008.sof or .pof
* '''Features'''
** '''bugfix''': unreliable reset due to unsafe and incomplete state machines is fixed.
** '''bugfix''': flux_jump sign problem fixed, so far proved in const_mode, to be tested in servo_mode with cold setup.
** servo_mode=2 or ramp previously only went from 0 to ramp_amp, but now goes from -8192 to -8192+ramp_amp
** new commands are added: ''scratch'' and ''card_type''. Scratch takes 8 values and can be used by software to detect reset.
** slot_id and fw_rev are now integrated as part of all_cards.vhd
** lvds_tx_b=0, This will allow Clock Card to use the secondary backplane lvds line and check whether RC is plugged in.
** filter_coeff in misc_banks_admin commented as it is not implemented and causes timing problems.

* '''Bugs'''
** reading gainp/gaini/gaind right after power up hangs the reply datapath to CC. resetmce clears this error as temporary solution. the problem is caused by first read ack of pid_ram_admin.
** slot_id is only set after a resetmce is issued. (using the latest all_cards in the next revision will fix this)
** has spurious spikes on channel 7 data, which max out the integral, and cause the detectors to come unlocked. This firmware officially meets timing requirements, but the bug could be due to marginal timing on the longest data paths, i.e. ~0.1 ns in some cases.

== Revision 4.0.5 ==
* '''Filename''' : rc_v04000005_01nov2007.sof or .pof
* '''Features'''
** data mode 9 (mixed filt + flux jump) with windowing readjusted compared to data mode 8

* '''Bugs'''
** unreliable resetmce. Sometimes, firmware waked up non-responsive on lvds lines.
** In data mode 5 and 9, flux-jump counter is not reported properly due to a sign error. However, flux jumping works fine.

== Revision 3.0.19 ==
* '''Filename''' : rc_v03000019_16feb2007_raw.sof (no pof as one is not likely to run with this as regular firmware)
* '''Features'''
** data mode 3 is enabled.
** filter is disabled as a compromise to fit the raw-mode buffer.

* '''Bugs'''
** unreliable resetmce. Sometimes, firmware waked up non-responsive on lvds lines.

== Old Firmware Revisions ==
* '''4.0.4''': rc_v04000004_11oct2007.sof data mode 8 added (mixed filt + flux jump)
* '''4.0.3''': rc_v04000003_19sep2007.sof data mode 7 bit split readjusted to 10b error being bit 4 to 14
* '''4.0.2''': rc_v04000002_11sep2007.sof pid resolution increased to 10b, data mode 7 added
* '''4.0.1''': rc_v04000001_06sep2007.sof
* '''4.0.0''': rc_v04000000_29aug2007.sof supports readout_row_index * [[ bugs ]]

= To-Do List =
* the starting point for the servo is currently zero and it would be nice to have it programmable.

= RC Synthesis Notes =
# The following note applies when using Quartus versions earlier than Q7: Quartus.ini file had to exist in synth directory up to revision 4.0.a due to a bug that started in Quartus 6.1 and would synthesize away arbitrary parts of readout card. We contacted Altera at the time and they provided us the ini file.
# Timing: There is no "lock region" defined for readout card. Timing on readout card is tight and since version 3 or so any new feature would initially fail timing till some synthesis options were tweaked. One path that remains to be consistently marginal is from addr_gen counter (i.e. tga_o counter) in dispatch_wishbone.vhd to wishbone slaves particularly misc_banks_admin.vhd. Modules that are rewritten to address timing concerns are fsfb_corr, all_cards, misc_banks_admin, and finally instantiating an lpm counter instead of a counter from components library. Surprisingly, the lpm counter reduced 87 failures to 37, although looking at the technology map viewer, it seemed that they were both synthesized the same.
# Compile time: This was at some point 4.5 hours, after going to dual core PC, this was reduced to 35 minutes. After extending pid gains to 12b and fixing offset/sa_bias update code, the compile time increased to 1.5hr again with utilization up to ~70%.
# wbs_fb_storage, ram_8x64, pid_ram had to be regenerated using latest (Q7.2) MegaWizard to get rid of the bug associated with failure to read after power up until a reset was issued.
# During simulations, the initialization of RAM block with .hex files needs to be disabled. This is done by commenting out the following lines from the MegaWizard generated Megafunction files (remember to un-comment them before synthesizing the code):
lpm_file => "C:/scuba2_repository/cards/readout_card/fsfb_calc/source/rtl/ram_40x64.hex", and
lpm_file : STRING;
#Starting Q10.0 use TimeQuest timing analyzer as oppose to the classic one. The classic one is being phased out by Altera. In order to use TimeQuest, you need to have an sdc file present in your project directory.
----
[http://e-mode.phas.ubc.ca/mcewiki/index.php/Main_Page MCE Main Page]

Readout Card firmware

2011-05-04T21:56:53Z

Bburger: /* Revision 5.1.0 (not recommended) */

* Synthesis Reminders (for firmware developers)
** quartus.ini is not needed anymore (Fixed as of Q7, Altera SR10783580 2010-10-24)
** Remember that readout_card/fsfb_clac/source/rtl/ram_40x64.vhd must be initialized with the ram_40x64.hex file in the same directory.
= Revision 5.1.2 =
* '''Filename:'''
** rc_stratix3_v05010002_18jan2011.sof (for Rev. E cards)
** rc_stratix3_v05010002_18jan2011.jic (for Rev. E cards)
** rc_v05010002_03feb2011.sof (for Rev. B cards)
** rc_v05010002_03feb2011.pof (for Rev. B cards)

* '''Features:'''
** based on 5.1.1 with k1 and k2 (filter params) limited to k1<16 and k2<32 in order to resolve the timing when compiling for smaller Stratix FPGA on RC Rev. B.

* '''Bug fix:'''
** the 2-rows-off filtered data readout introduced with configurable filter in rev. 5.1.0 and 5.1.1 is fixed now.

* '''Bugs:'''
** none so far.

* '''FPGA Resource Usage''' (readout_card.fit.rpt, rev. B)
; Total logic elements ; 33,285 / 41,250 ( 81 % ) ;
; Total pins ; 358 / 616 ( 58 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt, rev. B)
; Fast Model Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 6.591 ns
; Fast Model Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 7.206 ns
; Fast Model Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 18.299 ns

== Revision 5.1.1 (not recommended) ==
* '''Filename:'''
** rc_v05010001_01dec2010.sof (for Rev. B cards)

* '''Features:'''
** based on 5.1.0, but k1 and k2 (filter params) are now limited to k1<16 and k2<32 in order to resolve the timing failures of compiling 5.1.0 for smaller Stratix FPGA on RC Rev. B.

* '''Bugs:'''
** filter mode data is off by 2 rows.

== Revision 5.1.0 (not recommended) ==
* '''Filename:'''
** rc_stratix3_v05010000_01nov2010.sof (for Rev. E cards)
** rc_v05010000_01nov2010.sof (for Rev. B cards) has timing failures '''do not use!!!'''

* '''Features:'''
** added configurable filter parameters specified by ''fltr_coeff'', default is the fcutoff/fsampl=122Hz/15kHz. see [[ Digital 4-pole Butterworth Low-pass filter ]].
** ''fltr_type'' is set to 255 to indicate configurable filter parameters.
** see [http://www.phas.ubc.ca/~mce/mcedocs/software/SC2_ELE_S580_515_mce_command_description.pdf MCE command description]
* '''Details'''
** It is built on Quartus10.1.
** tcl files had to be updated as cmp syntax is not supported in Q10 anymore.
** Rev. E cards now can be identified by reading back pcb_rev as part of card_type, therefore both stratix I and III sof/pof/jic are generated from the same source.

* '''Bugs:'''
** rc_v05010000_01nov2010.sof has timing failures that were overlooked, do not use this firmware for Rev.B cards.
** '''filter mode data is off by 2 rows.'''

* '''FPGA Resource Usage and Timing Report''' (readout_card.fit.rpt and readout_card.tan.rpt): logic usage is upto 85% from 66% in 5.0.d/e/f

= Revision 5.0.f =
* '''Filename:'''
** rc_v0500000f_22oct2010.sof (for Rev. B cards)
** rc_stratix3_v0500000f_22oct2010.sof (for Rev. E cards)

* '''Features:'''
** Bugfix: integral clamp should work now. only positive integral_clamp values are valid!

* '''Details:''':
** SQ1FB is applied 18 clock cycles after start of a row visit (SQ1_Bias being applied) regardless of flux-jump being enabled or not. In pre-5.0.b firmware SQ1FB was being applied after 7 clock cycles when flux-jump was disabled and after 18 clock cycles when flux-jump was enabled.
** available for both Rev. E and Rev. B cards, the upper byte of card_type parameter now reports the pcb revision.
** development note: It is built on Quartus10.1.

* '''Bugs:'''
**none yet!

* '''FPGA Resource Usage and Timing Report''' (readout_card.fit.rpt and readout_card.tan.rpt): no change compared to 5.0.a/b/c/d

== Revision 5.0.e (not recommended) ==
* '''Filename:'''
** rc_v0500000e_06oct2010.sof

* '''Details:'''
** an unsuccessful attempt to fix integral_clamp, but changed the functionality so that it clamps at the value, but it doesn't hold the clamp. i.e., if the calculated sq1fb becomes less than the specified clamp value, the sq1fb is not clamped anymore. This is not a desired functionality!

== Revision 5.0.d (not recommended) ==
* '''Filename:'''
** rc_v0500000d_04aug2010.sof

* '''Features:'''
** Bugfix: To fix the bug associated with negative flux-jumps, reverted to signed multiplier and hence, incremented the width of the flux-quanta multiplier input by 1.

* '''Details:''':
** SQ1FB is applied 18 clock cycles after start of a row visit (SQ1_Bias being applied) regardless of flux-jump being enabled or not. In pre-5.0.b firmware SQ1FB was being applied after 7 clock cycles when flux-jump was disabled and after 18 clock cycles when flux-jump was enabled.

* '''Bugs:'''
** '''integral_clamping is broken'''. To test the clamping, a servo-locked ramp was initiated on the sq1fb and then flux-jumping was turned on and observed by attaching a scope to the SQ1FB output. With integral_clamp=80000000, flux_quanta=8000, gaini=1, flux-jump enabled, we see [[http://e-mode.phas.ubc.ca/mcewiki/index.php/Image:Clamp_unstable.png scope snapshot]] used slow_fb_ramp.py script for testing.

* '''FPGA Resource Usage and Timing Report''' (readout_card.fit.rpt and readout_card.tan.rpt): no change compared to 5.0.a/b/c

== Revision 5.0.c (not recommended) ==
* '''Filename:'''
** rc_v0500000c_16jun2010.sof

* '''Features:'''
** Based on rev. 5.0.b
** Re-introduced flux-jump counter clamping to maintain continuity in behavior from past versions of firmware in the field.
** '''Important''': SQ1FB is applied 18 clock cycles after start of a row visit (SQ1_Bias being applied) regardless of flux-jump being enabled or not. In pre-5.0.b firmware SQ1FB was being applied after 7 clock cycles when flux-jump was disabled and after 18 clock cycles when flux-jump was enabled.

* '''Details:'''
* '''Bugs:'''
** '''flux-jump is broken'''. flux-jumping block misbehaves at the first jump in the negative range.

* '''FPGA Resource Usage''' (readout_card.fit.rpt): [[rc_5.0.c_fit_rpt]]
; Total logic elements ; 26,800 / 41,250 ( 65 % ) ;
; Total pins ; 358 / 616 ( 58 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;
; DSP block 9-bit elements ; 76 / 112 ( 68 % ) ;
; Total PLLs ; 1 / 6 ( 17 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt): [[rc_5.0.c_tan_rpt]]
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.964 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 4.382 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 15.924 ns ;

== Revision 5.0.b (not recommended) ==
* '''Filename:'''
** rc_v0500000b_03jun2010.sof

* '''Features:'''
** Based on rev. 5.0.a
** A bug that caused jumps in first-stage feedback, and detected as spikes in the raw data of pixels that were in servo_mode=0,1,2 was fixed. The jumps in FSFB were due to flux-jumping being enabled on live pixes with non-zero flx_quanta, and being disabled on the fly on dead pixels with flx_quanta=0. Flux-jumping is now disabled on a column-by-column basis if a column is in servo_mode = 0,1,2.
** Ineffective clamping was removed from the flux-jumping block (as per 5.0.9), as it is now replaced by the clamping that was perfected in rev. 5.0.10
** A sticky bit that only affected servo_mode=0,1,2 was also removed from the flux-jumping block.
** flx_lp_init commands now also clear the flux-jumping block as well.
** The 11-clock-cycle delay (in applying SQ1_FB) that in previous firmware only occurred when flux-jumping was enabled, now (in this version) is in effect all the time. Due to the bug-fix above, flux-jumping can be disabled on a column-by-column basis by setting servo_mode=0,1,2 when en_fb_jump=1. Before the change, this meant that constant values could be applied with or without the 11-cycle delay if en_fb_jump=1 or 0. To make the delay consistent, it is now always 11 cycles. As background, the flux-jumping block is pipelined, meaning that it does calculations for all 8 channels serially. The serialization is because of DSP-block limitations in the Readout Card FPGA that prevent us from doing all 8 channels in parallel. The reason that it takes 11 cycles to complete the flux-jumping calculations is because the values are computed for the eight channels in three ALU stages: 8 + 3 = 11 cycles. Adding 11 cycles to the 7 cycles of latency from other stages in the system results in: 11 + 7 = 18 cycles of latency from the start of a row dwell period before the first-stage feedback is applied. In rc_v5.0.c, I enforce the 18-cycle delay even when flux-jumping is not enabled to maintain uniformity across all eight channels, because flux-jumping is enabled/disabled on a per-channel basis. In other words, if I hadn't enforced the 18-cycle delay, some channels could have their feedback applied after 7 cycles, while others could have it applied after 18 cycles. I wasn't a fan of this non-uniformity. I realize that 18 cycles is a long time. In fact, so is 7. In the last few months, we have been discussing how to reduce these times to 1 cycle, because every experiment out there wants to multiplex as fast as possible, and the 7/18-delay is a rate limiting step.
** The flux-jumping code was re-arranged in the flux-jumping block to reflect the flow of data through the pipeline and make it easier to understand.

* '''Details:'''

* '''Bugs:'''
** flux-jump does not work when jumping to negative values.

* '''FPGA Resource Usage''' (readout_card.fit.rpt): [[rc_5.0.b_fit_rpt]]
; Total logic elements ; 26,745 / 41,250 ( 65 % ) ;
; Total pins ; 358 / 616 ( 58 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;
; DSP block 9-bit elements ; 76 / 112 ( 68 % ) ;
; Total PLLs ; 1 / 6 ( 17 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;
* '''FPGA Timing Analysis''' (readout_card.tan.rpt): [[rc_5.0.b_tan_rpt]]
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.459 ns
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.895 ns
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 15.956 ns

= Revision 5.0.a =
* '''Filename:'''
** rc_v0500000a_12mar2010.sof

* '''Features:'''
** Based on the merger of rev. 5.0.8 and 5.0.9.
** '''integral_clamp''' command is added where a clamp value is set for the integral term and once the integral term hits that value, the integral-term is clamped to that value and p-term and d-term are clamped to zero. When integral_term=0 then no clamping is in effect, similar to previous releases of firmware.
** The low pass filter has 20-bit input and f_3dB/f_samp = 122Hz/15kHz .
** The flux-jump clamping that was removed in 5.0.9 is included once again here, as we decided this is safer for now.

* '''Details:'''
** "lock_dat_left" parameter that was removed in 5.0.9 is now implemented as "lock_dat_lsb"

* '''Bugs:'''
** flx_lp_init does not reinitialize the flux-jump block

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis
** tag name: rc_v0500000a_12mar2009! years were mixed up!

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
* '''FPGA Timing Analysis''' (readout_card.tan.rpt):

== Revision 5.0.9 (buggy) ==
* '''Filename:'''
** rc_v05000009_13nov2009.sof

* '''Features:'''
** Based on rev. 5.0.4
** Removes a sticky bit in pid calculation result storage -- in fsfb_processor.
** Adds a command to clamp the growth of the I-term to prevent wrapping and track down the source of Caltech's FSFB jumps.
** Removed the unused lock_dat_left parameter. The ability to shift left was moved to the fsfb_corr block some time ago.
** Fixed a sign extension bug acting on the flux quanta, which limited the value to 8191. Changed the extension from signed to unsigned.
** Removed ineffective clamping in the flux-jump calculation block.
** IMPORTANT: Must be used in conjunction with firmware rev. 5.0.0+ of all other cards.

* '''Details:'''

* '''Bugs:'''
** integral_clamp read/write command does not work.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 27,960 / 41,250 ( 68 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.825 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.878 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 14.397 ns ;

== Revision 5.0.8 (UBC only) ==
* '''Filename:'''
** rc_v05000008_09oct2009.sof

* '''Features:'''
** Based on rev. 5.0.4
** type 1 low-pass filter: f3dB=122Hz for fsample=15kHz
** Filter-input-width changed from 18b to 20b with no sticky bits!
** removed sticky bits in internal arithmetic of the filter.

= Revision 5.0.7 (type-2 filter) =
* '''Filename:'''
** rc_v05000007_09oct2009.sof

* '''Features:'''
** Based on rev. 5.0.4
** type-2 low-pass-filter: f3dB=75Hz for fsample=30000.
** Filter-input-width changed from 18b to 20b with no sticky bits!
** inter-biquad-gain-scaling for the filter is 2^14
** filter results are scaled down by 2^3 in the output of the filter.
** removed sticky bits in internal arithmetics
** _correction_ disabled in fsfb_proc_pidz

* '''Details:'''
** quartus.ini file was '''not''' present in synth directory.

* '''Bugs:'''
** none to report

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
== Revision 5.0.6 (UBC only) ==
* '''Filename:'''
** rc_stratix3_v05000006_15sep2009.sof

* '''Features:'''
** Only Valid for Rev. C/D Cards
** Based on rev. 5.0.3
** tcl file updated for Rev. D and aligned with top-level and qsf (project file).
** flux loop commented, just to try sampling the ADC.
** compiled with Q9.1

== Revision 5.0.5 (UBC only) ==
* '''Filename:'''
** rc_v05000005_04sep2009.sof

* '''Features:'''
** Based on rev. 5.0.2
** changed the low-pass-filter to f(3db)=75Hz for f(sample)=30000.

* '''Details:'''
** quartus.ini file was '''not''' present in synth directory.

* '''Bugs:'''
** negative inputs to the filter cause filter to have a non-flat pass-band region. may have to do with sign-handling...

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
* '''FPGA Timing Analysis''' (readout_card.tan.rpt):

= Revision 5.0.4 =
* '''Filename:'''
** rc_v05000004_28aug2009.sof

* '''Features:'''
** Based on rev. 5.0.2
** BUG Fix: handles 14-bit flux quanta (changed the multiplier to unsigned)
** BUG Fix: changed standard logic vector extension from signed to unsigned in flux-jumping slave.
** IMPORTANT: Must be used in conjunction with firmware rev. 5.0.0+ of all other cards.

* '''Details:'''

* '''Bugs:'''
** None so far.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,170 / 41,250 ( 63 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.541 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.612 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 15.398 ns ;

= Revision 5.0.3 =
* '''Filename:'''
** rc_stratix3_v05000003_21aug2009.sof

* '''Features:'''
** ONLY valid REV C/D RC Cards
** Based on rev. 5.0.2
** flux loop commented, just to try sampling the ADC.
** updated tcl file, but still need to rely on project file as well as qsf file.
** changed default level of adc_sclk to '1'
** dac_clr_n was changed from an output to an input.
** added 'locked' interface to rc_pll_stratix_iii
** renamed the adc_pll clock signals to more explanitory names
** added the FPGA_DEVICE_FAMILY generic to the dispatch interace for synthesis of the dc_fifo in lvds_rx
** uncommented DDR interface to force the syntesizer to use correct left and right PLLs (in conjunction with ADC and DDR PLLs)
** added test signals to test_status to see clocks on the scope.
== Revision 5.0.2 (buggy) ==
* '''Filename:'''
** rc_v05000002_test00_tagged.sof

* '''Features:'''
** Based on rev. 5.0.1
** Fixed a bug in wbs_frame_data that stored data incorrectly if reporting 1 or 2 pixels only.
** IMPORTANT: Must be used in conjunction with firmware rev. 5.0.0+ of all other cards.

* '''Details:'''

* '''Bugs:'''
** None so far.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,186 / 41,250 ( 63 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.755 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.979 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.067 ns ;

== Revision 5.0.1 (buggy) (Filter + Raw + Rectangle, 2 LVDS) ==
* '''Filename:'''
** rc_v05000001_26may2009.sof

* '''Features:'''
** Combines features in rev. 5.0.0 (2 LVDS Lines) and rev. 4.0.e (Filtered + Raw), with the NEW rectangle mode.
** IMPORTANT: Must be used in conjunction with firmware rev. 5.0.0+ of all other cards.

* '''Details:'''
** [[CVS Diff Between sys_v05000000 and rc_v05000001]]

* '''Bugs:'''
** Has a bug in wbs_frame_data that stored data incorrectly if reporting 1 or 2 pixels only.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,565 / 41,250 ( 64 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.656 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.861 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 14.167 ns ;

== Revision 5.0.0 (Filter Only, 2 LVDS) ==
* '''Filename:'''
** rc_v05000000_22dec2008.sof (tagged as sys_v05000000_22dec2008)

* '''Features:'''
** IMPORTANT: Must be used in conjunction with firmware v05000000+ of all other cards!!!
** Adds the ability to read out one column of data continuously from readout cards
** Adds data mode 11, which is an engineering mode. Data points are 32-bits, and bits [9..3]=row_index, [2..0]=column_index. This mode is useful for determining which pixels one is reading out in the array, in column mode for example.

* '''Details:'''
** [[CVS Diff Between rc_v0400000c and sys_v05000000]]

* '''Bugs:'''
** None so far.

* '''Synthesis Notes:'''
** The quartus.ini file was not present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,607 / 41,250 ( 65 % ) ;
; Total memory bits ; 406,016 / 3,423,744 ( 12 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.558 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.892 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.987 ns ;

== Revision 4.0.f (Filter + Raw, 1 LVDS) ==
* '''Filename:'''
** rc_v0400000f_12feb2010.sof

* '''Features:'''
** Based on 4.0.e and in parallel with 5.0.9 (equivalent version, clamping is not included)
** Incorporates fixes that were done to flux-jumping between 5.0.2 - 5.0.4 - 5.0.9. Namely:
*** Changes a multiplier from signed to unsigned (in fsfb_corr_multplier.vhd).
*** Changes sign extension from signed to unsigned (in flux_quanta_ram_admin.vhd).

* '''Details:'''

* '''Bugs:'''
** None reported yet.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,773 / 41,250 ( 65 % ) ;
; Total memory bits ; 1,321,984 / 3,423,744 ( 39 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.539 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 4.118 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 17.318 ns ;

== Revision 4.0.e (Filter + Raw, 1 LVDS) ==
* '''Filename:'''
** rc_v0400000e_27apr2009.sof

* '''Features:'''
** Based on 4.0.d
** Combines both raw- and filtered-data modes.
** fpga_temp, card_temp, card_id commands are disabled.
** Tested by Matt Hasselfield.

* '''Details:'''

* '''Bugs:'''
** fpga_temp, card_temp, card_id commands are disabled.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 27,048 / 41,250 ( 66 % ) ;
; Total memory bits ; 1,321,984 / 3,423,744 ( 39 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.675 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.907 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.728 ns ;

== Revision 4.0.d (Raw Only, 1 LVDS) ==
* '''Filename:''' rc_v0400000d_20090417.sof

* '''Features:'''
** Based on v4.0.c, but has the filter removed, and implements a single 65536-index RAM block for storing 50 MHz raw-data samples.
** The firmware takes a new command called readout_col_index which specifies which column to capture raw data from.
** Other than readout_col_index, the firmware functions the same as previous raw-data firmware, including then need to issue a capture_raw command.
** For more information on raw-data, see: http://e-mode.phas.ubc.ca/mcewiki/index.php/Raw-mode_readout
** This firmware also integrates some of the improvements that were implemented in 4.4.0, like the removal of the tga_o signal from an FSM in dispatch_wishbone.vhd.

* '''Details:'''
** Differences between 4.0.c and 4.0.d
U system/test/source/tb/tb_cc_rcs_bcs_ac.vhd
U all_cards/dispatch/source/rtl/dispatch_wishbone.vhd
U library/sys_param/source/rtl/wishbone_pack.vhd
U readout_card/adc_sample_coadd/source/rtl/adc_sample_coadd.vhd
U readout_card/adc_sample_coadd/source/rtl/adc_sample_coadd_pack.vhd
U readout_card/flux_loop/source/rtl/flux_loop.vhd
U readout_card/flux_loop/source/rtl/flux_loop_pack.vhd
U readout_card/flux_loop_ctrl/source/rtl/flux_loop_ctrl.vhd
U readout_card/flux_loop_ctrl/source/rtl/flux_loop_ctrl_pack.vhd
U readout_card/flux_loop_ctrl/source/tb/tb1_flux_loop_ctrl.vhd
U readout_card/flux_loop_ctrl/source/tb/tb2_flux_loop_ctrl.vhd
U readout_card/fsfb_calc/source/rtl/fsfb_fltr_regs.vhd
U readout_card/fsfb_corr/source/rtl/fsfb_corr.vhd
U readout_card/readout_card/source/rtl/readout_card.vhd
U readout_card/readout_card/source/rtl/readout_card_pack.vhd
U readout_card/wbs_frame_data/source/rtl/wbs_frame_data.vhd
U readout_card/wbs_frame_data/source/rtl/wbs_frame_data_pack.vhd

* '''Bugs:'''
** None so far.
** fpga_temp, card_temp, card_id commands are not supported.

* '''Synthesis Notes:'''
** The quartus.ini file was present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 24,554 / 41,250 ( 60 % ) ;
; Total memory bits ; 1,262,592 / 3,423,744 ( 37 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.991 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.864 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 17.052 ns ;

== Revision 4.4.1 ==
* '''Filename:''' rc_v04040001_21nov2008

* '''Features:'''
** Fixes a bug that froze up the firmware if any of the following commands were issued: CARD_ID_ADDR, CARD_TEMP_ADDR, FPGA_TEMP_ADDR in 4.4.0 only.

* '''Details:'''
** The bug fix include adding more logic to the wishbone ack path (readout_card.vhd), which subsequently decreased the minimum clock setup time to 1.588ns. The new logic will catch errors that the old logic wouldn't have, and is now consistent with the firmware on all the other cards. However, if timing becomes an issue, the logic may have to revert back to that which was in version 4.0.c.

* '''Bugs:'''
** None so far.

* '''Synthesis Notes:'''
** The quartus.ini file was not present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 27,241 / 41,250 ( 66 % ) ;
; Total memory bits ; 405,504 / 3,423,744 ( 12 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.588 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.585 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 17.057 ns ;

== Revision 4.4.0 (buggy) ==
* '''Filename:''' rc_v04040000_02oct2008
* '''Features:'''
** Reinstated the data modes in wbs_frame_data.vhd that were removed in 4.0.c. This firmware has the following modes: '''0, 1, 2, 4, 5, 7, 10'''. The modes that are not present are: '''3''' (raw data), '''6''' (replaced by data_mode = 7), '''8''' (replaced by data_mode = 10), '''9''' (replaced by data_mode = 10). For more information on data modes, see [[Data mode]].
** Re-integrated the id_thermo and fpga_thermo block in the readout_card.vhd top level that was removed in 4.0.c.
** Removed the sticky bit in fsfb_corr.vhd, which was enabled when flux-jumping was turned on. Because the feedback is signed, the sticky bit would usually reflect the value of the 14th bit, except in situations when the number of flux quanta to jump was greater than 1 (i.e. cosmic rays, IV-curves, etc). Flux jumps are made at a maximum rate of one per frame period, so that if the First-Stage Feedback increased past the 13th bit, it would not be reflected in the feedback applied. Now it is.
* '''Details:'''
** Simplified the FSM logic in wbs_frame_data.vhd that determines when to transition from IDLE to WSS1. This was done to lower the number of gates in that path, and ease the timing.
** Removed the z_dat_i port in fsfb_processor.vhd and fsfb_calc_pack.vhd to the fsfb_proc_pidz block, in an effort to make it clearer within that block that the z-term is always = 0.
** Removed the z-term sign extension in fsfb_proc_pidz.vhd, and the [d-term + z-term] adder to free up DSP resources since the z-term is always = 0.
** Adjusted the indentation in fsfb_io_controller.vhd to make the file more readable.
** Moved the tga_o signal out of the dispatch_wishbone.vhd FSM, and made it a continuous assignment. This signal had one of the highest fan-out counts in the RTL design, and actually was impossible to route in Stratix III chips in its previous configuration because of the number of gates on the fan-out. As a consequence of making it a continuous assignment, the Stratix III fitter was able to succeed, and the Stratix I timing characteristics were greatly improved. This is the most significant change in this revision. This change single-handedly increased the minimum slack from 1.282 ns in v0400000c to 2.372 ns (or 56.7 MHz max) in this revision.
* '''Bugs:'''
** The following commands lock up the Readout Card firmware: CARD_ID_ADDR, CARD_TEMP_ADDR, FPGA_TEMP_ADDR.
** fb_const0 commands to channel 0 do not work. The value is stored in the register, but not applied to the DAC. Thus, read-back returns the correct value, but the DAC does not
* '''Synthesis Notes:'''
** The quartus.ini file was not present in the synth directory during synthesis.
* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 27,099 / 41,250 ( 66 % ) ;
; Total memory bits ; 406,016 / 3,423,744 ( 12 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.372 ns ;
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 4.052 ns ;
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.066 ns ;

== Revision 4.0.c ==
* '''Filename:''' rc_v0400000c_15aug2008.sof
* '''Features:'''
** Only has data modes 0, 1, 4, and 10.
** Fixed the bug that exists in 4.0.b, 4.0.a, and 4.0.9 that prevented the fb_const value from being applied to channel zero (wbs_fb_data.vhd).
* '''Details:'''
** Changed a counter in the dispatch block to ease timing constraints in synthesis (dispatch_wishbone.vhd)
** Updated the tagged versions of dispatch.vhd , dispatch_cmd_receive.vhd, and dispatch_reply_transmit.vhd to the version that is used by all the other cards.
** '''Removed''' the fpga_termo (command: '''fpga_temp''') and id_thermo (commands: '''card_temp, card_id''') to ease timing constraints in synthesis (readout_card.vhd)
** Updated the tagged version of fpga_termo.vhd to include the new 'stale bit' feature
** Updated the tagged version of frame_timing_core.vhd to include the new 'err_o' interface
* '''Bugs:'''
** None reported yet
* '''Synthesis Notes:'''
** The quartus.ini file was not present in the synth directory during synthesis.
* '''FPGA Resource Usage:'''
Total logic elements : 25,058 / 41,250 ( 61 % )
Total memory bits : 400,896 / 3,423,744 ( 12 % )

* '''Timing Analysis''' (readout_card.tan.rpt):
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.282 ns ;
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.736 ns ;
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.665 ns ;

== Revision 4.0.b (buggy) ==
Note: This revision is on a watch list, after the bug detected 15 July 2008. See the bug section for more details.
* '''Filename''' : rc_v0400000b_04aug2008.sof
* '''Features'''
** data_mode 10 is added to provide more filtfb bits (compared to data mode 9) for planet observations. filtered_dat(27 downto 3) & flux_cnt_dat(6 downto 0)

* '''Bugs'''
** An unexplained bug that appeared in 4.0.a and may still be present in 4.0.b is a problem with the readout of channels being clipped out of data reporting. [[Bug 1 Notes]]

* ''' Synthesis note '''
** Quartus.ini removed.

== Revision 4.0.a (buggy) ==
Note: This revision is on a watch list, after the bug detected 15 July 2008. See the bug section for more details.
* '''Filename''' : rc_v0400000a_07jul2008.sof
* '''Bug Fix'''
** mce_status and adc_offset/flx_quanta commands do not fail after power up.
* ''' Synthesis note '''
** Quartus.ini removed.

* '''Bugs'''
** Seems to clip out channel 0 from data reporting.

== Revision 4.0.9 (buggy) ==
* '''Filename''' : rc_v04000009_26jun2008.sof
* '''Features'''
** sa_bias and offset DACs only refreshed when new values are written. (in previous versions, DACs were refreshed every frame)
* '''Bugs'''
** fb_const0 commands to channel 0 do not work. The value is stored in the register, but not applied to the DAC. Thus, read-back returns the correct value, but the DAC does not.
** reading flx_quanta and adc_offset right after power up hangs the reply datapath to CC. resetmce clears this error as temporary solution. the problem is caused by first read ack of the wishbone slave.

== Revision 4.0.8 ==
* '''Filename''' : rc_v04000008_26jun2008.sof
* '''Features'''
** The gaini, gainp, gaind resolution increased to 12-bit, i.e. -2048 to 2047 (formerly 10-bit).

* '''Bug fix'''
** the bug associated with gainpid read before mce_reset is fixed.

* ''' Synthesis note '''
** Quartus.ini removed.

== Revision 4.3.7 ==
* '''Filename''' : rc_v04030007_26may2008_raw.sof
* '''Features'''
** 14-bit raw mode enabled to buffer a snapshot of 50MHz samples for 2 frames of row_len * num_rows samples.
** In order to extend the raw-mode to 14-bit, an assumption is made that the raw buffer is not written to while being read. Therefore, make sure there is at least 2*row_len*num_rows*20ns between issuing captr_raw command and reading back the raw data.
** In order to save RAM for raw mode, two memory-intensive features are disabled:
*** low-pass filter disabled ( mixed filtfb data modes 6, 7, 9 are also disabled)
*** PID (gainp0, gaini0, gaind0) readback disabled. one can still set PID values and run servo, but can not read back the values.

== Revision 4.2.7 ==
* '''Filename''' : rc_v04020007_24may2008_raw.sof
* '''Features'''
** raw mode enabled to buffer a snapshot of 50MHz samples for 2 frames of row_len * num_rows samples.
** In order to save RAM for raw mode, two memory-intensive features are disabled:
*** low-pass filter disabled ( mixed filtfb data modes 6, 7, 9 are also disabled)
*** PID (gainp0, gaini0, gaind0) readback disabled. one can still set PID values and run servo, but can not read back the values.
* '''Bug fix'''
** the bug associated with reading from raw-buffer is fixed.

== Revision 4.1.7 ==
* '''Filename''' : rc_v04010007_25apr2008_raw.sof
* '''Features'''
** raw mode enabled to buffer a snapshot of 50MHz samples for 2 frames of row_len * num_rows samples.
** In order to save RAM for raw mode, two memory-intensive features are disabled:
*** low-pass filter disabled ( mixed filtfb data modes 6, 7, 9 are also disabled)
*** PID (gainp0, gaini0, gaind0) readback disabled. one can still set PID values and run servo, but can not read back the values.
* '''Bugs'''
** after each readout frame, raw-buffer readout counter falls behind by 3 and this causes skipping 3 50MHz samples in the data stream and column-data being messed up in subsequent frames. Data can be rearranged by post processing.

== Revision 4.0.6 (buggy) ==
* '''Filename''' : rc_v04000006_15feb2008.sof or .pof
* '''Features'''
** '''bugfix''': unreliable reset due to unsafe and incomplete state machines is fixed.
** '''bugfix''': flux_jump sign problem fixed, so far proved in const_mode, to be tested in servo_mode with cold setup.
** servo_mode=2 or ramp previously only went from 0 to ramp_amp, but now goes from -8192 to -8192+ramp_amp
** new commands are added: ''scratch'' and ''card_type''. Scratch takes 8 values and can be used by software to detect reset.
** slot_id and fw_rev are now integrated as part of all_cards.vhd
** lvds_tx_b=0, This will allow Clock Card to use the secondary backplane lvds line and check whether RC is plugged in.
** filter_coeff in misc_banks_admin commented as it is not implemented and causes timing problems.

* '''Bugs'''
** reading gainp/gaini/gaind right after power up hangs the reply datapath to CC. resetmce clears this error as temporary solution. the problem is caused by first read ack of pid_ram_admin.
** slot_id is only set after a resetmce is issued. (using the latest all_cards in the next revision will fix this)
** has spurious spikes on channel 7 data, which max out the integral, and cause the detectors to come unlocked. This firmware officially meets timing requirements, but the bug could be due to marginal timing on the longest data paths, i.e. ~0.1 ns in some cases.

== Revision 4.0.5 ==
* '''Filename''' : rc_v04000005_01nov2007.sof or .pof
* '''Features'''
** data mode 9 (mixed filt + flux jump) with windowing readjusted compared to data mode 8

* '''Bugs'''
** unreliable resetmce. Sometimes, firmware waked up non-responsive on lvds lines.
** In data mode 5 and 9, flux-jump counter is not reported properly due to a sign error. However, flux jumping works fine.

== Revision 3.0.19 ==
* '''Filename''' : rc_v03000019_16feb2007_raw.sof (no pof as one is not likely to run with this as regular firmware)
* '''Features'''
** data mode 3 is enabled.
** filter is disabled as a compromise to fit the raw-mode buffer.

* '''Bugs'''
** unreliable resetmce. Sometimes, firmware waked up non-responsive on lvds lines.

== Old Firmware Revisions ==
* '''4.0.4''': rc_v04000004_11oct2007.sof data mode 8 added (mixed filt + flux jump)
* '''4.0.3''': rc_v04000003_19sep2007.sof data mode 7 bit split readjusted to 10b error being bit 4 to 14
* '''4.0.2''': rc_v04000002_11sep2007.sof pid resolution increased to 10b, data mode 7 added
* '''4.0.1''': rc_v04000001_06sep2007.sof
* '''4.0.0''': rc_v04000000_29aug2007.sof supports readout_row_index * [[ bugs ]]

= To-Do List =
* the starting point for the servo is currently zero and it would be nice to have it programmable.

= RC Synthesis Notes =
# The following note applies when using Quartus versions earlier than Q7: Quartus.ini file had to exist in synth directory up to revision 4.0.a due to a bug that started in Quartus 6.1 and would synthesize away arbitrary parts of readout card. We contacted Altera at the time and they provided us the ini file.
# Timing: There is no "lock region" defined for readout card. Timing on readout card is tight and since version 3 or so any new feature would initially fail timing till some synthesis options were tweaked. One path that remains to be consistently marginal is from addr_gen counter (i.e. tga_o counter) in dispatch_wishbone.vhd to wishbone slaves particularly misc_banks_admin.vhd. Modules that are rewritten to address timing concerns are fsfb_corr, all_cards, misc_banks_admin, and finally instantiating an lpm counter instead of a counter from components library. Surprisingly, the lpm counter reduced 87 failures to 37, although looking at the technology map viewer, it seemed that they were both synthesized the same.
# Compile time: This was at some point 4.5 hours, after going to dual core PC, this was reduced to 35 minutes. After extending pid gains to 12b and fixing offset/sa_bias update code, the compile time increased to 1.5hr again with utilization up to ~70%.
# wbs_fb_storage, ram_8x64, pid_ram had to be regenerated using latest (Q7.2) MegaWizard to get rid of the bug associated with failure to read after power up until a reset was issued.
# During simulations, the initialization of RAM block with .hex files needs to be disabled. This is done by commenting out the following lines from the MegaWizard generated Megafunction files (remember to un-comment them before synthesizing the code):
lpm_file => "C:/scuba2_repository/cards/readout_card/fsfb_calc/source/rtl/ram_40x64.hex", and
lpm_file : STRING;
#Starting Q10.0 use TimeQuest timing analyzer as oppose to the classic one. The classic one is being phased out by Altera. In order to use TimeQuest, you need to have an sdc file present in your project directory.
----
[http://e-mode.phas.ubc.ca/mcewiki/index.php/Main_Page MCE Main Page]

Readout Card firmware

2011-05-04T21:55:25Z

Bburger: /* Revision 5.0.d (not recommended) */

* Synthesis Reminders (for firmware developers)
** quartus.ini is not needed anymore (Fixed as of Q7, Altera SR10783580 2010-10-24)
** Remember that readout_card/fsfb_clac/source/rtl/ram_40x64.vhd must be initialized with the ram_40x64.hex file in the same directory.
= Revision 5.1.2 =
* '''Filename:'''
** rc_stratix3_v05010002_18jan2011.sof (for Rev. E cards)
** rc_stratix3_v05010002_18jan2011.jic (for Rev. E cards)
** rc_v05010002_03feb2011.sof (for Rev. B cards)
** rc_v05010002_03feb2011.pof (for Rev. B cards)

* '''Features:'''
** based on 5.1.1 with k1 and k2 (filter params) limited to k1<16 and k2<32 in order to resolve the timing when compiling for smaller Stratix FPGA on RC Rev. B.

* '''Bug fix:'''
** the 2-rows-off filtered data readout introduced with configurable filter in rev. 5.1.0 and 5.1.1 is fixed now.

* '''Bugs:'''
** none so far.

* '''FPGA Resource Usage''' (readout_card.fit.rpt, rev. B)
; Total logic elements ; 33,285 / 41,250 ( 81 % ) ;
; Total pins ; 358 / 616 ( 58 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt, rev. B)
; Fast Model Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 6.591 ns
; Fast Model Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 7.206 ns
; Fast Model Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 18.299 ns

== Revision 5.1.1 (not recommended) ==
* '''Filename:'''
** rc_v05010001_01dec2010.sof (for Rev. B cards)

* '''Features:'''
** based on 5.1.0, but k1 and k2 (filter params) are now limited to k1<16 and k2<32 in order to resolve the timing failures of compiling 5.1.0 for smaller Stratix FPGA on RC Rev. B.

* '''Bugs:'''
** filter mode data is off by 2 rows.

== Revision 5.1.0 (not recommended) ==
* '''Filename:'''
** rc_stratix3_v05010000_01nov2010.sof (for Rev. E cards)
** rc_v05010000_01nov2010.sof (for Rev. B cards) has timing failures '''do not use!!!'''

* '''Features:'''
** added configurable filter parameters specified by ''fltr_coeff'', default is the fcutoff/fsampl=122Hz/15kHz. see [[ Digital 4-pole Butterworth Low-pass filter ]].
** ''fltr_type'' is set to 255 to indicate configurable filter parameters.
** see [http://www.phas.ubc.ca/~mce/mcedocs/software/SC2_ELE_S580_515_mce_command_description.pdf MCE command description]
** development notes:
*** It is built on Quartus10.1.
*** tcl files had to be updated as cmp syntax is not supported in Q10 anymore.
*** Rev. E cards now can be identified by reading back pcb_rev as part of card_type, therefore both stratix I and III sof/pof/jic are generated from the same source.

* '''Bugs:'''
** rc_v05010000_01nov2010.sof has timing failures that were overlooked, do not use this firmware for Rev.B cards.
** '''filter mode data is off by 2 rows.'''

* '''FPGA Resource Usage and Timing Report''' (readout_card.fit.rpt and readout_card.tan.rpt): logic usage is upto 85% from 66% in 5.0.d/e/f

= Revision 5.0.f =
* '''Filename:'''
** rc_v0500000f_22oct2010.sof (for Rev. B cards)
** rc_stratix3_v0500000f_22oct2010.sof (for Rev. E cards)

* '''Features:'''
** Bugfix: integral clamp should work now. only positive integral_clamp values are valid!

* '''Details:''':
** SQ1FB is applied 18 clock cycles after start of a row visit (SQ1_Bias being applied) regardless of flux-jump being enabled or not. In pre-5.0.b firmware SQ1FB was being applied after 7 clock cycles when flux-jump was disabled and after 18 clock cycles when flux-jump was enabled.
** available for both Rev. E and Rev. B cards, the upper byte of card_type parameter now reports the pcb revision.
** development note: It is built on Quartus10.1.

* '''Bugs:'''
**none yet!

* '''FPGA Resource Usage and Timing Report''' (readout_card.fit.rpt and readout_card.tan.rpt): no change compared to 5.0.a/b/c/d

== Revision 5.0.e (not recommended) ==
* '''Filename:'''
** rc_v0500000e_06oct2010.sof

* '''Details:'''
** an unsuccessful attempt to fix integral_clamp, but changed the functionality so that it clamps at the value, but it doesn't hold the clamp. i.e., if the calculated sq1fb becomes less than the specified clamp value, the sq1fb is not clamped anymore. This is not a desired functionality!

== Revision 5.0.d (not recommended) ==
* '''Filename:'''
** rc_v0500000d_04aug2010.sof

* '''Features:'''
** Bugfix: To fix the bug associated with negative flux-jumps, reverted to signed multiplier and hence, incremented the width of the flux-quanta multiplier input by 1.

* '''Details:''':
** SQ1FB is applied 18 clock cycles after start of a row visit (SQ1_Bias being applied) regardless of flux-jump being enabled or not. In pre-5.0.b firmware SQ1FB was being applied after 7 clock cycles when flux-jump was disabled and after 18 clock cycles when flux-jump was enabled.

* '''Bugs:'''
** '''integral_clamping is broken'''. To test the clamping, a servo-locked ramp was initiated on the sq1fb and then flux-jumping was turned on and observed by attaching a scope to the SQ1FB output. With integral_clamp=80000000, flux_quanta=8000, gaini=1, flux-jump enabled, we see [[http://e-mode.phas.ubc.ca/mcewiki/index.php/Image:Clamp_unstable.png scope snapshot]] used slow_fb_ramp.py script for testing.

* '''FPGA Resource Usage and Timing Report''' (readout_card.fit.rpt and readout_card.tan.rpt): no change compared to 5.0.a/b/c

== Revision 5.0.c (not recommended) ==
* '''Filename:'''
** rc_v0500000c_16jun2010.sof

* '''Features:'''
** Based on rev. 5.0.b
** Re-introduced flux-jump counter clamping to maintain continuity in behavior from past versions of firmware in the field.
** '''Important''': SQ1FB is applied 18 clock cycles after start of a row visit (SQ1_Bias being applied) regardless of flux-jump being enabled or not. In pre-5.0.b firmware SQ1FB was being applied after 7 clock cycles when flux-jump was disabled and after 18 clock cycles when flux-jump was enabled.

* '''Details:'''
* '''Bugs:'''
** '''flux-jump is broken'''. flux-jumping block misbehaves at the first jump in the negative range.

* '''FPGA Resource Usage''' (readout_card.fit.rpt): [[rc_5.0.c_fit_rpt]]
; Total logic elements ; 26,800 / 41,250 ( 65 % ) ;
; Total pins ; 358 / 616 ( 58 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;
; DSP block 9-bit elements ; 76 / 112 ( 68 % ) ;
; Total PLLs ; 1 / 6 ( 17 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt): [[rc_5.0.c_tan_rpt]]
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.964 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 4.382 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 15.924 ns ;

== Revision 5.0.b (not recommended) ==
* '''Filename:'''
** rc_v0500000b_03jun2010.sof

* '''Features:'''
** Based on rev. 5.0.a
** A bug that caused jumps in first-stage feedback, and detected as spikes in the raw data of pixels that were in servo_mode=0,1,2 was fixed. The jumps in FSFB were due to flux-jumping being enabled on live pixes with non-zero flx_quanta, and being disabled on the fly on dead pixels with flx_quanta=0. Flux-jumping is now disabled on a column-by-column basis if a column is in servo_mode = 0,1,2.
** Ineffective clamping was removed from the flux-jumping block (as per 5.0.9), as it is now replaced by the clamping that was perfected in rev. 5.0.10
** A sticky bit that only affected servo_mode=0,1,2 was also removed from the flux-jumping block.
** flx_lp_init commands now also clear the flux-jumping block as well.
** The 11-clock-cycle delay (in applying SQ1_FB) that in previous firmware only occurred when flux-jumping was enabled, now (in this version) is in effect all the time. Due to the bug-fix above, flux-jumping can be disabled on a column-by-column basis by setting servo_mode=0,1,2 when en_fb_jump=1. Before the change, this meant that constant values could be applied with or without the 11-cycle delay if en_fb_jump=1 or 0. To make the delay consistent, it is now always 11 cycles. As background, the flux-jumping block is pipelined, meaning that it does calculations for all 8 channels serially. The serialization is because of DSP-block limitations in the Readout Card FPGA that prevent us from doing all 8 channels in parallel. The reason that it takes 11 cycles to complete the flux-jumping calculations is because the values are computed for the eight channels in three ALU stages: 8 + 3 = 11 cycles. Adding 11 cycles to the 7 cycles of latency from other stages in the system results in: 11 + 7 = 18 cycles of latency from the start of a row dwell period before the first-stage feedback is applied. In rc_v5.0.c, I enforce the 18-cycle delay even when flux-jumping is not enabled to maintain uniformity across all eight channels, because flux-jumping is enabled/disabled on a per-channel basis. In other words, if I hadn't enforced the 18-cycle delay, some channels could have their feedback applied after 7 cycles, while others could have it applied after 18 cycles. I wasn't a fan of this non-uniformity. I realize that 18 cycles is a long time. In fact, so is 7. In the last few months, we have been discussing how to reduce these times to 1 cycle, because every experiment out there wants to multiplex as fast as possible, and the 7/18-delay is a rate limiting step.
** The flux-jumping code was re-arranged in the flux-jumping block to reflect the flow of data through the pipeline and make it easier to understand.

* '''Details:'''

* '''Bugs:'''
** flux-jump does not work when jumping to negative values.

* '''FPGA Resource Usage''' (readout_card.fit.rpt): [[rc_5.0.b_fit_rpt]]
; Total logic elements ; 26,745 / 41,250 ( 65 % ) ;
; Total pins ; 358 / 616 ( 58 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;
; DSP block 9-bit elements ; 76 / 112 ( 68 % ) ;
; Total PLLs ; 1 / 6 ( 17 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;
* '''FPGA Timing Analysis''' (readout_card.tan.rpt): [[rc_5.0.b_tan_rpt]]
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.459 ns
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.895 ns
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 15.956 ns

= Revision 5.0.a =
* '''Filename:'''
** rc_v0500000a_12mar2010.sof

* '''Features:'''
** Based on the merger of rev. 5.0.8 and 5.0.9.
** '''integral_clamp''' command is added where a clamp value is set for the integral term and once the integral term hits that value, the integral-term is clamped to that value and p-term and d-term are clamped to zero. When integral_term=0 then no clamping is in effect, similar to previous releases of firmware.
** The low pass filter has 20-bit input and f_3dB/f_samp = 122Hz/15kHz .
** The flux-jump clamping that was removed in 5.0.9 is included once again here, as we decided this is safer for now.

* '''Details:'''
** "lock_dat_left" parameter that was removed in 5.0.9 is now implemented as "lock_dat_lsb"

* '''Bugs:'''
** flx_lp_init does not reinitialize the flux-jump block

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis
** tag name: rc_v0500000a_12mar2009! years were mixed up!

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
* '''FPGA Timing Analysis''' (readout_card.tan.rpt):

== Revision 5.0.9 (buggy) ==
* '''Filename:'''
** rc_v05000009_13nov2009.sof

* '''Features:'''
** Based on rev. 5.0.4
** Removes a sticky bit in pid calculation result storage -- in fsfb_processor.
** Adds a command to clamp the growth of the I-term to prevent wrapping and track down the source of Caltech's FSFB jumps.
** Removed the unused lock_dat_left parameter. The ability to shift left was moved to the fsfb_corr block some time ago.
** Fixed a sign extension bug acting on the flux quanta, which limited the value to 8191. Changed the extension from signed to unsigned.
** Removed ineffective clamping in the flux-jump calculation block.
** IMPORTANT: Must be used in conjunction with firmware rev. 5.0.0+ of all other cards.

* '''Details:'''

* '''Bugs:'''
** integral_clamp read/write command does not work.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 27,960 / 41,250 ( 68 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.825 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.878 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 14.397 ns ;

== Revision 5.0.8 (UBC only) ==
* '''Filename:'''
** rc_v05000008_09oct2009.sof

* '''Features:'''
** Based on rev. 5.0.4
** type 1 low-pass filter: f3dB=122Hz for fsample=15kHz
** Filter-input-width changed from 18b to 20b with no sticky bits!
** removed sticky bits in internal arithmetic of the filter.

= Revision 5.0.7 (type-2 filter) =
* '''Filename:'''
** rc_v05000007_09oct2009.sof

* '''Features:'''
** Based on rev. 5.0.4
** type-2 low-pass-filter: f3dB=75Hz for fsample=30000.
** Filter-input-width changed from 18b to 20b with no sticky bits!
** inter-biquad-gain-scaling for the filter is 2^14
** filter results are scaled down by 2^3 in the output of the filter.
** removed sticky bits in internal arithmetics
** _correction_ disabled in fsfb_proc_pidz

* '''Details:'''
** quartus.ini file was '''not''' present in synth directory.

* '''Bugs:'''
** none to report

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
== Revision 5.0.6 (UBC only) ==
* '''Filename:'''
** rc_stratix3_v05000006_15sep2009.sof

* '''Features:'''
** Only Valid for Rev. C/D Cards
** Based on rev. 5.0.3
** tcl file updated for Rev. D and aligned with top-level and qsf (project file).
** flux loop commented, just to try sampling the ADC.
** compiled with Q9.1

== Revision 5.0.5 (UBC only) ==
* '''Filename:'''
** rc_v05000005_04sep2009.sof

* '''Features:'''
** Based on rev. 5.0.2
** changed the low-pass-filter to f(3db)=75Hz for f(sample)=30000.

* '''Details:'''
** quartus.ini file was '''not''' present in synth directory.

* '''Bugs:'''
** negative inputs to the filter cause filter to have a non-flat pass-band region. may have to do with sign-handling...

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
* '''FPGA Timing Analysis''' (readout_card.tan.rpt):

= Revision 5.0.4 =
* '''Filename:'''
** rc_v05000004_28aug2009.sof

* '''Features:'''
** Based on rev. 5.0.2
** BUG Fix: handles 14-bit flux quanta (changed the multiplier to unsigned)
** BUG Fix: changed standard logic vector extension from signed to unsigned in flux-jumping slave.
** IMPORTANT: Must be used in conjunction with firmware rev. 5.0.0+ of all other cards.

* '''Details:'''

* '''Bugs:'''
** None so far.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,170 / 41,250 ( 63 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.541 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.612 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 15.398 ns ;

= Revision 5.0.3 =
* '''Filename:'''
** rc_stratix3_v05000003_21aug2009.sof

* '''Features:'''
** ONLY valid REV C/D RC Cards
** Based on rev. 5.0.2
** flux loop commented, just to try sampling the ADC.
** updated tcl file, but still need to rely on project file as well as qsf file.
** changed default level of adc_sclk to '1'
** dac_clr_n was changed from an output to an input.
** added 'locked' interface to rc_pll_stratix_iii
** renamed the adc_pll clock signals to more explanitory names
** added the FPGA_DEVICE_FAMILY generic to the dispatch interace for synthesis of the dc_fifo in lvds_rx
** uncommented DDR interface to force the syntesizer to use correct left and right PLLs (in conjunction with ADC and DDR PLLs)
** added test signals to test_status to see clocks on the scope.
== Revision 5.0.2 (buggy) ==
* '''Filename:'''
** rc_v05000002_test00_tagged.sof

* '''Features:'''
** Based on rev. 5.0.1
** Fixed a bug in wbs_frame_data that stored data incorrectly if reporting 1 or 2 pixels only.
** IMPORTANT: Must be used in conjunction with firmware rev. 5.0.0+ of all other cards.

* '''Details:'''

* '''Bugs:'''
** None so far.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,186 / 41,250 ( 63 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.755 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.979 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.067 ns ;

== Revision 5.0.1 (buggy) (Filter + Raw + Rectangle, 2 LVDS) ==
* '''Filename:'''
** rc_v05000001_26may2009.sof

* '''Features:'''
** Combines features in rev. 5.0.0 (2 LVDS Lines) and rev. 4.0.e (Filtered + Raw), with the NEW rectangle mode.
** IMPORTANT: Must be used in conjunction with firmware rev. 5.0.0+ of all other cards.

* '''Details:'''
** [[CVS Diff Between sys_v05000000 and rc_v05000001]]

* '''Bugs:'''
** Has a bug in wbs_frame_data that stored data incorrectly if reporting 1 or 2 pixels only.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,565 / 41,250 ( 64 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.656 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.861 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 14.167 ns ;

== Revision 5.0.0 (Filter Only, 2 LVDS) ==
* '''Filename:'''
** rc_v05000000_22dec2008.sof (tagged as sys_v05000000_22dec2008)

* '''Features:'''
** IMPORTANT: Must be used in conjunction with firmware v05000000+ of all other cards!!!
** Adds the ability to read out one column of data continuously from readout cards
** Adds data mode 11, which is an engineering mode. Data points are 32-bits, and bits [9..3]=row_index, [2..0]=column_index. This mode is useful for determining which pixels one is reading out in the array, in column mode for example.

* '''Details:'''
** [[CVS Diff Between rc_v0400000c and sys_v05000000]]

* '''Bugs:'''
** None so far.

* '''Synthesis Notes:'''
** The quartus.ini file was not present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,607 / 41,250 ( 65 % ) ;
; Total memory bits ; 406,016 / 3,423,744 ( 12 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.558 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.892 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.987 ns ;

== Revision 4.0.f (Filter + Raw, 1 LVDS) ==
* '''Filename:'''
** rc_v0400000f_12feb2010.sof

* '''Features:'''
** Based on 4.0.e and in parallel with 5.0.9 (equivalent version, clamping is not included)
** Incorporates fixes that were done to flux-jumping between 5.0.2 - 5.0.4 - 5.0.9. Namely:
*** Changes a multiplier from signed to unsigned (in fsfb_corr_multplier.vhd).
*** Changes sign extension from signed to unsigned (in flux_quanta_ram_admin.vhd).

* '''Details:'''

* '''Bugs:'''
** None reported yet.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,773 / 41,250 ( 65 % ) ;
; Total memory bits ; 1,321,984 / 3,423,744 ( 39 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.539 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 4.118 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 17.318 ns ;

== Revision 4.0.e (Filter + Raw, 1 LVDS) ==
* '''Filename:'''
** rc_v0400000e_27apr2009.sof

* '''Features:'''
** Based on 4.0.d
** Combines both raw- and filtered-data modes.
** fpga_temp, card_temp, card_id commands are disabled.
** Tested by Matt Hasselfield.

* '''Details:'''

* '''Bugs:'''
** fpga_temp, card_temp, card_id commands are disabled.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 27,048 / 41,250 ( 66 % ) ;
; Total memory bits ; 1,321,984 / 3,423,744 ( 39 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.675 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.907 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.728 ns ;

== Revision 4.0.d (Raw Only, 1 LVDS) ==
* '''Filename:''' rc_v0400000d_20090417.sof

* '''Features:'''
** Based on v4.0.c, but has the filter removed, and implements a single 65536-index RAM block for storing 50 MHz raw-data samples.
** The firmware takes a new command called readout_col_index which specifies which column to capture raw data from.
** Other than readout_col_index, the firmware functions the same as previous raw-data firmware, including then need to issue a capture_raw command.
** For more information on raw-data, see: http://e-mode.phas.ubc.ca/mcewiki/index.php/Raw-mode_readout
** This firmware also integrates some of the improvements that were implemented in 4.4.0, like the removal of the tga_o signal from an FSM in dispatch_wishbone.vhd.

* '''Details:'''
** Differences between 4.0.c and 4.0.d
U system/test/source/tb/tb_cc_rcs_bcs_ac.vhd
U all_cards/dispatch/source/rtl/dispatch_wishbone.vhd
U library/sys_param/source/rtl/wishbone_pack.vhd
U readout_card/adc_sample_coadd/source/rtl/adc_sample_coadd.vhd
U readout_card/adc_sample_coadd/source/rtl/adc_sample_coadd_pack.vhd
U readout_card/flux_loop/source/rtl/flux_loop.vhd
U readout_card/flux_loop/source/rtl/flux_loop_pack.vhd
U readout_card/flux_loop_ctrl/source/rtl/flux_loop_ctrl.vhd
U readout_card/flux_loop_ctrl/source/rtl/flux_loop_ctrl_pack.vhd
U readout_card/flux_loop_ctrl/source/tb/tb1_flux_loop_ctrl.vhd
U readout_card/flux_loop_ctrl/source/tb/tb2_flux_loop_ctrl.vhd
U readout_card/fsfb_calc/source/rtl/fsfb_fltr_regs.vhd
U readout_card/fsfb_corr/source/rtl/fsfb_corr.vhd
U readout_card/readout_card/source/rtl/readout_card.vhd
U readout_card/readout_card/source/rtl/readout_card_pack.vhd
U readout_card/wbs_frame_data/source/rtl/wbs_frame_data.vhd
U readout_card/wbs_frame_data/source/rtl/wbs_frame_data_pack.vhd

* '''Bugs:'''
** None so far.
** fpga_temp, card_temp, card_id commands are not supported.

* '''Synthesis Notes:'''
** The quartus.ini file was present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 24,554 / 41,250 ( 60 % ) ;
; Total memory bits ; 1,262,592 / 3,423,744 ( 37 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.991 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.864 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 17.052 ns ;

== Revision 4.4.1 ==
* '''Filename:''' rc_v04040001_21nov2008

* '''Features:'''
** Fixes a bug that froze up the firmware if any of the following commands were issued: CARD_ID_ADDR, CARD_TEMP_ADDR, FPGA_TEMP_ADDR in 4.4.0 only.

* '''Details:'''
** The bug fix include adding more logic to the wishbone ack path (readout_card.vhd), which subsequently decreased the minimum clock setup time to 1.588ns. The new logic will catch errors that the old logic wouldn't have, and is now consistent with the firmware on all the other cards. However, if timing becomes an issue, the logic may have to revert back to that which was in version 4.0.c.

* '''Bugs:'''
** None so far.

* '''Synthesis Notes:'''
** The quartus.ini file was not present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 27,241 / 41,250 ( 66 % ) ;
; Total memory bits ; 405,504 / 3,423,744 ( 12 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.588 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.585 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 17.057 ns ;

== Revision 4.4.0 (buggy) ==
* '''Filename:''' rc_v04040000_02oct2008
* '''Features:'''
** Reinstated the data modes in wbs_frame_data.vhd that were removed in 4.0.c. This firmware has the following modes: '''0, 1, 2, 4, 5, 7, 10'''. The modes that are not present are: '''3''' (raw data), '''6''' (replaced by data_mode = 7), '''8''' (replaced by data_mode = 10), '''9''' (replaced by data_mode = 10). For more information on data modes, see [[Data mode]].
** Re-integrated the id_thermo and fpga_thermo block in the readout_card.vhd top level that was removed in 4.0.c.
** Removed the sticky bit in fsfb_corr.vhd, which was enabled when flux-jumping was turned on. Because the feedback is signed, the sticky bit would usually reflect the value of the 14th bit, except in situations when the number of flux quanta to jump was greater than 1 (i.e. cosmic rays, IV-curves, etc). Flux jumps are made at a maximum rate of one per frame period, so that if the First-Stage Feedback increased past the 13th bit, it would not be reflected in the feedback applied. Now it is.
* '''Details:'''
** Simplified the FSM logic in wbs_frame_data.vhd that determines when to transition from IDLE to WSS1. This was done to lower the number of gates in that path, and ease the timing.
** Removed the z_dat_i port in fsfb_processor.vhd and fsfb_calc_pack.vhd to the fsfb_proc_pidz block, in an effort to make it clearer within that block that the z-term is always = 0.
** Removed the z-term sign extension in fsfb_proc_pidz.vhd, and the [d-term + z-term] adder to free up DSP resources since the z-term is always = 0.
** Adjusted the indentation in fsfb_io_controller.vhd to make the file more readable.
** Moved the tga_o signal out of the dispatch_wishbone.vhd FSM, and made it a continuous assignment. This signal had one of the highest fan-out counts in the RTL design, and actually was impossible to route in Stratix III chips in its previous configuration because of the number of gates on the fan-out. As a consequence of making it a continuous assignment, the Stratix III fitter was able to succeed, and the Stratix I timing characteristics were greatly improved. This is the most significant change in this revision. This change single-handedly increased the minimum slack from 1.282 ns in v0400000c to 2.372 ns (or 56.7 MHz max) in this revision.
* '''Bugs:'''
** The following commands lock up the Readout Card firmware: CARD_ID_ADDR, CARD_TEMP_ADDR, FPGA_TEMP_ADDR.
** fb_const0 commands to channel 0 do not work. The value is stored in the register, but not applied to the DAC. Thus, read-back returns the correct value, but the DAC does not
* '''Synthesis Notes:'''
** The quartus.ini file was not present in the synth directory during synthesis.
* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 27,099 / 41,250 ( 66 % ) ;
; Total memory bits ; 406,016 / 3,423,744 ( 12 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.372 ns ;
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 4.052 ns ;
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.066 ns ;

== Revision 4.0.c ==
* '''Filename:''' rc_v0400000c_15aug2008.sof
* '''Features:'''
** Only has data modes 0, 1, 4, and 10.
** Fixed the bug that exists in 4.0.b, 4.0.a, and 4.0.9 that prevented the fb_const value from being applied to channel zero (wbs_fb_data.vhd).
* '''Details:'''
** Changed a counter in the dispatch block to ease timing constraints in synthesis (dispatch_wishbone.vhd)
** Updated the tagged versions of dispatch.vhd , dispatch_cmd_receive.vhd, and dispatch_reply_transmit.vhd to the version that is used by all the other cards.
** '''Removed''' the fpga_termo (command: '''fpga_temp''') and id_thermo (commands: '''card_temp, card_id''') to ease timing constraints in synthesis (readout_card.vhd)
** Updated the tagged version of fpga_termo.vhd to include the new 'stale bit' feature
** Updated the tagged version of frame_timing_core.vhd to include the new 'err_o' interface
* '''Bugs:'''
** None reported yet
* '''Synthesis Notes:'''
** The quartus.ini file was not present in the synth directory during synthesis.
* '''FPGA Resource Usage:'''
Total logic elements : 25,058 / 41,250 ( 61 % )
Total memory bits : 400,896 / 3,423,744 ( 12 % )

* '''Timing Analysis''' (readout_card.tan.rpt):
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.282 ns ;
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.736 ns ;
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.665 ns ;

== Revision 4.0.b (buggy) ==
Note: This revision is on a watch list, after the bug detected 15 July 2008. See the bug section for more details.
* '''Filename''' : rc_v0400000b_04aug2008.sof
* '''Features'''
** data_mode 10 is added to provide more filtfb bits (compared to data mode 9) for planet observations. filtered_dat(27 downto 3) & flux_cnt_dat(6 downto 0)

* '''Bugs'''
** An unexplained bug that appeared in 4.0.a and may still be present in 4.0.b is a problem with the readout of channels being clipped out of data reporting. [[Bug 1 Notes]]

* ''' Synthesis note '''
** Quartus.ini removed.

== Revision 4.0.a (buggy) ==
Note: This revision is on a watch list, after the bug detected 15 July 2008. See the bug section for more details.
* '''Filename''' : rc_v0400000a_07jul2008.sof
* '''Bug Fix'''
** mce_status and adc_offset/flx_quanta commands do not fail after power up.
* ''' Synthesis note '''
** Quartus.ini removed.

* '''Bugs'''
** Seems to clip out channel 0 from data reporting.

== Revision 4.0.9 (buggy) ==
* '''Filename''' : rc_v04000009_26jun2008.sof
* '''Features'''
** sa_bias and offset DACs only refreshed when new values are written. (in previous versions, DACs were refreshed every frame)
* '''Bugs'''
** fb_const0 commands to channel 0 do not work. The value is stored in the register, but not applied to the DAC. Thus, read-back returns the correct value, but the DAC does not.
** reading flx_quanta and adc_offset right after power up hangs the reply datapath to CC. resetmce clears this error as temporary solution. the problem is caused by first read ack of the wishbone slave.

== Revision 4.0.8 ==
* '''Filename''' : rc_v04000008_26jun2008.sof
* '''Features'''
** The gaini, gainp, gaind resolution increased to 12-bit, i.e. -2048 to 2047 (formerly 10-bit).

* '''Bug fix'''
** the bug associated with gainpid read before mce_reset is fixed.

* ''' Synthesis note '''
** Quartus.ini removed.

== Revision 4.3.7 ==
* '''Filename''' : rc_v04030007_26may2008_raw.sof
* '''Features'''
** 14-bit raw mode enabled to buffer a snapshot of 50MHz samples for 2 frames of row_len * num_rows samples.
** In order to extend the raw-mode to 14-bit, an assumption is made that the raw buffer is not written to while being read. Therefore, make sure there is at least 2*row_len*num_rows*20ns between issuing captr_raw command and reading back the raw data.
** In order to save RAM for raw mode, two memory-intensive features are disabled:
*** low-pass filter disabled ( mixed filtfb data modes 6, 7, 9 are also disabled)
*** PID (gainp0, gaini0, gaind0) readback disabled. one can still set PID values and run servo, but can not read back the values.

== Revision 4.2.7 ==
* '''Filename''' : rc_v04020007_24may2008_raw.sof
* '''Features'''
** raw mode enabled to buffer a snapshot of 50MHz samples for 2 frames of row_len * num_rows samples.
** In order to save RAM for raw mode, two memory-intensive features are disabled:
*** low-pass filter disabled ( mixed filtfb data modes 6, 7, 9 are also disabled)
*** PID (gainp0, gaini0, gaind0) readback disabled. one can still set PID values and run servo, but can not read back the values.
* '''Bug fix'''
** the bug associated with reading from raw-buffer is fixed.

== Revision 4.1.7 ==
* '''Filename''' : rc_v04010007_25apr2008_raw.sof
* '''Features'''
** raw mode enabled to buffer a snapshot of 50MHz samples for 2 frames of row_len * num_rows samples.
** In order to save RAM for raw mode, two memory-intensive features are disabled:
*** low-pass filter disabled ( mixed filtfb data modes 6, 7, 9 are also disabled)
*** PID (gainp0, gaini0, gaind0) readback disabled. one can still set PID values and run servo, but can not read back the values.
* '''Bugs'''
** after each readout frame, raw-buffer readout counter falls behind by 3 and this causes skipping 3 50MHz samples in the data stream and column-data being messed up in subsequent frames. Data can be rearranged by post processing.

== Revision 4.0.6 (buggy) ==
* '''Filename''' : rc_v04000006_15feb2008.sof or .pof
* '''Features'''
** '''bugfix''': unreliable reset due to unsafe and incomplete state machines is fixed.
** '''bugfix''': flux_jump sign problem fixed, so far proved in const_mode, to be tested in servo_mode with cold setup.
** servo_mode=2 or ramp previously only went from 0 to ramp_amp, but now goes from -8192 to -8192+ramp_amp
** new commands are added: ''scratch'' and ''card_type''. Scratch takes 8 values and can be used by software to detect reset.
** slot_id and fw_rev are now integrated as part of all_cards.vhd
** lvds_tx_b=0, This will allow Clock Card to use the secondary backplane lvds line and check whether RC is plugged in.
** filter_coeff in misc_banks_admin commented as it is not implemented and causes timing problems.

* '''Bugs'''
** reading gainp/gaini/gaind right after power up hangs the reply datapath to CC. resetmce clears this error as temporary solution. the problem is caused by first read ack of pid_ram_admin.
** slot_id is only set after a resetmce is issued. (using the latest all_cards in the next revision will fix this)
** has spurious spikes on channel 7 data, which max out the integral, and cause the detectors to come unlocked. This firmware officially meets timing requirements, but the bug could be due to marginal timing on the longest data paths, i.e. ~0.1 ns in some cases.

== Revision 4.0.5 ==
* '''Filename''' : rc_v04000005_01nov2007.sof or .pof
* '''Features'''
** data mode 9 (mixed filt + flux jump) with windowing readjusted compared to data mode 8

* '''Bugs'''
** unreliable resetmce. Sometimes, firmware waked up non-responsive on lvds lines.
** In data mode 5 and 9, flux-jump counter is not reported properly due to a sign error. However, flux jumping works fine.

== Revision 3.0.19 ==
* '''Filename''' : rc_v03000019_16feb2007_raw.sof (no pof as one is not likely to run with this as regular firmware)
* '''Features'''
** data mode 3 is enabled.
** filter is disabled as a compromise to fit the raw-mode buffer.

* '''Bugs'''
** unreliable resetmce. Sometimes, firmware waked up non-responsive on lvds lines.

== Old Firmware Revisions ==
* '''4.0.4''': rc_v04000004_11oct2007.sof data mode 8 added (mixed filt + flux jump)
* '''4.0.3''': rc_v04000003_19sep2007.sof data mode 7 bit split readjusted to 10b error being bit 4 to 14
* '''4.0.2''': rc_v04000002_11sep2007.sof pid resolution increased to 10b, data mode 7 added
* '''4.0.1''': rc_v04000001_06sep2007.sof
* '''4.0.0''': rc_v04000000_29aug2007.sof supports readout_row_index * [[ bugs ]]

= To-Do List =
* the starting point for the servo is currently zero and it would be nice to have it programmable.

= RC Synthesis Notes =
# The following note applies when using Quartus versions earlier than Q7: Quartus.ini file had to exist in synth directory up to revision 4.0.a due to a bug that started in Quartus 6.1 and would synthesize away arbitrary parts of readout card. We contacted Altera at the time and they provided us the ini file.
# Timing: There is no "lock region" defined for readout card. Timing on readout card is tight and since version 3 or so any new feature would initially fail timing till some synthesis options were tweaked. One path that remains to be consistently marginal is from addr_gen counter (i.e. tga_o counter) in dispatch_wishbone.vhd to wishbone slaves particularly misc_banks_admin.vhd. Modules that are rewritten to address timing concerns are fsfb_corr, all_cards, misc_banks_admin, and finally instantiating an lpm counter instead of a counter from components library. Surprisingly, the lpm counter reduced 87 failures to 37, although looking at the technology map viewer, it seemed that they were both synthesized the same.
# Compile time: This was at some point 4.5 hours, after going to dual core PC, this was reduced to 35 minutes. After extending pid gains to 12b and fixing offset/sa_bias update code, the compile time increased to 1.5hr again with utilization up to ~70%.
# wbs_fb_storage, ram_8x64, pid_ram had to be regenerated using latest (Q7.2) MegaWizard to get rid of the bug associated with failure to read after power up until a reset was issued.
# During simulations, the initialization of RAM block with .hex files needs to be disabled. This is done by commenting out the following lines from the MegaWizard generated Megafunction files (remember to un-comment them before synthesizing the code):
lpm_file => "C:/scuba2_repository/cards/readout_card/fsfb_calc/source/rtl/ram_40x64.hex", and
lpm_file : STRING;
#Starting Q10.0 use TimeQuest timing analyzer as oppose to the classic one. The classic one is being phased out by Altera. In order to use TimeQuest, you need to have an sdc file present in your project directory.
----
[http://e-mode.phas.ubc.ca/mcewiki/index.php/Main_Page MCE Main Page]

Readout Card firmware

2011-05-04T21:53:55Z

Bburger: /* Revision 5.1.2 */

* Synthesis Reminders (for firmware developers)
** quartus.ini is not needed anymore (Fixed as of Q7, Altera SR10783580 2010-10-24)
** Remember that readout_card/fsfb_clac/source/rtl/ram_40x64.vhd must be initialized with the ram_40x64.hex file in the same directory.
= Revision 5.1.2 =
* '''Filename:'''
** rc_stratix3_v05010002_18jan2011.sof (for Rev. E cards)
** rc_stratix3_v05010002_18jan2011.jic (for Rev. E cards)
** rc_v05010002_03feb2011.sof (for Rev. B cards)
** rc_v05010002_03feb2011.pof (for Rev. B cards)

* '''Features:'''
** based on 5.1.1 with k1 and k2 (filter params) limited to k1<16 and k2<32 in order to resolve the timing when compiling for smaller Stratix FPGA on RC Rev. B.

* '''Bug fix:'''
** the 2-rows-off filtered data readout introduced with configurable filter in rev. 5.1.0 and 5.1.1 is fixed now.

* '''Bugs:'''
** none so far.

* '''FPGA Resource Usage''' (readout_card.fit.rpt, rev. B)
; Total logic elements ; 33,285 / 41,250 ( 81 % ) ;
; Total pins ; 358 / 616 ( 58 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt, rev. B)
; Fast Model Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 6.591 ns
; Fast Model Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 7.206 ns
; Fast Model Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 18.299 ns

== Revision 5.1.1 (not recommended) ==
* '''Filename:'''
** rc_v05010001_01dec2010.sof (for Rev. B cards)

* '''Features:'''
** based on 5.1.0, but k1 and k2 (filter params) are now limited to k1<16 and k2<32 in order to resolve the timing failures of compiling 5.1.0 for smaller Stratix FPGA on RC Rev. B.

* '''Bugs:'''
** filter mode data is off by 2 rows.

== Revision 5.1.0 (not recommended) ==
* '''Filename:'''
** rc_stratix3_v05010000_01nov2010.sof (for Rev. E cards)
** rc_v05010000_01nov2010.sof (for Rev. B cards) has timing failures '''do not use!!!'''

* '''Features:'''
** added configurable filter parameters specified by ''fltr_coeff'', default is the fcutoff/fsampl=122Hz/15kHz. see [[ Digital 4-pole Butterworth Low-pass filter ]].
** ''fltr_type'' is set to 255 to indicate configurable filter parameters.
** see [http://www.phas.ubc.ca/~mce/mcedocs/software/SC2_ELE_S580_515_mce_command_description.pdf MCE command description]
** development notes:
*** It is built on Quartus10.1.
*** tcl files had to be updated as cmp syntax is not supported in Q10 anymore.
*** Rev. E cards now can be identified by reading back pcb_rev as part of card_type, therefore both stratix I and III sof/pof/jic are generated from the same source.

* '''Bugs:'''
** rc_v05010000_01nov2010.sof has timing failures that were overlooked, do not use this firmware for Rev.B cards.
** '''filter mode data is off by 2 rows.'''

* '''FPGA Resource Usage and Timing Report''' (readout_card.fit.rpt and readout_card.tan.rpt): logic usage is upto 85% from 66% in 5.0.d/e/f

= Revision 5.0.f =
* '''Filename:'''
** rc_v0500000f_22oct2010.sof (for Rev. B cards)
** rc_stratix3_v0500000f_22oct2010.sof (for Rev. E cards)

* '''Features:'''
** Bugfix: integral clamp should work now. only positive integral_clamp values are valid!

* '''Details:''':
** SQ1FB is applied 18 clock cycles after start of a row visit (SQ1_Bias being applied) regardless of flux-jump being enabled or not. In pre-5.0.b firmware SQ1FB was being applied after 7 clock cycles when flux-jump was disabled and after 18 clock cycles when flux-jump was enabled.
** available for both Rev. E and Rev. B cards, the upper byte of card_type parameter now reports the pcb revision.
** development note: It is built on Quartus10.1.

* '''Bugs:'''
**none yet!

* '''FPGA Resource Usage and Timing Report''' (readout_card.fit.rpt and readout_card.tan.rpt): no change compared to 5.0.a/b/c/d

== Revision 5.0.e (not recommended) ==
* '''Filename:'''
** rc_v0500000e_06oct2010.sof

* '''Details:'''
** an unsuccessful attempt to fix integral_clamp, but changed the functionality so that it clamps at the value, but it doesn't hold the clamp. i.e., if the calculated sq1fb becomes less than the specified clamp value, the sq1fb is not clamped anymore. This is not a desired functionality!

== Revision 5.0.d (not recommended) ==
* '''Filename:'''
** rc_v0500000d_04aug2010.sof

* '''Features:'''
** Bugfix: To fix the bug associated with negative flux-jumps, reverted to signed multiplier and hence, incremented the width of the flux-quanta multiplier input by 1.

* '''Details:''': SQ1FB is applied 18 clock cycles after start of a row visit (SQ1_Bias being applied) regardless of flux-jump being enabled or not. In pre-5.0.b firmware SQ1FB was being applied after 7 clock cycles when flux-jump was disabled and after 18 clock cycles when flux-jump was enabled.

* '''Bugs:'''
** '''integral_clamping is broken'''. To test the clamping, a servo-locked ramp was initiated on the sq1fb and then flux-jumping was turned on and observed by attaching a scope to the SQ1FB output. With integral_clamp=80000000, flux_quanta=8000, gaini=1, flux-jump enabled, we see [[http://e-mode.phas.ubc.ca/mcewiki/index.php/Image:Clamp_unstable.png scope snapshot]] used slow_fb_ramp.py script for testing.

* '''FPGA Resource Usage and Timing Report''' (readout_card.fit.rpt and readout_card.tan.rpt): no change compared to 5.0.a/b/c

== Revision 5.0.c (not recommended) ==
* '''Filename:'''
** rc_v0500000c_16jun2010.sof

* '''Features:'''
** Based on rev. 5.0.b
** Re-introduced flux-jump counter clamping to maintain continuity in behavior from past versions of firmware in the field.
** '''Important''': SQ1FB is applied 18 clock cycles after start of a row visit (SQ1_Bias being applied) regardless of flux-jump being enabled or not. In pre-5.0.b firmware SQ1FB was being applied after 7 clock cycles when flux-jump was disabled and after 18 clock cycles when flux-jump was enabled.

* '''Details:'''
* '''Bugs:'''
** '''flux-jump is broken'''. flux-jumping block misbehaves at the first jump in the negative range.

* '''FPGA Resource Usage''' (readout_card.fit.rpt): [[rc_5.0.c_fit_rpt]]
; Total logic elements ; 26,800 / 41,250 ( 65 % ) ;
; Total pins ; 358 / 616 ( 58 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;
; DSP block 9-bit elements ; 76 / 112 ( 68 % ) ;
; Total PLLs ; 1 / 6 ( 17 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt): [[rc_5.0.c_tan_rpt]]
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.964 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 4.382 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 15.924 ns ;

== Revision 5.0.b (not recommended) ==
* '''Filename:'''
** rc_v0500000b_03jun2010.sof

* '''Features:'''
** Based on rev. 5.0.a
** A bug that caused jumps in first-stage feedback, and detected as spikes in the raw data of pixels that were in servo_mode=0,1,2 was fixed. The jumps in FSFB were due to flux-jumping being enabled on live pixes with non-zero flx_quanta, and being disabled on the fly on dead pixels with flx_quanta=0. Flux-jumping is now disabled on a column-by-column basis if a column is in servo_mode = 0,1,2.
** Ineffective clamping was removed from the flux-jumping block (as per 5.0.9), as it is now replaced by the clamping that was perfected in rev. 5.0.10
** A sticky bit that only affected servo_mode=0,1,2 was also removed from the flux-jumping block.
** flx_lp_init commands now also clear the flux-jumping block as well.
** The 11-clock-cycle delay (in applying SQ1_FB) that in previous firmware only occurred when flux-jumping was enabled, now (in this version) is in effect all the time. Due to the bug-fix above, flux-jumping can be disabled on a column-by-column basis by setting servo_mode=0,1,2 when en_fb_jump=1. Before the change, this meant that constant values could be applied with or without the 11-cycle delay if en_fb_jump=1 or 0. To make the delay consistent, it is now always 11 cycles. As background, the flux-jumping block is pipelined, meaning that it does calculations for all 8 channels serially. The serialization is because of DSP-block limitations in the Readout Card FPGA that prevent us from doing all 8 channels in parallel. The reason that it takes 11 cycles to complete the flux-jumping calculations is because the values are computed for the eight channels in three ALU stages: 8 + 3 = 11 cycles. Adding 11 cycles to the 7 cycles of latency from other stages in the system results in: 11 + 7 = 18 cycles of latency from the start of a row dwell period before the first-stage feedback is applied. In rc_v5.0.c, I enforce the 18-cycle delay even when flux-jumping is not enabled to maintain uniformity across all eight channels, because flux-jumping is enabled/disabled on a per-channel basis. In other words, if I hadn't enforced the 18-cycle delay, some channels could have their feedback applied after 7 cycles, while others could have it applied after 18 cycles. I wasn't a fan of this non-uniformity. I realize that 18 cycles is a long time. In fact, so is 7. In the last few months, we have been discussing how to reduce these times to 1 cycle, because every experiment out there wants to multiplex as fast as possible, and the 7/18-delay is a rate limiting step.
** The flux-jumping code was re-arranged in the flux-jumping block to reflect the flow of data through the pipeline and make it easier to understand.

* '''Details:'''

* '''Bugs:'''
** flux-jump does not work when jumping to negative values.

* '''FPGA Resource Usage''' (readout_card.fit.rpt): [[rc_5.0.b_fit_rpt]]
; Total logic elements ; 26,745 / 41,250 ( 65 % ) ;
; Total pins ; 358 / 616 ( 58 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;
; DSP block 9-bit elements ; 76 / 112 ( 68 % ) ;
; Total PLLs ; 1 / 6 ( 17 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;
* '''FPGA Timing Analysis''' (readout_card.tan.rpt): [[rc_5.0.b_tan_rpt]]
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.459 ns
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.895 ns
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 15.956 ns

= Revision 5.0.a =
* '''Filename:'''
** rc_v0500000a_12mar2010.sof

* '''Features:'''
** Based on the merger of rev. 5.0.8 and 5.0.9.
** '''integral_clamp''' command is added where a clamp value is set for the integral term and once the integral term hits that value, the integral-term is clamped to that value and p-term and d-term are clamped to zero. When integral_term=0 then no clamping is in effect, similar to previous releases of firmware.
** The low pass filter has 20-bit input and f_3dB/f_samp = 122Hz/15kHz .
** The flux-jump clamping that was removed in 5.0.9 is included once again here, as we decided this is safer for now.

* '''Details:'''
** "lock_dat_left" parameter that was removed in 5.0.9 is now implemented as "lock_dat_lsb"

* '''Bugs:'''
** flx_lp_init does not reinitialize the flux-jump block

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis
** tag name: rc_v0500000a_12mar2009! years were mixed up!

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
* '''FPGA Timing Analysis''' (readout_card.tan.rpt):

== Revision 5.0.9 (buggy) ==
* '''Filename:'''
** rc_v05000009_13nov2009.sof

* '''Features:'''
** Based on rev. 5.0.4
** Removes a sticky bit in pid calculation result storage -- in fsfb_processor.
** Adds a command to clamp the growth of the I-term to prevent wrapping and track down the source of Caltech's FSFB jumps.
** Removed the unused lock_dat_left parameter. The ability to shift left was moved to the fsfb_corr block some time ago.
** Fixed a sign extension bug acting on the flux quanta, which limited the value to 8191. Changed the extension from signed to unsigned.
** Removed ineffective clamping in the flux-jump calculation block.
** IMPORTANT: Must be used in conjunction with firmware rev. 5.0.0+ of all other cards.

* '''Details:'''

* '''Bugs:'''
** integral_clamp read/write command does not work.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 27,960 / 41,250 ( 68 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.825 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.878 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 14.397 ns ;

== Revision 5.0.8 (UBC only) ==
* '''Filename:'''
** rc_v05000008_09oct2009.sof

* '''Features:'''
** Based on rev. 5.0.4
** type 1 low-pass filter: f3dB=122Hz for fsample=15kHz
** Filter-input-width changed from 18b to 20b with no sticky bits!
** removed sticky bits in internal arithmetic of the filter.

= Revision 5.0.7 (type-2 filter) =
* '''Filename:'''
** rc_v05000007_09oct2009.sof

* '''Features:'''
** Based on rev. 5.0.4
** type-2 low-pass-filter: f3dB=75Hz for fsample=30000.
** Filter-input-width changed from 18b to 20b with no sticky bits!
** inter-biquad-gain-scaling for the filter is 2^14
** filter results are scaled down by 2^3 in the output of the filter.
** removed sticky bits in internal arithmetics
** _correction_ disabled in fsfb_proc_pidz

* '''Details:'''
** quartus.ini file was '''not''' present in synth directory.

* '''Bugs:'''
** none to report

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
== Revision 5.0.6 (UBC only) ==
* '''Filename:'''
** rc_stratix3_v05000006_15sep2009.sof

* '''Features:'''
** Only Valid for Rev. C/D Cards
** Based on rev. 5.0.3
** tcl file updated for Rev. D and aligned with top-level and qsf (project file).
** flux loop commented, just to try sampling the ADC.
** compiled with Q9.1

== Revision 5.0.5 (UBC only) ==
* '''Filename:'''
** rc_v05000005_04sep2009.sof

* '''Features:'''
** Based on rev. 5.0.2
** changed the low-pass-filter to f(3db)=75Hz for f(sample)=30000.

* '''Details:'''
** quartus.ini file was '''not''' present in synth directory.

* '''Bugs:'''
** negative inputs to the filter cause filter to have a non-flat pass-band region. may have to do with sign-handling...

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
* '''FPGA Timing Analysis''' (readout_card.tan.rpt):

= Revision 5.0.4 =
* '''Filename:'''
** rc_v05000004_28aug2009.sof

* '''Features:'''
** Based on rev. 5.0.2
** BUG Fix: handles 14-bit flux quanta (changed the multiplier to unsigned)
** BUG Fix: changed standard logic vector extension from signed to unsigned in flux-jumping slave.
** IMPORTANT: Must be used in conjunction with firmware rev. 5.0.0+ of all other cards.

* '''Details:'''

* '''Bugs:'''
** None so far.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,170 / 41,250 ( 63 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.541 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.612 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 15.398 ns ;

= Revision 5.0.3 =
* '''Filename:'''
** rc_stratix3_v05000003_21aug2009.sof

* '''Features:'''
** ONLY valid REV C/D RC Cards
** Based on rev. 5.0.2
** flux loop commented, just to try sampling the ADC.
** updated tcl file, but still need to rely on project file as well as qsf file.
** changed default level of adc_sclk to '1'
** dac_clr_n was changed from an output to an input.
** added 'locked' interface to rc_pll_stratix_iii
** renamed the adc_pll clock signals to more explanitory names
** added the FPGA_DEVICE_FAMILY generic to the dispatch interace for synthesis of the dc_fifo in lvds_rx
** uncommented DDR interface to force the syntesizer to use correct left and right PLLs (in conjunction with ADC and DDR PLLs)
** added test signals to test_status to see clocks on the scope.
== Revision 5.0.2 (buggy) ==
* '''Filename:'''
** rc_v05000002_test00_tagged.sof

* '''Features:'''
** Based on rev. 5.0.1
** Fixed a bug in wbs_frame_data that stored data incorrectly if reporting 1 or 2 pixels only.
** IMPORTANT: Must be used in conjunction with firmware rev. 5.0.0+ of all other cards.

* '''Details:'''

* '''Bugs:'''
** None so far.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,186 / 41,250 ( 63 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.755 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.979 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.067 ns ;

== Revision 5.0.1 (buggy) (Filter + Raw + Rectangle, 2 LVDS) ==
* '''Filename:'''
** rc_v05000001_26may2009.sof

* '''Features:'''
** Combines features in rev. 5.0.0 (2 LVDS Lines) and rev. 4.0.e (Filtered + Raw), with the NEW rectangle mode.
** IMPORTANT: Must be used in conjunction with firmware rev. 5.0.0+ of all other cards.

* '''Details:'''
** [[CVS Diff Between sys_v05000000 and rc_v05000001]]

* '''Bugs:'''
** Has a bug in wbs_frame_data that stored data incorrectly if reporting 1 or 2 pixels only.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,565 / 41,250 ( 64 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.656 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.861 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 14.167 ns ;

== Revision 5.0.0 (Filter Only, 2 LVDS) ==
* '''Filename:'''
** rc_v05000000_22dec2008.sof (tagged as sys_v05000000_22dec2008)

* '''Features:'''
** IMPORTANT: Must be used in conjunction with firmware v05000000+ of all other cards!!!
** Adds the ability to read out one column of data continuously from readout cards
** Adds data mode 11, which is an engineering mode. Data points are 32-bits, and bits [9..3]=row_index, [2..0]=column_index. This mode is useful for determining which pixels one is reading out in the array, in column mode for example.

* '''Details:'''
** [[CVS Diff Between rc_v0400000c and sys_v05000000]]

* '''Bugs:'''
** None so far.

* '''Synthesis Notes:'''
** The quartus.ini file was not present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,607 / 41,250 ( 65 % ) ;
; Total memory bits ; 406,016 / 3,423,744 ( 12 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.558 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.892 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.987 ns ;

== Revision 4.0.f (Filter + Raw, 1 LVDS) ==
* '''Filename:'''
** rc_v0400000f_12feb2010.sof

* '''Features:'''
** Based on 4.0.e and in parallel with 5.0.9 (equivalent version, clamping is not included)
** Incorporates fixes that were done to flux-jumping between 5.0.2 - 5.0.4 - 5.0.9. Namely:
*** Changes a multiplier from signed to unsigned (in fsfb_corr_multplier.vhd).
*** Changes sign extension from signed to unsigned (in flux_quanta_ram_admin.vhd).

* '''Details:'''

* '''Bugs:'''
** None reported yet.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,773 / 41,250 ( 65 % ) ;
; Total memory bits ; 1,321,984 / 3,423,744 ( 39 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.539 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 4.118 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 17.318 ns ;

== Revision 4.0.e (Filter + Raw, 1 LVDS) ==
* '''Filename:'''
** rc_v0400000e_27apr2009.sof

* '''Features:'''
** Based on 4.0.d
** Combines both raw- and filtered-data modes.
** fpga_temp, card_temp, card_id commands are disabled.
** Tested by Matt Hasselfield.

* '''Details:'''

* '''Bugs:'''
** fpga_temp, card_temp, card_id commands are disabled.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 27,048 / 41,250 ( 66 % ) ;
; Total memory bits ; 1,321,984 / 3,423,744 ( 39 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.675 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.907 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.728 ns ;

== Revision 4.0.d (Raw Only, 1 LVDS) ==
* '''Filename:''' rc_v0400000d_20090417.sof

* '''Features:'''
** Based on v4.0.c, but has the filter removed, and implements a single 65536-index RAM block for storing 50 MHz raw-data samples.
** The firmware takes a new command called readout_col_index which specifies which column to capture raw data from.
** Other than readout_col_index, the firmware functions the same as previous raw-data firmware, including then need to issue a capture_raw command.
** For more information on raw-data, see: http://e-mode.phas.ubc.ca/mcewiki/index.php/Raw-mode_readout
** This firmware also integrates some of the improvements that were implemented in 4.4.0, like the removal of the tga_o signal from an FSM in dispatch_wishbone.vhd.

* '''Details:'''
** Differences between 4.0.c and 4.0.d
U system/test/source/tb/tb_cc_rcs_bcs_ac.vhd
U all_cards/dispatch/source/rtl/dispatch_wishbone.vhd
U library/sys_param/source/rtl/wishbone_pack.vhd
U readout_card/adc_sample_coadd/source/rtl/adc_sample_coadd.vhd
U readout_card/adc_sample_coadd/source/rtl/adc_sample_coadd_pack.vhd
U readout_card/flux_loop/source/rtl/flux_loop.vhd
U readout_card/flux_loop/source/rtl/flux_loop_pack.vhd
U readout_card/flux_loop_ctrl/source/rtl/flux_loop_ctrl.vhd
U readout_card/flux_loop_ctrl/source/rtl/flux_loop_ctrl_pack.vhd
U readout_card/flux_loop_ctrl/source/tb/tb1_flux_loop_ctrl.vhd
U readout_card/flux_loop_ctrl/source/tb/tb2_flux_loop_ctrl.vhd
U readout_card/fsfb_calc/source/rtl/fsfb_fltr_regs.vhd
U readout_card/fsfb_corr/source/rtl/fsfb_corr.vhd
U readout_card/readout_card/source/rtl/readout_card.vhd
U readout_card/readout_card/source/rtl/readout_card_pack.vhd
U readout_card/wbs_frame_data/source/rtl/wbs_frame_data.vhd
U readout_card/wbs_frame_data/source/rtl/wbs_frame_data_pack.vhd

* '''Bugs:'''
** None so far.
** fpga_temp, card_temp, card_id commands are not supported.

* '''Synthesis Notes:'''
** The quartus.ini file was present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 24,554 / 41,250 ( 60 % ) ;
; Total memory bits ; 1,262,592 / 3,423,744 ( 37 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.991 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.864 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 17.052 ns ;

== Revision 4.4.1 ==
* '''Filename:''' rc_v04040001_21nov2008

* '''Features:'''
** Fixes a bug that froze up the firmware if any of the following commands were issued: CARD_ID_ADDR, CARD_TEMP_ADDR, FPGA_TEMP_ADDR in 4.4.0 only.

* '''Details:'''
** The bug fix include adding more logic to the wishbone ack path (readout_card.vhd), which subsequently decreased the minimum clock setup time to 1.588ns. The new logic will catch errors that the old logic wouldn't have, and is now consistent with the firmware on all the other cards. However, if timing becomes an issue, the logic may have to revert back to that which was in version 4.0.c.

* '''Bugs:'''
** None so far.

* '''Synthesis Notes:'''
** The quartus.ini file was not present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 27,241 / 41,250 ( 66 % ) ;
; Total memory bits ; 405,504 / 3,423,744 ( 12 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.588 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.585 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 17.057 ns ;

== Revision 4.4.0 (buggy) ==
* '''Filename:''' rc_v04040000_02oct2008
* '''Features:'''
** Reinstated the data modes in wbs_frame_data.vhd that were removed in 4.0.c. This firmware has the following modes: '''0, 1, 2, 4, 5, 7, 10'''. The modes that are not present are: '''3''' (raw data), '''6''' (replaced by data_mode = 7), '''8''' (replaced by data_mode = 10), '''9''' (replaced by data_mode = 10). For more information on data modes, see [[Data mode]].
** Re-integrated the id_thermo and fpga_thermo block in the readout_card.vhd top level that was removed in 4.0.c.
** Removed the sticky bit in fsfb_corr.vhd, which was enabled when flux-jumping was turned on. Because the feedback is signed, the sticky bit would usually reflect the value of the 14th bit, except in situations when the number of flux quanta to jump was greater than 1 (i.e. cosmic rays, IV-curves, etc). Flux jumps are made at a maximum rate of one per frame period, so that if the First-Stage Feedback increased past the 13th bit, it would not be reflected in the feedback applied. Now it is.
* '''Details:'''
** Simplified the FSM logic in wbs_frame_data.vhd that determines when to transition from IDLE to WSS1. This was done to lower the number of gates in that path, and ease the timing.
** Removed the z_dat_i port in fsfb_processor.vhd and fsfb_calc_pack.vhd to the fsfb_proc_pidz block, in an effort to make it clearer within that block that the z-term is always = 0.
** Removed the z-term sign extension in fsfb_proc_pidz.vhd, and the [d-term + z-term] adder to free up DSP resources since the z-term is always = 0.
** Adjusted the indentation in fsfb_io_controller.vhd to make the file more readable.
** Moved the tga_o signal out of the dispatch_wishbone.vhd FSM, and made it a continuous assignment. This signal had one of the highest fan-out counts in the RTL design, and actually was impossible to route in Stratix III chips in its previous configuration because of the number of gates on the fan-out. As a consequence of making it a continuous assignment, the Stratix III fitter was able to succeed, and the Stratix I timing characteristics were greatly improved. This is the most significant change in this revision. This change single-handedly increased the minimum slack from 1.282 ns in v0400000c to 2.372 ns (or 56.7 MHz max) in this revision.
* '''Bugs:'''
** The following commands lock up the Readout Card firmware: CARD_ID_ADDR, CARD_TEMP_ADDR, FPGA_TEMP_ADDR.
** fb_const0 commands to channel 0 do not work. The value is stored in the register, but not applied to the DAC. Thus, read-back returns the correct value, but the DAC does not
* '''Synthesis Notes:'''
** The quartus.ini file was not present in the synth directory during synthesis.
* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 27,099 / 41,250 ( 66 % ) ;
; Total memory bits ; 406,016 / 3,423,744 ( 12 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.372 ns ;
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 4.052 ns ;
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.066 ns ;

== Revision 4.0.c ==
* '''Filename:''' rc_v0400000c_15aug2008.sof
* '''Features:'''
** Only has data modes 0, 1, 4, and 10.
** Fixed the bug that exists in 4.0.b, 4.0.a, and 4.0.9 that prevented the fb_const value from being applied to channel zero (wbs_fb_data.vhd).
* '''Details:'''
** Changed a counter in the dispatch block to ease timing constraints in synthesis (dispatch_wishbone.vhd)
** Updated the tagged versions of dispatch.vhd , dispatch_cmd_receive.vhd, and dispatch_reply_transmit.vhd to the version that is used by all the other cards.
** '''Removed''' the fpga_termo (command: '''fpga_temp''') and id_thermo (commands: '''card_temp, card_id''') to ease timing constraints in synthesis (readout_card.vhd)
** Updated the tagged version of fpga_termo.vhd to include the new 'stale bit' feature
** Updated the tagged version of frame_timing_core.vhd to include the new 'err_o' interface
* '''Bugs:'''
** None reported yet
* '''Synthesis Notes:'''
** The quartus.ini file was not present in the synth directory during synthesis.
* '''FPGA Resource Usage:'''
Total logic elements : 25,058 / 41,250 ( 61 % )
Total memory bits : 400,896 / 3,423,744 ( 12 % )

* '''Timing Analysis''' (readout_card.tan.rpt):
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.282 ns ;
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.736 ns ;
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.665 ns ;

== Revision 4.0.b (buggy) ==
Note: This revision is on a watch list, after the bug detected 15 July 2008. See the bug section for more details.
* '''Filename''' : rc_v0400000b_04aug2008.sof
* '''Features'''
** data_mode 10 is added to provide more filtfb bits (compared to data mode 9) for planet observations. filtered_dat(27 downto 3) & flux_cnt_dat(6 downto 0)

* '''Bugs'''
** An unexplained bug that appeared in 4.0.a and may still be present in 4.0.b is a problem with the readout of channels being clipped out of data reporting. [[Bug 1 Notes]]

* ''' Synthesis note '''
** Quartus.ini removed.

== Revision 4.0.a (buggy) ==
Note: This revision is on a watch list, after the bug detected 15 July 2008. See the bug section for more details.
* '''Filename''' : rc_v0400000a_07jul2008.sof
* '''Bug Fix'''
** mce_status and adc_offset/flx_quanta commands do not fail after power up.
* ''' Synthesis note '''
** Quartus.ini removed.

* '''Bugs'''
** Seems to clip out channel 0 from data reporting.

== Revision 4.0.9 (buggy) ==
* '''Filename''' : rc_v04000009_26jun2008.sof
* '''Features'''
** sa_bias and offset DACs only refreshed when new values are written. (in previous versions, DACs were refreshed every frame)
* '''Bugs'''
** fb_const0 commands to channel 0 do not work. The value is stored in the register, but not applied to the DAC. Thus, read-back returns the correct value, but the DAC does not.
** reading flx_quanta and adc_offset right after power up hangs the reply datapath to CC. resetmce clears this error as temporary solution. the problem is caused by first read ack of the wishbone slave.

== Revision 4.0.8 ==
* '''Filename''' : rc_v04000008_26jun2008.sof
* '''Features'''
** The gaini, gainp, gaind resolution increased to 12-bit, i.e. -2048 to 2047 (formerly 10-bit).

* '''Bug fix'''
** the bug associated with gainpid read before mce_reset is fixed.

* ''' Synthesis note '''
** Quartus.ini removed.

== Revision 4.3.7 ==
* '''Filename''' : rc_v04030007_26may2008_raw.sof
* '''Features'''
** 14-bit raw mode enabled to buffer a snapshot of 50MHz samples for 2 frames of row_len * num_rows samples.
** In order to extend the raw-mode to 14-bit, an assumption is made that the raw buffer is not written to while being read. Therefore, make sure there is at least 2*row_len*num_rows*20ns between issuing captr_raw command and reading back the raw data.
** In order to save RAM for raw mode, two memory-intensive features are disabled:
*** low-pass filter disabled ( mixed filtfb data modes 6, 7, 9 are also disabled)
*** PID (gainp0, gaini0, gaind0) readback disabled. one can still set PID values and run servo, but can not read back the values.

== Revision 4.2.7 ==
* '''Filename''' : rc_v04020007_24may2008_raw.sof
* '''Features'''
** raw mode enabled to buffer a snapshot of 50MHz samples for 2 frames of row_len * num_rows samples.
** In order to save RAM for raw mode, two memory-intensive features are disabled:
*** low-pass filter disabled ( mixed filtfb data modes 6, 7, 9 are also disabled)
*** PID (gainp0, gaini0, gaind0) readback disabled. one can still set PID values and run servo, but can not read back the values.
* '''Bug fix'''
** the bug associated with reading from raw-buffer is fixed.

== Revision 4.1.7 ==
* '''Filename''' : rc_v04010007_25apr2008_raw.sof
* '''Features'''
** raw mode enabled to buffer a snapshot of 50MHz samples for 2 frames of row_len * num_rows samples.
** In order to save RAM for raw mode, two memory-intensive features are disabled:
*** low-pass filter disabled ( mixed filtfb data modes 6, 7, 9 are also disabled)
*** PID (gainp0, gaini0, gaind0) readback disabled. one can still set PID values and run servo, but can not read back the values.
* '''Bugs'''
** after each readout frame, raw-buffer readout counter falls behind by 3 and this causes skipping 3 50MHz samples in the data stream and column-data being messed up in subsequent frames. Data can be rearranged by post processing.

== Revision 4.0.6 (buggy) ==
* '''Filename''' : rc_v04000006_15feb2008.sof or .pof
* '''Features'''
** '''bugfix''': unreliable reset due to unsafe and incomplete state machines is fixed.
** '''bugfix''': flux_jump sign problem fixed, so far proved in const_mode, to be tested in servo_mode with cold setup.
** servo_mode=2 or ramp previously only went from 0 to ramp_amp, but now goes from -8192 to -8192+ramp_amp
** new commands are added: ''scratch'' and ''card_type''. Scratch takes 8 values and can be used by software to detect reset.
** slot_id and fw_rev are now integrated as part of all_cards.vhd
** lvds_tx_b=0, This will allow Clock Card to use the secondary backplane lvds line and check whether RC is plugged in.
** filter_coeff in misc_banks_admin commented as it is not implemented and causes timing problems.

* '''Bugs'''
** reading gainp/gaini/gaind right after power up hangs the reply datapath to CC. resetmce clears this error as temporary solution. the problem is caused by first read ack of pid_ram_admin.
** slot_id is only set after a resetmce is issued. (using the latest all_cards in the next revision will fix this)
** has spurious spikes on channel 7 data, which max out the integral, and cause the detectors to come unlocked. This firmware officially meets timing requirements, but the bug could be due to marginal timing on the longest data paths, i.e. ~0.1 ns in some cases.

== Revision 4.0.5 ==
* '''Filename''' : rc_v04000005_01nov2007.sof or .pof
* '''Features'''
** data mode 9 (mixed filt + flux jump) with windowing readjusted compared to data mode 8

* '''Bugs'''
** unreliable resetmce. Sometimes, firmware waked up non-responsive on lvds lines.
** In data mode 5 and 9, flux-jump counter is not reported properly due to a sign error. However, flux jumping works fine.

== Revision 3.0.19 ==
* '''Filename''' : rc_v03000019_16feb2007_raw.sof (no pof as one is not likely to run with this as regular firmware)
* '''Features'''
** data mode 3 is enabled.
** filter is disabled as a compromise to fit the raw-mode buffer.

* '''Bugs'''
** unreliable resetmce. Sometimes, firmware waked up non-responsive on lvds lines.

== Old Firmware Revisions ==
* '''4.0.4''': rc_v04000004_11oct2007.sof data mode 8 added (mixed filt + flux jump)
* '''4.0.3''': rc_v04000003_19sep2007.sof data mode 7 bit split readjusted to 10b error being bit 4 to 14
* '''4.0.2''': rc_v04000002_11sep2007.sof pid resolution increased to 10b, data mode 7 added
* '''4.0.1''': rc_v04000001_06sep2007.sof
* '''4.0.0''': rc_v04000000_29aug2007.sof supports readout_row_index * [[ bugs ]]

= To-Do List =
* the starting point for the servo is currently zero and it would be nice to have it programmable.

= RC Synthesis Notes =
# The following note applies when using Quartus versions earlier than Q7: Quartus.ini file had to exist in synth directory up to revision 4.0.a due to a bug that started in Quartus 6.1 and would synthesize away arbitrary parts of readout card. We contacted Altera at the time and they provided us the ini file.
# Timing: There is no "lock region" defined for readout card. Timing on readout card is tight and since version 3 or so any new feature would initially fail timing till some synthesis options were tweaked. One path that remains to be consistently marginal is from addr_gen counter (i.e. tga_o counter) in dispatch_wishbone.vhd to wishbone slaves particularly misc_banks_admin.vhd. Modules that are rewritten to address timing concerns are fsfb_corr, all_cards, misc_banks_admin, and finally instantiating an lpm counter instead of a counter from components library. Surprisingly, the lpm counter reduced 87 failures to 37, although looking at the technology map viewer, it seemed that they were both synthesized the same.
# Compile time: This was at some point 4.5 hours, after going to dual core PC, this was reduced to 35 minutes. After extending pid gains to 12b and fixing offset/sa_bias update code, the compile time increased to 1.5hr again with utilization up to ~70%.
# wbs_fb_storage, ram_8x64, pid_ram had to be regenerated using latest (Q7.2) MegaWizard to get rid of the bug associated with failure to read after power up until a reset was issued.
# During simulations, the initialization of RAM block with .hex files needs to be disabled. This is done by commenting out the following lines from the MegaWizard generated Megafunction files (remember to un-comment them before synthesizing the code):
lpm_file => "C:/scuba2_repository/cards/readout_card/fsfb_calc/source/rtl/ram_40x64.hex", and
lpm_file : STRING;
#Starting Q10.0 use TimeQuest timing analyzer as oppose to the classic one. The classic one is being phased out by Altera. In order to use TimeQuest, you need to have an sdc file present in your project directory.
----
[http://e-mode.phas.ubc.ca/mcewiki/index.php/Main_Page MCE Main Page]

Readout Card firmware

2011-05-04T21:52:30Z

Bburger: /* Revision 5.0.d */

* Synthesis Reminders (for firmware developers)
** quartus.ini is not needed anymore (Fixed as of Q7, Altera SR10783580 2010-10-24)
** Remember that readout_card/fsfb_clac/source/rtl/ram_40x64.vhd must be initialized with the ram_40x64.hex file in the same directory.
= Revision 5.1.2 =
* '''Filename:'''
** rc_stratix3_v05010002_18jan2011.sof (for Rev. E cards)
** rc_stratix3_v05010002_18jan2011.jic (for Rev. E cards)
** rc_v05010002_03feb2011.sof (for Rev. B cards)
** rc_v05010002_03feb2011.pof (for Rev. B cards)

* '''Features:'''
** based on 5.1.1 with k1 and k2 (filter params) limited to k1<16 and k2<32 in order to resolve the timing when compiling for smaller Stratix FPGA on RC Rev. B.

* '''Bug fix:'''
** the 2-rows-off filtered data readout introduced with configurable filter in rev. 5.1.0 and 5.1.1 is fixed now.

* '''Bugs:'''
** none so far.

* '''FPGA Resource Usage''' (readout_card.fit.rpt)
; Total logic elements ; 33,285 / 41,250 ( 81 % ) ;
; Total pins ; 358 / 616 ( 58 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt)
; Fast Model Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 6.591 ns
; Fast Model Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 7.206 ns
; Fast Model Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 18.299 ns

== Revision 5.1.1 (not recommended) ==
* '''Filename:'''
** rc_v05010001_01dec2010.sof (for Rev. B cards)

* '''Features:'''
** based on 5.1.0, but k1 and k2 (filter params) are now limited to k1<16 and k2<32 in order to resolve the timing failures of compiling 5.1.0 for smaller Stratix FPGA on RC Rev. B.

* '''Bugs:'''
** filter mode data is off by 2 rows.

== Revision 5.1.0 (not recommended) ==
* '''Filename:'''
** rc_stratix3_v05010000_01nov2010.sof (for Rev. E cards)
** rc_v05010000_01nov2010.sof (for Rev. B cards) has timing failures '''do not use!!!'''

* '''Features:'''
** added configurable filter parameters specified by ''fltr_coeff'', default is the fcutoff/fsampl=122Hz/15kHz. see [[ Digital 4-pole Butterworth Low-pass filter ]].
** ''fltr_type'' is set to 255 to indicate configurable filter parameters.
** see [http://www.phas.ubc.ca/~mce/mcedocs/software/SC2_ELE_S580_515_mce_command_description.pdf MCE command description]
** development notes:
*** It is built on Quartus10.1.
*** tcl files had to be updated as cmp syntax is not supported in Q10 anymore.
*** Rev. E cards now can be identified by reading back pcb_rev as part of card_type, therefore both stratix I and III sof/pof/jic are generated from the same source.

* '''Bugs:'''
** rc_v05010000_01nov2010.sof has timing failures that were overlooked, do not use this firmware for Rev.B cards.
** '''filter mode data is off by 2 rows.'''

* '''FPGA Resource Usage and Timing Report''' (readout_card.fit.rpt and readout_card.tan.rpt): logic usage is upto 85% from 66% in 5.0.d/e/f

= Revision 5.0.f =
* '''Filename:'''
** rc_v0500000f_22oct2010.sof (for Rev. B cards)
** rc_stratix3_v0500000f_22oct2010.sof (for Rev. E cards)

* '''Features:'''
** Bugfix: integral clamp should work now. only positive integral_clamp values are valid!

* '''Details:''':
** SQ1FB is applied 18 clock cycles after start of a row visit (SQ1_Bias being applied) regardless of flux-jump being enabled or not. In pre-5.0.b firmware SQ1FB was being applied after 7 clock cycles when flux-jump was disabled and after 18 clock cycles when flux-jump was enabled.
** available for both Rev. E and Rev. B cards, the upper byte of card_type parameter now reports the pcb revision.
** development note: It is built on Quartus10.1.

* '''Bugs:'''
**none yet!

* '''FPGA Resource Usage and Timing Report''' (readout_card.fit.rpt and readout_card.tan.rpt): no change compared to 5.0.a/b/c/d

== Revision 5.0.e (not recommended) ==
* '''Filename:'''
** rc_v0500000e_06oct2010.sof

* '''Details:'''
** an unsuccessful attempt to fix integral_clamp, but changed the functionality so that it clamps at the value, but it doesn't hold the clamp. i.e., if the calculated sq1fb becomes less than the specified clamp value, the sq1fb is not clamped anymore. This is not a desired functionality!

== Revision 5.0.d (not recommended) ==
* '''Filename:'''
** rc_v0500000d_04aug2010.sof

* '''Features:'''
** Bugfix: To fix the bug associated with negative flux-jumps, reverted to signed multiplier and hence, incremented the width of the flux-quanta multiplier input by 1.

* '''Details:''': SQ1FB is applied 18 clock cycles after start of a row visit (SQ1_Bias being applied) regardless of flux-jump being enabled or not. In pre-5.0.b firmware SQ1FB was being applied after 7 clock cycles when flux-jump was disabled and after 18 clock cycles when flux-jump was enabled.

* '''Bugs:'''
** '''integral_clamping is broken'''. To test the clamping, a servo-locked ramp was initiated on the sq1fb and then flux-jumping was turned on and observed by attaching a scope to the SQ1FB output. With integral_clamp=80000000, flux_quanta=8000, gaini=1, flux-jump enabled, we see [[http://e-mode.phas.ubc.ca/mcewiki/index.php/Image:Clamp_unstable.png scope snapshot]] used slow_fb_ramp.py script for testing.

* '''FPGA Resource Usage and Timing Report''' (readout_card.fit.rpt and readout_card.tan.rpt): no change compared to 5.0.a/b/c

== Revision 5.0.c (not recommended) ==
* '''Filename:'''
** rc_v0500000c_16jun2010.sof

* '''Features:'''
** Based on rev. 5.0.b
** Re-introduced flux-jump counter clamping to maintain continuity in behavior from past versions of firmware in the field.
** '''Important''': SQ1FB is applied 18 clock cycles after start of a row visit (SQ1_Bias being applied) regardless of flux-jump being enabled or not. In pre-5.0.b firmware SQ1FB was being applied after 7 clock cycles when flux-jump was disabled and after 18 clock cycles when flux-jump was enabled.

* '''Details:'''
* '''Bugs:'''
** '''flux-jump is broken'''. flux-jumping block misbehaves at the first jump in the negative range.

* '''FPGA Resource Usage''' (readout_card.fit.rpt): [[rc_5.0.c_fit_rpt]]
; Total logic elements ; 26,800 / 41,250 ( 65 % ) ;
; Total pins ; 358 / 616 ( 58 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;
; DSP block 9-bit elements ; 76 / 112 ( 68 % ) ;
; Total PLLs ; 1 / 6 ( 17 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt): [[rc_5.0.c_tan_rpt]]
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.964 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 4.382 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 15.924 ns ;

== Revision 5.0.b (not recommended) ==
* '''Filename:'''
** rc_v0500000b_03jun2010.sof

* '''Features:'''
** Based on rev. 5.0.a
** A bug that caused jumps in first-stage feedback, and detected as spikes in the raw data of pixels that were in servo_mode=0,1,2 was fixed. The jumps in FSFB were due to flux-jumping being enabled on live pixes with non-zero flx_quanta, and being disabled on the fly on dead pixels with flx_quanta=0. Flux-jumping is now disabled on a column-by-column basis if a column is in servo_mode = 0,1,2.
** Ineffective clamping was removed from the flux-jumping block (as per 5.0.9), as it is now replaced by the clamping that was perfected in rev. 5.0.10
** A sticky bit that only affected servo_mode=0,1,2 was also removed from the flux-jumping block.
** flx_lp_init commands now also clear the flux-jumping block as well.
** The 11-clock-cycle delay (in applying SQ1_FB) that in previous firmware only occurred when flux-jumping was enabled, now (in this version) is in effect all the time. Due to the bug-fix above, flux-jumping can be disabled on a column-by-column basis by setting servo_mode=0,1,2 when en_fb_jump=1. Before the change, this meant that constant values could be applied with or without the 11-cycle delay if en_fb_jump=1 or 0. To make the delay consistent, it is now always 11 cycles. As background, the flux-jumping block is pipelined, meaning that it does calculations for all 8 channels serially. The serialization is because of DSP-block limitations in the Readout Card FPGA that prevent us from doing all 8 channels in parallel. The reason that it takes 11 cycles to complete the flux-jumping calculations is because the values are computed for the eight channels in three ALU stages: 8 + 3 = 11 cycles. Adding 11 cycles to the 7 cycles of latency from other stages in the system results in: 11 + 7 = 18 cycles of latency from the start of a row dwell period before the first-stage feedback is applied. In rc_v5.0.c, I enforce the 18-cycle delay even when flux-jumping is not enabled to maintain uniformity across all eight channels, because flux-jumping is enabled/disabled on a per-channel basis. In other words, if I hadn't enforced the 18-cycle delay, some channels could have their feedback applied after 7 cycles, while others could have it applied after 18 cycles. I wasn't a fan of this non-uniformity. I realize that 18 cycles is a long time. In fact, so is 7. In the last few months, we have been discussing how to reduce these times to 1 cycle, because every experiment out there wants to multiplex as fast as possible, and the 7/18-delay is a rate limiting step.
** The flux-jumping code was re-arranged in the flux-jumping block to reflect the flow of data through the pipeline and make it easier to understand.

* '''Details:'''

* '''Bugs:'''
** flux-jump does not work when jumping to negative values.

* '''FPGA Resource Usage''' (readout_card.fit.rpt): [[rc_5.0.b_fit_rpt]]
; Total logic elements ; 26,745 / 41,250 ( 65 % ) ;
; Total pins ; 358 / 616 ( 58 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;
; DSP block 9-bit elements ; 76 / 112 ( 68 % ) ;
; Total PLLs ; 1 / 6 ( 17 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;
* '''FPGA Timing Analysis''' (readout_card.tan.rpt): [[rc_5.0.b_tan_rpt]]
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.459 ns
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.895 ns
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 15.956 ns

= Revision 5.0.a =
* '''Filename:'''
** rc_v0500000a_12mar2010.sof

* '''Features:'''
** Based on the merger of rev. 5.0.8 and 5.0.9.
** '''integral_clamp''' command is added where a clamp value is set for the integral term and once the integral term hits that value, the integral-term is clamped to that value and p-term and d-term are clamped to zero. When integral_term=0 then no clamping is in effect, similar to previous releases of firmware.
** The low pass filter has 20-bit input and f_3dB/f_samp = 122Hz/15kHz .
** The flux-jump clamping that was removed in 5.0.9 is included once again here, as we decided this is safer for now.

* '''Details:'''
** "lock_dat_left" parameter that was removed in 5.0.9 is now implemented as "lock_dat_lsb"

* '''Bugs:'''
** flx_lp_init does not reinitialize the flux-jump block

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis
** tag name: rc_v0500000a_12mar2009! years were mixed up!

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
* '''FPGA Timing Analysis''' (readout_card.tan.rpt):

== Revision 5.0.9 (buggy) ==
* '''Filename:'''
** rc_v05000009_13nov2009.sof

* '''Features:'''
** Based on rev. 5.0.4
** Removes a sticky bit in pid calculation result storage -- in fsfb_processor.
** Adds a command to clamp the growth of the I-term to prevent wrapping and track down the source of Caltech's FSFB jumps.
** Removed the unused lock_dat_left parameter. The ability to shift left was moved to the fsfb_corr block some time ago.
** Fixed a sign extension bug acting on the flux quanta, which limited the value to 8191. Changed the extension from signed to unsigned.
** Removed ineffective clamping in the flux-jump calculation block.
** IMPORTANT: Must be used in conjunction with firmware rev. 5.0.0+ of all other cards.

* '''Details:'''

* '''Bugs:'''
** integral_clamp read/write command does not work.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 27,960 / 41,250 ( 68 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.825 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.878 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 14.397 ns ;

== Revision 5.0.8 (UBC only) ==
* '''Filename:'''
** rc_v05000008_09oct2009.sof

* '''Features:'''
** Based on rev. 5.0.4
** type 1 low-pass filter: f3dB=122Hz for fsample=15kHz
** Filter-input-width changed from 18b to 20b with no sticky bits!
** removed sticky bits in internal arithmetic of the filter.

= Revision 5.0.7 (type-2 filter) =
* '''Filename:'''
** rc_v05000007_09oct2009.sof

* '''Features:'''
** Based on rev. 5.0.4
** type-2 low-pass-filter: f3dB=75Hz for fsample=30000.
** Filter-input-width changed from 18b to 20b with no sticky bits!
** inter-biquad-gain-scaling for the filter is 2^14
** filter results are scaled down by 2^3 in the output of the filter.
** removed sticky bits in internal arithmetics
** _correction_ disabled in fsfb_proc_pidz

* '''Details:'''
** quartus.ini file was '''not''' present in synth directory.

* '''Bugs:'''
** none to report

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
== Revision 5.0.6 (UBC only) ==
* '''Filename:'''
** rc_stratix3_v05000006_15sep2009.sof

* '''Features:'''
** Only Valid for Rev. C/D Cards
** Based on rev. 5.0.3
** tcl file updated for Rev. D and aligned with top-level and qsf (project file).
** flux loop commented, just to try sampling the ADC.
** compiled with Q9.1

== Revision 5.0.5 (UBC only) ==
* '''Filename:'''
** rc_v05000005_04sep2009.sof

* '''Features:'''
** Based on rev. 5.0.2
** changed the low-pass-filter to f(3db)=75Hz for f(sample)=30000.

* '''Details:'''
** quartus.ini file was '''not''' present in synth directory.

* '''Bugs:'''
** negative inputs to the filter cause filter to have a non-flat pass-band region. may have to do with sign-handling...

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
* '''FPGA Timing Analysis''' (readout_card.tan.rpt):

= Revision 5.0.4 =
* '''Filename:'''
** rc_v05000004_28aug2009.sof

* '''Features:'''
** Based on rev. 5.0.2
** BUG Fix: handles 14-bit flux quanta (changed the multiplier to unsigned)
** BUG Fix: changed standard logic vector extension from signed to unsigned in flux-jumping slave.
** IMPORTANT: Must be used in conjunction with firmware rev. 5.0.0+ of all other cards.

* '''Details:'''

* '''Bugs:'''
** None so far.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,170 / 41,250 ( 63 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.541 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.612 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 15.398 ns ;

= Revision 5.0.3 =
* '''Filename:'''
** rc_stratix3_v05000003_21aug2009.sof

* '''Features:'''
** ONLY valid REV C/D RC Cards
** Based on rev. 5.0.2
** flux loop commented, just to try sampling the ADC.
** updated tcl file, but still need to rely on project file as well as qsf file.
** changed default level of adc_sclk to '1'
** dac_clr_n was changed from an output to an input.
** added 'locked' interface to rc_pll_stratix_iii
** renamed the adc_pll clock signals to more explanitory names
** added the FPGA_DEVICE_FAMILY generic to the dispatch interace for synthesis of the dc_fifo in lvds_rx
** uncommented DDR interface to force the syntesizer to use correct left and right PLLs (in conjunction with ADC and DDR PLLs)
** added test signals to test_status to see clocks on the scope.
== Revision 5.0.2 (buggy) ==
* '''Filename:'''
** rc_v05000002_test00_tagged.sof

* '''Features:'''
** Based on rev. 5.0.1
** Fixed a bug in wbs_frame_data that stored data incorrectly if reporting 1 or 2 pixels only.
** IMPORTANT: Must be used in conjunction with firmware rev. 5.0.0+ of all other cards.

* '''Details:'''

* '''Bugs:'''
** None so far.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,186 / 41,250 ( 63 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.755 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.979 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.067 ns ;

== Revision 5.0.1 (buggy) (Filter + Raw + Rectangle, 2 LVDS) ==
* '''Filename:'''
** rc_v05000001_26may2009.sof

* '''Features:'''
** Combines features in rev. 5.0.0 (2 LVDS Lines) and rev. 4.0.e (Filtered + Raw), with the NEW rectangle mode.
** IMPORTANT: Must be used in conjunction with firmware rev. 5.0.0+ of all other cards.

* '''Details:'''
** [[CVS Diff Between sys_v05000000 and rc_v05000001]]

* '''Bugs:'''
** Has a bug in wbs_frame_data that stored data incorrectly if reporting 1 or 2 pixels only.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,565 / 41,250 ( 64 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.656 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.861 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 14.167 ns ;

== Revision 5.0.0 (Filter Only, 2 LVDS) ==
* '''Filename:'''
** rc_v05000000_22dec2008.sof (tagged as sys_v05000000_22dec2008)

* '''Features:'''
** IMPORTANT: Must be used in conjunction with firmware v05000000+ of all other cards!!!
** Adds the ability to read out one column of data continuously from readout cards
** Adds data mode 11, which is an engineering mode. Data points are 32-bits, and bits [9..3]=row_index, [2..0]=column_index. This mode is useful for determining which pixels one is reading out in the array, in column mode for example.

* '''Details:'''
** [[CVS Diff Between rc_v0400000c and sys_v05000000]]

* '''Bugs:'''
** None so far.

* '''Synthesis Notes:'''
** The quartus.ini file was not present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,607 / 41,250 ( 65 % ) ;
; Total memory bits ; 406,016 / 3,423,744 ( 12 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.558 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.892 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.987 ns ;

== Revision 4.0.f (Filter + Raw, 1 LVDS) ==
* '''Filename:'''
** rc_v0400000f_12feb2010.sof

* '''Features:'''
** Based on 4.0.e and in parallel with 5.0.9 (equivalent version, clamping is not included)
** Incorporates fixes that were done to flux-jumping between 5.0.2 - 5.0.4 - 5.0.9. Namely:
*** Changes a multiplier from signed to unsigned (in fsfb_corr_multplier.vhd).
*** Changes sign extension from signed to unsigned (in flux_quanta_ram_admin.vhd).

* '''Details:'''

* '''Bugs:'''
** None reported yet.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,773 / 41,250 ( 65 % ) ;
; Total memory bits ; 1,321,984 / 3,423,744 ( 39 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.539 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 4.118 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 17.318 ns ;

== Revision 4.0.e (Filter + Raw, 1 LVDS) ==
* '''Filename:'''
** rc_v0400000e_27apr2009.sof

* '''Features:'''
** Based on 4.0.d
** Combines both raw- and filtered-data modes.
** fpga_temp, card_temp, card_id commands are disabled.
** Tested by Matt Hasselfield.

* '''Details:'''

* '''Bugs:'''
** fpga_temp, card_temp, card_id commands are disabled.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 27,048 / 41,250 ( 66 % ) ;
; Total memory bits ; 1,321,984 / 3,423,744 ( 39 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.675 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.907 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.728 ns ;

== Revision 4.0.d (Raw Only, 1 LVDS) ==
* '''Filename:''' rc_v0400000d_20090417.sof

* '''Features:'''
** Based on v4.0.c, but has the filter removed, and implements a single 65536-index RAM block for storing 50 MHz raw-data samples.
** The firmware takes a new command called readout_col_index which specifies which column to capture raw data from.
** Other than readout_col_index, the firmware functions the same as previous raw-data firmware, including then need to issue a capture_raw command.
** For more information on raw-data, see: http://e-mode.phas.ubc.ca/mcewiki/index.php/Raw-mode_readout
** This firmware also integrates some of the improvements that were implemented in 4.4.0, like the removal of the tga_o signal from an FSM in dispatch_wishbone.vhd.

* '''Details:'''
** Differences between 4.0.c and 4.0.d
U system/test/source/tb/tb_cc_rcs_bcs_ac.vhd
U all_cards/dispatch/source/rtl/dispatch_wishbone.vhd
U library/sys_param/source/rtl/wishbone_pack.vhd
U readout_card/adc_sample_coadd/source/rtl/adc_sample_coadd.vhd
U readout_card/adc_sample_coadd/source/rtl/adc_sample_coadd_pack.vhd
U readout_card/flux_loop/source/rtl/flux_loop.vhd
U readout_card/flux_loop/source/rtl/flux_loop_pack.vhd
U readout_card/flux_loop_ctrl/source/rtl/flux_loop_ctrl.vhd
U readout_card/flux_loop_ctrl/source/rtl/flux_loop_ctrl_pack.vhd
U readout_card/flux_loop_ctrl/source/tb/tb1_flux_loop_ctrl.vhd
U readout_card/flux_loop_ctrl/source/tb/tb2_flux_loop_ctrl.vhd
U readout_card/fsfb_calc/source/rtl/fsfb_fltr_regs.vhd
U readout_card/fsfb_corr/source/rtl/fsfb_corr.vhd
U readout_card/readout_card/source/rtl/readout_card.vhd
U readout_card/readout_card/source/rtl/readout_card_pack.vhd
U readout_card/wbs_frame_data/source/rtl/wbs_frame_data.vhd
U readout_card/wbs_frame_data/source/rtl/wbs_frame_data_pack.vhd

* '''Bugs:'''
** None so far.
** fpga_temp, card_temp, card_id commands are not supported.

* '''Synthesis Notes:'''
** The quartus.ini file was present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 24,554 / 41,250 ( 60 % ) ;
; Total memory bits ; 1,262,592 / 3,423,744 ( 37 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.991 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.864 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 17.052 ns ;

== Revision 4.4.1 ==
* '''Filename:''' rc_v04040001_21nov2008

* '''Features:'''
** Fixes a bug that froze up the firmware if any of the following commands were issued: CARD_ID_ADDR, CARD_TEMP_ADDR, FPGA_TEMP_ADDR in 4.4.0 only.

* '''Details:'''
** The bug fix include adding more logic to the wishbone ack path (readout_card.vhd), which subsequently decreased the minimum clock setup time to 1.588ns. The new logic will catch errors that the old logic wouldn't have, and is now consistent with the firmware on all the other cards. However, if timing becomes an issue, the logic may have to revert back to that which was in version 4.0.c.

* '''Bugs:'''
** None so far.

* '''Synthesis Notes:'''
** The quartus.ini file was not present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 27,241 / 41,250 ( 66 % ) ;
; Total memory bits ; 405,504 / 3,423,744 ( 12 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.588 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.585 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 17.057 ns ;

== Revision 4.4.0 (buggy) ==
* '''Filename:''' rc_v04040000_02oct2008
* '''Features:'''
** Reinstated the data modes in wbs_frame_data.vhd that were removed in 4.0.c. This firmware has the following modes: '''0, 1, 2, 4, 5, 7, 10'''. The modes that are not present are: '''3''' (raw data), '''6''' (replaced by data_mode = 7), '''8''' (replaced by data_mode = 10), '''9''' (replaced by data_mode = 10). For more information on data modes, see [[Data mode]].
** Re-integrated the id_thermo and fpga_thermo block in the readout_card.vhd top level that was removed in 4.0.c.
** Removed the sticky bit in fsfb_corr.vhd, which was enabled when flux-jumping was turned on. Because the feedback is signed, the sticky bit would usually reflect the value of the 14th bit, except in situations when the number of flux quanta to jump was greater than 1 (i.e. cosmic rays, IV-curves, etc). Flux jumps are made at a maximum rate of one per frame period, so that if the First-Stage Feedback increased past the 13th bit, it would not be reflected in the feedback applied. Now it is.
* '''Details:'''
** Simplified the FSM logic in wbs_frame_data.vhd that determines when to transition from IDLE to WSS1. This was done to lower the number of gates in that path, and ease the timing.
** Removed the z_dat_i port in fsfb_processor.vhd and fsfb_calc_pack.vhd to the fsfb_proc_pidz block, in an effort to make it clearer within that block that the z-term is always = 0.
** Removed the z-term sign extension in fsfb_proc_pidz.vhd, and the [d-term + z-term] adder to free up DSP resources since the z-term is always = 0.
** Adjusted the indentation in fsfb_io_controller.vhd to make the file more readable.
** Moved the tga_o signal out of the dispatch_wishbone.vhd FSM, and made it a continuous assignment. This signal had one of the highest fan-out counts in the RTL design, and actually was impossible to route in Stratix III chips in its previous configuration because of the number of gates on the fan-out. As a consequence of making it a continuous assignment, the Stratix III fitter was able to succeed, and the Stratix I timing characteristics were greatly improved. This is the most significant change in this revision. This change single-handedly increased the minimum slack from 1.282 ns in v0400000c to 2.372 ns (or 56.7 MHz max) in this revision.
* '''Bugs:'''
** The following commands lock up the Readout Card firmware: CARD_ID_ADDR, CARD_TEMP_ADDR, FPGA_TEMP_ADDR.
** fb_const0 commands to channel 0 do not work. The value is stored in the register, but not applied to the DAC. Thus, read-back returns the correct value, but the DAC does not
* '''Synthesis Notes:'''
** The quartus.ini file was not present in the synth directory during synthesis.
* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 27,099 / 41,250 ( 66 % ) ;
; Total memory bits ; 406,016 / 3,423,744 ( 12 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.372 ns ;
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 4.052 ns ;
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.066 ns ;

== Revision 4.0.c ==
* '''Filename:''' rc_v0400000c_15aug2008.sof
* '''Features:'''
** Only has data modes 0, 1, 4, and 10.
** Fixed the bug that exists in 4.0.b, 4.0.a, and 4.0.9 that prevented the fb_const value from being applied to channel zero (wbs_fb_data.vhd).
* '''Details:'''
** Changed a counter in the dispatch block to ease timing constraints in synthesis (dispatch_wishbone.vhd)
** Updated the tagged versions of dispatch.vhd , dispatch_cmd_receive.vhd, and dispatch_reply_transmit.vhd to the version that is used by all the other cards.
** '''Removed''' the fpga_termo (command: '''fpga_temp''') and id_thermo (commands: '''card_temp, card_id''') to ease timing constraints in synthesis (readout_card.vhd)
** Updated the tagged version of fpga_termo.vhd to include the new 'stale bit' feature
** Updated the tagged version of frame_timing_core.vhd to include the new 'err_o' interface
* '''Bugs:'''
** None reported yet
* '''Synthesis Notes:'''
** The quartus.ini file was not present in the synth directory during synthesis.
* '''FPGA Resource Usage:'''
Total logic elements : 25,058 / 41,250 ( 61 % )
Total memory bits : 400,896 / 3,423,744 ( 12 % )

* '''Timing Analysis''' (readout_card.tan.rpt):
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.282 ns ;
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.736 ns ;
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.665 ns ;

== Revision 4.0.b (buggy) ==
Note: This revision is on a watch list, after the bug detected 15 July 2008. See the bug section for more details.
* '''Filename''' : rc_v0400000b_04aug2008.sof
* '''Features'''
** data_mode 10 is added to provide more filtfb bits (compared to data mode 9) for planet observations. filtered_dat(27 downto 3) & flux_cnt_dat(6 downto 0)

* '''Bugs'''
** An unexplained bug that appeared in 4.0.a and may still be present in 4.0.b is a problem with the readout of channels being clipped out of data reporting. [[Bug 1 Notes]]

* ''' Synthesis note '''
** Quartus.ini removed.

== Revision 4.0.a (buggy) ==
Note: This revision is on a watch list, after the bug detected 15 July 2008. See the bug section for more details.
* '''Filename''' : rc_v0400000a_07jul2008.sof
* '''Bug Fix'''
** mce_status and adc_offset/flx_quanta commands do not fail after power up.
* ''' Synthesis note '''
** Quartus.ini removed.

* '''Bugs'''
** Seems to clip out channel 0 from data reporting.

== Revision 4.0.9 (buggy) ==
* '''Filename''' : rc_v04000009_26jun2008.sof
* '''Features'''
** sa_bias and offset DACs only refreshed when new values are written. (in previous versions, DACs were refreshed every frame)
* '''Bugs'''
** fb_const0 commands to channel 0 do not work. The value is stored in the register, but not applied to the DAC. Thus, read-back returns the correct value, but the DAC does not.
** reading flx_quanta and adc_offset right after power up hangs the reply datapath to CC. resetmce clears this error as temporary solution. the problem is caused by first read ack of the wishbone slave.

== Revision 4.0.8 ==
* '''Filename''' : rc_v04000008_26jun2008.sof
* '''Features'''
** The gaini, gainp, gaind resolution increased to 12-bit, i.e. -2048 to 2047 (formerly 10-bit).

* '''Bug fix'''
** the bug associated with gainpid read before mce_reset is fixed.

* ''' Synthesis note '''
** Quartus.ini removed.

== Revision 4.3.7 ==
* '''Filename''' : rc_v04030007_26may2008_raw.sof
* '''Features'''
** 14-bit raw mode enabled to buffer a snapshot of 50MHz samples for 2 frames of row_len * num_rows samples.
** In order to extend the raw-mode to 14-bit, an assumption is made that the raw buffer is not written to while being read. Therefore, make sure there is at least 2*row_len*num_rows*20ns between issuing captr_raw command and reading back the raw data.
** In order to save RAM for raw mode, two memory-intensive features are disabled:
*** low-pass filter disabled ( mixed filtfb data modes 6, 7, 9 are also disabled)
*** PID (gainp0, gaini0, gaind0) readback disabled. one can still set PID values and run servo, but can not read back the values.

== Revision 4.2.7 ==
* '''Filename''' : rc_v04020007_24may2008_raw.sof
* '''Features'''
** raw mode enabled to buffer a snapshot of 50MHz samples for 2 frames of row_len * num_rows samples.
** In order to save RAM for raw mode, two memory-intensive features are disabled:
*** low-pass filter disabled ( mixed filtfb data modes 6, 7, 9 are also disabled)
*** PID (gainp0, gaini0, gaind0) readback disabled. one can still set PID values and run servo, but can not read back the values.
* '''Bug fix'''
** the bug associated with reading from raw-buffer is fixed.

== Revision 4.1.7 ==
* '''Filename''' : rc_v04010007_25apr2008_raw.sof
* '''Features'''
** raw mode enabled to buffer a snapshot of 50MHz samples for 2 frames of row_len * num_rows samples.
** In order to save RAM for raw mode, two memory-intensive features are disabled:
*** low-pass filter disabled ( mixed filtfb data modes 6, 7, 9 are also disabled)
*** PID (gainp0, gaini0, gaind0) readback disabled. one can still set PID values and run servo, but can not read back the values.
* '''Bugs'''
** after each readout frame, raw-buffer readout counter falls behind by 3 and this causes skipping 3 50MHz samples in the data stream and column-data being messed up in subsequent frames. Data can be rearranged by post processing.

== Revision 4.0.6 (buggy) ==
* '''Filename''' : rc_v04000006_15feb2008.sof or .pof
* '''Features'''
** '''bugfix''': unreliable reset due to unsafe and incomplete state machines is fixed.
** '''bugfix''': flux_jump sign problem fixed, so far proved in const_mode, to be tested in servo_mode with cold setup.
** servo_mode=2 or ramp previously only went from 0 to ramp_amp, but now goes from -8192 to -8192+ramp_amp
** new commands are added: ''scratch'' and ''card_type''. Scratch takes 8 values and can be used by software to detect reset.
** slot_id and fw_rev are now integrated as part of all_cards.vhd
** lvds_tx_b=0, This will allow Clock Card to use the secondary backplane lvds line and check whether RC is plugged in.
** filter_coeff in misc_banks_admin commented as it is not implemented and causes timing problems.

* '''Bugs'''
** reading gainp/gaini/gaind right after power up hangs the reply datapath to CC. resetmce clears this error as temporary solution. the problem is caused by first read ack of pid_ram_admin.
** slot_id is only set after a resetmce is issued. (using the latest all_cards in the next revision will fix this)
** has spurious spikes on channel 7 data, which max out the integral, and cause the detectors to come unlocked. This firmware officially meets timing requirements, but the bug could be due to marginal timing on the longest data paths, i.e. ~0.1 ns in some cases.

== Revision 4.0.5 ==
* '''Filename''' : rc_v04000005_01nov2007.sof or .pof
* '''Features'''
** data mode 9 (mixed filt + flux jump) with windowing readjusted compared to data mode 8

* '''Bugs'''
** unreliable resetmce. Sometimes, firmware waked up non-responsive on lvds lines.
** In data mode 5 and 9, flux-jump counter is not reported properly due to a sign error. However, flux jumping works fine.

== Revision 3.0.19 ==
* '''Filename''' : rc_v03000019_16feb2007_raw.sof (no pof as one is not likely to run with this as regular firmware)
* '''Features'''
** data mode 3 is enabled.
** filter is disabled as a compromise to fit the raw-mode buffer.

* '''Bugs'''
** unreliable resetmce. Sometimes, firmware waked up non-responsive on lvds lines.

== Old Firmware Revisions ==
* '''4.0.4''': rc_v04000004_11oct2007.sof data mode 8 added (mixed filt + flux jump)
* '''4.0.3''': rc_v04000003_19sep2007.sof data mode 7 bit split readjusted to 10b error being bit 4 to 14
* '''4.0.2''': rc_v04000002_11sep2007.sof pid resolution increased to 10b, data mode 7 added
* '''4.0.1''': rc_v04000001_06sep2007.sof
* '''4.0.0''': rc_v04000000_29aug2007.sof supports readout_row_index * [[ bugs ]]

= To-Do List =
* the starting point for the servo is currently zero and it would be nice to have it programmable.

= RC Synthesis Notes =
# The following note applies when using Quartus versions earlier than Q7: Quartus.ini file had to exist in synth directory up to revision 4.0.a due to a bug that started in Quartus 6.1 and would synthesize away arbitrary parts of readout card. We contacted Altera at the time and they provided us the ini file.
# Timing: There is no "lock region" defined for readout card. Timing on readout card is tight and since version 3 or so any new feature would initially fail timing till some synthesis options were tweaked. One path that remains to be consistently marginal is from addr_gen counter (i.e. tga_o counter) in dispatch_wishbone.vhd to wishbone slaves particularly misc_banks_admin.vhd. Modules that are rewritten to address timing concerns are fsfb_corr, all_cards, misc_banks_admin, and finally instantiating an lpm counter instead of a counter from components library. Surprisingly, the lpm counter reduced 87 failures to 37, although looking at the technology map viewer, it seemed that they were both synthesized the same.
# Compile time: This was at some point 4.5 hours, after going to dual core PC, this was reduced to 35 minutes. After extending pid gains to 12b and fixing offset/sa_bias update code, the compile time increased to 1.5hr again with utilization up to ~70%.
# wbs_fb_storage, ram_8x64, pid_ram had to be regenerated using latest (Q7.2) MegaWizard to get rid of the bug associated with failure to read after power up until a reset was issued.
# During simulations, the initialization of RAM block with .hex files needs to be disabled. This is done by commenting out the following lines from the MegaWizard generated Megafunction files (remember to un-comment them before synthesizing the code):
lpm_file => "C:/scuba2_repository/cards/readout_card/fsfb_calc/source/rtl/ram_40x64.hex", and
lpm_file : STRING;
#Starting Q10.0 use TimeQuest timing analyzer as oppose to the classic one. The classic one is being phased out by Altera. In order to use TimeQuest, you need to have an sdc file present in your project directory.
----
[http://e-mode.phas.ubc.ca/mcewiki/index.php/Main_Page MCE Main Page]

Readout Card firmware

2011-05-04T21:52:02Z

Bburger: /* Revision 5.0.d */

* Synthesis Reminders (for firmware developers)
** quartus.ini is not needed anymore (Fixed as of Q7, Altera SR10783580 2010-10-24)
** Remember that readout_card/fsfb_clac/source/rtl/ram_40x64.vhd must be initialized with the ram_40x64.hex file in the same directory.
= Revision 5.1.2 =
* '''Filename:'''
** rc_stratix3_v05010002_18jan2011.sof (for Rev. E cards)
** rc_stratix3_v05010002_18jan2011.jic (for Rev. E cards)
** rc_v05010002_03feb2011.sof (for Rev. B cards)
** rc_v05010002_03feb2011.pof (for Rev. B cards)

* '''Features:'''
** based on 5.1.1 with k1 and k2 (filter params) limited to k1<16 and k2<32 in order to resolve the timing when compiling for smaller Stratix FPGA on RC Rev. B.

* '''Bug fix:'''
** the 2-rows-off filtered data readout introduced with configurable filter in rev. 5.1.0 and 5.1.1 is fixed now.

* '''Bugs:'''
** none so far.

* '''FPGA Resource Usage''' (readout_card.fit.rpt)
; Total logic elements ; 33,285 / 41,250 ( 81 % ) ;
; Total pins ; 358 / 616 ( 58 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt)
; Fast Model Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 6.591 ns
; Fast Model Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 7.206 ns
; Fast Model Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 18.299 ns

== Revision 5.1.1 (not recommended) ==
* '''Filename:'''
** rc_v05010001_01dec2010.sof (for Rev. B cards)

* '''Features:'''
** based on 5.1.0, but k1 and k2 (filter params) are now limited to k1<16 and k2<32 in order to resolve the timing failures of compiling 5.1.0 for smaller Stratix FPGA on RC Rev. B.

* '''Bugs:'''
** filter mode data is off by 2 rows.

== Revision 5.1.0 (not recommended) ==
* '''Filename:'''
** rc_stratix3_v05010000_01nov2010.sof (for Rev. E cards)
** rc_v05010000_01nov2010.sof (for Rev. B cards) has timing failures '''do not use!!!'''

* '''Features:'''
** added configurable filter parameters specified by ''fltr_coeff'', default is the fcutoff/fsampl=122Hz/15kHz. see [[ Digital 4-pole Butterworth Low-pass filter ]].
** ''fltr_type'' is set to 255 to indicate configurable filter parameters.
** see [http://www.phas.ubc.ca/~mce/mcedocs/software/SC2_ELE_S580_515_mce_command_description.pdf MCE command description]
** development notes:
*** It is built on Quartus10.1.
*** tcl files had to be updated as cmp syntax is not supported in Q10 anymore.
*** Rev. E cards now can be identified by reading back pcb_rev as part of card_type, therefore both stratix I and III sof/pof/jic are generated from the same source.

* '''Bugs:'''
** rc_v05010000_01nov2010.sof has timing failures that were overlooked, do not use this firmware for Rev.B cards.
** '''filter mode data is off by 2 rows.'''

* '''FPGA Resource Usage and Timing Report''' (readout_card.fit.rpt and readout_card.tan.rpt): logic usage is upto 85% from 66% in 5.0.d/e/f

= Revision 5.0.f =
* '''Filename:'''
** rc_v0500000f_22oct2010.sof (for Rev. B cards)
** rc_stratix3_v0500000f_22oct2010.sof (for Rev. E cards)

* '''Features:'''
** Bugfix: integral clamp should work now. only positive integral_clamp values are valid!

* '''Details:''':
** SQ1FB is applied 18 clock cycles after start of a row visit (SQ1_Bias being applied) regardless of flux-jump being enabled or not. In pre-5.0.b firmware SQ1FB was being applied after 7 clock cycles when flux-jump was disabled and after 18 clock cycles when flux-jump was enabled.
** available for both Rev. E and Rev. B cards, the upper byte of card_type parameter now reports the pcb revision.
** development note: It is built on Quartus10.1.

* '''Bugs:'''
**none yet!

* '''FPGA Resource Usage and Timing Report''' (readout_card.fit.rpt and readout_card.tan.rpt): no change compared to 5.0.a/b/c/d

== Revision 5.0.e (not recommended) ==
* '''Filename:'''
** rc_v0500000e_06oct2010.sof

* '''Details:'''
** an unsuccessful attempt to fix integral_clamp, but changed the functionality so that it clamps at the value, but it doesn't hold the clamp. i.e., if the calculated sq1fb becomes less than the specified clamp value, the sq1fb is not clamped anymore. This is not a desired functionality!

== Revision 5.0.d ==
* '''Filename:'''
** rc_v0500000d_04aug2010.sof

* '''Features:'''
** Bugfix: To fix the bug associated with negative flux-jumps, reverted to signed multiplier and hence, incremented the width of the flux-quanta multiplier input by 1.

* '''Details:''': SQ1FB is applied 18 clock cycles after start of a row visit (SQ1_Bias being applied) regardless of flux-jump being enabled or not. In pre-5.0.b firmware SQ1FB was being applied after 7 clock cycles when flux-jump was disabled and after 18 clock cycles when flux-jump was enabled.

* '''Bugs:'''
** '''integral_clamping is broken'''. To test the clamping, a servo-locked ramp was initiated on the sq1fb and then flux-jumping was turned on and observed by attaching a scope to the SQ1FB output. With integral_clamp=80000000, flux_quanta=8000, gaini=1, flux-jump enabled, we see [[http://e-mode.phas.ubc.ca/mcewiki/index.php/Image:Clamp_unstable.png scope snapshot]] used slow_fb_ramp.py script for testing.

* '''FPGA Resource Usage and Timing Report''' (readout_card.fit.rpt and readout_card.tan.rpt): no change compared to 5.0.a/b/c

== Revision 5.0.c (not recommended) ==
* '''Filename:'''
** rc_v0500000c_16jun2010.sof

* '''Features:'''
** Based on rev. 5.0.b
** Re-introduced flux-jump counter clamping to maintain continuity in behavior from past versions of firmware in the field.
** '''Important''': SQ1FB is applied 18 clock cycles after start of a row visit (SQ1_Bias being applied) regardless of flux-jump being enabled or not. In pre-5.0.b firmware SQ1FB was being applied after 7 clock cycles when flux-jump was disabled and after 18 clock cycles when flux-jump was enabled.

* '''Details:'''
* '''Bugs:'''
** '''flux-jump is broken'''. flux-jumping block misbehaves at the first jump in the negative range.

* '''FPGA Resource Usage''' (readout_card.fit.rpt): [[rc_5.0.c_fit_rpt]]
; Total logic elements ; 26,800 / 41,250 ( 65 % ) ;
; Total pins ; 358 / 616 ( 58 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;
; DSP block 9-bit elements ; 76 / 112 ( 68 % ) ;
; Total PLLs ; 1 / 6 ( 17 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt): [[rc_5.0.c_tan_rpt]]
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.964 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 4.382 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 15.924 ns ;

== Revision 5.0.b (not recommended) ==
* '''Filename:'''
** rc_v0500000b_03jun2010.sof

* '''Features:'''
** Based on rev. 5.0.a
** A bug that caused jumps in first-stage feedback, and detected as spikes in the raw data of pixels that were in servo_mode=0,1,2 was fixed. The jumps in FSFB were due to flux-jumping being enabled on live pixes with non-zero flx_quanta, and being disabled on the fly on dead pixels with flx_quanta=0. Flux-jumping is now disabled on a column-by-column basis if a column is in servo_mode = 0,1,2.
** Ineffective clamping was removed from the flux-jumping block (as per 5.0.9), as it is now replaced by the clamping that was perfected in rev. 5.0.10
** A sticky bit that only affected servo_mode=0,1,2 was also removed from the flux-jumping block.
** flx_lp_init commands now also clear the flux-jumping block as well.
** The 11-clock-cycle delay (in applying SQ1_FB) that in previous firmware only occurred when flux-jumping was enabled, now (in this version) is in effect all the time. Due to the bug-fix above, flux-jumping can be disabled on a column-by-column basis by setting servo_mode=0,1,2 when en_fb_jump=1. Before the change, this meant that constant values could be applied with or without the 11-cycle delay if en_fb_jump=1 or 0. To make the delay consistent, it is now always 11 cycles. As background, the flux-jumping block is pipelined, meaning that it does calculations for all 8 channels serially. The serialization is because of DSP-block limitations in the Readout Card FPGA that prevent us from doing all 8 channels in parallel. The reason that it takes 11 cycles to complete the flux-jumping calculations is because the values are computed for the eight channels in three ALU stages: 8 + 3 = 11 cycles. Adding 11 cycles to the 7 cycles of latency from other stages in the system results in: 11 + 7 = 18 cycles of latency from the start of a row dwell period before the first-stage feedback is applied. In rc_v5.0.c, I enforce the 18-cycle delay even when flux-jumping is not enabled to maintain uniformity across all eight channels, because flux-jumping is enabled/disabled on a per-channel basis. In other words, if I hadn't enforced the 18-cycle delay, some channels could have their feedback applied after 7 cycles, while others could have it applied after 18 cycles. I wasn't a fan of this non-uniformity. I realize that 18 cycles is a long time. In fact, so is 7. In the last few months, we have been discussing how to reduce these times to 1 cycle, because every experiment out there wants to multiplex as fast as possible, and the 7/18-delay is a rate limiting step.
** The flux-jumping code was re-arranged in the flux-jumping block to reflect the flow of data through the pipeline and make it easier to understand.

* '''Details:'''

* '''Bugs:'''
** flux-jump does not work when jumping to negative values.

* '''FPGA Resource Usage''' (readout_card.fit.rpt): [[rc_5.0.b_fit_rpt]]
; Total logic elements ; 26,745 / 41,250 ( 65 % ) ;
; Total pins ; 358 / 616 ( 58 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;
; DSP block 9-bit elements ; 76 / 112 ( 68 % ) ;
; Total PLLs ; 1 / 6 ( 17 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;
* '''FPGA Timing Analysis''' (readout_card.tan.rpt): [[rc_5.0.b_tan_rpt]]
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.459 ns
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.895 ns
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 15.956 ns

= Revision 5.0.a =
* '''Filename:'''
** rc_v0500000a_12mar2010.sof

* '''Features:'''
** Based on the merger of rev. 5.0.8 and 5.0.9.
** '''integral_clamp''' command is added where a clamp value is set for the integral term and once the integral term hits that value, the integral-term is clamped to that value and p-term and d-term are clamped to zero. When integral_term=0 then no clamping is in effect, similar to previous releases of firmware.
** The low pass filter has 20-bit input and f_3dB/f_samp = 122Hz/15kHz .
** The flux-jump clamping that was removed in 5.0.9 is included once again here, as we decided this is safer for now.

* '''Details:'''
** "lock_dat_left" parameter that was removed in 5.0.9 is now implemented as "lock_dat_lsb"

* '''Bugs:'''
** flx_lp_init does not reinitialize the flux-jump block

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis
** tag name: rc_v0500000a_12mar2009! years were mixed up!

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
* '''FPGA Timing Analysis''' (readout_card.tan.rpt):

== Revision 5.0.9 (buggy) ==
* '''Filename:'''
** rc_v05000009_13nov2009.sof

* '''Features:'''
** Based on rev. 5.0.4
** Removes a sticky bit in pid calculation result storage -- in fsfb_processor.
** Adds a command to clamp the growth of the I-term to prevent wrapping and track down the source of Caltech's FSFB jumps.
** Removed the unused lock_dat_left parameter. The ability to shift left was moved to the fsfb_corr block some time ago.
** Fixed a sign extension bug acting on the flux quanta, which limited the value to 8191. Changed the extension from signed to unsigned.
** Removed ineffective clamping in the flux-jump calculation block.
** IMPORTANT: Must be used in conjunction with firmware rev. 5.0.0+ of all other cards.

* '''Details:'''

* '''Bugs:'''
** integral_clamp read/write command does not work.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 27,960 / 41,250 ( 68 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.825 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.878 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 14.397 ns ;

== Revision 5.0.8 (UBC only) ==
* '''Filename:'''
** rc_v05000008_09oct2009.sof

* '''Features:'''
** Based on rev. 5.0.4
** type 1 low-pass filter: f3dB=122Hz for fsample=15kHz
** Filter-input-width changed from 18b to 20b with no sticky bits!
** removed sticky bits in internal arithmetic of the filter.

= Revision 5.0.7 (type-2 filter) =
* '''Filename:'''
** rc_v05000007_09oct2009.sof

* '''Features:'''
** Based on rev. 5.0.4
** type-2 low-pass-filter: f3dB=75Hz for fsample=30000.
** Filter-input-width changed from 18b to 20b with no sticky bits!
** inter-biquad-gain-scaling for the filter is 2^14
** filter results are scaled down by 2^3 in the output of the filter.
** removed sticky bits in internal arithmetics
** _correction_ disabled in fsfb_proc_pidz

* '''Details:'''
** quartus.ini file was '''not''' present in synth directory.

* '''Bugs:'''
** none to report

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
== Revision 5.0.6 (UBC only) ==
* '''Filename:'''
** rc_stratix3_v05000006_15sep2009.sof

* '''Features:'''
** Only Valid for Rev. C/D Cards
** Based on rev. 5.0.3
** tcl file updated for Rev. D and aligned with top-level and qsf (project file).
** flux loop commented, just to try sampling the ADC.
** compiled with Q9.1

== Revision 5.0.5 (UBC only) ==
* '''Filename:'''
** rc_v05000005_04sep2009.sof

* '''Features:'''
** Based on rev. 5.0.2
** changed the low-pass-filter to f(3db)=75Hz for f(sample)=30000.

* '''Details:'''
** quartus.ini file was '''not''' present in synth directory.

* '''Bugs:'''
** negative inputs to the filter cause filter to have a non-flat pass-band region. may have to do with sign-handling...

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
* '''FPGA Timing Analysis''' (readout_card.tan.rpt):

= Revision 5.0.4 =
* '''Filename:'''
** rc_v05000004_28aug2009.sof

* '''Features:'''
** Based on rev. 5.0.2
** BUG Fix: handles 14-bit flux quanta (changed the multiplier to unsigned)
** BUG Fix: changed standard logic vector extension from signed to unsigned in flux-jumping slave.
** IMPORTANT: Must be used in conjunction with firmware rev. 5.0.0+ of all other cards.

* '''Details:'''

* '''Bugs:'''
** None so far.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,170 / 41,250 ( 63 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.541 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.612 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 15.398 ns ;

= Revision 5.0.3 =
* '''Filename:'''
** rc_stratix3_v05000003_21aug2009.sof

* '''Features:'''
** ONLY valid REV C/D RC Cards
** Based on rev. 5.0.2
** flux loop commented, just to try sampling the ADC.
** updated tcl file, but still need to rely on project file as well as qsf file.
** changed default level of adc_sclk to '1'
** dac_clr_n was changed from an output to an input.
** added 'locked' interface to rc_pll_stratix_iii
** renamed the adc_pll clock signals to more explanitory names
** added the FPGA_DEVICE_FAMILY generic to the dispatch interace for synthesis of the dc_fifo in lvds_rx
** uncommented DDR interface to force the syntesizer to use correct left and right PLLs (in conjunction with ADC and DDR PLLs)
** added test signals to test_status to see clocks on the scope.
== Revision 5.0.2 (buggy) ==
* '''Filename:'''
** rc_v05000002_test00_tagged.sof

* '''Features:'''
** Based on rev. 5.0.1
** Fixed a bug in wbs_frame_data that stored data incorrectly if reporting 1 or 2 pixels only.
** IMPORTANT: Must be used in conjunction with firmware rev. 5.0.0+ of all other cards.

* '''Details:'''

* '''Bugs:'''
** None so far.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,186 / 41,250 ( 63 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.755 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.979 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.067 ns ;

== Revision 5.0.1 (buggy) (Filter + Raw + Rectangle, 2 LVDS) ==
* '''Filename:'''
** rc_v05000001_26may2009.sof

* '''Features:'''
** Combines features in rev. 5.0.0 (2 LVDS Lines) and rev. 4.0.e (Filtered + Raw), with the NEW rectangle mode.
** IMPORTANT: Must be used in conjunction with firmware rev. 5.0.0+ of all other cards.

* '''Details:'''
** [[CVS Diff Between sys_v05000000 and rc_v05000001]]

* '''Bugs:'''
** Has a bug in wbs_frame_data that stored data incorrectly if reporting 1 or 2 pixels only.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,565 / 41,250 ( 64 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.656 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.861 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 14.167 ns ;

== Revision 5.0.0 (Filter Only, 2 LVDS) ==
* '''Filename:'''
** rc_v05000000_22dec2008.sof (tagged as sys_v05000000_22dec2008)

* '''Features:'''
** IMPORTANT: Must be used in conjunction with firmware v05000000+ of all other cards!!!
** Adds the ability to read out one column of data continuously from readout cards
** Adds data mode 11, which is an engineering mode. Data points are 32-bits, and bits [9..3]=row_index, [2..0]=column_index. This mode is useful for determining which pixels one is reading out in the array, in column mode for example.

* '''Details:'''
** [[CVS Diff Between rc_v0400000c and sys_v05000000]]

* '''Bugs:'''
** None so far.

* '''Synthesis Notes:'''
** The quartus.ini file was not present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,607 / 41,250 ( 65 % ) ;
; Total memory bits ; 406,016 / 3,423,744 ( 12 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.558 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.892 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.987 ns ;

== Revision 4.0.f (Filter + Raw, 1 LVDS) ==
* '''Filename:'''
** rc_v0400000f_12feb2010.sof

* '''Features:'''
** Based on 4.0.e and in parallel with 5.0.9 (equivalent version, clamping is not included)
** Incorporates fixes that were done to flux-jumping between 5.0.2 - 5.0.4 - 5.0.9. Namely:
*** Changes a multiplier from signed to unsigned (in fsfb_corr_multplier.vhd).
*** Changes sign extension from signed to unsigned (in flux_quanta_ram_admin.vhd).

* '''Details:'''

* '''Bugs:'''
** None reported yet.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,773 / 41,250 ( 65 % ) ;
; Total memory bits ; 1,321,984 / 3,423,744 ( 39 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.539 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 4.118 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 17.318 ns ;

== Revision 4.0.e (Filter + Raw, 1 LVDS) ==
* '''Filename:'''
** rc_v0400000e_27apr2009.sof

* '''Features:'''
** Based on 4.0.d
** Combines both raw- and filtered-data modes.
** fpga_temp, card_temp, card_id commands are disabled.
** Tested by Matt Hasselfield.

* '''Details:'''

* '''Bugs:'''
** fpga_temp, card_temp, card_id commands are disabled.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 27,048 / 41,250 ( 66 % ) ;
; Total memory bits ; 1,321,984 / 3,423,744 ( 39 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.675 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.907 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.728 ns ;

== Revision 4.0.d (Raw Only, 1 LVDS) ==
* '''Filename:''' rc_v0400000d_20090417.sof

* '''Features:'''
** Based on v4.0.c, but has the filter removed, and implements a single 65536-index RAM block for storing 50 MHz raw-data samples.
** The firmware takes a new command called readout_col_index which specifies which column to capture raw data from.
** Other than readout_col_index, the firmware functions the same as previous raw-data firmware, including then need to issue a capture_raw command.
** For more information on raw-data, see: http://e-mode.phas.ubc.ca/mcewiki/index.php/Raw-mode_readout
** This firmware also integrates some of the improvements that were implemented in 4.4.0, like the removal of the tga_o signal from an FSM in dispatch_wishbone.vhd.

* '''Details:'''
** Differences between 4.0.c and 4.0.d
U system/test/source/tb/tb_cc_rcs_bcs_ac.vhd
U all_cards/dispatch/source/rtl/dispatch_wishbone.vhd
U library/sys_param/source/rtl/wishbone_pack.vhd
U readout_card/adc_sample_coadd/source/rtl/adc_sample_coadd.vhd
U readout_card/adc_sample_coadd/source/rtl/adc_sample_coadd_pack.vhd
U readout_card/flux_loop/source/rtl/flux_loop.vhd
U readout_card/flux_loop/source/rtl/flux_loop_pack.vhd
U readout_card/flux_loop_ctrl/source/rtl/flux_loop_ctrl.vhd
U readout_card/flux_loop_ctrl/source/rtl/flux_loop_ctrl_pack.vhd
U readout_card/flux_loop_ctrl/source/tb/tb1_flux_loop_ctrl.vhd
U readout_card/flux_loop_ctrl/source/tb/tb2_flux_loop_ctrl.vhd
U readout_card/fsfb_calc/source/rtl/fsfb_fltr_regs.vhd
U readout_card/fsfb_corr/source/rtl/fsfb_corr.vhd
U readout_card/readout_card/source/rtl/readout_card.vhd
U readout_card/readout_card/source/rtl/readout_card_pack.vhd
U readout_card/wbs_frame_data/source/rtl/wbs_frame_data.vhd
U readout_card/wbs_frame_data/source/rtl/wbs_frame_data_pack.vhd

* '''Bugs:'''
** None so far.
** fpga_temp, card_temp, card_id commands are not supported.

* '''Synthesis Notes:'''
** The quartus.ini file was present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 24,554 / 41,250 ( 60 % ) ;
; Total memory bits ; 1,262,592 / 3,423,744 ( 37 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.991 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.864 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 17.052 ns ;

== Revision 4.4.1 ==
* '''Filename:''' rc_v04040001_21nov2008

* '''Features:'''
** Fixes a bug that froze up the firmware if any of the following commands were issued: CARD_ID_ADDR, CARD_TEMP_ADDR, FPGA_TEMP_ADDR in 4.4.0 only.

* '''Details:'''
** The bug fix include adding more logic to the wishbone ack path (readout_card.vhd), which subsequently decreased the minimum clock setup time to 1.588ns. The new logic will catch errors that the old logic wouldn't have, and is now consistent with the firmware on all the other cards. However, if timing becomes an issue, the logic may have to revert back to that which was in version 4.0.c.

* '''Bugs:'''
** None so far.

* '''Synthesis Notes:'''
** The quartus.ini file was not present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 27,241 / 41,250 ( 66 % ) ;
; Total memory bits ; 405,504 / 3,423,744 ( 12 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.588 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.585 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 17.057 ns ;

== Revision 4.4.0 (buggy) ==
* '''Filename:''' rc_v04040000_02oct2008
* '''Features:'''
** Reinstated the data modes in wbs_frame_data.vhd that were removed in 4.0.c. This firmware has the following modes: '''0, 1, 2, 4, 5, 7, 10'''. The modes that are not present are: '''3''' (raw data), '''6''' (replaced by data_mode = 7), '''8''' (replaced by data_mode = 10), '''9''' (replaced by data_mode = 10). For more information on data modes, see [[Data mode]].
** Re-integrated the id_thermo and fpga_thermo block in the readout_card.vhd top level that was removed in 4.0.c.
** Removed the sticky bit in fsfb_corr.vhd, which was enabled when flux-jumping was turned on. Because the feedback is signed, the sticky bit would usually reflect the value of the 14th bit, except in situations when the number of flux quanta to jump was greater than 1 (i.e. cosmic rays, IV-curves, etc). Flux jumps are made at a maximum rate of one per frame period, so that if the First-Stage Feedback increased past the 13th bit, it would not be reflected in the feedback applied. Now it is.
* '''Details:'''
** Simplified the FSM logic in wbs_frame_data.vhd that determines when to transition from IDLE to WSS1. This was done to lower the number of gates in that path, and ease the timing.
** Removed the z_dat_i port in fsfb_processor.vhd and fsfb_calc_pack.vhd to the fsfb_proc_pidz block, in an effort to make it clearer within that block that the z-term is always = 0.
** Removed the z-term sign extension in fsfb_proc_pidz.vhd, and the [d-term + z-term] adder to free up DSP resources since the z-term is always = 0.
** Adjusted the indentation in fsfb_io_controller.vhd to make the file more readable.
** Moved the tga_o signal out of the dispatch_wishbone.vhd FSM, and made it a continuous assignment. This signal had one of the highest fan-out counts in the RTL design, and actually was impossible to route in Stratix III chips in its previous configuration because of the number of gates on the fan-out. As a consequence of making it a continuous assignment, the Stratix III fitter was able to succeed, and the Stratix I timing characteristics were greatly improved. This is the most significant change in this revision. This change single-handedly increased the minimum slack from 1.282 ns in v0400000c to 2.372 ns (or 56.7 MHz max) in this revision.
* '''Bugs:'''
** The following commands lock up the Readout Card firmware: CARD_ID_ADDR, CARD_TEMP_ADDR, FPGA_TEMP_ADDR.
** fb_const0 commands to channel 0 do not work. The value is stored in the register, but not applied to the DAC. Thus, read-back returns the correct value, but the DAC does not
* '''Synthesis Notes:'''
** The quartus.ini file was not present in the synth directory during synthesis.
* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 27,099 / 41,250 ( 66 % ) ;
; Total memory bits ; 406,016 / 3,423,744 ( 12 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.372 ns ;
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 4.052 ns ;
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.066 ns ;

== Revision 4.0.c ==
* '''Filename:''' rc_v0400000c_15aug2008.sof
* '''Features:'''
** Only has data modes 0, 1, 4, and 10.
** Fixed the bug that exists in 4.0.b, 4.0.a, and 4.0.9 that prevented the fb_const value from being applied to channel zero (wbs_fb_data.vhd).
* '''Details:'''
** Changed a counter in the dispatch block to ease timing constraints in synthesis (dispatch_wishbone.vhd)
** Updated the tagged versions of dispatch.vhd , dispatch_cmd_receive.vhd, and dispatch_reply_transmit.vhd to the version that is used by all the other cards.
** '''Removed''' the fpga_termo (command: '''fpga_temp''') and id_thermo (commands: '''card_temp, card_id''') to ease timing constraints in synthesis (readout_card.vhd)
** Updated the tagged version of fpga_termo.vhd to include the new 'stale bit' feature
** Updated the tagged version of frame_timing_core.vhd to include the new 'err_o' interface
* '''Bugs:'''
** None reported yet
* '''Synthesis Notes:'''
** The quartus.ini file was not present in the synth directory during synthesis.
* '''FPGA Resource Usage:'''
Total logic elements : 25,058 / 41,250 ( 61 % )
Total memory bits : 400,896 / 3,423,744 ( 12 % )

* '''Timing Analysis''' (readout_card.tan.rpt):
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.282 ns ;
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.736 ns ;
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.665 ns ;

== Revision 4.0.b (buggy) ==
Note: This revision is on a watch list, after the bug detected 15 July 2008. See the bug section for more details.
* '''Filename''' : rc_v0400000b_04aug2008.sof
* '''Features'''
** data_mode 10 is added to provide more filtfb bits (compared to data mode 9) for planet observations. filtered_dat(27 downto 3) & flux_cnt_dat(6 downto 0)

* '''Bugs'''
** An unexplained bug that appeared in 4.0.a and may still be present in 4.0.b is a problem with the readout of channels being clipped out of data reporting. [[Bug 1 Notes]]

* ''' Synthesis note '''
** Quartus.ini removed.

== Revision 4.0.a (buggy) ==
Note: This revision is on a watch list, after the bug detected 15 July 2008. See the bug section for more details.
* '''Filename''' : rc_v0400000a_07jul2008.sof
* '''Bug Fix'''
** mce_status and adc_offset/flx_quanta commands do not fail after power up.
* ''' Synthesis note '''
** Quartus.ini removed.

* '''Bugs'''
** Seems to clip out channel 0 from data reporting.

== Revision 4.0.9 (buggy) ==
* '''Filename''' : rc_v04000009_26jun2008.sof
* '''Features'''
** sa_bias and offset DACs only refreshed when new values are written. (in previous versions, DACs were refreshed every frame)
* '''Bugs'''
** fb_const0 commands to channel 0 do not work. The value is stored in the register, but not applied to the DAC. Thus, read-back returns the correct value, but the DAC does not.
** reading flx_quanta and adc_offset right after power up hangs the reply datapath to CC. resetmce clears this error as temporary solution. the problem is caused by first read ack of the wishbone slave.

== Revision 4.0.8 ==
* '''Filename''' : rc_v04000008_26jun2008.sof
* '''Features'''
** The gaini, gainp, gaind resolution increased to 12-bit, i.e. -2048 to 2047 (formerly 10-bit).

* '''Bug fix'''
** the bug associated with gainpid read before mce_reset is fixed.

* ''' Synthesis note '''
** Quartus.ini removed.

== Revision 4.3.7 ==
* '''Filename''' : rc_v04030007_26may2008_raw.sof
* '''Features'''
** 14-bit raw mode enabled to buffer a snapshot of 50MHz samples for 2 frames of row_len * num_rows samples.
** In order to extend the raw-mode to 14-bit, an assumption is made that the raw buffer is not written to while being read. Therefore, make sure there is at least 2*row_len*num_rows*20ns between issuing captr_raw command and reading back the raw data.
** In order to save RAM for raw mode, two memory-intensive features are disabled:
*** low-pass filter disabled ( mixed filtfb data modes 6, 7, 9 are also disabled)
*** PID (gainp0, gaini0, gaind0) readback disabled. one can still set PID values and run servo, but can not read back the values.

== Revision 4.2.7 ==
* '''Filename''' : rc_v04020007_24may2008_raw.sof
* '''Features'''
** raw mode enabled to buffer a snapshot of 50MHz samples for 2 frames of row_len * num_rows samples.
** In order to save RAM for raw mode, two memory-intensive features are disabled:
*** low-pass filter disabled ( mixed filtfb data modes 6, 7, 9 are also disabled)
*** PID (gainp0, gaini0, gaind0) readback disabled. one can still set PID values and run servo, but can not read back the values.
* '''Bug fix'''
** the bug associated with reading from raw-buffer is fixed.

== Revision 4.1.7 ==
* '''Filename''' : rc_v04010007_25apr2008_raw.sof
* '''Features'''
** raw mode enabled to buffer a snapshot of 50MHz samples for 2 frames of row_len * num_rows samples.
** In order to save RAM for raw mode, two memory-intensive features are disabled:
*** low-pass filter disabled ( mixed filtfb data modes 6, 7, 9 are also disabled)
*** PID (gainp0, gaini0, gaind0) readback disabled. one can still set PID values and run servo, but can not read back the values.
* '''Bugs'''
** after each readout frame, raw-buffer readout counter falls behind by 3 and this causes skipping 3 50MHz samples in the data stream and column-data being messed up in subsequent frames. Data can be rearranged by post processing.

== Revision 4.0.6 (buggy) ==
* '''Filename''' : rc_v04000006_15feb2008.sof or .pof
* '''Features'''
** '''bugfix''': unreliable reset due to unsafe and incomplete state machines is fixed.
** '''bugfix''': flux_jump sign problem fixed, so far proved in const_mode, to be tested in servo_mode with cold setup.
** servo_mode=2 or ramp previously only went from 0 to ramp_amp, but now goes from -8192 to -8192+ramp_amp
** new commands are added: ''scratch'' and ''card_type''. Scratch takes 8 values and can be used by software to detect reset.
** slot_id and fw_rev are now integrated as part of all_cards.vhd
** lvds_tx_b=0, This will allow Clock Card to use the secondary backplane lvds line and check whether RC is plugged in.
** filter_coeff in misc_banks_admin commented as it is not implemented and causes timing problems.

* '''Bugs'''
** reading gainp/gaini/gaind right after power up hangs the reply datapath to CC. resetmce clears this error as temporary solution. the problem is caused by first read ack of pid_ram_admin.
** slot_id is only set after a resetmce is issued. (using the latest all_cards in the next revision will fix this)
** has spurious spikes on channel 7 data, which max out the integral, and cause the detectors to come unlocked. This firmware officially meets timing requirements, but the bug could be due to marginal timing on the longest data paths, i.e. ~0.1 ns in some cases.

== Revision 4.0.5 ==
* '''Filename''' : rc_v04000005_01nov2007.sof or .pof
* '''Features'''
** data mode 9 (mixed filt + flux jump) with windowing readjusted compared to data mode 8

* '''Bugs'''
** unreliable resetmce. Sometimes, firmware waked up non-responsive on lvds lines.
** In data mode 5 and 9, flux-jump counter is not reported properly due to a sign error. However, flux jumping works fine.

== Revision 3.0.19 ==
* '''Filename''' : rc_v03000019_16feb2007_raw.sof (no pof as one is not likely to run with this as regular firmware)
* '''Features'''
** data mode 3 is enabled.
** filter is disabled as a compromise to fit the raw-mode buffer.

* '''Bugs'''
** unreliable resetmce. Sometimes, firmware waked up non-responsive on lvds lines.

== Old Firmware Revisions ==
* '''4.0.4''': rc_v04000004_11oct2007.sof data mode 8 added (mixed filt + flux jump)
* '''4.0.3''': rc_v04000003_19sep2007.sof data mode 7 bit split readjusted to 10b error being bit 4 to 14
* '''4.0.2''': rc_v04000002_11sep2007.sof pid resolution increased to 10b, data mode 7 added
* '''4.0.1''': rc_v04000001_06sep2007.sof
* '''4.0.0''': rc_v04000000_29aug2007.sof supports readout_row_index * [[ bugs ]]

= To-Do List =
* the starting point for the servo is currently zero and it would be nice to have it programmable.

= RC Synthesis Notes =
# The following note applies when using Quartus versions earlier than Q7: Quartus.ini file had to exist in synth directory up to revision 4.0.a due to a bug that started in Quartus 6.1 and would synthesize away arbitrary parts of readout card. We contacted Altera at the time and they provided us the ini file.
# Timing: There is no "lock region" defined for readout card. Timing on readout card is tight and since version 3 or so any new feature would initially fail timing till some synthesis options were tweaked. One path that remains to be consistently marginal is from addr_gen counter (i.e. tga_o counter) in dispatch_wishbone.vhd to wishbone slaves particularly misc_banks_admin.vhd. Modules that are rewritten to address timing concerns are fsfb_corr, all_cards, misc_banks_admin, and finally instantiating an lpm counter instead of a counter from components library. Surprisingly, the lpm counter reduced 87 failures to 37, although looking at the technology map viewer, it seemed that they were both synthesized the same.
# Compile time: This was at some point 4.5 hours, after going to dual core PC, this was reduced to 35 minutes. After extending pid gains to 12b and fixing offset/sa_bias update code, the compile time increased to 1.5hr again with utilization up to ~70%.
# wbs_fb_storage, ram_8x64, pid_ram had to be regenerated using latest (Q7.2) MegaWizard to get rid of the bug associated with failure to read after power up until a reset was issued.
# During simulations, the initialization of RAM block with .hex files needs to be disabled. This is done by commenting out the following lines from the MegaWizard generated Megafunction files (remember to un-comment them before synthesizing the code):
lpm_file => "C:/scuba2_repository/cards/readout_card/fsfb_calc/source/rtl/ram_40x64.hex", and
lpm_file : STRING;
#Starting Q10.0 use TimeQuest timing analyzer as oppose to the classic one. The classic one is being phased out by Altera. In order to use TimeQuest, you need to have an sdc file present in your project directory.
----
[http://e-mode.phas.ubc.ca/mcewiki/index.php/Main_Page MCE Main Page]

Readout Card firmware

2011-05-04T21:47:04Z

Bburger: /* Revision 5.0.d */

* Synthesis Reminders (for firmware developers)
** quartus.ini is not needed anymore (Fixed as of Q7, Altera SR10783580 2010-10-24)
** Remember that readout_card/fsfb_clac/source/rtl/ram_40x64.vhd must be initialized with the ram_40x64.hex file in the same directory.
= Revision 5.1.2 =
* '''Filename:'''
** rc_stratix3_v05010002_18jan2011.sof (for Rev. E cards)
** rc_stratix3_v05010002_18jan2011.jic (for Rev. E cards)
** rc_v05010002_03feb2011.sof (for Rev. B cards)
** rc_v05010002_03feb2011.pof (for Rev. B cards)

* '''Features:'''
** based on 5.1.1 with k1 and k2 (filter params) limited to k1<16 and k2<32 in order to resolve the timing when compiling for smaller Stratix FPGA on RC Rev. B.

* '''Bug fix:'''
** the 2-rows-off filtered data readout introduced with configurable filter in rev. 5.1.0 and 5.1.1 is fixed now.

* '''Bugs:'''
** none so far.

* '''FPGA Resource Usage''' (readout_card.fit.rpt)
; Total logic elements ; 33,285 / 41,250 ( 81 % ) ;
; Total pins ; 358 / 616 ( 58 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt)
; Fast Model Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 6.591 ns
; Fast Model Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 7.206 ns
; Fast Model Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 18.299 ns

== Revision 5.1.1 (not recommended) ==
* '''Filename:'''
** rc_v05010001_01dec2010.sof (for Rev. B cards)

* '''Features:'''
** based on 5.1.0, but k1 and k2 (filter params) are now limited to k1<16 and k2<32 in order to resolve the timing failures of compiling 5.1.0 for smaller Stratix FPGA on RC Rev. B.

* '''Bugs:'''
** filter mode data is off by 2 rows.

== Revision 5.1.0 (not recommended) ==
* '''Filename:'''
** rc_stratix3_v05010000_01nov2010.sof (for Rev. E cards)
** rc_v05010000_01nov2010.sof (for Rev. B cards) has timing failures '''do not use!!!'''

* '''Features:'''
** added configurable filter parameters specified by ''fltr_coeff'', default is the fcutoff/fsampl=122Hz/15kHz. see [[ Digital 4-pole Butterworth Low-pass filter ]].
** ''fltr_type'' is set to 255 to indicate configurable filter parameters.
** see [http://www.phas.ubc.ca/~mce/mcedocs/software/SC2_ELE_S580_515_mce_command_description.pdf MCE command description]
** development notes:
*** It is built on Quartus10.1.
*** tcl files had to be updated as cmp syntax is not supported in Q10 anymore.
*** Rev. E cards now can be identified by reading back pcb_rev as part of card_type, therefore both stratix I and III sof/pof/jic are generated from the same source.

* '''Bugs:'''
** rc_v05010000_01nov2010.sof has timing failures that were overlooked, do not use this firmware for Rev.B cards.
** '''filter mode data is off by 2 rows.'''

* '''FPGA Resource Usage and Timing Report''' (readout_card.fit.rpt and readout_card.tan.rpt): logic usage is upto 85% from 66% in 5.0.d/e/f

= Revision 5.0.f =
* '''Filename:'''
** rc_v0500000f_22oct2010.sof (for Rev. B cards)
** rc_stratix3_v0500000f_22oct2010.sof (for Rev. E cards)

* '''Features:'''
** Bugfix: integral clamp should work now. only positive integral_clamp values are valid!

* '''Details:''':
** SQ1FB is applied 18 clock cycles after start of a row visit (SQ1_Bias being applied) regardless of flux-jump being enabled or not. In pre-5.0.b firmware SQ1FB was being applied after 7 clock cycles when flux-jump was disabled and after 18 clock cycles when flux-jump was enabled.
** available for both Rev. E and Rev. B cards, the upper byte of card_type parameter now reports the pcb revision.
** development note: It is built on Quartus10.1.

* '''Bugs:'''
**none yet!

* '''FPGA Resource Usage and Timing Report''' (readout_card.fit.rpt and readout_card.tan.rpt): no change compared to 5.0.a/b/c/d

== Revision 5.0.e (not recommended) ==
* '''Filename:'''
** rc_v0500000e_06oct2010.sof

* '''Details:'''
** an unsuccessful attempt to fix integral_clamp, but changed the functionality so that it clamps at the value, but it doesn't hold the clamp. i.e., if the calculated sq1fb becomes less than the specified clamp value, the sq1fb is not clamped anymore. This is not a desired functionality!

= Revision 5.0.d =
* '''Filename:'''
** rc_v0500000d_04aug2010.sof

* '''Features:'''
** Bugfix: To fix the bug associated with negative flux-jumps, reverted to signed multiplier and hence, incremented the width of the flux-quanta multiplier input by 1.

* '''Details:''': SQ1FB is applied 18 clock cycles after start of a row visit (SQ1_Bias being applied) regardless of flux-jump being enabled or not. In pre-5.0.b firmware SQ1FB was being applied after 7 clock cycles when flux-jump was disabled and after 18 clock cycles when flux-jump was enabled.

* '''Bugs:'''
** '''integral_clamping is broken'''. To test the clamping, a servo-locked ramp was initiated on the sq1fb and then flux-jumping was turned on and observed by attaching a scope to the SQ1FB output. With integral_clamp=80000000, flux_quanta=8000, gaini=1, flux-jump enabled, we see [[http://e-mode.phas.ubc.ca/mcewiki/index.php/Image:Clamp_unstable.png scope snapshot]] used slow_fb_ramp.py script for testing.

* '''FPGA Resource Usage and Timing Report''' (readout_card.fit.rpt and readout_card.tan.rpt): no change compared to 5.0.a/b/c

== Revision 5.0.c (not recommended) ==
* '''Filename:'''
** rc_v0500000c_16jun2010.sof

* '''Features:'''
** Based on rev. 5.0.b
** Re-introduced flux-jump counter clamping to maintain continuity in behavior from past versions of firmware in the field.
** '''Important''': SQ1FB is applied 18 clock cycles after start of a row visit (SQ1_Bias being applied) regardless of flux-jump being enabled or not. In pre-5.0.b firmware SQ1FB was being applied after 7 clock cycles when flux-jump was disabled and after 18 clock cycles when flux-jump was enabled.

* '''Details:'''
* '''Bugs:'''
** '''flux-jump is broken'''. flux-jumping block misbehaves at the first jump in the negative range.

* '''FPGA Resource Usage''' (readout_card.fit.rpt): [[rc_5.0.c_fit_rpt]]
; Total logic elements ; 26,800 / 41,250 ( 65 % ) ;
; Total pins ; 358 / 616 ( 58 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;
; DSP block 9-bit elements ; 76 / 112 ( 68 % ) ;
; Total PLLs ; 1 / 6 ( 17 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt): [[rc_5.0.c_tan_rpt]]
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.964 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 4.382 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 15.924 ns ;

== Revision 5.0.b (not recommended) ==
* '''Filename:'''
** rc_v0500000b_03jun2010.sof

* '''Features:'''
** Based on rev. 5.0.a
** A bug that caused jumps in first-stage feedback, and detected as spikes in the raw data of pixels that were in servo_mode=0,1,2 was fixed. The jumps in FSFB were due to flux-jumping being enabled on live pixes with non-zero flx_quanta, and being disabled on the fly on dead pixels with flx_quanta=0. Flux-jumping is now disabled on a column-by-column basis if a column is in servo_mode = 0,1,2.
** Ineffective clamping was removed from the flux-jumping block (as per 5.0.9), as it is now replaced by the clamping that was perfected in rev. 5.0.10
** A sticky bit that only affected servo_mode=0,1,2 was also removed from the flux-jumping block.
** flx_lp_init commands now also clear the flux-jumping block as well.
** The 11-clock-cycle delay (in applying SQ1_FB) that in previous firmware only occurred when flux-jumping was enabled, now (in this version) is in effect all the time. Due to the bug-fix above, flux-jumping can be disabled on a column-by-column basis by setting servo_mode=0,1,2 when en_fb_jump=1. Before the change, this meant that constant values could be applied with or without the 11-cycle delay if en_fb_jump=1 or 0. To make the delay consistent, it is now always 11 cycles. As background, the flux-jumping block is pipelined, meaning that it does calculations for all 8 channels serially. The serialization is because of DSP-block limitations in the Readout Card FPGA that prevent us from doing all 8 channels in parallel. The reason that it takes 11 cycles to complete the flux-jumping calculations is because the values are computed for the eight channels in three ALU stages: 8 + 3 = 11 cycles. Adding 11 cycles to the 7 cycles of latency from other stages in the system results in: 11 + 7 = 18 cycles of latency from the start of a row dwell period before the first-stage feedback is applied. In rc_v5.0.c, I enforce the 18-cycle delay even when flux-jumping is not enabled to maintain uniformity across all eight channels, because flux-jumping is enabled/disabled on a per-channel basis. In other words, if I hadn't enforced the 18-cycle delay, some channels could have their feedback applied after 7 cycles, while others could have it applied after 18 cycles. I wasn't a fan of this non-uniformity. I realize that 18 cycles is a long time. In fact, so is 7. In the last few months, we have been discussing how to reduce these times to 1 cycle, because every experiment out there wants to multiplex as fast as possible, and the 7/18-delay is a rate limiting step.
** The flux-jumping code was re-arranged in the flux-jumping block to reflect the flow of data through the pipeline and make it easier to understand.

* '''Details:'''

* '''Bugs:'''
** flux-jump does not work when jumping to negative values.

* '''FPGA Resource Usage''' (readout_card.fit.rpt): [[rc_5.0.b_fit_rpt]]
; Total logic elements ; 26,745 / 41,250 ( 65 % ) ;
; Total pins ; 358 / 616 ( 58 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;
; DSP block 9-bit elements ; 76 / 112 ( 68 % ) ;
; Total PLLs ; 1 / 6 ( 17 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;
* '''FPGA Timing Analysis''' (readout_card.tan.rpt): [[rc_5.0.b_tan_rpt]]
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.459 ns
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.895 ns
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 15.956 ns

= Revision 5.0.a =
* '''Filename:'''
** rc_v0500000a_12mar2010.sof

* '''Features:'''
** Based on the merger of rev. 5.0.8 and 5.0.9.
** '''integral_clamp''' command is added where a clamp value is set for the integral term and once the integral term hits that value, the integral-term is clamped to that value and p-term and d-term are clamped to zero. When integral_term=0 then no clamping is in effect, similar to previous releases of firmware.
** The low pass filter has 20-bit input and f_3dB/f_samp = 122Hz/15kHz .
** The flux-jump clamping that was removed in 5.0.9 is included once again here, as we decided this is safer for now.

* '''Details:'''
** "lock_dat_left" parameter that was removed in 5.0.9 is now implemented as "lock_dat_lsb"

* '''Bugs:'''
** flx_lp_init does not reinitialize the flux-jump block

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis
** tag name: rc_v0500000a_12mar2009! years were mixed up!

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
* '''FPGA Timing Analysis''' (readout_card.tan.rpt):

== Revision 5.0.9 (buggy) ==
* '''Filename:'''
** rc_v05000009_13nov2009.sof

* '''Features:'''
** Based on rev. 5.0.4
** Removes a sticky bit in pid calculation result storage -- in fsfb_processor.
** Adds a command to clamp the growth of the I-term to prevent wrapping and track down the source of Caltech's FSFB jumps.
** Removed the unused lock_dat_left parameter. The ability to shift left was moved to the fsfb_corr block some time ago.
** Fixed a sign extension bug acting on the flux quanta, which limited the value to 8191. Changed the extension from signed to unsigned.
** Removed ineffective clamping in the flux-jump calculation block.
** IMPORTANT: Must be used in conjunction with firmware rev. 5.0.0+ of all other cards.

* '''Details:'''

* '''Bugs:'''
** integral_clamp read/write command does not work.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 27,960 / 41,250 ( 68 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.825 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.878 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 14.397 ns ;

== Revision 5.0.8 (UBC only) ==
* '''Filename:'''
** rc_v05000008_09oct2009.sof

* '''Features:'''
** Based on rev. 5.0.4
** type 1 low-pass filter: f3dB=122Hz for fsample=15kHz
** Filter-input-width changed from 18b to 20b with no sticky bits!
** removed sticky bits in internal arithmetic of the filter.

= Revision 5.0.7 (type-2 filter) =
* '''Filename:'''
** rc_v05000007_09oct2009.sof

* '''Features:'''
** Based on rev. 5.0.4
** type-2 low-pass-filter: f3dB=75Hz for fsample=30000.
** Filter-input-width changed from 18b to 20b with no sticky bits!
** inter-biquad-gain-scaling for the filter is 2^14
** filter results are scaled down by 2^3 in the output of the filter.
** removed sticky bits in internal arithmetics
** _correction_ disabled in fsfb_proc_pidz

* '''Details:'''
** quartus.ini file was '''not''' present in synth directory.

* '''Bugs:'''
** none to report

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
== Revision 5.0.6 (UBC only) ==
* '''Filename:'''
** rc_stratix3_v05000006_15sep2009.sof

* '''Features:'''
** Only Valid for Rev. C/D Cards
** Based on rev. 5.0.3
** tcl file updated for Rev. D and aligned with top-level and qsf (project file).
** flux loop commented, just to try sampling the ADC.
** compiled with Q9.1

== Revision 5.0.5 (UBC only) ==
* '''Filename:'''
** rc_v05000005_04sep2009.sof

* '''Features:'''
** Based on rev. 5.0.2
** changed the low-pass-filter to f(3db)=75Hz for f(sample)=30000.

* '''Details:'''
** quartus.ini file was '''not''' present in synth directory.

* '''Bugs:'''
** negative inputs to the filter cause filter to have a non-flat pass-band region. may have to do with sign-handling...

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
* '''FPGA Timing Analysis''' (readout_card.tan.rpt):

= Revision 5.0.4 =
* '''Filename:'''
** rc_v05000004_28aug2009.sof

* '''Features:'''
** Based on rev. 5.0.2
** BUG Fix: handles 14-bit flux quanta (changed the multiplier to unsigned)
** BUG Fix: changed standard logic vector extension from signed to unsigned in flux-jumping slave.
** IMPORTANT: Must be used in conjunction with firmware rev. 5.0.0+ of all other cards.

* '''Details:'''

* '''Bugs:'''
** None so far.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,170 / 41,250 ( 63 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.541 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.612 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 15.398 ns ;

= Revision 5.0.3 =
* '''Filename:'''
** rc_stratix3_v05000003_21aug2009.sof

* '''Features:'''
** ONLY valid REV C/D RC Cards
** Based on rev. 5.0.2
** flux loop commented, just to try sampling the ADC.
** updated tcl file, but still need to rely on project file as well as qsf file.
** changed default level of adc_sclk to '1'
** dac_clr_n was changed from an output to an input.
** added 'locked' interface to rc_pll_stratix_iii
** renamed the adc_pll clock signals to more explanitory names
** added the FPGA_DEVICE_FAMILY generic to the dispatch interace for synthesis of the dc_fifo in lvds_rx
** uncommented DDR interface to force the syntesizer to use correct left and right PLLs (in conjunction with ADC and DDR PLLs)
** added test signals to test_status to see clocks on the scope.
== Revision 5.0.2 (buggy) ==
* '''Filename:'''
** rc_v05000002_test00_tagged.sof

* '''Features:'''
** Based on rev. 5.0.1
** Fixed a bug in wbs_frame_data that stored data incorrectly if reporting 1 or 2 pixels only.
** IMPORTANT: Must be used in conjunction with firmware rev. 5.0.0+ of all other cards.

* '''Details:'''

* '''Bugs:'''
** None so far.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,186 / 41,250 ( 63 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.755 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.979 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.067 ns ;

== Revision 5.0.1 (buggy) (Filter + Raw + Rectangle, 2 LVDS) ==
* '''Filename:'''
** rc_v05000001_26may2009.sof

* '''Features:'''
** Combines features in rev. 5.0.0 (2 LVDS Lines) and rev. 4.0.e (Filtered + Raw), with the NEW rectangle mode.
** IMPORTANT: Must be used in conjunction with firmware rev. 5.0.0+ of all other cards.

* '''Details:'''
** [[CVS Diff Between sys_v05000000 and rc_v05000001]]

* '''Bugs:'''
** Has a bug in wbs_frame_data that stored data incorrectly if reporting 1 or 2 pixels only.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,565 / 41,250 ( 64 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.656 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.861 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 14.167 ns ;

== Revision 5.0.0 (Filter Only, 2 LVDS) ==
* '''Filename:'''
** rc_v05000000_22dec2008.sof (tagged as sys_v05000000_22dec2008)

* '''Features:'''
** IMPORTANT: Must be used in conjunction with firmware v05000000+ of all other cards!!!
** Adds the ability to read out one column of data continuously from readout cards
** Adds data mode 11, which is an engineering mode. Data points are 32-bits, and bits [9..3]=row_index, [2..0]=column_index. This mode is useful for determining which pixels one is reading out in the array, in column mode for example.

* '''Details:'''
** [[CVS Diff Between rc_v0400000c and sys_v05000000]]

* '''Bugs:'''
** None so far.

* '''Synthesis Notes:'''
** The quartus.ini file was not present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,607 / 41,250 ( 65 % ) ;
; Total memory bits ; 406,016 / 3,423,744 ( 12 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.558 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.892 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.987 ns ;

== Revision 4.0.f (Filter + Raw, 1 LVDS) ==
* '''Filename:'''
** rc_v0400000f_12feb2010.sof

* '''Features:'''
** Based on 4.0.e and in parallel with 5.0.9 (equivalent version, clamping is not included)
** Incorporates fixes that were done to flux-jumping between 5.0.2 - 5.0.4 - 5.0.9. Namely:
*** Changes a multiplier from signed to unsigned (in fsfb_corr_multplier.vhd).
*** Changes sign extension from signed to unsigned (in flux_quanta_ram_admin.vhd).

* '''Details:'''

* '''Bugs:'''
** None reported yet.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,773 / 41,250 ( 65 % ) ;
; Total memory bits ; 1,321,984 / 3,423,744 ( 39 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.539 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 4.118 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 17.318 ns ;

== Revision 4.0.e (Filter + Raw, 1 LVDS) ==
* '''Filename:'''
** rc_v0400000e_27apr2009.sof

* '''Features:'''
** Based on 4.0.d
** Combines both raw- and filtered-data modes.
** fpga_temp, card_temp, card_id commands are disabled.
** Tested by Matt Hasselfield.

* '''Details:'''

* '''Bugs:'''
** fpga_temp, card_temp, card_id commands are disabled.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 27,048 / 41,250 ( 66 % ) ;
; Total memory bits ; 1,321,984 / 3,423,744 ( 39 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.675 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.907 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.728 ns ;

== Revision 4.0.d (Raw Only, 1 LVDS) ==
* '''Filename:''' rc_v0400000d_20090417.sof

* '''Features:'''
** Based on v4.0.c, but has the filter removed, and implements a single 65536-index RAM block for storing 50 MHz raw-data samples.
** The firmware takes a new command called readout_col_index which specifies which column to capture raw data from.
** Other than readout_col_index, the firmware functions the same as previous raw-data firmware, including then need to issue a capture_raw command.
** For more information on raw-data, see: http://e-mode.phas.ubc.ca/mcewiki/index.php/Raw-mode_readout
** This firmware also integrates some of the improvements that were implemented in 4.4.0, like the removal of the tga_o signal from an FSM in dispatch_wishbone.vhd.

* '''Details:'''
** Differences between 4.0.c and 4.0.d
U system/test/source/tb/tb_cc_rcs_bcs_ac.vhd
U all_cards/dispatch/source/rtl/dispatch_wishbone.vhd
U library/sys_param/source/rtl/wishbone_pack.vhd
U readout_card/adc_sample_coadd/source/rtl/adc_sample_coadd.vhd
U readout_card/adc_sample_coadd/source/rtl/adc_sample_coadd_pack.vhd
U readout_card/flux_loop/source/rtl/flux_loop.vhd
U readout_card/flux_loop/source/rtl/flux_loop_pack.vhd
U readout_card/flux_loop_ctrl/source/rtl/flux_loop_ctrl.vhd
U readout_card/flux_loop_ctrl/source/rtl/flux_loop_ctrl_pack.vhd
U readout_card/flux_loop_ctrl/source/tb/tb1_flux_loop_ctrl.vhd
U readout_card/flux_loop_ctrl/source/tb/tb2_flux_loop_ctrl.vhd
U readout_card/fsfb_calc/source/rtl/fsfb_fltr_regs.vhd
U readout_card/fsfb_corr/source/rtl/fsfb_corr.vhd
U readout_card/readout_card/source/rtl/readout_card.vhd
U readout_card/readout_card/source/rtl/readout_card_pack.vhd
U readout_card/wbs_frame_data/source/rtl/wbs_frame_data.vhd
U readout_card/wbs_frame_data/source/rtl/wbs_frame_data_pack.vhd

* '''Bugs:'''
** None so far.
** fpga_temp, card_temp, card_id commands are not supported.

* '''Synthesis Notes:'''
** The quartus.ini file was present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 24,554 / 41,250 ( 60 % ) ;
; Total memory bits ; 1,262,592 / 3,423,744 ( 37 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.991 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.864 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 17.052 ns ;

== Revision 4.4.1 ==
* '''Filename:''' rc_v04040001_21nov2008

* '''Features:'''
** Fixes a bug that froze up the firmware if any of the following commands were issued: CARD_ID_ADDR, CARD_TEMP_ADDR, FPGA_TEMP_ADDR in 4.4.0 only.

* '''Details:'''
** The bug fix include adding more logic to the wishbone ack path (readout_card.vhd), which subsequently decreased the minimum clock setup time to 1.588ns. The new logic will catch errors that the old logic wouldn't have, and is now consistent with the firmware on all the other cards. However, if timing becomes an issue, the logic may have to revert back to that which was in version 4.0.c.

* '''Bugs:'''
** None so far.

* '''Synthesis Notes:'''
** The quartus.ini file was not present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 27,241 / 41,250 ( 66 % ) ;
; Total memory bits ; 405,504 / 3,423,744 ( 12 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.588 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.585 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 17.057 ns ;

== Revision 4.4.0 (buggy) ==
* '''Filename:''' rc_v04040000_02oct2008
* '''Features:'''
** Reinstated the data modes in wbs_frame_data.vhd that were removed in 4.0.c. This firmware has the following modes: '''0, 1, 2, 4, 5, 7, 10'''. The modes that are not present are: '''3''' (raw data), '''6''' (replaced by data_mode = 7), '''8''' (replaced by data_mode = 10), '''9''' (replaced by data_mode = 10). For more information on data modes, see [[Data mode]].
** Re-integrated the id_thermo and fpga_thermo block in the readout_card.vhd top level that was removed in 4.0.c.
** Removed the sticky bit in fsfb_corr.vhd, which was enabled when flux-jumping was turned on. Because the feedback is signed, the sticky bit would usually reflect the value of the 14th bit, except in situations when the number of flux quanta to jump was greater than 1 (i.e. cosmic rays, IV-curves, etc). Flux jumps are made at a maximum rate of one per frame period, so that if the First-Stage Feedback increased past the 13th bit, it would not be reflected in the feedback applied. Now it is.
* '''Details:'''
** Simplified the FSM logic in wbs_frame_data.vhd that determines when to transition from IDLE to WSS1. This was done to lower the number of gates in that path, and ease the timing.
** Removed the z_dat_i port in fsfb_processor.vhd and fsfb_calc_pack.vhd to the fsfb_proc_pidz block, in an effort to make it clearer within that block that the z-term is always = 0.
** Removed the z-term sign extension in fsfb_proc_pidz.vhd, and the [d-term + z-term] adder to free up DSP resources since the z-term is always = 0.
** Adjusted the indentation in fsfb_io_controller.vhd to make the file more readable.
** Moved the tga_o signal out of the dispatch_wishbone.vhd FSM, and made it a continuous assignment. This signal had one of the highest fan-out counts in the RTL design, and actually was impossible to route in Stratix III chips in its previous configuration because of the number of gates on the fan-out. As a consequence of making it a continuous assignment, the Stratix III fitter was able to succeed, and the Stratix I timing characteristics were greatly improved. This is the most significant change in this revision. This change single-handedly increased the minimum slack from 1.282 ns in v0400000c to 2.372 ns (or 56.7 MHz max) in this revision.
* '''Bugs:'''
** The following commands lock up the Readout Card firmware: CARD_ID_ADDR, CARD_TEMP_ADDR, FPGA_TEMP_ADDR.
** fb_const0 commands to channel 0 do not work. The value is stored in the register, but not applied to the DAC. Thus, read-back returns the correct value, but the DAC does not
* '''Synthesis Notes:'''
** The quartus.ini file was not present in the synth directory during synthesis.
* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 27,099 / 41,250 ( 66 % ) ;
; Total memory bits ; 406,016 / 3,423,744 ( 12 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.372 ns ;
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 4.052 ns ;
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.066 ns ;

== Revision 4.0.c ==
* '''Filename:''' rc_v0400000c_15aug2008.sof
* '''Features:'''
** Only has data modes 0, 1, 4, and 10.
** Fixed the bug that exists in 4.0.b, 4.0.a, and 4.0.9 that prevented the fb_const value from being applied to channel zero (wbs_fb_data.vhd).
* '''Details:'''
** Changed a counter in the dispatch block to ease timing constraints in synthesis (dispatch_wishbone.vhd)
** Updated the tagged versions of dispatch.vhd , dispatch_cmd_receive.vhd, and dispatch_reply_transmit.vhd to the version that is used by all the other cards.
** '''Removed''' the fpga_termo (command: '''fpga_temp''') and id_thermo (commands: '''card_temp, card_id''') to ease timing constraints in synthesis (readout_card.vhd)
** Updated the tagged version of fpga_termo.vhd to include the new 'stale bit' feature
** Updated the tagged version of frame_timing_core.vhd to include the new 'err_o' interface
* '''Bugs:'''
** None reported yet
* '''Synthesis Notes:'''
** The quartus.ini file was not present in the synth directory during synthesis.
* '''FPGA Resource Usage:'''
Total logic elements : 25,058 / 41,250 ( 61 % )
Total memory bits : 400,896 / 3,423,744 ( 12 % )

* '''Timing Analysis''' (readout_card.tan.rpt):
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.282 ns ;
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.736 ns ;
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.665 ns ;

== Revision 4.0.b (buggy) ==
Note: This revision is on a watch list, after the bug detected 15 July 2008. See the bug section for more details.
* '''Filename''' : rc_v0400000b_04aug2008.sof
* '''Features'''
** data_mode 10 is added to provide more filtfb bits (compared to data mode 9) for planet observations. filtered_dat(27 downto 3) & flux_cnt_dat(6 downto 0)

* '''Bugs'''
** An unexplained bug that appeared in 4.0.a and may still be present in 4.0.b is a problem with the readout of channels being clipped out of data reporting. [[Bug 1 Notes]]

* ''' Synthesis note '''
** Quartus.ini removed.

== Revision 4.0.a (buggy) ==
Note: This revision is on a watch list, after the bug detected 15 July 2008. See the bug section for more details.
* '''Filename''' : rc_v0400000a_07jul2008.sof
* '''Bug Fix'''
** mce_status and adc_offset/flx_quanta commands do not fail after power up.
* ''' Synthesis note '''
** Quartus.ini removed.

* '''Bugs'''
** Seems to clip out channel 0 from data reporting.

== Revision 4.0.9 (buggy) ==
* '''Filename''' : rc_v04000009_26jun2008.sof
* '''Features'''
** sa_bias and offset DACs only refreshed when new values are written. (in previous versions, DACs were refreshed every frame)
* '''Bugs'''
** fb_const0 commands to channel 0 do not work. The value is stored in the register, but not applied to the DAC. Thus, read-back returns the correct value, but the DAC does not.
** reading flx_quanta and adc_offset right after power up hangs the reply datapath to CC. resetmce clears this error as temporary solution. the problem is caused by first read ack of the wishbone slave.

== Revision 4.0.8 ==
* '''Filename''' : rc_v04000008_26jun2008.sof
* '''Features'''
** The gaini, gainp, gaind resolution increased to 12-bit, i.e. -2048 to 2047 (formerly 10-bit).

* '''Bug fix'''
** the bug associated with gainpid read before mce_reset is fixed.

* ''' Synthesis note '''
** Quartus.ini removed.

== Revision 4.3.7 ==
* '''Filename''' : rc_v04030007_26may2008_raw.sof
* '''Features'''
** 14-bit raw mode enabled to buffer a snapshot of 50MHz samples for 2 frames of row_len * num_rows samples.
** In order to extend the raw-mode to 14-bit, an assumption is made that the raw buffer is not written to while being read. Therefore, make sure there is at least 2*row_len*num_rows*20ns between issuing captr_raw command and reading back the raw data.
** In order to save RAM for raw mode, two memory-intensive features are disabled:
*** low-pass filter disabled ( mixed filtfb data modes 6, 7, 9 are also disabled)
*** PID (gainp0, gaini0, gaind0) readback disabled. one can still set PID values and run servo, but can not read back the values.

== Revision 4.2.7 ==
* '''Filename''' : rc_v04020007_24may2008_raw.sof
* '''Features'''
** raw mode enabled to buffer a snapshot of 50MHz samples for 2 frames of row_len * num_rows samples.
** In order to save RAM for raw mode, two memory-intensive features are disabled:
*** low-pass filter disabled ( mixed filtfb data modes 6, 7, 9 are also disabled)
*** PID (gainp0, gaini0, gaind0) readback disabled. one can still set PID values and run servo, but can not read back the values.
* '''Bug fix'''
** the bug associated with reading from raw-buffer is fixed.

== Revision 4.1.7 ==
* '''Filename''' : rc_v04010007_25apr2008_raw.sof
* '''Features'''
** raw mode enabled to buffer a snapshot of 50MHz samples for 2 frames of row_len * num_rows samples.
** In order to save RAM for raw mode, two memory-intensive features are disabled:
*** low-pass filter disabled ( mixed filtfb data modes 6, 7, 9 are also disabled)
*** PID (gainp0, gaini0, gaind0) readback disabled. one can still set PID values and run servo, but can not read back the values.
* '''Bugs'''
** after each readout frame, raw-buffer readout counter falls behind by 3 and this causes skipping 3 50MHz samples in the data stream and column-data being messed up in subsequent frames. Data can be rearranged by post processing.

== Revision 4.0.6 (buggy) ==
* '''Filename''' : rc_v04000006_15feb2008.sof or .pof
* '''Features'''
** '''bugfix''': unreliable reset due to unsafe and incomplete state machines is fixed.
** '''bugfix''': flux_jump sign problem fixed, so far proved in const_mode, to be tested in servo_mode with cold setup.
** servo_mode=2 or ramp previously only went from 0 to ramp_amp, but now goes from -8192 to -8192+ramp_amp
** new commands are added: ''scratch'' and ''card_type''. Scratch takes 8 values and can be used by software to detect reset.
** slot_id and fw_rev are now integrated as part of all_cards.vhd
** lvds_tx_b=0, This will allow Clock Card to use the secondary backplane lvds line and check whether RC is plugged in.
** filter_coeff in misc_banks_admin commented as it is not implemented and causes timing problems.

* '''Bugs'''
** reading gainp/gaini/gaind right after power up hangs the reply datapath to CC. resetmce clears this error as temporary solution. the problem is caused by first read ack of pid_ram_admin.
** slot_id is only set after a resetmce is issued. (using the latest all_cards in the next revision will fix this)
** has spurious spikes on channel 7 data, which max out the integral, and cause the detectors to come unlocked. This firmware officially meets timing requirements, but the bug could be due to marginal timing on the longest data paths, i.e. ~0.1 ns in some cases.

== Revision 4.0.5 ==
* '''Filename''' : rc_v04000005_01nov2007.sof or .pof
* '''Features'''
** data mode 9 (mixed filt + flux jump) with windowing readjusted compared to data mode 8

* '''Bugs'''
** unreliable resetmce. Sometimes, firmware waked up non-responsive on lvds lines.
** In data mode 5 and 9, flux-jump counter is not reported properly due to a sign error. However, flux jumping works fine.

== Revision 3.0.19 ==
* '''Filename''' : rc_v03000019_16feb2007_raw.sof (no pof as one is not likely to run with this as regular firmware)
* '''Features'''
** data mode 3 is enabled.
** filter is disabled as a compromise to fit the raw-mode buffer.

* '''Bugs'''
** unreliable resetmce. Sometimes, firmware waked up non-responsive on lvds lines.

== Old Firmware Revisions ==
* '''4.0.4''': rc_v04000004_11oct2007.sof data mode 8 added (mixed filt + flux jump)
* '''4.0.3''': rc_v04000003_19sep2007.sof data mode 7 bit split readjusted to 10b error being bit 4 to 14
* '''4.0.2''': rc_v04000002_11sep2007.sof pid resolution increased to 10b, data mode 7 added
* '''4.0.1''': rc_v04000001_06sep2007.sof
* '''4.0.0''': rc_v04000000_29aug2007.sof supports readout_row_index * [[ bugs ]]

= To-Do List =
* the starting point for the servo is currently zero and it would be nice to have it programmable.

= RC Synthesis Notes =
# The following note applies when using Quartus versions earlier than Q7: Quartus.ini file had to exist in synth directory up to revision 4.0.a due to a bug that started in Quartus 6.1 and would synthesize away arbitrary parts of readout card. We contacted Altera at the time and they provided us the ini file.
# Timing: There is no "lock region" defined for readout card. Timing on readout card is tight and since version 3 or so any new feature would initially fail timing till some synthesis options were tweaked. One path that remains to be consistently marginal is from addr_gen counter (i.e. tga_o counter) in dispatch_wishbone.vhd to wishbone slaves particularly misc_banks_admin.vhd. Modules that are rewritten to address timing concerns are fsfb_corr, all_cards, misc_banks_admin, and finally instantiating an lpm counter instead of a counter from components library. Surprisingly, the lpm counter reduced 87 failures to 37, although looking at the technology map viewer, it seemed that they were both synthesized the same.
# Compile time: This was at some point 4.5 hours, after going to dual core PC, this was reduced to 35 minutes. After extending pid gains to 12b and fixing offset/sa_bias update code, the compile time increased to 1.5hr again with utilization up to ~70%.
# wbs_fb_storage, ram_8x64, pid_ram had to be regenerated using latest (Q7.2) MegaWizard to get rid of the bug associated with failure to read after power up until a reset was issued.
# During simulations, the initialization of RAM block with .hex files needs to be disabled. This is done by commenting out the following lines from the MegaWizard generated Megafunction files (remember to un-comment them before synthesizing the code):
lpm_file => "C:/scuba2_repository/cards/readout_card/fsfb_calc/source/rtl/ram_40x64.hex", and
lpm_file : STRING;
#Starting Q10.0 use TimeQuest timing analyzer as oppose to the classic one. The classic one is being phased out by Altera. In order to use TimeQuest, you need to have an sdc file present in your project directory.
----
[http://e-mode.phas.ubc.ca/mcewiki/index.php/Main_Page MCE Main Page]

Readout Card firmware

2011-05-04T21:46:57Z

Bburger: /* Revision 5.0.f */

* Synthesis Reminders (for firmware developers)
** quartus.ini is not needed anymore (Fixed as of Q7, Altera SR10783580 2010-10-24)
** Remember that readout_card/fsfb_clac/source/rtl/ram_40x64.vhd must be initialized with the ram_40x64.hex file in the same directory.
= Revision 5.1.2 =
* '''Filename:'''
** rc_stratix3_v05010002_18jan2011.sof (for Rev. E cards)
** rc_stratix3_v05010002_18jan2011.jic (for Rev. E cards)
** rc_v05010002_03feb2011.sof (for Rev. B cards)
** rc_v05010002_03feb2011.pof (for Rev. B cards)

* '''Features:'''
** based on 5.1.1 with k1 and k2 (filter params) limited to k1<16 and k2<32 in order to resolve the timing when compiling for smaller Stratix FPGA on RC Rev. B.

* '''Bug fix:'''
** the 2-rows-off filtered data readout introduced with configurable filter in rev. 5.1.0 and 5.1.1 is fixed now.

* '''Bugs:'''
** none so far.

* '''FPGA Resource Usage''' (readout_card.fit.rpt)
; Total logic elements ; 33,285 / 41,250 ( 81 % ) ;
; Total pins ; 358 / 616 ( 58 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt)
; Fast Model Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 6.591 ns
; Fast Model Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 7.206 ns
; Fast Model Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 18.299 ns

== Revision 5.1.1 (not recommended) ==
* '''Filename:'''
** rc_v05010001_01dec2010.sof (for Rev. B cards)

* '''Features:'''
** based on 5.1.0, but k1 and k2 (filter params) are now limited to k1<16 and k2<32 in order to resolve the timing failures of compiling 5.1.0 for smaller Stratix FPGA on RC Rev. B.

* '''Bugs:'''
** filter mode data is off by 2 rows.

== Revision 5.1.0 (not recommended) ==
* '''Filename:'''
** rc_stratix3_v05010000_01nov2010.sof (for Rev. E cards)
** rc_v05010000_01nov2010.sof (for Rev. B cards) has timing failures '''do not use!!!'''

* '''Features:'''
** added configurable filter parameters specified by ''fltr_coeff'', default is the fcutoff/fsampl=122Hz/15kHz. see [[ Digital 4-pole Butterworth Low-pass filter ]].
** ''fltr_type'' is set to 255 to indicate configurable filter parameters.
** see [http://www.phas.ubc.ca/~mce/mcedocs/software/SC2_ELE_S580_515_mce_command_description.pdf MCE command description]
** development notes:
*** It is built on Quartus10.1.
*** tcl files had to be updated as cmp syntax is not supported in Q10 anymore.
*** Rev. E cards now can be identified by reading back pcb_rev as part of card_type, therefore both stratix I and III sof/pof/jic are generated from the same source.

* '''Bugs:'''
** rc_v05010000_01nov2010.sof has timing failures that were overlooked, do not use this firmware for Rev.B cards.
** '''filter mode data is off by 2 rows.'''

* '''FPGA Resource Usage and Timing Report''' (readout_card.fit.rpt and readout_card.tan.rpt): logic usage is upto 85% from 66% in 5.0.d/e/f

= Revision 5.0.f =
* '''Filename:'''
** rc_v0500000f_22oct2010.sof (for Rev. B cards)
** rc_stratix3_v0500000f_22oct2010.sof (for Rev. E cards)

* '''Features:'''
** Bugfix: integral clamp should work now. only positive integral_clamp values are valid!

* '''Details:''':
** SQ1FB is applied 18 clock cycles after start of a row visit (SQ1_Bias being applied) regardless of flux-jump being enabled or not. In pre-5.0.b firmware SQ1FB was being applied after 7 clock cycles when flux-jump was disabled and after 18 clock cycles when flux-jump was enabled.
** available for both Rev. E and Rev. B cards, the upper byte of card_type parameter now reports the pcb revision.
** development note: It is built on Quartus10.1.

* '''Bugs:'''
**none yet!

* '''FPGA Resource Usage and Timing Report''' (readout_card.fit.rpt and readout_card.tan.rpt): no change compared to 5.0.a/b/c/d

== Revision 5.0.e (not recommended) ==
* '''Filename:'''
** rc_v0500000e_06oct2010.sof

* '''Details:'''
** an unsuccessful attempt to fix integral_clamp, but changed the functionality so that it clamps at the value, but it doesn't hold the clamp. i.e., if the calculated sq1fb becomes less than the specified clamp value, the sq1fb is not clamped anymore. This is not a desired functionality!

== Revision 5.0.d ==
* '''Filename:'''
** rc_v0500000d_04aug2010.sof

* '''Features:'''
** Bugfix: To fix the bug associated with negative flux-jumps, reverted to signed multiplier and hence, incremented the width of the flux-quanta multiplier input by 1.

* '''Details:''': SQ1FB is applied 18 clock cycles after start of a row visit (SQ1_Bias being applied) regardless of flux-jump being enabled or not. In pre-5.0.b firmware SQ1FB was being applied after 7 clock cycles when flux-jump was disabled and after 18 clock cycles when flux-jump was enabled.

* '''Bugs:'''
** '''integral_clamping is broken'''. To test the clamping, a servo-locked ramp was initiated on the sq1fb and then flux-jumping was turned on and observed by attaching a scope to the SQ1FB output. With integral_clamp=80000000, flux_quanta=8000, gaini=1, flux-jump enabled, we see [[http://e-mode.phas.ubc.ca/mcewiki/index.php/Image:Clamp_unstable.png scope snapshot]] used slow_fb_ramp.py script for testing.

* '''FPGA Resource Usage and Timing Report''' (readout_card.fit.rpt and readout_card.tan.rpt): no change compared to 5.0.a/b/c

== Revision 5.0.c (not recommended) ==
* '''Filename:'''
** rc_v0500000c_16jun2010.sof

* '''Features:'''
** Based on rev. 5.0.b
** Re-introduced flux-jump counter clamping to maintain continuity in behavior from past versions of firmware in the field.
** '''Important''': SQ1FB is applied 18 clock cycles after start of a row visit (SQ1_Bias being applied) regardless of flux-jump being enabled or not. In pre-5.0.b firmware SQ1FB was being applied after 7 clock cycles when flux-jump was disabled and after 18 clock cycles when flux-jump was enabled.

* '''Details:'''
* '''Bugs:'''
** '''flux-jump is broken'''. flux-jumping block misbehaves at the first jump in the negative range.

* '''FPGA Resource Usage''' (readout_card.fit.rpt): [[rc_5.0.c_fit_rpt]]
; Total logic elements ; 26,800 / 41,250 ( 65 % ) ;
; Total pins ; 358 / 616 ( 58 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;
; DSP block 9-bit elements ; 76 / 112 ( 68 % ) ;
; Total PLLs ; 1 / 6 ( 17 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt): [[rc_5.0.c_tan_rpt]]
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.964 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 4.382 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 15.924 ns ;

== Revision 5.0.b (not recommended) ==
* '''Filename:'''
** rc_v0500000b_03jun2010.sof

* '''Features:'''
** Based on rev. 5.0.a
** A bug that caused jumps in first-stage feedback, and detected as spikes in the raw data of pixels that were in servo_mode=0,1,2 was fixed. The jumps in FSFB were due to flux-jumping being enabled on live pixes with non-zero flx_quanta, and being disabled on the fly on dead pixels with flx_quanta=0. Flux-jumping is now disabled on a column-by-column basis if a column is in servo_mode = 0,1,2.
** Ineffective clamping was removed from the flux-jumping block (as per 5.0.9), as it is now replaced by the clamping that was perfected in rev. 5.0.10
** A sticky bit that only affected servo_mode=0,1,2 was also removed from the flux-jumping block.
** flx_lp_init commands now also clear the flux-jumping block as well.
** The 11-clock-cycle delay (in applying SQ1_FB) that in previous firmware only occurred when flux-jumping was enabled, now (in this version) is in effect all the time. Due to the bug-fix above, flux-jumping can be disabled on a column-by-column basis by setting servo_mode=0,1,2 when en_fb_jump=1. Before the change, this meant that constant values could be applied with or without the 11-cycle delay if en_fb_jump=1 or 0. To make the delay consistent, it is now always 11 cycles. As background, the flux-jumping block is pipelined, meaning that it does calculations for all 8 channels serially. The serialization is because of DSP-block limitations in the Readout Card FPGA that prevent us from doing all 8 channels in parallel. The reason that it takes 11 cycles to complete the flux-jumping calculations is because the values are computed for the eight channels in three ALU stages: 8 + 3 = 11 cycles. Adding 11 cycles to the 7 cycles of latency from other stages in the system results in: 11 + 7 = 18 cycles of latency from the start of a row dwell period before the first-stage feedback is applied. In rc_v5.0.c, I enforce the 18-cycle delay even when flux-jumping is not enabled to maintain uniformity across all eight channels, because flux-jumping is enabled/disabled on a per-channel basis. In other words, if I hadn't enforced the 18-cycle delay, some channels could have their feedback applied after 7 cycles, while others could have it applied after 18 cycles. I wasn't a fan of this non-uniformity. I realize that 18 cycles is a long time. In fact, so is 7. In the last few months, we have been discussing how to reduce these times to 1 cycle, because every experiment out there wants to multiplex as fast as possible, and the 7/18-delay is a rate limiting step.
** The flux-jumping code was re-arranged in the flux-jumping block to reflect the flow of data through the pipeline and make it easier to understand.

* '''Details:'''

* '''Bugs:'''
** flux-jump does not work when jumping to negative values.

* '''FPGA Resource Usage''' (readout_card.fit.rpt): [[rc_5.0.b_fit_rpt]]
; Total logic elements ; 26,745 / 41,250 ( 65 % ) ;
; Total pins ; 358 / 616 ( 58 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;
; DSP block 9-bit elements ; 76 / 112 ( 68 % ) ;
; Total PLLs ; 1 / 6 ( 17 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;
* '''FPGA Timing Analysis''' (readout_card.tan.rpt): [[rc_5.0.b_tan_rpt]]
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.459 ns
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.895 ns
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 15.956 ns

= Revision 5.0.a =
* '''Filename:'''
** rc_v0500000a_12mar2010.sof

* '''Features:'''
** Based on the merger of rev. 5.0.8 and 5.0.9.
** '''integral_clamp''' command is added where a clamp value is set for the integral term and once the integral term hits that value, the integral-term is clamped to that value and p-term and d-term are clamped to zero. When integral_term=0 then no clamping is in effect, similar to previous releases of firmware.
** The low pass filter has 20-bit input and f_3dB/f_samp = 122Hz/15kHz .
** The flux-jump clamping that was removed in 5.0.9 is included once again here, as we decided this is safer for now.

* '''Details:'''
** "lock_dat_left" parameter that was removed in 5.0.9 is now implemented as "lock_dat_lsb"

* '''Bugs:'''
** flx_lp_init does not reinitialize the flux-jump block

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis
** tag name: rc_v0500000a_12mar2009! years were mixed up!

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
* '''FPGA Timing Analysis''' (readout_card.tan.rpt):

== Revision 5.0.9 (buggy) ==
* '''Filename:'''
** rc_v05000009_13nov2009.sof

* '''Features:'''
** Based on rev. 5.0.4
** Removes a sticky bit in pid calculation result storage -- in fsfb_processor.
** Adds a command to clamp the growth of the I-term to prevent wrapping and track down the source of Caltech's FSFB jumps.
** Removed the unused lock_dat_left parameter. The ability to shift left was moved to the fsfb_corr block some time ago.
** Fixed a sign extension bug acting on the flux quanta, which limited the value to 8191. Changed the extension from signed to unsigned.
** Removed ineffective clamping in the flux-jump calculation block.
** IMPORTANT: Must be used in conjunction with firmware rev. 5.0.0+ of all other cards.

* '''Details:'''

* '''Bugs:'''
** integral_clamp read/write command does not work.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 27,960 / 41,250 ( 68 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.825 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.878 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 14.397 ns ;

== Revision 5.0.8 (UBC only) ==
* '''Filename:'''
** rc_v05000008_09oct2009.sof

* '''Features:'''
** Based on rev. 5.0.4
** type 1 low-pass filter: f3dB=122Hz for fsample=15kHz
** Filter-input-width changed from 18b to 20b with no sticky bits!
** removed sticky bits in internal arithmetic of the filter.

= Revision 5.0.7 (type-2 filter) =
* '''Filename:'''
** rc_v05000007_09oct2009.sof

* '''Features:'''
** Based on rev. 5.0.4
** type-2 low-pass-filter: f3dB=75Hz for fsample=30000.
** Filter-input-width changed from 18b to 20b with no sticky bits!
** inter-biquad-gain-scaling for the filter is 2^14
** filter results are scaled down by 2^3 in the output of the filter.
** removed sticky bits in internal arithmetics
** _correction_ disabled in fsfb_proc_pidz

* '''Details:'''
** quartus.ini file was '''not''' present in synth directory.

* '''Bugs:'''
** none to report

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
== Revision 5.0.6 (UBC only) ==
* '''Filename:'''
** rc_stratix3_v05000006_15sep2009.sof

* '''Features:'''
** Only Valid for Rev. C/D Cards
** Based on rev. 5.0.3
** tcl file updated for Rev. D and aligned with top-level and qsf (project file).
** flux loop commented, just to try sampling the ADC.
** compiled with Q9.1

== Revision 5.0.5 (UBC only) ==
* '''Filename:'''
** rc_v05000005_04sep2009.sof

* '''Features:'''
** Based on rev. 5.0.2
** changed the low-pass-filter to f(3db)=75Hz for f(sample)=30000.

* '''Details:'''
** quartus.ini file was '''not''' present in synth directory.

* '''Bugs:'''
** negative inputs to the filter cause filter to have a non-flat pass-band region. may have to do with sign-handling...

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
* '''FPGA Timing Analysis''' (readout_card.tan.rpt):

= Revision 5.0.4 =
* '''Filename:'''
** rc_v05000004_28aug2009.sof

* '''Features:'''
** Based on rev. 5.0.2
** BUG Fix: handles 14-bit flux quanta (changed the multiplier to unsigned)
** BUG Fix: changed standard logic vector extension from signed to unsigned in flux-jumping slave.
** IMPORTANT: Must be used in conjunction with firmware rev. 5.0.0+ of all other cards.

* '''Details:'''

* '''Bugs:'''
** None so far.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,170 / 41,250 ( 63 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.541 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.612 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 15.398 ns ;

= Revision 5.0.3 =
* '''Filename:'''
** rc_stratix3_v05000003_21aug2009.sof

* '''Features:'''
** ONLY valid REV C/D RC Cards
** Based on rev. 5.0.2
** flux loop commented, just to try sampling the ADC.
** updated tcl file, but still need to rely on project file as well as qsf file.
** changed default level of adc_sclk to '1'
** dac_clr_n was changed from an output to an input.
** added 'locked' interface to rc_pll_stratix_iii
** renamed the adc_pll clock signals to more explanitory names
** added the FPGA_DEVICE_FAMILY generic to the dispatch interace for synthesis of the dc_fifo in lvds_rx
** uncommented DDR interface to force the syntesizer to use correct left and right PLLs (in conjunction with ADC and DDR PLLs)
** added test signals to test_status to see clocks on the scope.
== Revision 5.0.2 (buggy) ==
* '''Filename:'''
** rc_v05000002_test00_tagged.sof

* '''Features:'''
** Based on rev. 5.0.1
** Fixed a bug in wbs_frame_data that stored data incorrectly if reporting 1 or 2 pixels only.
** IMPORTANT: Must be used in conjunction with firmware rev. 5.0.0+ of all other cards.

* '''Details:'''

* '''Bugs:'''
** None so far.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,186 / 41,250 ( 63 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.755 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.979 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.067 ns ;

== Revision 5.0.1 (buggy) (Filter + Raw + Rectangle, 2 LVDS) ==
* '''Filename:'''
** rc_v05000001_26may2009.sof

* '''Features:'''
** Combines features in rev. 5.0.0 (2 LVDS Lines) and rev. 4.0.e (Filtered + Raw), with the NEW rectangle mode.
** IMPORTANT: Must be used in conjunction with firmware rev. 5.0.0+ of all other cards.

* '''Details:'''
** [[CVS Diff Between sys_v05000000 and rc_v05000001]]

* '''Bugs:'''
** Has a bug in wbs_frame_data that stored data incorrectly if reporting 1 or 2 pixels only.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,565 / 41,250 ( 64 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.656 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.861 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 14.167 ns ;

== Revision 5.0.0 (Filter Only, 2 LVDS) ==
* '''Filename:'''
** rc_v05000000_22dec2008.sof (tagged as sys_v05000000_22dec2008)

* '''Features:'''
** IMPORTANT: Must be used in conjunction with firmware v05000000+ of all other cards!!!
** Adds the ability to read out one column of data continuously from readout cards
** Adds data mode 11, which is an engineering mode. Data points are 32-bits, and bits [9..3]=row_index, [2..0]=column_index. This mode is useful for determining which pixels one is reading out in the array, in column mode for example.

* '''Details:'''
** [[CVS Diff Between rc_v0400000c and sys_v05000000]]

* '''Bugs:'''
** None so far.

* '''Synthesis Notes:'''
** The quartus.ini file was not present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,607 / 41,250 ( 65 % ) ;
; Total memory bits ; 406,016 / 3,423,744 ( 12 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.558 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.892 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.987 ns ;

== Revision 4.0.f (Filter + Raw, 1 LVDS) ==
* '''Filename:'''
** rc_v0400000f_12feb2010.sof

* '''Features:'''
** Based on 4.0.e and in parallel with 5.0.9 (equivalent version, clamping is not included)
** Incorporates fixes that were done to flux-jumping between 5.0.2 - 5.0.4 - 5.0.9. Namely:
*** Changes a multiplier from signed to unsigned (in fsfb_corr_multplier.vhd).
*** Changes sign extension from signed to unsigned (in flux_quanta_ram_admin.vhd).

* '''Details:'''

* '''Bugs:'''
** None reported yet.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,773 / 41,250 ( 65 % ) ;
; Total memory bits ; 1,321,984 / 3,423,744 ( 39 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.539 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 4.118 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 17.318 ns ;

== Revision 4.0.e (Filter + Raw, 1 LVDS) ==
* '''Filename:'''
** rc_v0400000e_27apr2009.sof

* '''Features:'''
** Based on 4.0.d
** Combines both raw- and filtered-data modes.
** fpga_temp, card_temp, card_id commands are disabled.
** Tested by Matt Hasselfield.

* '''Details:'''

* '''Bugs:'''
** fpga_temp, card_temp, card_id commands are disabled.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 27,048 / 41,250 ( 66 % ) ;
; Total memory bits ; 1,321,984 / 3,423,744 ( 39 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.675 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.907 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.728 ns ;

== Revision 4.0.d (Raw Only, 1 LVDS) ==
* '''Filename:''' rc_v0400000d_20090417.sof

* '''Features:'''
** Based on v4.0.c, but has the filter removed, and implements a single 65536-index RAM block for storing 50 MHz raw-data samples.
** The firmware takes a new command called readout_col_index which specifies which column to capture raw data from.
** Other than readout_col_index, the firmware functions the same as previous raw-data firmware, including then need to issue a capture_raw command.
** For more information on raw-data, see: http://e-mode.phas.ubc.ca/mcewiki/index.php/Raw-mode_readout
** This firmware also integrates some of the improvements that were implemented in 4.4.0, like the removal of the tga_o signal from an FSM in dispatch_wishbone.vhd.

* '''Details:'''
** Differences between 4.0.c and 4.0.d
U system/test/source/tb/tb_cc_rcs_bcs_ac.vhd
U all_cards/dispatch/source/rtl/dispatch_wishbone.vhd
U library/sys_param/source/rtl/wishbone_pack.vhd
U readout_card/adc_sample_coadd/source/rtl/adc_sample_coadd.vhd
U readout_card/adc_sample_coadd/source/rtl/adc_sample_coadd_pack.vhd
U readout_card/flux_loop/source/rtl/flux_loop.vhd
U readout_card/flux_loop/source/rtl/flux_loop_pack.vhd
U readout_card/flux_loop_ctrl/source/rtl/flux_loop_ctrl.vhd
U readout_card/flux_loop_ctrl/source/rtl/flux_loop_ctrl_pack.vhd
U readout_card/flux_loop_ctrl/source/tb/tb1_flux_loop_ctrl.vhd
U readout_card/flux_loop_ctrl/source/tb/tb2_flux_loop_ctrl.vhd
U readout_card/fsfb_calc/source/rtl/fsfb_fltr_regs.vhd
U readout_card/fsfb_corr/source/rtl/fsfb_corr.vhd
U readout_card/readout_card/source/rtl/readout_card.vhd
U readout_card/readout_card/source/rtl/readout_card_pack.vhd
U readout_card/wbs_frame_data/source/rtl/wbs_frame_data.vhd
U readout_card/wbs_frame_data/source/rtl/wbs_frame_data_pack.vhd

* '''Bugs:'''
** None so far.
** fpga_temp, card_temp, card_id commands are not supported.

* '''Synthesis Notes:'''
** The quartus.ini file was present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 24,554 / 41,250 ( 60 % ) ;
; Total memory bits ; 1,262,592 / 3,423,744 ( 37 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.991 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.864 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 17.052 ns ;

== Revision 4.4.1 ==
* '''Filename:''' rc_v04040001_21nov2008

* '''Features:'''
** Fixes a bug that froze up the firmware if any of the following commands were issued: CARD_ID_ADDR, CARD_TEMP_ADDR, FPGA_TEMP_ADDR in 4.4.0 only.

* '''Details:'''
** The bug fix include adding more logic to the wishbone ack path (readout_card.vhd), which subsequently decreased the minimum clock setup time to 1.588ns. The new logic will catch errors that the old logic wouldn't have, and is now consistent with the firmware on all the other cards. However, if timing becomes an issue, the logic may have to revert back to that which was in version 4.0.c.

* '''Bugs:'''
** None so far.

* '''Synthesis Notes:'''
** The quartus.ini file was not present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 27,241 / 41,250 ( 66 % ) ;
; Total memory bits ; 405,504 / 3,423,744 ( 12 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.588 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.585 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 17.057 ns ;

== Revision 4.4.0 (buggy) ==
* '''Filename:''' rc_v04040000_02oct2008
* '''Features:'''
** Reinstated the data modes in wbs_frame_data.vhd that were removed in 4.0.c. This firmware has the following modes: '''0, 1, 2, 4, 5, 7, 10'''. The modes that are not present are: '''3''' (raw data), '''6''' (replaced by data_mode = 7), '''8''' (replaced by data_mode = 10), '''9''' (replaced by data_mode = 10). For more information on data modes, see [[Data mode]].
** Re-integrated the id_thermo and fpga_thermo block in the readout_card.vhd top level that was removed in 4.0.c.
** Removed the sticky bit in fsfb_corr.vhd, which was enabled when flux-jumping was turned on. Because the feedback is signed, the sticky bit would usually reflect the value of the 14th bit, except in situations when the number of flux quanta to jump was greater than 1 (i.e. cosmic rays, IV-curves, etc). Flux jumps are made at a maximum rate of one per frame period, so that if the First-Stage Feedback increased past the 13th bit, it would not be reflected in the feedback applied. Now it is.
* '''Details:'''
** Simplified the FSM logic in wbs_frame_data.vhd that determines when to transition from IDLE to WSS1. This was done to lower the number of gates in that path, and ease the timing.
** Removed the z_dat_i port in fsfb_processor.vhd and fsfb_calc_pack.vhd to the fsfb_proc_pidz block, in an effort to make it clearer within that block that the z-term is always = 0.
** Removed the z-term sign extension in fsfb_proc_pidz.vhd, and the [d-term + z-term] adder to free up DSP resources since the z-term is always = 0.
** Adjusted the indentation in fsfb_io_controller.vhd to make the file more readable.
** Moved the tga_o signal out of the dispatch_wishbone.vhd FSM, and made it a continuous assignment. This signal had one of the highest fan-out counts in the RTL design, and actually was impossible to route in Stratix III chips in its previous configuration because of the number of gates on the fan-out. As a consequence of making it a continuous assignment, the Stratix III fitter was able to succeed, and the Stratix I timing characteristics were greatly improved. This is the most significant change in this revision. This change single-handedly increased the minimum slack from 1.282 ns in v0400000c to 2.372 ns (or 56.7 MHz max) in this revision.
* '''Bugs:'''
** The following commands lock up the Readout Card firmware: CARD_ID_ADDR, CARD_TEMP_ADDR, FPGA_TEMP_ADDR.
** fb_const0 commands to channel 0 do not work. The value is stored in the register, but not applied to the DAC. Thus, read-back returns the correct value, but the DAC does not
* '''Synthesis Notes:'''
** The quartus.ini file was not present in the synth directory during synthesis.
* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 27,099 / 41,250 ( 66 % ) ;
; Total memory bits ; 406,016 / 3,423,744 ( 12 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.372 ns ;
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 4.052 ns ;
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.066 ns ;

== Revision 4.0.c ==
* '''Filename:''' rc_v0400000c_15aug2008.sof
* '''Features:'''
** Only has data modes 0, 1, 4, and 10.
** Fixed the bug that exists in 4.0.b, 4.0.a, and 4.0.9 that prevented the fb_const value from being applied to channel zero (wbs_fb_data.vhd).
* '''Details:'''
** Changed a counter in the dispatch block to ease timing constraints in synthesis (dispatch_wishbone.vhd)
** Updated the tagged versions of dispatch.vhd , dispatch_cmd_receive.vhd, and dispatch_reply_transmit.vhd to the version that is used by all the other cards.
** '''Removed''' the fpga_termo (command: '''fpga_temp''') and id_thermo (commands: '''card_temp, card_id''') to ease timing constraints in synthesis (readout_card.vhd)
** Updated the tagged version of fpga_termo.vhd to include the new 'stale bit' feature
** Updated the tagged version of frame_timing_core.vhd to include the new 'err_o' interface
* '''Bugs:'''
** None reported yet
* '''Synthesis Notes:'''
** The quartus.ini file was not present in the synth directory during synthesis.
* '''FPGA Resource Usage:'''
Total logic elements : 25,058 / 41,250 ( 61 % )
Total memory bits : 400,896 / 3,423,744 ( 12 % )

* '''Timing Analysis''' (readout_card.tan.rpt):
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.282 ns ;
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.736 ns ;
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.665 ns ;

== Revision 4.0.b (buggy) ==
Note: This revision is on a watch list, after the bug detected 15 July 2008. See the bug section for more details.
* '''Filename''' : rc_v0400000b_04aug2008.sof
* '''Features'''
** data_mode 10 is added to provide more filtfb bits (compared to data mode 9) for planet observations. filtered_dat(27 downto 3) & flux_cnt_dat(6 downto 0)

* '''Bugs'''
** An unexplained bug that appeared in 4.0.a and may still be present in 4.0.b is a problem with the readout of channels being clipped out of data reporting. [[Bug 1 Notes]]

* ''' Synthesis note '''
** Quartus.ini removed.

== Revision 4.0.a (buggy) ==
Note: This revision is on a watch list, after the bug detected 15 July 2008. See the bug section for more details.
* '''Filename''' : rc_v0400000a_07jul2008.sof
* '''Bug Fix'''
** mce_status and adc_offset/flx_quanta commands do not fail after power up.
* ''' Synthesis note '''
** Quartus.ini removed.

* '''Bugs'''
** Seems to clip out channel 0 from data reporting.

== Revision 4.0.9 (buggy) ==
* '''Filename''' : rc_v04000009_26jun2008.sof
* '''Features'''
** sa_bias and offset DACs only refreshed when new values are written. (in previous versions, DACs were refreshed every frame)
* '''Bugs'''
** fb_const0 commands to channel 0 do not work. The value is stored in the register, but not applied to the DAC. Thus, read-back returns the correct value, but the DAC does not.
** reading flx_quanta and adc_offset right after power up hangs the reply datapath to CC. resetmce clears this error as temporary solution. the problem is caused by first read ack of the wishbone slave.

== Revision 4.0.8 ==
* '''Filename''' : rc_v04000008_26jun2008.sof
* '''Features'''
** The gaini, gainp, gaind resolution increased to 12-bit, i.e. -2048 to 2047 (formerly 10-bit).

* '''Bug fix'''
** the bug associated with gainpid read before mce_reset is fixed.

* ''' Synthesis note '''
** Quartus.ini removed.

== Revision 4.3.7 ==
* '''Filename''' : rc_v04030007_26may2008_raw.sof
* '''Features'''
** 14-bit raw mode enabled to buffer a snapshot of 50MHz samples for 2 frames of row_len * num_rows samples.
** In order to extend the raw-mode to 14-bit, an assumption is made that the raw buffer is not written to while being read. Therefore, make sure there is at least 2*row_len*num_rows*20ns between issuing captr_raw command and reading back the raw data.
** In order to save RAM for raw mode, two memory-intensive features are disabled:
*** low-pass filter disabled ( mixed filtfb data modes 6, 7, 9 are also disabled)
*** PID (gainp0, gaini0, gaind0) readback disabled. one can still set PID values and run servo, but can not read back the values.

== Revision 4.2.7 ==
* '''Filename''' : rc_v04020007_24may2008_raw.sof
* '''Features'''
** raw mode enabled to buffer a snapshot of 50MHz samples for 2 frames of row_len * num_rows samples.
** In order to save RAM for raw mode, two memory-intensive features are disabled:
*** low-pass filter disabled ( mixed filtfb data modes 6, 7, 9 are also disabled)
*** PID (gainp0, gaini0, gaind0) readback disabled. one can still set PID values and run servo, but can not read back the values.
* '''Bug fix'''
** the bug associated with reading from raw-buffer is fixed.

== Revision 4.1.7 ==
* '''Filename''' : rc_v04010007_25apr2008_raw.sof
* '''Features'''
** raw mode enabled to buffer a snapshot of 50MHz samples for 2 frames of row_len * num_rows samples.
** In order to save RAM for raw mode, two memory-intensive features are disabled:
*** low-pass filter disabled ( mixed filtfb data modes 6, 7, 9 are also disabled)
*** PID (gainp0, gaini0, gaind0) readback disabled. one can still set PID values and run servo, but can not read back the values.
* '''Bugs'''
** after each readout frame, raw-buffer readout counter falls behind by 3 and this causes skipping 3 50MHz samples in the data stream and column-data being messed up in subsequent frames. Data can be rearranged by post processing.

== Revision 4.0.6 (buggy) ==
* '''Filename''' : rc_v04000006_15feb2008.sof or .pof
* '''Features'''
** '''bugfix''': unreliable reset due to unsafe and incomplete state machines is fixed.
** '''bugfix''': flux_jump sign problem fixed, so far proved in const_mode, to be tested in servo_mode with cold setup.
** servo_mode=2 or ramp previously only went from 0 to ramp_amp, but now goes from -8192 to -8192+ramp_amp
** new commands are added: ''scratch'' and ''card_type''. Scratch takes 8 values and can be used by software to detect reset.
** slot_id and fw_rev are now integrated as part of all_cards.vhd
** lvds_tx_b=0, This will allow Clock Card to use the secondary backplane lvds line and check whether RC is plugged in.
** filter_coeff in misc_banks_admin commented as it is not implemented and causes timing problems.

* '''Bugs'''
** reading gainp/gaini/gaind right after power up hangs the reply datapath to CC. resetmce clears this error as temporary solution. the problem is caused by first read ack of pid_ram_admin.
** slot_id is only set after a resetmce is issued. (using the latest all_cards in the next revision will fix this)
** has spurious spikes on channel 7 data, which max out the integral, and cause the detectors to come unlocked. This firmware officially meets timing requirements, but the bug could be due to marginal timing on the longest data paths, i.e. ~0.1 ns in some cases.

== Revision 4.0.5 ==
* '''Filename''' : rc_v04000005_01nov2007.sof or .pof
* '''Features'''
** data mode 9 (mixed filt + flux jump) with windowing readjusted compared to data mode 8

* '''Bugs'''
** unreliable resetmce. Sometimes, firmware waked up non-responsive on lvds lines.
** In data mode 5 and 9, flux-jump counter is not reported properly due to a sign error. However, flux jumping works fine.

== Revision 3.0.19 ==
* '''Filename''' : rc_v03000019_16feb2007_raw.sof (no pof as one is not likely to run with this as regular firmware)
* '''Features'''
** data mode 3 is enabled.
** filter is disabled as a compromise to fit the raw-mode buffer.

* '''Bugs'''
** unreliable resetmce. Sometimes, firmware waked up non-responsive on lvds lines.

== Old Firmware Revisions ==
* '''4.0.4''': rc_v04000004_11oct2007.sof data mode 8 added (mixed filt + flux jump)
* '''4.0.3''': rc_v04000003_19sep2007.sof data mode 7 bit split readjusted to 10b error being bit 4 to 14
* '''4.0.2''': rc_v04000002_11sep2007.sof pid resolution increased to 10b, data mode 7 added
* '''4.0.1''': rc_v04000001_06sep2007.sof
* '''4.0.0''': rc_v04000000_29aug2007.sof supports readout_row_index * [[ bugs ]]

= To-Do List =
* the starting point for the servo is currently zero and it would be nice to have it programmable.

= RC Synthesis Notes =
# The following note applies when using Quartus versions earlier than Q7: Quartus.ini file had to exist in synth directory up to revision 4.0.a due to a bug that started in Quartus 6.1 and would synthesize away arbitrary parts of readout card. We contacted Altera at the time and they provided us the ini file.
# Timing: There is no "lock region" defined for readout card. Timing on readout card is tight and since version 3 or so any new feature would initially fail timing till some synthesis options were tweaked. One path that remains to be consistently marginal is from addr_gen counter (i.e. tga_o counter) in dispatch_wishbone.vhd to wishbone slaves particularly misc_banks_admin.vhd. Modules that are rewritten to address timing concerns are fsfb_corr, all_cards, misc_banks_admin, and finally instantiating an lpm counter instead of a counter from components library. Surprisingly, the lpm counter reduced 87 failures to 37, although looking at the technology map viewer, it seemed that they were both synthesized the same.
# Compile time: This was at some point 4.5 hours, after going to dual core PC, this was reduced to 35 minutes. After extending pid gains to 12b and fixing offset/sa_bias update code, the compile time increased to 1.5hr again with utilization up to ~70%.
# wbs_fb_storage, ram_8x64, pid_ram had to be regenerated using latest (Q7.2) MegaWizard to get rid of the bug associated with failure to read after power up until a reset was issued.
# During simulations, the initialization of RAM block with .hex files needs to be disabled. This is done by commenting out the following lines from the MegaWizard generated Megafunction files (remember to un-comment them before synthesizing the code):
lpm_file => "C:/scuba2_repository/cards/readout_card/fsfb_calc/source/rtl/ram_40x64.hex", and
lpm_file : STRING;
#Starting Q10.0 use TimeQuest timing analyzer as oppose to the classic one. The classic one is being phased out by Altera. In order to use TimeQuest, you need to have an sdc file present in your project directory.
----
[http://e-mode.phas.ubc.ca/mcewiki/index.php/Main_Page MCE Main Page]

Readout Card firmware

2011-05-04T21:46:41Z

Bburger: /* Revision 5.1.2 */

* Synthesis Reminders (for firmware developers)
** quartus.ini is not needed anymore (Fixed as of Q7, Altera SR10783580 2010-10-24)
** Remember that readout_card/fsfb_clac/source/rtl/ram_40x64.vhd must be initialized with the ram_40x64.hex file in the same directory.
= Revision 5.1.2 =
* '''Filename:'''
** rc_stratix3_v05010002_18jan2011.sof (for Rev. E cards)
** rc_stratix3_v05010002_18jan2011.jic (for Rev. E cards)
** rc_v05010002_03feb2011.sof (for Rev. B cards)
** rc_v05010002_03feb2011.pof (for Rev. B cards)

* '''Features:'''
** based on 5.1.1 with k1 and k2 (filter params) limited to k1<16 and k2<32 in order to resolve the timing when compiling for smaller Stratix FPGA on RC Rev. B.

* '''Bug fix:'''
** the 2-rows-off filtered data readout introduced with configurable filter in rev. 5.1.0 and 5.1.1 is fixed now.

* '''Bugs:'''
** none so far.

* '''FPGA Resource Usage''' (readout_card.fit.rpt)
; Total logic elements ; 33,285 / 41,250 ( 81 % ) ;
; Total pins ; 358 / 616 ( 58 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt)
; Fast Model Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 6.591 ns
; Fast Model Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 7.206 ns
; Fast Model Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 18.299 ns

== Revision 5.1.1 (not recommended) ==
* '''Filename:'''
** rc_v05010001_01dec2010.sof (for Rev. B cards)

* '''Features:'''
** based on 5.1.0, but k1 and k2 (filter params) are now limited to k1<16 and k2<32 in order to resolve the timing failures of compiling 5.1.0 for smaller Stratix FPGA on RC Rev. B.

* '''Bugs:'''
** filter mode data is off by 2 rows.

== Revision 5.1.0 (not recommended) ==
* '''Filename:'''
** rc_stratix3_v05010000_01nov2010.sof (for Rev. E cards)
** rc_v05010000_01nov2010.sof (for Rev. B cards) has timing failures '''do not use!!!'''

* '''Features:'''
** added configurable filter parameters specified by ''fltr_coeff'', default is the fcutoff/fsampl=122Hz/15kHz. see [[ Digital 4-pole Butterworth Low-pass filter ]].
** ''fltr_type'' is set to 255 to indicate configurable filter parameters.
** see [http://www.phas.ubc.ca/~mce/mcedocs/software/SC2_ELE_S580_515_mce_command_description.pdf MCE command description]
** development notes:
*** It is built on Quartus10.1.
*** tcl files had to be updated as cmp syntax is not supported in Q10 anymore.
*** Rev. E cards now can be identified by reading back pcb_rev as part of card_type, therefore both stratix I and III sof/pof/jic are generated from the same source.

* '''Bugs:'''
** rc_v05010000_01nov2010.sof has timing failures that were overlooked, do not use this firmware for Rev.B cards.
** '''filter mode data is off by 2 rows.'''

* '''FPGA Resource Usage and Timing Report''' (readout_card.fit.rpt and readout_card.tan.rpt): logic usage is upto 85% from 66% in 5.0.d/e/f

== Revision 5.0.f ==
* '''Filename:'''
** rc_v0500000f_22oct2010.sof (for Rev. B cards)
** rc_stratix3_v0500000f_22oct2010.sof (for Rev. E cards)

* '''Features:'''
** Bugfix: integral clamp should work now. only positive integral_clamp values are valid!

* '''Details:''':
** SQ1FB is applied 18 clock cycles after start of a row visit (SQ1_Bias being applied) regardless of flux-jump being enabled or not. In pre-5.0.b firmware SQ1FB was being applied after 7 clock cycles when flux-jump was disabled and after 18 clock cycles when flux-jump was enabled.
** available for both Rev. E and Rev. B cards, the upper byte of card_type parameter now reports the pcb revision.
** development note: It is built on Quartus10.1.

* '''Bugs:'''
**none yet!

* '''FPGA Resource Usage and Timing Report''' (readout_card.fit.rpt and readout_card.tan.rpt): no change compared to 5.0.a/b/c/d

== Revision 5.0.e (not recommended) ==
* '''Filename:'''
** rc_v0500000e_06oct2010.sof

* '''Details:'''
** an unsuccessful attempt to fix integral_clamp, but changed the functionality so that it clamps at the value, but it doesn't hold the clamp. i.e., if the calculated sq1fb becomes less than the specified clamp value, the sq1fb is not clamped anymore. This is not a desired functionality!

== Revision 5.0.d ==
* '''Filename:'''
** rc_v0500000d_04aug2010.sof

* '''Features:'''
** Bugfix: To fix the bug associated with negative flux-jumps, reverted to signed multiplier and hence, incremented the width of the flux-quanta multiplier input by 1.

* '''Details:''': SQ1FB is applied 18 clock cycles after start of a row visit (SQ1_Bias being applied) regardless of flux-jump being enabled or not. In pre-5.0.b firmware SQ1FB was being applied after 7 clock cycles when flux-jump was disabled and after 18 clock cycles when flux-jump was enabled.

* '''Bugs:'''
** '''integral_clamping is broken'''. To test the clamping, a servo-locked ramp was initiated on the sq1fb and then flux-jumping was turned on and observed by attaching a scope to the SQ1FB output. With integral_clamp=80000000, flux_quanta=8000, gaini=1, flux-jump enabled, we see [[http://e-mode.phas.ubc.ca/mcewiki/index.php/Image:Clamp_unstable.png scope snapshot]] used slow_fb_ramp.py script for testing.

* '''FPGA Resource Usage and Timing Report''' (readout_card.fit.rpt and readout_card.tan.rpt): no change compared to 5.0.a/b/c

== Revision 5.0.c (not recommended) ==
* '''Filename:'''
** rc_v0500000c_16jun2010.sof

* '''Features:'''
** Based on rev. 5.0.b
** Re-introduced flux-jump counter clamping to maintain continuity in behavior from past versions of firmware in the field.
** '''Important''': SQ1FB is applied 18 clock cycles after start of a row visit (SQ1_Bias being applied) regardless of flux-jump being enabled or not. In pre-5.0.b firmware SQ1FB was being applied after 7 clock cycles when flux-jump was disabled and after 18 clock cycles when flux-jump was enabled.

* '''Details:'''
* '''Bugs:'''
** '''flux-jump is broken'''. flux-jumping block misbehaves at the first jump in the negative range.

* '''FPGA Resource Usage''' (readout_card.fit.rpt): [[rc_5.0.c_fit_rpt]]
; Total logic elements ; 26,800 / 41,250 ( 65 % ) ;
; Total pins ; 358 / 616 ( 58 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;
; DSP block 9-bit elements ; 76 / 112 ( 68 % ) ;
; Total PLLs ; 1 / 6 ( 17 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt): [[rc_5.0.c_tan_rpt]]
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.964 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 4.382 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 15.924 ns ;

== Revision 5.0.b (not recommended) ==
* '''Filename:'''
** rc_v0500000b_03jun2010.sof

* '''Features:'''
** Based on rev. 5.0.a
** A bug that caused jumps in first-stage feedback, and detected as spikes in the raw data of pixels that were in servo_mode=0,1,2 was fixed. The jumps in FSFB were due to flux-jumping being enabled on live pixes with non-zero flx_quanta, and being disabled on the fly on dead pixels with flx_quanta=0. Flux-jumping is now disabled on a column-by-column basis if a column is in servo_mode = 0,1,2.
** Ineffective clamping was removed from the flux-jumping block (as per 5.0.9), as it is now replaced by the clamping that was perfected in rev. 5.0.10
** A sticky bit that only affected servo_mode=0,1,2 was also removed from the flux-jumping block.
** flx_lp_init commands now also clear the flux-jumping block as well.
** The 11-clock-cycle delay (in applying SQ1_FB) that in previous firmware only occurred when flux-jumping was enabled, now (in this version) is in effect all the time. Due to the bug-fix above, flux-jumping can be disabled on a column-by-column basis by setting servo_mode=0,1,2 when en_fb_jump=1. Before the change, this meant that constant values could be applied with or without the 11-cycle delay if en_fb_jump=1 or 0. To make the delay consistent, it is now always 11 cycles. As background, the flux-jumping block is pipelined, meaning that it does calculations for all 8 channels serially. The serialization is because of DSP-block limitations in the Readout Card FPGA that prevent us from doing all 8 channels in parallel. The reason that it takes 11 cycles to complete the flux-jumping calculations is because the values are computed for the eight channels in three ALU stages: 8 + 3 = 11 cycles. Adding 11 cycles to the 7 cycles of latency from other stages in the system results in: 11 + 7 = 18 cycles of latency from the start of a row dwell period before the first-stage feedback is applied. In rc_v5.0.c, I enforce the 18-cycle delay even when flux-jumping is not enabled to maintain uniformity across all eight channels, because flux-jumping is enabled/disabled on a per-channel basis. In other words, if I hadn't enforced the 18-cycle delay, some channels could have their feedback applied after 7 cycles, while others could have it applied after 18 cycles. I wasn't a fan of this non-uniformity. I realize that 18 cycles is a long time. In fact, so is 7. In the last few months, we have been discussing how to reduce these times to 1 cycle, because every experiment out there wants to multiplex as fast as possible, and the 7/18-delay is a rate limiting step.
** The flux-jumping code was re-arranged in the flux-jumping block to reflect the flow of data through the pipeline and make it easier to understand.

* '''Details:'''

* '''Bugs:'''
** flux-jump does not work when jumping to negative values.

* '''FPGA Resource Usage''' (readout_card.fit.rpt): [[rc_5.0.b_fit_rpt]]
; Total logic elements ; 26,745 / 41,250 ( 65 % ) ;
; Total pins ; 358 / 616 ( 58 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;
; DSP block 9-bit elements ; 76 / 112 ( 68 % ) ;
; Total PLLs ; 1 / 6 ( 17 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;
* '''FPGA Timing Analysis''' (readout_card.tan.rpt): [[rc_5.0.b_tan_rpt]]
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.459 ns
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.895 ns
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 15.956 ns

= Revision 5.0.a =
* '''Filename:'''
** rc_v0500000a_12mar2010.sof

* '''Features:'''
** Based on the merger of rev. 5.0.8 and 5.0.9.
** '''integral_clamp''' command is added where a clamp value is set for the integral term and once the integral term hits that value, the integral-term is clamped to that value and p-term and d-term are clamped to zero. When integral_term=0 then no clamping is in effect, similar to previous releases of firmware.
** The low pass filter has 20-bit input and f_3dB/f_samp = 122Hz/15kHz .
** The flux-jump clamping that was removed in 5.0.9 is included once again here, as we decided this is safer for now.

* '''Details:'''
** "lock_dat_left" parameter that was removed in 5.0.9 is now implemented as "lock_dat_lsb"

* '''Bugs:'''
** flx_lp_init does not reinitialize the flux-jump block

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis
** tag name: rc_v0500000a_12mar2009! years were mixed up!

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
* '''FPGA Timing Analysis''' (readout_card.tan.rpt):

== Revision 5.0.9 (buggy) ==
* '''Filename:'''
** rc_v05000009_13nov2009.sof

* '''Features:'''
** Based on rev. 5.0.4
** Removes a sticky bit in pid calculation result storage -- in fsfb_processor.
** Adds a command to clamp the growth of the I-term to prevent wrapping and track down the source of Caltech's FSFB jumps.
** Removed the unused lock_dat_left parameter. The ability to shift left was moved to the fsfb_corr block some time ago.
** Fixed a sign extension bug acting on the flux quanta, which limited the value to 8191. Changed the extension from signed to unsigned.
** Removed ineffective clamping in the flux-jump calculation block.
** IMPORTANT: Must be used in conjunction with firmware rev. 5.0.0+ of all other cards.

* '''Details:'''

* '''Bugs:'''
** integral_clamp read/write command does not work.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 27,960 / 41,250 ( 68 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.825 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.878 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 14.397 ns ;

== Revision 5.0.8 (UBC only) ==
* '''Filename:'''
** rc_v05000008_09oct2009.sof

* '''Features:'''
** Based on rev. 5.0.4
** type 1 low-pass filter: f3dB=122Hz for fsample=15kHz
** Filter-input-width changed from 18b to 20b with no sticky bits!
** removed sticky bits in internal arithmetic of the filter.

= Revision 5.0.7 (type-2 filter) =
* '''Filename:'''
** rc_v05000007_09oct2009.sof

* '''Features:'''
** Based on rev. 5.0.4
** type-2 low-pass-filter: f3dB=75Hz for fsample=30000.
** Filter-input-width changed from 18b to 20b with no sticky bits!
** inter-biquad-gain-scaling for the filter is 2^14
** filter results are scaled down by 2^3 in the output of the filter.
** removed sticky bits in internal arithmetics
** _correction_ disabled in fsfb_proc_pidz

* '''Details:'''
** quartus.ini file was '''not''' present in synth directory.

* '''Bugs:'''
** none to report

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
== Revision 5.0.6 (UBC only) ==
* '''Filename:'''
** rc_stratix3_v05000006_15sep2009.sof

* '''Features:'''
** Only Valid for Rev. C/D Cards
** Based on rev. 5.0.3
** tcl file updated for Rev. D and aligned with top-level and qsf (project file).
** flux loop commented, just to try sampling the ADC.
** compiled with Q9.1

== Revision 5.0.5 (UBC only) ==
* '''Filename:'''
** rc_v05000005_04sep2009.sof

* '''Features:'''
** Based on rev. 5.0.2
** changed the low-pass-filter to f(3db)=75Hz for f(sample)=30000.

* '''Details:'''
** quartus.ini file was '''not''' present in synth directory.

* '''Bugs:'''
** negative inputs to the filter cause filter to have a non-flat pass-band region. may have to do with sign-handling...

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
* '''FPGA Timing Analysis''' (readout_card.tan.rpt):

= Revision 5.0.4 =
* '''Filename:'''
** rc_v05000004_28aug2009.sof

* '''Features:'''
** Based on rev. 5.0.2
** BUG Fix: handles 14-bit flux quanta (changed the multiplier to unsigned)
** BUG Fix: changed standard logic vector extension from signed to unsigned in flux-jumping slave.
** IMPORTANT: Must be used in conjunction with firmware rev. 5.0.0+ of all other cards.

* '''Details:'''

* '''Bugs:'''
** None so far.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,170 / 41,250 ( 63 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.541 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.612 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 15.398 ns ;

= Revision 5.0.3 =
* '''Filename:'''
** rc_stratix3_v05000003_21aug2009.sof

* '''Features:'''
** ONLY valid REV C/D RC Cards
** Based on rev. 5.0.2
** flux loop commented, just to try sampling the ADC.
** updated tcl file, but still need to rely on project file as well as qsf file.
** changed default level of adc_sclk to '1'
** dac_clr_n was changed from an output to an input.
** added 'locked' interface to rc_pll_stratix_iii
** renamed the adc_pll clock signals to more explanitory names
** added the FPGA_DEVICE_FAMILY generic to the dispatch interace for synthesis of the dc_fifo in lvds_rx
** uncommented DDR interface to force the syntesizer to use correct left and right PLLs (in conjunction with ADC and DDR PLLs)
** added test signals to test_status to see clocks on the scope.
== Revision 5.0.2 (buggy) ==
* '''Filename:'''
** rc_v05000002_test00_tagged.sof

* '''Features:'''
** Based on rev. 5.0.1
** Fixed a bug in wbs_frame_data that stored data incorrectly if reporting 1 or 2 pixels only.
** IMPORTANT: Must be used in conjunction with firmware rev. 5.0.0+ of all other cards.

* '''Details:'''

* '''Bugs:'''
** None so far.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,186 / 41,250 ( 63 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.755 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.979 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.067 ns ;

== Revision 5.0.1 (buggy) (Filter + Raw + Rectangle, 2 LVDS) ==
* '''Filename:'''
** rc_v05000001_26may2009.sof

* '''Features:'''
** Combines features in rev. 5.0.0 (2 LVDS Lines) and rev. 4.0.e (Filtered + Raw), with the NEW rectangle mode.
** IMPORTANT: Must be used in conjunction with firmware rev. 5.0.0+ of all other cards.

* '''Details:'''
** [[CVS Diff Between sys_v05000000 and rc_v05000001]]

* '''Bugs:'''
** Has a bug in wbs_frame_data that stored data incorrectly if reporting 1 or 2 pixels only.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,565 / 41,250 ( 64 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.656 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.861 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 14.167 ns ;

== Revision 5.0.0 (Filter Only, 2 LVDS) ==
* '''Filename:'''
** rc_v05000000_22dec2008.sof (tagged as sys_v05000000_22dec2008)

* '''Features:'''
** IMPORTANT: Must be used in conjunction with firmware v05000000+ of all other cards!!!
** Adds the ability to read out one column of data continuously from readout cards
** Adds data mode 11, which is an engineering mode. Data points are 32-bits, and bits [9..3]=row_index, [2..0]=column_index. This mode is useful for determining which pixels one is reading out in the array, in column mode for example.

* '''Details:'''
** [[CVS Diff Between rc_v0400000c and sys_v05000000]]

* '''Bugs:'''
** None so far.

* '''Synthesis Notes:'''
** The quartus.ini file was not present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,607 / 41,250 ( 65 % ) ;
; Total memory bits ; 406,016 / 3,423,744 ( 12 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.558 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.892 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.987 ns ;

== Revision 4.0.f (Filter + Raw, 1 LVDS) ==
* '''Filename:'''
** rc_v0400000f_12feb2010.sof

* '''Features:'''
** Based on 4.0.e and in parallel with 5.0.9 (equivalent version, clamping is not included)
** Incorporates fixes that were done to flux-jumping between 5.0.2 - 5.0.4 - 5.0.9. Namely:
*** Changes a multiplier from signed to unsigned (in fsfb_corr_multplier.vhd).
*** Changes sign extension from signed to unsigned (in flux_quanta_ram_admin.vhd).

* '''Details:'''

* '''Bugs:'''
** None reported yet.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,773 / 41,250 ( 65 % ) ;
; Total memory bits ; 1,321,984 / 3,423,744 ( 39 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.539 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 4.118 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 17.318 ns ;

== Revision 4.0.e (Filter + Raw, 1 LVDS) ==
* '''Filename:'''
** rc_v0400000e_27apr2009.sof

* '''Features:'''
** Based on 4.0.d
** Combines both raw- and filtered-data modes.
** fpga_temp, card_temp, card_id commands are disabled.
** Tested by Matt Hasselfield.

* '''Details:'''

* '''Bugs:'''
** fpga_temp, card_temp, card_id commands are disabled.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 27,048 / 41,250 ( 66 % ) ;
; Total memory bits ; 1,321,984 / 3,423,744 ( 39 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.675 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.907 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.728 ns ;

== Revision 4.0.d (Raw Only, 1 LVDS) ==
* '''Filename:''' rc_v0400000d_20090417.sof

* '''Features:'''
** Based on v4.0.c, but has the filter removed, and implements a single 65536-index RAM block for storing 50 MHz raw-data samples.
** The firmware takes a new command called readout_col_index which specifies which column to capture raw data from.
** Other than readout_col_index, the firmware functions the same as previous raw-data firmware, including then need to issue a capture_raw command.
** For more information on raw-data, see: http://e-mode.phas.ubc.ca/mcewiki/index.php/Raw-mode_readout
** This firmware also integrates some of the improvements that were implemented in 4.4.0, like the removal of the tga_o signal from an FSM in dispatch_wishbone.vhd.

* '''Details:'''
** Differences between 4.0.c and 4.0.d
U system/test/source/tb/tb_cc_rcs_bcs_ac.vhd
U all_cards/dispatch/source/rtl/dispatch_wishbone.vhd
U library/sys_param/source/rtl/wishbone_pack.vhd
U readout_card/adc_sample_coadd/source/rtl/adc_sample_coadd.vhd
U readout_card/adc_sample_coadd/source/rtl/adc_sample_coadd_pack.vhd
U readout_card/flux_loop/source/rtl/flux_loop.vhd
U readout_card/flux_loop/source/rtl/flux_loop_pack.vhd
U readout_card/flux_loop_ctrl/source/rtl/flux_loop_ctrl.vhd
U readout_card/flux_loop_ctrl/source/rtl/flux_loop_ctrl_pack.vhd
U readout_card/flux_loop_ctrl/source/tb/tb1_flux_loop_ctrl.vhd
U readout_card/flux_loop_ctrl/source/tb/tb2_flux_loop_ctrl.vhd
U readout_card/fsfb_calc/source/rtl/fsfb_fltr_regs.vhd
U readout_card/fsfb_corr/source/rtl/fsfb_corr.vhd
U readout_card/readout_card/source/rtl/readout_card.vhd
U readout_card/readout_card/source/rtl/readout_card_pack.vhd
U readout_card/wbs_frame_data/source/rtl/wbs_frame_data.vhd
U readout_card/wbs_frame_data/source/rtl/wbs_frame_data_pack.vhd

* '''Bugs:'''
** None so far.
** fpga_temp, card_temp, card_id commands are not supported.

* '''Synthesis Notes:'''
** The quartus.ini file was present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 24,554 / 41,250 ( 60 % ) ;
; Total memory bits ; 1,262,592 / 3,423,744 ( 37 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.991 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.864 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 17.052 ns ;

== Revision 4.4.1 ==
* '''Filename:''' rc_v04040001_21nov2008

* '''Features:'''
** Fixes a bug that froze up the firmware if any of the following commands were issued: CARD_ID_ADDR, CARD_TEMP_ADDR, FPGA_TEMP_ADDR in 4.4.0 only.

* '''Details:'''
** The bug fix include adding more logic to the wishbone ack path (readout_card.vhd), which subsequently decreased the minimum clock setup time to 1.588ns. The new logic will catch errors that the old logic wouldn't have, and is now consistent with the firmware on all the other cards. However, if timing becomes an issue, the logic may have to revert back to that which was in version 4.0.c.

* '''Bugs:'''
** None so far.

* '''Synthesis Notes:'''
** The quartus.ini file was not present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 27,241 / 41,250 ( 66 % ) ;
; Total memory bits ; 405,504 / 3,423,744 ( 12 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.588 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.585 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 17.057 ns ;

== Revision 4.4.0 (buggy) ==
* '''Filename:''' rc_v04040000_02oct2008
* '''Features:'''
** Reinstated the data modes in wbs_frame_data.vhd that were removed in 4.0.c. This firmware has the following modes: '''0, 1, 2, 4, 5, 7, 10'''. The modes that are not present are: '''3''' (raw data), '''6''' (replaced by data_mode = 7), '''8''' (replaced by data_mode = 10), '''9''' (replaced by data_mode = 10). For more information on data modes, see [[Data mode]].
** Re-integrated the id_thermo and fpga_thermo block in the readout_card.vhd top level that was removed in 4.0.c.
** Removed the sticky bit in fsfb_corr.vhd, which was enabled when flux-jumping was turned on. Because the feedback is signed, the sticky bit would usually reflect the value of the 14th bit, except in situations when the number of flux quanta to jump was greater than 1 (i.e. cosmic rays, IV-curves, etc). Flux jumps are made at a maximum rate of one per frame period, so that if the First-Stage Feedback increased past the 13th bit, it would not be reflected in the feedback applied. Now it is.
* '''Details:'''
** Simplified the FSM logic in wbs_frame_data.vhd that determines when to transition from IDLE to WSS1. This was done to lower the number of gates in that path, and ease the timing.
** Removed the z_dat_i port in fsfb_processor.vhd and fsfb_calc_pack.vhd to the fsfb_proc_pidz block, in an effort to make it clearer within that block that the z-term is always = 0.
** Removed the z-term sign extension in fsfb_proc_pidz.vhd, and the [d-term + z-term] adder to free up DSP resources since the z-term is always = 0.
** Adjusted the indentation in fsfb_io_controller.vhd to make the file more readable.
** Moved the tga_o signal out of the dispatch_wishbone.vhd FSM, and made it a continuous assignment. This signal had one of the highest fan-out counts in the RTL design, and actually was impossible to route in Stratix III chips in its previous configuration because of the number of gates on the fan-out. As a consequence of making it a continuous assignment, the Stratix III fitter was able to succeed, and the Stratix I timing characteristics were greatly improved. This is the most significant change in this revision. This change single-handedly increased the minimum slack from 1.282 ns in v0400000c to 2.372 ns (or 56.7 MHz max) in this revision.
* '''Bugs:'''
** The following commands lock up the Readout Card firmware: CARD_ID_ADDR, CARD_TEMP_ADDR, FPGA_TEMP_ADDR.
** fb_const0 commands to channel 0 do not work. The value is stored in the register, but not applied to the DAC. Thus, read-back returns the correct value, but the DAC does not
* '''Synthesis Notes:'''
** The quartus.ini file was not present in the synth directory during synthesis.
* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 27,099 / 41,250 ( 66 % ) ;
; Total memory bits ; 406,016 / 3,423,744 ( 12 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.372 ns ;
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 4.052 ns ;
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.066 ns ;

== Revision 4.0.c ==
* '''Filename:''' rc_v0400000c_15aug2008.sof
* '''Features:'''
** Only has data modes 0, 1, 4, and 10.
** Fixed the bug that exists in 4.0.b, 4.0.a, and 4.0.9 that prevented the fb_const value from being applied to channel zero (wbs_fb_data.vhd).
* '''Details:'''
** Changed a counter in the dispatch block to ease timing constraints in synthesis (dispatch_wishbone.vhd)
** Updated the tagged versions of dispatch.vhd , dispatch_cmd_receive.vhd, and dispatch_reply_transmit.vhd to the version that is used by all the other cards.
** '''Removed''' the fpga_termo (command: '''fpga_temp''') and id_thermo (commands: '''card_temp, card_id''') to ease timing constraints in synthesis (readout_card.vhd)
** Updated the tagged version of fpga_termo.vhd to include the new 'stale bit' feature
** Updated the tagged version of frame_timing_core.vhd to include the new 'err_o' interface
* '''Bugs:'''
** None reported yet
* '''Synthesis Notes:'''
** The quartus.ini file was not present in the synth directory during synthesis.
* '''FPGA Resource Usage:'''
Total logic elements : 25,058 / 41,250 ( 61 % )
Total memory bits : 400,896 / 3,423,744 ( 12 % )

* '''Timing Analysis''' (readout_card.tan.rpt):
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.282 ns ;
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.736 ns ;
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.665 ns ;

== Revision 4.0.b (buggy) ==
Note: This revision is on a watch list, after the bug detected 15 July 2008. See the bug section for more details.
* '''Filename''' : rc_v0400000b_04aug2008.sof
* '''Features'''
** data_mode 10 is added to provide more filtfb bits (compared to data mode 9) for planet observations. filtered_dat(27 downto 3) & flux_cnt_dat(6 downto 0)

* '''Bugs'''
** An unexplained bug that appeared in 4.0.a and may still be present in 4.0.b is a problem with the readout of channels being clipped out of data reporting. [[Bug 1 Notes]]

* ''' Synthesis note '''
** Quartus.ini removed.

== Revision 4.0.a (buggy) ==
Note: This revision is on a watch list, after the bug detected 15 July 2008. See the bug section for more details.
* '''Filename''' : rc_v0400000a_07jul2008.sof
* '''Bug Fix'''
** mce_status and adc_offset/flx_quanta commands do not fail after power up.
* ''' Synthesis note '''
** Quartus.ini removed.

* '''Bugs'''
** Seems to clip out channel 0 from data reporting.

== Revision 4.0.9 (buggy) ==
* '''Filename''' : rc_v04000009_26jun2008.sof
* '''Features'''
** sa_bias and offset DACs only refreshed when new values are written. (in previous versions, DACs were refreshed every frame)
* '''Bugs'''
** fb_const0 commands to channel 0 do not work. The value is stored in the register, but not applied to the DAC. Thus, read-back returns the correct value, but the DAC does not.
** reading flx_quanta and adc_offset right after power up hangs the reply datapath to CC. resetmce clears this error as temporary solution. the problem is caused by first read ack of the wishbone slave.

== Revision 4.0.8 ==
* '''Filename''' : rc_v04000008_26jun2008.sof
* '''Features'''
** The gaini, gainp, gaind resolution increased to 12-bit, i.e. -2048 to 2047 (formerly 10-bit).

* '''Bug fix'''
** the bug associated with gainpid read before mce_reset is fixed.

* ''' Synthesis note '''
** Quartus.ini removed.

== Revision 4.3.7 ==
* '''Filename''' : rc_v04030007_26may2008_raw.sof
* '''Features'''
** 14-bit raw mode enabled to buffer a snapshot of 50MHz samples for 2 frames of row_len * num_rows samples.
** In order to extend the raw-mode to 14-bit, an assumption is made that the raw buffer is not written to while being read. Therefore, make sure there is at least 2*row_len*num_rows*20ns between issuing captr_raw command and reading back the raw data.
** In order to save RAM for raw mode, two memory-intensive features are disabled:
*** low-pass filter disabled ( mixed filtfb data modes 6, 7, 9 are also disabled)
*** PID (gainp0, gaini0, gaind0) readback disabled. one can still set PID values and run servo, but can not read back the values.

== Revision 4.2.7 ==
* '''Filename''' : rc_v04020007_24may2008_raw.sof
* '''Features'''
** raw mode enabled to buffer a snapshot of 50MHz samples for 2 frames of row_len * num_rows samples.
** In order to save RAM for raw mode, two memory-intensive features are disabled:
*** low-pass filter disabled ( mixed filtfb data modes 6, 7, 9 are also disabled)
*** PID (gainp0, gaini0, gaind0) readback disabled. one can still set PID values and run servo, but can not read back the values.
* '''Bug fix'''
** the bug associated with reading from raw-buffer is fixed.

== Revision 4.1.7 ==
* '''Filename''' : rc_v04010007_25apr2008_raw.sof
* '''Features'''
** raw mode enabled to buffer a snapshot of 50MHz samples for 2 frames of row_len * num_rows samples.
** In order to save RAM for raw mode, two memory-intensive features are disabled:
*** low-pass filter disabled ( mixed filtfb data modes 6, 7, 9 are also disabled)
*** PID (gainp0, gaini0, gaind0) readback disabled. one can still set PID values and run servo, but can not read back the values.
* '''Bugs'''
** after each readout frame, raw-buffer readout counter falls behind by 3 and this causes skipping 3 50MHz samples in the data stream and column-data being messed up in subsequent frames. Data can be rearranged by post processing.

== Revision 4.0.6 (buggy) ==
* '''Filename''' : rc_v04000006_15feb2008.sof or .pof
* '''Features'''
** '''bugfix''': unreliable reset due to unsafe and incomplete state machines is fixed.
** '''bugfix''': flux_jump sign problem fixed, so far proved in const_mode, to be tested in servo_mode with cold setup.
** servo_mode=2 or ramp previously only went from 0 to ramp_amp, but now goes from -8192 to -8192+ramp_amp
** new commands are added: ''scratch'' and ''card_type''. Scratch takes 8 values and can be used by software to detect reset.
** slot_id and fw_rev are now integrated as part of all_cards.vhd
** lvds_tx_b=0, This will allow Clock Card to use the secondary backplane lvds line and check whether RC is plugged in.
** filter_coeff in misc_banks_admin commented as it is not implemented and causes timing problems.

* '''Bugs'''
** reading gainp/gaini/gaind right after power up hangs the reply datapath to CC. resetmce clears this error as temporary solution. the problem is caused by first read ack of pid_ram_admin.
** slot_id is only set after a resetmce is issued. (using the latest all_cards in the next revision will fix this)
** has spurious spikes on channel 7 data, which max out the integral, and cause the detectors to come unlocked. This firmware officially meets timing requirements, but the bug could be due to marginal timing on the longest data paths, i.e. ~0.1 ns in some cases.

== Revision 4.0.5 ==
* '''Filename''' : rc_v04000005_01nov2007.sof or .pof
* '''Features'''
** data mode 9 (mixed filt + flux jump) with windowing readjusted compared to data mode 8

* '''Bugs'''
** unreliable resetmce. Sometimes, firmware waked up non-responsive on lvds lines.
** In data mode 5 and 9, flux-jump counter is not reported properly due to a sign error. However, flux jumping works fine.

== Revision 3.0.19 ==
* '''Filename''' : rc_v03000019_16feb2007_raw.sof (no pof as one is not likely to run with this as regular firmware)
* '''Features'''
** data mode 3 is enabled.
** filter is disabled as a compromise to fit the raw-mode buffer.

* '''Bugs'''
** unreliable resetmce. Sometimes, firmware waked up non-responsive on lvds lines.

== Old Firmware Revisions ==
* '''4.0.4''': rc_v04000004_11oct2007.sof data mode 8 added (mixed filt + flux jump)
* '''4.0.3''': rc_v04000003_19sep2007.sof data mode 7 bit split readjusted to 10b error being bit 4 to 14
* '''4.0.2''': rc_v04000002_11sep2007.sof pid resolution increased to 10b, data mode 7 added
* '''4.0.1''': rc_v04000001_06sep2007.sof
* '''4.0.0''': rc_v04000000_29aug2007.sof supports readout_row_index * [[ bugs ]]

= To-Do List =
* the starting point for the servo is currently zero and it would be nice to have it programmable.

= RC Synthesis Notes =
# The following note applies when using Quartus versions earlier than Q7: Quartus.ini file had to exist in synth directory up to revision 4.0.a due to a bug that started in Quartus 6.1 and would synthesize away arbitrary parts of readout card. We contacted Altera at the time and they provided us the ini file.
# Timing: There is no "lock region" defined for readout card. Timing on readout card is tight and since version 3 or so any new feature would initially fail timing till some synthesis options were tweaked. One path that remains to be consistently marginal is from addr_gen counter (i.e. tga_o counter) in dispatch_wishbone.vhd to wishbone slaves particularly misc_banks_admin.vhd. Modules that are rewritten to address timing concerns are fsfb_corr, all_cards, misc_banks_admin, and finally instantiating an lpm counter instead of a counter from components library. Surprisingly, the lpm counter reduced 87 failures to 37, although looking at the technology map viewer, it seemed that they were both synthesized the same.
# Compile time: This was at some point 4.5 hours, after going to dual core PC, this was reduced to 35 minutes. After extending pid gains to 12b and fixing offset/sa_bias update code, the compile time increased to 1.5hr again with utilization up to ~70%.
# wbs_fb_storage, ram_8x64, pid_ram had to be regenerated using latest (Q7.2) MegaWizard to get rid of the bug associated with failure to read after power up until a reset was issued.
# During simulations, the initialization of RAM block with .hex files needs to be disabled. This is done by commenting out the following lines from the MegaWizard generated Megafunction files (remember to un-comment them before synthesizing the code):
lpm_file => "C:/scuba2_repository/cards/readout_card/fsfb_calc/source/rtl/ram_40x64.hex", and
lpm_file : STRING;
#Starting Q10.0 use TimeQuest timing analyzer as oppose to the classic one. The classic one is being phased out by Altera. In order to use TimeQuest, you need to have an sdc file present in your project directory.
----
[http://e-mode.phas.ubc.ca/mcewiki/index.php/Main_Page MCE Main Page]

Readout Card firmware

2011-05-04T21:45:19Z

Bburger: /* Revision 5.0.f */

* Synthesis Reminders (for firmware developers)
** quartus.ini is not needed anymore (Fixed as of Q7, Altera SR10783580 2010-10-24)
** Remember that readout_card/fsfb_clac/source/rtl/ram_40x64.vhd must be initialized with the ram_40x64.hex file in the same directory.
== Revision 5.1.2 ==
* '''Filename:'''
** rc_stratix3_v05010002_18jan2011.sof (for Rev. E cards)
** rc_stratix3_v05010002_18jan2011.jic (for Rev. E cards)
** rc_v05010002_03feb2011.sof (for Rev. B cards)
** rc_v05010002_03feb2011.pof (for Rev. B cards)

* '''Features:'''
** based on 5.1.1 with k1 and k2 (filter params) limited to k1<16 and k2<32 in order to resolve the timing when compiling for smaller Stratix FPGA on RC Rev. B.

* '''Bug fix:'''
** the 2-rows-off filtered data readout introduced with configurable filter in rev. 5.1.0 and 5.1.1 is fixed now.

* '''Bugs:'''
** none so far.

* '''FPGA Resource Usage''' (readout_card.fit.rpt)
; Total logic elements ; 33,285 / 41,250 ( 81 % ) ;
; Total pins ; 358 / 616 ( 58 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt)
; Fast Model Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 6.591 ns
; Fast Model Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 7.206 ns
; Fast Model Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 18.299 ns

== Revision 5.1.1 (not recommended) ==
* '''Filename:'''
** rc_v05010001_01dec2010.sof (for Rev. B cards)

* '''Features:'''
** based on 5.1.0, but k1 and k2 (filter params) are now limited to k1<16 and k2<32 in order to resolve the timing failures of compiling 5.1.0 for smaller Stratix FPGA on RC Rev. B.

* '''Bugs:'''
** filter mode data is off by 2 rows.

== Revision 5.1.0 (not recommended) ==
* '''Filename:'''
** rc_stratix3_v05010000_01nov2010.sof (for Rev. E cards)
** rc_v05010000_01nov2010.sof (for Rev. B cards) has timing failures '''do not use!!!'''

* '''Features:'''
** added configurable filter parameters specified by ''fltr_coeff'', default is the fcutoff/fsampl=122Hz/15kHz. see [[ Digital 4-pole Butterworth Low-pass filter ]].
** ''fltr_type'' is set to 255 to indicate configurable filter parameters.
** see [http://www.phas.ubc.ca/~mce/mcedocs/software/SC2_ELE_S580_515_mce_command_description.pdf MCE command description]
** development notes:
*** It is built on Quartus10.1.
*** tcl files had to be updated as cmp syntax is not supported in Q10 anymore.
*** Rev. E cards now can be identified by reading back pcb_rev as part of card_type, therefore both stratix I and III sof/pof/jic are generated from the same source.

* '''Bugs:'''
** rc_v05010000_01nov2010.sof has timing failures that were overlooked, do not use this firmware for Rev.B cards.
** '''filter mode data is off by 2 rows.'''

* '''FPGA Resource Usage and Timing Report''' (readout_card.fit.rpt and readout_card.tan.rpt): logic usage is upto 85% from 66% in 5.0.d/e/f

== Revision 5.0.f ==
* '''Filename:'''
** rc_v0500000f_22oct2010.sof (for Rev. B cards)
** rc_stratix3_v0500000f_22oct2010.sof (for Rev. E cards)

* '''Features:'''
** Bugfix: integral clamp should work now. only positive integral_clamp values are valid!

* '''Details:''':
** SQ1FB is applied 18 clock cycles after start of a row visit (SQ1_Bias being applied) regardless of flux-jump being enabled or not. In pre-5.0.b firmware SQ1FB was being applied after 7 clock cycles when flux-jump was disabled and after 18 clock cycles when flux-jump was enabled.
** available for both Rev. E and Rev. B cards, the upper byte of card_type parameter now reports the pcb revision.
** development note: It is built on Quartus10.1.

* '''Bugs:'''
**none yet!

* '''FPGA Resource Usage and Timing Report''' (readout_card.fit.rpt and readout_card.tan.rpt): no change compared to 5.0.a/b/c/d

== Revision 5.0.e (not recommended) ==
* '''Filename:'''
** rc_v0500000e_06oct2010.sof

* '''Details:'''
** an unsuccessful attempt to fix integral_clamp, but changed the functionality so that it clamps at the value, but it doesn't hold the clamp. i.e., if the calculated sq1fb becomes less than the specified clamp value, the sq1fb is not clamped anymore. This is not a desired functionality!

== Revision 5.0.d ==
* '''Filename:'''
** rc_v0500000d_04aug2010.sof

* '''Features:'''
** Bugfix: To fix the bug associated with negative flux-jumps, reverted to signed multiplier and hence, incremented the width of the flux-quanta multiplier input by 1.

* '''Details:''': SQ1FB is applied 18 clock cycles after start of a row visit (SQ1_Bias being applied) regardless of flux-jump being enabled or not. In pre-5.0.b firmware SQ1FB was being applied after 7 clock cycles when flux-jump was disabled and after 18 clock cycles when flux-jump was enabled.

* '''Bugs:'''
** '''integral_clamping is broken'''. To test the clamping, a servo-locked ramp was initiated on the sq1fb and then flux-jumping was turned on and observed by attaching a scope to the SQ1FB output. With integral_clamp=80000000, flux_quanta=8000, gaini=1, flux-jump enabled, we see [[http://e-mode.phas.ubc.ca/mcewiki/index.php/Image:Clamp_unstable.png scope snapshot]] used slow_fb_ramp.py script for testing.

* '''FPGA Resource Usage and Timing Report''' (readout_card.fit.rpt and readout_card.tan.rpt): no change compared to 5.0.a/b/c

== Revision 5.0.c (not recommended) ==
* '''Filename:'''
** rc_v0500000c_16jun2010.sof

* '''Features:'''
** Based on rev. 5.0.b
** Re-introduced flux-jump counter clamping to maintain continuity in behavior from past versions of firmware in the field.
** '''Important''': SQ1FB is applied 18 clock cycles after start of a row visit (SQ1_Bias being applied) regardless of flux-jump being enabled or not. In pre-5.0.b firmware SQ1FB was being applied after 7 clock cycles when flux-jump was disabled and after 18 clock cycles when flux-jump was enabled.

* '''Details:'''
* '''Bugs:'''
** '''flux-jump is broken'''. flux-jumping block misbehaves at the first jump in the negative range.

* '''FPGA Resource Usage''' (readout_card.fit.rpt): [[rc_5.0.c_fit_rpt]]
; Total logic elements ; 26,800 / 41,250 ( 65 % ) ;
; Total pins ; 358 / 616 ( 58 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;
; DSP block 9-bit elements ; 76 / 112 ( 68 % ) ;
; Total PLLs ; 1 / 6 ( 17 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt): [[rc_5.0.c_tan_rpt]]
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.964 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 4.382 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 15.924 ns ;

== Revision 5.0.b (not recommended) ==
* '''Filename:'''
** rc_v0500000b_03jun2010.sof

* '''Features:'''
** Based on rev. 5.0.a
** A bug that caused jumps in first-stage feedback, and detected as spikes in the raw data of pixels that were in servo_mode=0,1,2 was fixed. The jumps in FSFB were due to flux-jumping being enabled on live pixes with non-zero flx_quanta, and being disabled on the fly on dead pixels with flx_quanta=0. Flux-jumping is now disabled on a column-by-column basis if a column is in servo_mode = 0,1,2.
** Ineffective clamping was removed from the flux-jumping block (as per 5.0.9), as it is now replaced by the clamping that was perfected in rev. 5.0.10
** A sticky bit that only affected servo_mode=0,1,2 was also removed from the flux-jumping block.
** flx_lp_init commands now also clear the flux-jumping block as well.
** The 11-clock-cycle delay (in applying SQ1_FB) that in previous firmware only occurred when flux-jumping was enabled, now (in this version) is in effect all the time. Due to the bug-fix above, flux-jumping can be disabled on a column-by-column basis by setting servo_mode=0,1,2 when en_fb_jump=1. Before the change, this meant that constant values could be applied with or without the 11-cycle delay if en_fb_jump=1 or 0. To make the delay consistent, it is now always 11 cycles. As background, the flux-jumping block is pipelined, meaning that it does calculations for all 8 channels serially. The serialization is because of DSP-block limitations in the Readout Card FPGA that prevent us from doing all 8 channels in parallel. The reason that it takes 11 cycles to complete the flux-jumping calculations is because the values are computed for the eight channels in three ALU stages: 8 + 3 = 11 cycles. Adding 11 cycles to the 7 cycles of latency from other stages in the system results in: 11 + 7 = 18 cycles of latency from the start of a row dwell period before the first-stage feedback is applied. In rc_v5.0.c, I enforce the 18-cycle delay even when flux-jumping is not enabled to maintain uniformity across all eight channels, because flux-jumping is enabled/disabled on a per-channel basis. In other words, if I hadn't enforced the 18-cycle delay, some channels could have their feedback applied after 7 cycles, while others could have it applied after 18 cycles. I wasn't a fan of this non-uniformity. I realize that 18 cycles is a long time. In fact, so is 7. In the last few months, we have been discussing how to reduce these times to 1 cycle, because every experiment out there wants to multiplex as fast as possible, and the 7/18-delay is a rate limiting step.
** The flux-jumping code was re-arranged in the flux-jumping block to reflect the flow of data through the pipeline and make it easier to understand.

* '''Details:'''

* '''Bugs:'''
** flux-jump does not work when jumping to negative values.

* '''FPGA Resource Usage''' (readout_card.fit.rpt): [[rc_5.0.b_fit_rpt]]
; Total logic elements ; 26,745 / 41,250 ( 65 % ) ;
; Total pins ; 358 / 616 ( 58 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;
; DSP block 9-bit elements ; 76 / 112 ( 68 % ) ;
; Total PLLs ; 1 / 6 ( 17 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;
* '''FPGA Timing Analysis''' (readout_card.tan.rpt): [[rc_5.0.b_tan_rpt]]
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.459 ns
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.895 ns
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 15.956 ns

= Revision 5.0.a =
* '''Filename:'''
** rc_v0500000a_12mar2010.sof

* '''Features:'''
** Based on the merger of rev. 5.0.8 and 5.0.9.
** '''integral_clamp''' command is added where a clamp value is set for the integral term and once the integral term hits that value, the integral-term is clamped to that value and p-term and d-term are clamped to zero. When integral_term=0 then no clamping is in effect, similar to previous releases of firmware.
** The low pass filter has 20-bit input and f_3dB/f_samp = 122Hz/15kHz .
** The flux-jump clamping that was removed in 5.0.9 is included once again here, as we decided this is safer for now.

* '''Details:'''
** "lock_dat_left" parameter that was removed in 5.0.9 is now implemented as "lock_dat_lsb"

* '''Bugs:'''
** flx_lp_init does not reinitialize the flux-jump block

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis
** tag name: rc_v0500000a_12mar2009! years were mixed up!

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
* '''FPGA Timing Analysis''' (readout_card.tan.rpt):

== Revision 5.0.9 (buggy) ==
* '''Filename:'''
** rc_v05000009_13nov2009.sof

* '''Features:'''
** Based on rev. 5.0.4
** Removes a sticky bit in pid calculation result storage -- in fsfb_processor.
** Adds a command to clamp the growth of the I-term to prevent wrapping and track down the source of Caltech's FSFB jumps.
** Removed the unused lock_dat_left parameter. The ability to shift left was moved to the fsfb_corr block some time ago.
** Fixed a sign extension bug acting on the flux quanta, which limited the value to 8191. Changed the extension from signed to unsigned.
** Removed ineffective clamping in the flux-jump calculation block.
** IMPORTANT: Must be used in conjunction with firmware rev. 5.0.0+ of all other cards.

* '''Details:'''

* '''Bugs:'''
** integral_clamp read/write command does not work.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 27,960 / 41,250 ( 68 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.825 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.878 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 14.397 ns ;

== Revision 5.0.8 (UBC only) ==
* '''Filename:'''
** rc_v05000008_09oct2009.sof

* '''Features:'''
** Based on rev. 5.0.4
** type 1 low-pass filter: f3dB=122Hz for fsample=15kHz
** Filter-input-width changed from 18b to 20b with no sticky bits!
** removed sticky bits in internal arithmetic of the filter.

= Revision 5.0.7 (type-2 filter) =
* '''Filename:'''
** rc_v05000007_09oct2009.sof

* '''Features:'''
** Based on rev. 5.0.4
** type-2 low-pass-filter: f3dB=75Hz for fsample=30000.
** Filter-input-width changed from 18b to 20b with no sticky bits!
** inter-biquad-gain-scaling for the filter is 2^14
** filter results are scaled down by 2^3 in the output of the filter.
** removed sticky bits in internal arithmetics
** _correction_ disabled in fsfb_proc_pidz

* '''Details:'''
** quartus.ini file was '''not''' present in synth directory.

* '''Bugs:'''
** none to report

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
== Revision 5.0.6 (UBC only) ==
* '''Filename:'''
** rc_stratix3_v05000006_15sep2009.sof

* '''Features:'''
** Only Valid for Rev. C/D Cards
** Based on rev. 5.0.3
** tcl file updated for Rev. D and aligned with top-level and qsf (project file).
** flux loop commented, just to try sampling the ADC.
** compiled with Q9.1

== Revision 5.0.5 (UBC only) ==
* '''Filename:'''
** rc_v05000005_04sep2009.sof

* '''Features:'''
** Based on rev. 5.0.2
** changed the low-pass-filter to f(3db)=75Hz for f(sample)=30000.

* '''Details:'''
** quartus.ini file was '''not''' present in synth directory.

* '''Bugs:'''
** negative inputs to the filter cause filter to have a non-flat pass-band region. may have to do with sign-handling...

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
* '''FPGA Timing Analysis''' (readout_card.tan.rpt):

= Revision 5.0.4 =
* '''Filename:'''
** rc_v05000004_28aug2009.sof

* '''Features:'''
** Based on rev. 5.0.2
** BUG Fix: handles 14-bit flux quanta (changed the multiplier to unsigned)
** BUG Fix: changed standard logic vector extension from signed to unsigned in flux-jumping slave.
** IMPORTANT: Must be used in conjunction with firmware rev. 5.0.0+ of all other cards.

* '''Details:'''

* '''Bugs:'''
** None so far.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,170 / 41,250 ( 63 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.541 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.612 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 15.398 ns ;

= Revision 5.0.3 =
* '''Filename:'''
** rc_stratix3_v05000003_21aug2009.sof

* '''Features:'''
** ONLY valid REV C/D RC Cards
** Based on rev. 5.0.2
** flux loop commented, just to try sampling the ADC.
** updated tcl file, but still need to rely on project file as well as qsf file.
** changed default level of adc_sclk to '1'
** dac_clr_n was changed from an output to an input.
** added 'locked' interface to rc_pll_stratix_iii
** renamed the adc_pll clock signals to more explanitory names
** added the FPGA_DEVICE_FAMILY generic to the dispatch interace for synthesis of the dc_fifo in lvds_rx
** uncommented DDR interface to force the syntesizer to use correct left and right PLLs (in conjunction with ADC and DDR PLLs)
** added test signals to test_status to see clocks on the scope.
== Revision 5.0.2 (buggy) ==
* '''Filename:'''
** rc_v05000002_test00_tagged.sof

* '''Features:'''
** Based on rev. 5.0.1
** Fixed a bug in wbs_frame_data that stored data incorrectly if reporting 1 or 2 pixels only.
** IMPORTANT: Must be used in conjunction with firmware rev. 5.0.0+ of all other cards.

* '''Details:'''

* '''Bugs:'''
** None so far.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,186 / 41,250 ( 63 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.755 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.979 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.067 ns ;

== Revision 5.0.1 (buggy) (Filter + Raw + Rectangle, 2 LVDS) ==
* '''Filename:'''
** rc_v05000001_26may2009.sof

* '''Features:'''
** Combines features in rev. 5.0.0 (2 LVDS Lines) and rev. 4.0.e (Filtered + Raw), with the NEW rectangle mode.
** IMPORTANT: Must be used in conjunction with firmware rev. 5.0.0+ of all other cards.

* '''Details:'''
** [[CVS Diff Between sys_v05000000 and rc_v05000001]]

* '''Bugs:'''
** Has a bug in wbs_frame_data that stored data incorrectly if reporting 1 or 2 pixels only.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,565 / 41,250 ( 64 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.656 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.861 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 14.167 ns ;

== Revision 5.0.0 (Filter Only, 2 LVDS) ==
* '''Filename:'''
** rc_v05000000_22dec2008.sof (tagged as sys_v05000000_22dec2008)

* '''Features:'''
** IMPORTANT: Must be used in conjunction with firmware v05000000+ of all other cards!!!
** Adds the ability to read out one column of data continuously from readout cards
** Adds data mode 11, which is an engineering mode. Data points are 32-bits, and bits [9..3]=row_index, [2..0]=column_index. This mode is useful for determining which pixels one is reading out in the array, in column mode for example.

* '''Details:'''
** [[CVS Diff Between rc_v0400000c and sys_v05000000]]

* '''Bugs:'''
** None so far.

* '''Synthesis Notes:'''
** The quartus.ini file was not present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,607 / 41,250 ( 65 % ) ;
; Total memory bits ; 406,016 / 3,423,744 ( 12 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.558 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.892 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.987 ns ;

== Revision 4.0.f (Filter + Raw, 1 LVDS) ==
* '''Filename:'''
** rc_v0400000f_12feb2010.sof

* '''Features:'''
** Based on 4.0.e and in parallel with 5.0.9 (equivalent version, clamping is not included)
** Incorporates fixes that were done to flux-jumping between 5.0.2 - 5.0.4 - 5.0.9. Namely:
*** Changes a multiplier from signed to unsigned (in fsfb_corr_multplier.vhd).
*** Changes sign extension from signed to unsigned (in flux_quanta_ram_admin.vhd).

* '''Details:'''

* '''Bugs:'''
** None reported yet.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,773 / 41,250 ( 65 % ) ;
; Total memory bits ; 1,321,984 / 3,423,744 ( 39 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.539 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 4.118 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 17.318 ns ;

== Revision 4.0.e (Filter + Raw, 1 LVDS) ==
* '''Filename:'''
** rc_v0400000e_27apr2009.sof

* '''Features:'''
** Based on 4.0.d
** Combines both raw- and filtered-data modes.
** fpga_temp, card_temp, card_id commands are disabled.
** Tested by Matt Hasselfield.

* '''Details:'''

* '''Bugs:'''
** fpga_temp, card_temp, card_id commands are disabled.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 27,048 / 41,250 ( 66 % ) ;
; Total memory bits ; 1,321,984 / 3,423,744 ( 39 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.675 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.907 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.728 ns ;

== Revision 4.0.d (Raw Only, 1 LVDS) ==
* '''Filename:''' rc_v0400000d_20090417.sof

* '''Features:'''
** Based on v4.0.c, but has the filter removed, and implements a single 65536-index RAM block for storing 50 MHz raw-data samples.
** The firmware takes a new command called readout_col_index which specifies which column to capture raw data from.
** Other than readout_col_index, the firmware functions the same as previous raw-data firmware, including then need to issue a capture_raw command.
** For more information on raw-data, see: http://e-mode.phas.ubc.ca/mcewiki/index.php/Raw-mode_readout
** This firmware also integrates some of the improvements that were implemented in 4.4.0, like the removal of the tga_o signal from an FSM in dispatch_wishbone.vhd.

* '''Details:'''
** Differences between 4.0.c and 4.0.d
U system/test/source/tb/tb_cc_rcs_bcs_ac.vhd
U all_cards/dispatch/source/rtl/dispatch_wishbone.vhd
U library/sys_param/source/rtl/wishbone_pack.vhd
U readout_card/adc_sample_coadd/source/rtl/adc_sample_coadd.vhd
U readout_card/adc_sample_coadd/source/rtl/adc_sample_coadd_pack.vhd
U readout_card/flux_loop/source/rtl/flux_loop.vhd
U readout_card/flux_loop/source/rtl/flux_loop_pack.vhd
U readout_card/flux_loop_ctrl/source/rtl/flux_loop_ctrl.vhd
U readout_card/flux_loop_ctrl/source/rtl/flux_loop_ctrl_pack.vhd
U readout_card/flux_loop_ctrl/source/tb/tb1_flux_loop_ctrl.vhd
U readout_card/flux_loop_ctrl/source/tb/tb2_flux_loop_ctrl.vhd
U readout_card/fsfb_calc/source/rtl/fsfb_fltr_regs.vhd
U readout_card/fsfb_corr/source/rtl/fsfb_corr.vhd
U readout_card/readout_card/source/rtl/readout_card.vhd
U readout_card/readout_card/source/rtl/readout_card_pack.vhd
U readout_card/wbs_frame_data/source/rtl/wbs_frame_data.vhd
U readout_card/wbs_frame_data/source/rtl/wbs_frame_data_pack.vhd

* '''Bugs:'''
** None so far.
** fpga_temp, card_temp, card_id commands are not supported.

* '''Synthesis Notes:'''
** The quartus.ini file was present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 24,554 / 41,250 ( 60 % ) ;
; Total memory bits ; 1,262,592 / 3,423,744 ( 37 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.991 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.864 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 17.052 ns ;

== Revision 4.4.1 ==
* '''Filename:''' rc_v04040001_21nov2008

* '''Features:'''
** Fixes a bug that froze up the firmware if any of the following commands were issued: CARD_ID_ADDR, CARD_TEMP_ADDR, FPGA_TEMP_ADDR in 4.4.0 only.

* '''Details:'''
** The bug fix include adding more logic to the wishbone ack path (readout_card.vhd), which subsequently decreased the minimum clock setup time to 1.588ns. The new logic will catch errors that the old logic wouldn't have, and is now consistent with the firmware on all the other cards. However, if timing becomes an issue, the logic may have to revert back to that which was in version 4.0.c.

* '''Bugs:'''
** None so far.

* '''Synthesis Notes:'''
** The quartus.ini file was not present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 27,241 / 41,250 ( 66 % ) ;
; Total memory bits ; 405,504 / 3,423,744 ( 12 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.588 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.585 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 17.057 ns ;

== Revision 4.4.0 (buggy) ==
* '''Filename:''' rc_v04040000_02oct2008
* '''Features:'''
** Reinstated the data modes in wbs_frame_data.vhd that were removed in 4.0.c. This firmware has the following modes: '''0, 1, 2, 4, 5, 7, 10'''. The modes that are not present are: '''3''' (raw data), '''6''' (replaced by data_mode = 7), '''8''' (replaced by data_mode = 10), '''9''' (replaced by data_mode = 10). For more information on data modes, see [[Data mode]].
** Re-integrated the id_thermo and fpga_thermo block in the readout_card.vhd top level that was removed in 4.0.c.
** Removed the sticky bit in fsfb_corr.vhd, which was enabled when flux-jumping was turned on. Because the feedback is signed, the sticky bit would usually reflect the value of the 14th bit, except in situations when the number of flux quanta to jump was greater than 1 (i.e. cosmic rays, IV-curves, etc). Flux jumps are made at a maximum rate of one per frame period, so that if the First-Stage Feedback increased past the 13th bit, it would not be reflected in the feedback applied. Now it is.
* '''Details:'''
** Simplified the FSM logic in wbs_frame_data.vhd that determines when to transition from IDLE to WSS1. This was done to lower the number of gates in that path, and ease the timing.
** Removed the z_dat_i port in fsfb_processor.vhd and fsfb_calc_pack.vhd to the fsfb_proc_pidz block, in an effort to make it clearer within that block that the z-term is always = 0.
** Removed the z-term sign extension in fsfb_proc_pidz.vhd, and the [d-term + z-term] adder to free up DSP resources since the z-term is always = 0.
** Adjusted the indentation in fsfb_io_controller.vhd to make the file more readable.
** Moved the tga_o signal out of the dispatch_wishbone.vhd FSM, and made it a continuous assignment. This signal had one of the highest fan-out counts in the RTL design, and actually was impossible to route in Stratix III chips in its previous configuration because of the number of gates on the fan-out. As a consequence of making it a continuous assignment, the Stratix III fitter was able to succeed, and the Stratix I timing characteristics were greatly improved. This is the most significant change in this revision. This change single-handedly increased the minimum slack from 1.282 ns in v0400000c to 2.372 ns (or 56.7 MHz max) in this revision.
* '''Bugs:'''
** The following commands lock up the Readout Card firmware: CARD_ID_ADDR, CARD_TEMP_ADDR, FPGA_TEMP_ADDR.
** fb_const0 commands to channel 0 do not work. The value is stored in the register, but not applied to the DAC. Thus, read-back returns the correct value, but the DAC does not
* '''Synthesis Notes:'''
** The quartus.ini file was not present in the synth directory during synthesis.
* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 27,099 / 41,250 ( 66 % ) ;
; Total memory bits ; 406,016 / 3,423,744 ( 12 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.372 ns ;
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 4.052 ns ;
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.066 ns ;

== Revision 4.0.c ==
* '''Filename:''' rc_v0400000c_15aug2008.sof
* '''Features:'''
** Only has data modes 0, 1, 4, and 10.
** Fixed the bug that exists in 4.0.b, 4.0.a, and 4.0.9 that prevented the fb_const value from being applied to channel zero (wbs_fb_data.vhd).
* '''Details:'''
** Changed a counter in the dispatch block to ease timing constraints in synthesis (dispatch_wishbone.vhd)
** Updated the tagged versions of dispatch.vhd , dispatch_cmd_receive.vhd, and dispatch_reply_transmit.vhd to the version that is used by all the other cards.
** '''Removed''' the fpga_termo (command: '''fpga_temp''') and id_thermo (commands: '''card_temp, card_id''') to ease timing constraints in synthesis (readout_card.vhd)
** Updated the tagged version of fpga_termo.vhd to include the new 'stale bit' feature
** Updated the tagged version of frame_timing_core.vhd to include the new 'err_o' interface
* '''Bugs:'''
** None reported yet
* '''Synthesis Notes:'''
** The quartus.ini file was not present in the synth directory during synthesis.
* '''FPGA Resource Usage:'''
Total logic elements : 25,058 / 41,250 ( 61 % )
Total memory bits : 400,896 / 3,423,744 ( 12 % )

* '''Timing Analysis''' (readout_card.tan.rpt):
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.282 ns ;
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.736 ns ;
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.665 ns ;

== Revision 4.0.b (buggy) ==
Note: This revision is on a watch list, after the bug detected 15 July 2008. See the bug section for more details.
* '''Filename''' : rc_v0400000b_04aug2008.sof
* '''Features'''
** data_mode 10 is added to provide more filtfb bits (compared to data mode 9) for planet observations. filtered_dat(27 downto 3) & flux_cnt_dat(6 downto 0)

* '''Bugs'''
** An unexplained bug that appeared in 4.0.a and may still be present in 4.0.b is a problem with the readout of channels being clipped out of data reporting. [[Bug 1 Notes]]

* ''' Synthesis note '''
** Quartus.ini removed.

== Revision 4.0.a (buggy) ==
Note: This revision is on a watch list, after the bug detected 15 July 2008. See the bug section for more details.
* '''Filename''' : rc_v0400000a_07jul2008.sof
* '''Bug Fix'''
** mce_status and adc_offset/flx_quanta commands do not fail after power up.
* ''' Synthesis note '''
** Quartus.ini removed.

* '''Bugs'''
** Seems to clip out channel 0 from data reporting.

== Revision 4.0.9 (buggy) ==
* '''Filename''' : rc_v04000009_26jun2008.sof
* '''Features'''
** sa_bias and offset DACs only refreshed when new values are written. (in previous versions, DACs were refreshed every frame)
* '''Bugs'''
** fb_const0 commands to channel 0 do not work. The value is stored in the register, but not applied to the DAC. Thus, read-back returns the correct value, but the DAC does not.
** reading flx_quanta and adc_offset right after power up hangs the reply datapath to CC. resetmce clears this error as temporary solution. the problem is caused by first read ack of the wishbone slave.

== Revision 4.0.8 ==
* '''Filename''' : rc_v04000008_26jun2008.sof
* '''Features'''
** The gaini, gainp, gaind resolution increased to 12-bit, i.e. -2048 to 2047 (formerly 10-bit).

* '''Bug fix'''
** the bug associated with gainpid read before mce_reset is fixed.

* ''' Synthesis note '''
** Quartus.ini removed.

== Revision 4.3.7 ==
* '''Filename''' : rc_v04030007_26may2008_raw.sof
* '''Features'''
** 14-bit raw mode enabled to buffer a snapshot of 50MHz samples for 2 frames of row_len * num_rows samples.
** In order to extend the raw-mode to 14-bit, an assumption is made that the raw buffer is not written to while being read. Therefore, make sure there is at least 2*row_len*num_rows*20ns between issuing captr_raw command and reading back the raw data.
** In order to save RAM for raw mode, two memory-intensive features are disabled:
*** low-pass filter disabled ( mixed filtfb data modes 6, 7, 9 are also disabled)
*** PID (gainp0, gaini0, gaind0) readback disabled. one can still set PID values and run servo, but can not read back the values.

== Revision 4.2.7 ==
* '''Filename''' : rc_v04020007_24may2008_raw.sof
* '''Features'''
** raw mode enabled to buffer a snapshot of 50MHz samples for 2 frames of row_len * num_rows samples.
** In order to save RAM for raw mode, two memory-intensive features are disabled:
*** low-pass filter disabled ( mixed filtfb data modes 6, 7, 9 are also disabled)
*** PID (gainp0, gaini0, gaind0) readback disabled. one can still set PID values and run servo, but can not read back the values.
* '''Bug fix'''
** the bug associated with reading from raw-buffer is fixed.

== Revision 4.1.7 ==
* '''Filename''' : rc_v04010007_25apr2008_raw.sof
* '''Features'''
** raw mode enabled to buffer a snapshot of 50MHz samples for 2 frames of row_len * num_rows samples.
** In order to save RAM for raw mode, two memory-intensive features are disabled:
*** low-pass filter disabled ( mixed filtfb data modes 6, 7, 9 are also disabled)
*** PID (gainp0, gaini0, gaind0) readback disabled. one can still set PID values and run servo, but can not read back the values.
* '''Bugs'''
** after each readout frame, raw-buffer readout counter falls behind by 3 and this causes skipping 3 50MHz samples in the data stream and column-data being messed up in subsequent frames. Data can be rearranged by post processing.

== Revision 4.0.6 (buggy) ==
* '''Filename''' : rc_v04000006_15feb2008.sof or .pof
* '''Features'''
** '''bugfix''': unreliable reset due to unsafe and incomplete state machines is fixed.
** '''bugfix''': flux_jump sign problem fixed, so far proved in const_mode, to be tested in servo_mode with cold setup.
** servo_mode=2 or ramp previously only went from 0 to ramp_amp, but now goes from -8192 to -8192+ramp_amp
** new commands are added: ''scratch'' and ''card_type''. Scratch takes 8 values and can be used by software to detect reset.
** slot_id and fw_rev are now integrated as part of all_cards.vhd
** lvds_tx_b=0, This will allow Clock Card to use the secondary backplane lvds line and check whether RC is plugged in.
** filter_coeff in misc_banks_admin commented as it is not implemented and causes timing problems.

* '''Bugs'''
** reading gainp/gaini/gaind right after power up hangs the reply datapath to CC. resetmce clears this error as temporary solution. the problem is caused by first read ack of pid_ram_admin.
** slot_id is only set after a resetmce is issued. (using the latest all_cards in the next revision will fix this)
** has spurious spikes on channel 7 data, which max out the integral, and cause the detectors to come unlocked. This firmware officially meets timing requirements, but the bug could be due to marginal timing on the longest data paths, i.e. ~0.1 ns in some cases.

== Revision 4.0.5 ==
* '''Filename''' : rc_v04000005_01nov2007.sof or .pof
* '''Features'''
** data mode 9 (mixed filt + flux jump) with windowing readjusted compared to data mode 8

* '''Bugs'''
** unreliable resetmce. Sometimes, firmware waked up non-responsive on lvds lines.
** In data mode 5 and 9, flux-jump counter is not reported properly due to a sign error. However, flux jumping works fine.

== Revision 3.0.19 ==
* '''Filename''' : rc_v03000019_16feb2007_raw.sof (no pof as one is not likely to run with this as regular firmware)
* '''Features'''
** data mode 3 is enabled.
** filter is disabled as a compromise to fit the raw-mode buffer.

* '''Bugs'''
** unreliable resetmce. Sometimes, firmware waked up non-responsive on lvds lines.

== Old Firmware Revisions ==
* '''4.0.4''': rc_v04000004_11oct2007.sof data mode 8 added (mixed filt + flux jump)
* '''4.0.3''': rc_v04000003_19sep2007.sof data mode 7 bit split readjusted to 10b error being bit 4 to 14
* '''4.0.2''': rc_v04000002_11sep2007.sof pid resolution increased to 10b, data mode 7 added
* '''4.0.1''': rc_v04000001_06sep2007.sof
* '''4.0.0''': rc_v04000000_29aug2007.sof supports readout_row_index * [[ bugs ]]

= To-Do List =
* the starting point for the servo is currently zero and it would be nice to have it programmable.

= RC Synthesis Notes =
# The following note applies when using Quartus versions earlier than Q7: Quartus.ini file had to exist in synth directory up to revision 4.0.a due to a bug that started in Quartus 6.1 and would synthesize away arbitrary parts of readout card. We contacted Altera at the time and they provided us the ini file.
# Timing: There is no "lock region" defined for readout card. Timing on readout card is tight and since version 3 or so any new feature would initially fail timing till some synthesis options were tweaked. One path that remains to be consistently marginal is from addr_gen counter (i.e. tga_o counter) in dispatch_wishbone.vhd to wishbone slaves particularly misc_banks_admin.vhd. Modules that are rewritten to address timing concerns are fsfb_corr, all_cards, misc_banks_admin, and finally instantiating an lpm counter instead of a counter from components library. Surprisingly, the lpm counter reduced 87 failures to 37, although looking at the technology map viewer, it seemed that they were both synthesized the same.
# Compile time: This was at some point 4.5 hours, after going to dual core PC, this was reduced to 35 minutes. After extending pid gains to 12b and fixing offset/sa_bias update code, the compile time increased to 1.5hr again with utilization up to ~70%.
# wbs_fb_storage, ram_8x64, pid_ram had to be regenerated using latest (Q7.2) MegaWizard to get rid of the bug associated with failure to read after power up until a reset was issued.
# During simulations, the initialization of RAM block with .hex files needs to be disabled. This is done by commenting out the following lines from the MegaWizard generated Megafunction files (remember to un-comment them before synthesizing the code):
lpm_file => "C:/scuba2_repository/cards/readout_card/fsfb_calc/source/rtl/ram_40x64.hex", and
lpm_file : STRING;
#Starting Q10.0 use TimeQuest timing analyzer as oppose to the classic one. The classic one is being phased out by Altera. In order to use TimeQuest, you need to have an sdc file present in your project directory.
----
[http://e-mode.phas.ubc.ca/mcewiki/index.php/Main_Page MCE Main Page]

Readout Card firmware

2011-05-04T21:45:08Z

Bburger: /* Revision 5.0.d */

* Synthesis Reminders (for firmware developers)
** quartus.ini is not needed anymore (Fixed as of Q7, Altera SR10783580 2010-10-24)
** Remember that readout_card/fsfb_clac/source/rtl/ram_40x64.vhd must be initialized with the ram_40x64.hex file in the same directory.
== Revision 5.1.2 ==
* '''Filename:'''
** rc_stratix3_v05010002_18jan2011.sof (for Rev. E cards)
** rc_stratix3_v05010002_18jan2011.jic (for Rev. E cards)
** rc_v05010002_03feb2011.sof (for Rev. B cards)
** rc_v05010002_03feb2011.pof (for Rev. B cards)

* '''Features:'''
** based on 5.1.1 with k1 and k2 (filter params) limited to k1<16 and k2<32 in order to resolve the timing when compiling for smaller Stratix FPGA on RC Rev. B.

* '''Bug fix:'''
** the 2-rows-off filtered data readout introduced with configurable filter in rev. 5.1.0 and 5.1.1 is fixed now.

* '''Bugs:'''
** none so far.

* '''FPGA Resource Usage''' (readout_card.fit.rpt)
; Total logic elements ; 33,285 / 41,250 ( 81 % ) ;
; Total pins ; 358 / 616 ( 58 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt)
; Fast Model Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 6.591 ns
; Fast Model Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 7.206 ns
; Fast Model Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 18.299 ns

== Revision 5.1.1 (not recommended) ==
* '''Filename:'''
** rc_v05010001_01dec2010.sof (for Rev. B cards)

* '''Features:'''
** based on 5.1.0, but k1 and k2 (filter params) are now limited to k1<16 and k2<32 in order to resolve the timing failures of compiling 5.1.0 for smaller Stratix FPGA on RC Rev. B.

* '''Bugs:'''
** filter mode data is off by 2 rows.

== Revision 5.1.0 (not recommended) ==
* '''Filename:'''
** rc_stratix3_v05010000_01nov2010.sof (for Rev. E cards)
** rc_v05010000_01nov2010.sof (for Rev. B cards) has timing failures '''do not use!!!'''

* '''Features:'''
** added configurable filter parameters specified by ''fltr_coeff'', default is the fcutoff/fsampl=122Hz/15kHz. see [[ Digital 4-pole Butterworth Low-pass filter ]].
** ''fltr_type'' is set to 255 to indicate configurable filter parameters.
** see [http://www.phas.ubc.ca/~mce/mcedocs/software/SC2_ELE_S580_515_mce_command_description.pdf MCE command description]
** development notes:
*** It is built on Quartus10.1.
*** tcl files had to be updated as cmp syntax is not supported in Q10 anymore.
*** Rev. E cards now can be identified by reading back pcb_rev as part of card_type, therefore both stratix I and III sof/pof/jic are generated from the same source.

* '''Bugs:'''
** rc_v05010000_01nov2010.sof has timing failures that were overlooked, do not use this firmware for Rev.B cards.
** '''filter mode data is off by 2 rows.'''

* '''FPGA Resource Usage and Timing Report''' (readout_card.fit.rpt and readout_card.tan.rpt): logic usage is upto 85% from 66% in 5.0.d/e/f

= Revision 5.0.f =
* '''Filename:'''
** rc_v0500000f_22oct2010.sof (for Rev. B cards)
** rc_stratix3_v0500000f_22oct2010.sof (for Rev. E cards)

* '''Features:'''
** Bugfix: integral clamp should work now. only positive integral_clamp values are valid!

* '''Details:''':
** SQ1FB is applied 18 clock cycles after start of a row visit (SQ1_Bias being applied) regardless of flux-jump being enabled or not. In pre-5.0.b firmware SQ1FB was being applied after 7 clock cycles when flux-jump was disabled and after 18 clock cycles when flux-jump was enabled.
** available for both Rev. E and Rev. B cards, the upper byte of card_type parameter now reports the pcb revision.
** development note: It is built on Quartus10.1.

* '''Bugs:'''
**none yet!

* '''FPGA Resource Usage and Timing Report''' (readout_card.fit.rpt and readout_card.tan.rpt): no change compared to 5.0.a/b/c/d

== Revision 5.0.e (not recommended) ==
* '''Filename:'''
** rc_v0500000e_06oct2010.sof

* '''Details:'''
** an unsuccessful attempt to fix integral_clamp, but changed the functionality so that it clamps at the value, but it doesn't hold the clamp. i.e., if the calculated sq1fb becomes less than the specified clamp value, the sq1fb is not clamped anymore. This is not a desired functionality!

== Revision 5.0.d ==
* '''Filename:'''
** rc_v0500000d_04aug2010.sof

* '''Features:'''
** Bugfix: To fix the bug associated with negative flux-jumps, reverted to signed multiplier and hence, incremented the width of the flux-quanta multiplier input by 1.

* '''Details:''': SQ1FB is applied 18 clock cycles after start of a row visit (SQ1_Bias being applied) regardless of flux-jump being enabled or not. In pre-5.0.b firmware SQ1FB was being applied after 7 clock cycles when flux-jump was disabled and after 18 clock cycles when flux-jump was enabled.

* '''Bugs:'''
** '''integral_clamping is broken'''. To test the clamping, a servo-locked ramp was initiated on the sq1fb and then flux-jumping was turned on and observed by attaching a scope to the SQ1FB output. With integral_clamp=80000000, flux_quanta=8000, gaini=1, flux-jump enabled, we see [[http://e-mode.phas.ubc.ca/mcewiki/index.php/Image:Clamp_unstable.png scope snapshot]] used slow_fb_ramp.py script for testing.

* '''FPGA Resource Usage and Timing Report''' (readout_card.fit.rpt and readout_card.tan.rpt): no change compared to 5.0.a/b/c

== Revision 5.0.c (not recommended) ==
* '''Filename:'''
** rc_v0500000c_16jun2010.sof

* '''Features:'''
** Based on rev. 5.0.b
** Re-introduced flux-jump counter clamping to maintain continuity in behavior from past versions of firmware in the field.
** '''Important''': SQ1FB is applied 18 clock cycles after start of a row visit (SQ1_Bias being applied) regardless of flux-jump being enabled or not. In pre-5.0.b firmware SQ1FB was being applied after 7 clock cycles when flux-jump was disabled and after 18 clock cycles when flux-jump was enabled.

* '''Details:'''
* '''Bugs:'''
** '''flux-jump is broken'''. flux-jumping block misbehaves at the first jump in the negative range.

* '''FPGA Resource Usage''' (readout_card.fit.rpt): [[rc_5.0.c_fit_rpt]]
; Total logic elements ; 26,800 / 41,250 ( 65 % ) ;
; Total pins ; 358 / 616 ( 58 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;
; DSP block 9-bit elements ; 76 / 112 ( 68 % ) ;
; Total PLLs ; 1 / 6 ( 17 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt): [[rc_5.0.c_tan_rpt]]
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.964 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 4.382 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 15.924 ns ;

== Revision 5.0.b (not recommended) ==
* '''Filename:'''
** rc_v0500000b_03jun2010.sof

* '''Features:'''
** Based on rev. 5.0.a
** A bug that caused jumps in first-stage feedback, and detected as spikes in the raw data of pixels that were in servo_mode=0,1,2 was fixed. The jumps in FSFB were due to flux-jumping being enabled on live pixes with non-zero flx_quanta, and being disabled on the fly on dead pixels with flx_quanta=0. Flux-jumping is now disabled on a column-by-column basis if a column is in servo_mode = 0,1,2.
** Ineffective clamping was removed from the flux-jumping block (as per 5.0.9), as it is now replaced by the clamping that was perfected in rev. 5.0.10
** A sticky bit that only affected servo_mode=0,1,2 was also removed from the flux-jumping block.
** flx_lp_init commands now also clear the flux-jumping block as well.
** The 11-clock-cycle delay (in applying SQ1_FB) that in previous firmware only occurred when flux-jumping was enabled, now (in this version) is in effect all the time. Due to the bug-fix above, flux-jumping can be disabled on a column-by-column basis by setting servo_mode=0,1,2 when en_fb_jump=1. Before the change, this meant that constant values could be applied with or without the 11-cycle delay if en_fb_jump=1 or 0. To make the delay consistent, it is now always 11 cycles. As background, the flux-jumping block is pipelined, meaning that it does calculations for all 8 channels serially. The serialization is because of DSP-block limitations in the Readout Card FPGA that prevent us from doing all 8 channels in parallel. The reason that it takes 11 cycles to complete the flux-jumping calculations is because the values are computed for the eight channels in three ALU stages: 8 + 3 = 11 cycles. Adding 11 cycles to the 7 cycles of latency from other stages in the system results in: 11 + 7 = 18 cycles of latency from the start of a row dwell period before the first-stage feedback is applied. In rc_v5.0.c, I enforce the 18-cycle delay even when flux-jumping is not enabled to maintain uniformity across all eight channels, because flux-jumping is enabled/disabled on a per-channel basis. In other words, if I hadn't enforced the 18-cycle delay, some channels could have their feedback applied after 7 cycles, while others could have it applied after 18 cycles. I wasn't a fan of this non-uniformity. I realize that 18 cycles is a long time. In fact, so is 7. In the last few months, we have been discussing how to reduce these times to 1 cycle, because every experiment out there wants to multiplex as fast as possible, and the 7/18-delay is a rate limiting step.
** The flux-jumping code was re-arranged in the flux-jumping block to reflect the flow of data through the pipeline and make it easier to understand.

* '''Details:'''

* '''Bugs:'''
** flux-jump does not work when jumping to negative values.

* '''FPGA Resource Usage''' (readout_card.fit.rpt): [[rc_5.0.b_fit_rpt]]
; Total logic elements ; 26,745 / 41,250 ( 65 % ) ;
; Total pins ; 358 / 616 ( 58 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;
; DSP block 9-bit elements ; 76 / 112 ( 68 % ) ;
; Total PLLs ; 1 / 6 ( 17 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;
* '''FPGA Timing Analysis''' (readout_card.tan.rpt): [[rc_5.0.b_tan_rpt]]
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.459 ns
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.895 ns
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 15.956 ns

= Revision 5.0.a =
* '''Filename:'''
** rc_v0500000a_12mar2010.sof

* '''Features:'''
** Based on the merger of rev. 5.0.8 and 5.0.9.
** '''integral_clamp''' command is added where a clamp value is set for the integral term and once the integral term hits that value, the integral-term is clamped to that value and p-term and d-term are clamped to zero. When integral_term=0 then no clamping is in effect, similar to previous releases of firmware.
** The low pass filter has 20-bit input and f_3dB/f_samp = 122Hz/15kHz .
** The flux-jump clamping that was removed in 5.0.9 is included once again here, as we decided this is safer for now.

* '''Details:'''
** "lock_dat_left" parameter that was removed in 5.0.9 is now implemented as "lock_dat_lsb"

* '''Bugs:'''
** flx_lp_init does not reinitialize the flux-jump block

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis
** tag name: rc_v0500000a_12mar2009! years were mixed up!

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
* '''FPGA Timing Analysis''' (readout_card.tan.rpt):

== Revision 5.0.9 (buggy) ==
* '''Filename:'''
** rc_v05000009_13nov2009.sof

* '''Features:'''
** Based on rev. 5.0.4
** Removes a sticky bit in pid calculation result storage -- in fsfb_processor.
** Adds a command to clamp the growth of the I-term to prevent wrapping and track down the source of Caltech's FSFB jumps.
** Removed the unused lock_dat_left parameter. The ability to shift left was moved to the fsfb_corr block some time ago.
** Fixed a sign extension bug acting on the flux quanta, which limited the value to 8191. Changed the extension from signed to unsigned.
** Removed ineffective clamping in the flux-jump calculation block.
** IMPORTANT: Must be used in conjunction with firmware rev. 5.0.0+ of all other cards.

* '''Details:'''

* '''Bugs:'''
** integral_clamp read/write command does not work.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 27,960 / 41,250 ( 68 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.825 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.878 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 14.397 ns ;

== Revision 5.0.8 (UBC only) ==
* '''Filename:'''
** rc_v05000008_09oct2009.sof

* '''Features:'''
** Based on rev. 5.0.4
** type 1 low-pass filter: f3dB=122Hz for fsample=15kHz
** Filter-input-width changed from 18b to 20b with no sticky bits!
** removed sticky bits in internal arithmetic of the filter.

= Revision 5.0.7 (type-2 filter) =
* '''Filename:'''
** rc_v05000007_09oct2009.sof

* '''Features:'''
** Based on rev. 5.0.4
** type-2 low-pass-filter: f3dB=75Hz for fsample=30000.
** Filter-input-width changed from 18b to 20b with no sticky bits!
** inter-biquad-gain-scaling for the filter is 2^14
** filter results are scaled down by 2^3 in the output of the filter.
** removed sticky bits in internal arithmetics
** _correction_ disabled in fsfb_proc_pidz

* '''Details:'''
** quartus.ini file was '''not''' present in synth directory.

* '''Bugs:'''
** none to report

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
== Revision 5.0.6 (UBC only) ==
* '''Filename:'''
** rc_stratix3_v05000006_15sep2009.sof

* '''Features:'''
** Only Valid for Rev. C/D Cards
** Based on rev. 5.0.3
** tcl file updated for Rev. D and aligned with top-level and qsf (project file).
** flux loop commented, just to try sampling the ADC.
** compiled with Q9.1

== Revision 5.0.5 (UBC only) ==
* '''Filename:'''
** rc_v05000005_04sep2009.sof

* '''Features:'''
** Based on rev. 5.0.2
** changed the low-pass-filter to f(3db)=75Hz for f(sample)=30000.

* '''Details:'''
** quartus.ini file was '''not''' present in synth directory.

* '''Bugs:'''
** negative inputs to the filter cause filter to have a non-flat pass-band region. may have to do with sign-handling...

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
* '''FPGA Timing Analysis''' (readout_card.tan.rpt):

= Revision 5.0.4 =
* '''Filename:'''
** rc_v05000004_28aug2009.sof

* '''Features:'''
** Based on rev. 5.0.2
** BUG Fix: handles 14-bit flux quanta (changed the multiplier to unsigned)
** BUG Fix: changed standard logic vector extension from signed to unsigned in flux-jumping slave.
** IMPORTANT: Must be used in conjunction with firmware rev. 5.0.0+ of all other cards.

* '''Details:'''

* '''Bugs:'''
** None so far.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,170 / 41,250 ( 63 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.541 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.612 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 15.398 ns ;

= Revision 5.0.3 =
* '''Filename:'''
** rc_stratix3_v05000003_21aug2009.sof

* '''Features:'''
** ONLY valid REV C/D RC Cards
** Based on rev. 5.0.2
** flux loop commented, just to try sampling the ADC.
** updated tcl file, but still need to rely on project file as well as qsf file.
** changed default level of adc_sclk to '1'
** dac_clr_n was changed from an output to an input.
** added 'locked' interface to rc_pll_stratix_iii
** renamed the adc_pll clock signals to more explanitory names
** added the FPGA_DEVICE_FAMILY generic to the dispatch interace for synthesis of the dc_fifo in lvds_rx
** uncommented DDR interface to force the syntesizer to use correct left and right PLLs (in conjunction with ADC and DDR PLLs)
** added test signals to test_status to see clocks on the scope.
== Revision 5.0.2 (buggy) ==
* '''Filename:'''
** rc_v05000002_test00_tagged.sof

* '''Features:'''
** Based on rev. 5.0.1
** Fixed a bug in wbs_frame_data that stored data incorrectly if reporting 1 or 2 pixels only.
** IMPORTANT: Must be used in conjunction with firmware rev. 5.0.0+ of all other cards.

* '''Details:'''

* '''Bugs:'''
** None so far.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,186 / 41,250 ( 63 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.755 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.979 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.067 ns ;

== Revision 5.0.1 (buggy) (Filter + Raw + Rectangle, 2 LVDS) ==
* '''Filename:'''
** rc_v05000001_26may2009.sof

* '''Features:'''
** Combines features in rev. 5.0.0 (2 LVDS Lines) and rev. 4.0.e (Filtered + Raw), with the NEW rectangle mode.
** IMPORTANT: Must be used in conjunction with firmware rev. 5.0.0+ of all other cards.

* '''Details:'''
** [[CVS Diff Between sys_v05000000 and rc_v05000001]]

* '''Bugs:'''
** Has a bug in wbs_frame_data that stored data incorrectly if reporting 1 or 2 pixels only.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,565 / 41,250 ( 64 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.656 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.861 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 14.167 ns ;

== Revision 5.0.0 (Filter Only, 2 LVDS) ==
* '''Filename:'''
** rc_v05000000_22dec2008.sof (tagged as sys_v05000000_22dec2008)

* '''Features:'''
** IMPORTANT: Must be used in conjunction with firmware v05000000+ of all other cards!!!
** Adds the ability to read out one column of data continuously from readout cards
** Adds data mode 11, which is an engineering mode. Data points are 32-bits, and bits [9..3]=row_index, [2..0]=column_index. This mode is useful for determining which pixels one is reading out in the array, in column mode for example.

* '''Details:'''
** [[CVS Diff Between rc_v0400000c and sys_v05000000]]

* '''Bugs:'''
** None so far.

* '''Synthesis Notes:'''
** The quartus.ini file was not present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,607 / 41,250 ( 65 % ) ;
; Total memory bits ; 406,016 / 3,423,744 ( 12 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.558 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.892 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.987 ns ;

== Revision 4.0.f (Filter + Raw, 1 LVDS) ==
* '''Filename:'''
** rc_v0400000f_12feb2010.sof

* '''Features:'''
** Based on 4.0.e and in parallel with 5.0.9 (equivalent version, clamping is not included)
** Incorporates fixes that were done to flux-jumping between 5.0.2 - 5.0.4 - 5.0.9. Namely:
*** Changes a multiplier from signed to unsigned (in fsfb_corr_multplier.vhd).
*** Changes sign extension from signed to unsigned (in flux_quanta_ram_admin.vhd).

* '''Details:'''

* '''Bugs:'''
** None reported yet.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,773 / 41,250 ( 65 % ) ;
; Total memory bits ; 1,321,984 / 3,423,744 ( 39 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.539 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 4.118 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 17.318 ns ;

== Revision 4.0.e (Filter + Raw, 1 LVDS) ==
* '''Filename:'''
** rc_v0400000e_27apr2009.sof

* '''Features:'''
** Based on 4.0.d
** Combines both raw- and filtered-data modes.
** fpga_temp, card_temp, card_id commands are disabled.
** Tested by Matt Hasselfield.

* '''Details:'''

* '''Bugs:'''
** fpga_temp, card_temp, card_id commands are disabled.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 27,048 / 41,250 ( 66 % ) ;
; Total memory bits ; 1,321,984 / 3,423,744 ( 39 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.675 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.907 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.728 ns ;

== Revision 4.0.d (Raw Only, 1 LVDS) ==
* '''Filename:''' rc_v0400000d_20090417.sof

* '''Features:'''
** Based on v4.0.c, but has the filter removed, and implements a single 65536-index RAM block for storing 50 MHz raw-data samples.
** The firmware takes a new command called readout_col_index which specifies which column to capture raw data from.
** Other than readout_col_index, the firmware functions the same as previous raw-data firmware, including then need to issue a capture_raw command.
** For more information on raw-data, see: http://e-mode.phas.ubc.ca/mcewiki/index.php/Raw-mode_readout
** This firmware also integrates some of the improvements that were implemented in 4.4.0, like the removal of the tga_o signal from an FSM in dispatch_wishbone.vhd.

* '''Details:'''
** Differences between 4.0.c and 4.0.d
U system/test/source/tb/tb_cc_rcs_bcs_ac.vhd
U all_cards/dispatch/source/rtl/dispatch_wishbone.vhd
U library/sys_param/source/rtl/wishbone_pack.vhd
U readout_card/adc_sample_coadd/source/rtl/adc_sample_coadd.vhd
U readout_card/adc_sample_coadd/source/rtl/adc_sample_coadd_pack.vhd
U readout_card/flux_loop/source/rtl/flux_loop.vhd
U readout_card/flux_loop/source/rtl/flux_loop_pack.vhd
U readout_card/flux_loop_ctrl/source/rtl/flux_loop_ctrl.vhd
U readout_card/flux_loop_ctrl/source/rtl/flux_loop_ctrl_pack.vhd
U readout_card/flux_loop_ctrl/source/tb/tb1_flux_loop_ctrl.vhd
U readout_card/flux_loop_ctrl/source/tb/tb2_flux_loop_ctrl.vhd
U readout_card/fsfb_calc/source/rtl/fsfb_fltr_regs.vhd
U readout_card/fsfb_corr/source/rtl/fsfb_corr.vhd
U readout_card/readout_card/source/rtl/readout_card.vhd
U readout_card/readout_card/source/rtl/readout_card_pack.vhd
U readout_card/wbs_frame_data/source/rtl/wbs_frame_data.vhd
U readout_card/wbs_frame_data/source/rtl/wbs_frame_data_pack.vhd

* '''Bugs:'''
** None so far.
** fpga_temp, card_temp, card_id commands are not supported.

* '''Synthesis Notes:'''
** The quartus.ini file was present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 24,554 / 41,250 ( 60 % ) ;
; Total memory bits ; 1,262,592 / 3,423,744 ( 37 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.991 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.864 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 17.052 ns ;

== Revision 4.4.1 ==
* '''Filename:''' rc_v04040001_21nov2008

* '''Features:'''
** Fixes a bug that froze up the firmware if any of the following commands were issued: CARD_ID_ADDR, CARD_TEMP_ADDR, FPGA_TEMP_ADDR in 4.4.0 only.

* '''Details:'''
** The bug fix include adding more logic to the wishbone ack path (readout_card.vhd), which subsequently decreased the minimum clock setup time to 1.588ns. The new logic will catch errors that the old logic wouldn't have, and is now consistent with the firmware on all the other cards. However, if timing becomes an issue, the logic may have to revert back to that which was in version 4.0.c.

* '''Bugs:'''
** None so far.

* '''Synthesis Notes:'''
** The quartus.ini file was not present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 27,241 / 41,250 ( 66 % ) ;
; Total memory bits ; 405,504 / 3,423,744 ( 12 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.588 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.585 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 17.057 ns ;

== Revision 4.4.0 (buggy) ==
* '''Filename:''' rc_v04040000_02oct2008
* '''Features:'''
** Reinstated the data modes in wbs_frame_data.vhd that were removed in 4.0.c. This firmware has the following modes: '''0, 1, 2, 4, 5, 7, 10'''. The modes that are not present are: '''3''' (raw data), '''6''' (replaced by data_mode = 7), '''8''' (replaced by data_mode = 10), '''9''' (replaced by data_mode = 10). For more information on data modes, see [[Data mode]].
** Re-integrated the id_thermo and fpga_thermo block in the readout_card.vhd top level that was removed in 4.0.c.
** Removed the sticky bit in fsfb_corr.vhd, which was enabled when flux-jumping was turned on. Because the feedback is signed, the sticky bit would usually reflect the value of the 14th bit, except in situations when the number of flux quanta to jump was greater than 1 (i.e. cosmic rays, IV-curves, etc). Flux jumps are made at a maximum rate of one per frame period, so that if the First-Stage Feedback increased past the 13th bit, it would not be reflected in the feedback applied. Now it is.
* '''Details:'''
** Simplified the FSM logic in wbs_frame_data.vhd that determines when to transition from IDLE to WSS1. This was done to lower the number of gates in that path, and ease the timing.
** Removed the z_dat_i port in fsfb_processor.vhd and fsfb_calc_pack.vhd to the fsfb_proc_pidz block, in an effort to make it clearer within that block that the z-term is always = 0.
** Removed the z-term sign extension in fsfb_proc_pidz.vhd, and the [d-term + z-term] adder to free up DSP resources since the z-term is always = 0.
** Adjusted the indentation in fsfb_io_controller.vhd to make the file more readable.
** Moved the tga_o signal out of the dispatch_wishbone.vhd FSM, and made it a continuous assignment. This signal had one of the highest fan-out counts in the RTL design, and actually was impossible to route in Stratix III chips in its previous configuration because of the number of gates on the fan-out. As a consequence of making it a continuous assignment, the Stratix III fitter was able to succeed, and the Stratix I timing characteristics were greatly improved. This is the most significant change in this revision. This change single-handedly increased the minimum slack from 1.282 ns in v0400000c to 2.372 ns (or 56.7 MHz max) in this revision.
* '''Bugs:'''
** The following commands lock up the Readout Card firmware: CARD_ID_ADDR, CARD_TEMP_ADDR, FPGA_TEMP_ADDR.
** fb_const0 commands to channel 0 do not work. The value is stored in the register, but not applied to the DAC. Thus, read-back returns the correct value, but the DAC does not
* '''Synthesis Notes:'''
** The quartus.ini file was not present in the synth directory during synthesis.
* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 27,099 / 41,250 ( 66 % ) ;
; Total memory bits ; 406,016 / 3,423,744 ( 12 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.372 ns ;
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 4.052 ns ;
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.066 ns ;

== Revision 4.0.c ==
* '''Filename:''' rc_v0400000c_15aug2008.sof
* '''Features:'''
** Only has data modes 0, 1, 4, and 10.
** Fixed the bug that exists in 4.0.b, 4.0.a, and 4.0.9 that prevented the fb_const value from being applied to channel zero (wbs_fb_data.vhd).
* '''Details:'''
** Changed a counter in the dispatch block to ease timing constraints in synthesis (dispatch_wishbone.vhd)
** Updated the tagged versions of dispatch.vhd , dispatch_cmd_receive.vhd, and dispatch_reply_transmit.vhd to the version that is used by all the other cards.
** '''Removed''' the fpga_termo (command: '''fpga_temp''') and id_thermo (commands: '''card_temp, card_id''') to ease timing constraints in synthesis (readout_card.vhd)
** Updated the tagged version of fpga_termo.vhd to include the new 'stale bit' feature
** Updated the tagged version of frame_timing_core.vhd to include the new 'err_o' interface
* '''Bugs:'''
** None reported yet
* '''Synthesis Notes:'''
** The quartus.ini file was not present in the synth directory during synthesis.
* '''FPGA Resource Usage:'''
Total logic elements : 25,058 / 41,250 ( 61 % )
Total memory bits : 400,896 / 3,423,744 ( 12 % )

* '''Timing Analysis''' (readout_card.tan.rpt):
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.282 ns ;
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.736 ns ;
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.665 ns ;

== Revision 4.0.b (buggy) ==
Note: This revision is on a watch list, after the bug detected 15 July 2008. See the bug section for more details.
* '''Filename''' : rc_v0400000b_04aug2008.sof
* '''Features'''
** data_mode 10 is added to provide more filtfb bits (compared to data mode 9) for planet observations. filtered_dat(27 downto 3) & flux_cnt_dat(6 downto 0)

* '''Bugs'''
** An unexplained bug that appeared in 4.0.a and may still be present in 4.0.b is a problem with the readout of channels being clipped out of data reporting. [[Bug 1 Notes]]

* ''' Synthesis note '''
** Quartus.ini removed.

== Revision 4.0.a (buggy) ==
Note: This revision is on a watch list, after the bug detected 15 July 2008. See the bug section for more details.
* '''Filename''' : rc_v0400000a_07jul2008.sof
* '''Bug Fix'''
** mce_status and adc_offset/flx_quanta commands do not fail after power up.
* ''' Synthesis note '''
** Quartus.ini removed.

* '''Bugs'''
** Seems to clip out channel 0 from data reporting.

== Revision 4.0.9 (buggy) ==
* '''Filename''' : rc_v04000009_26jun2008.sof
* '''Features'''
** sa_bias and offset DACs only refreshed when new values are written. (in previous versions, DACs were refreshed every frame)
* '''Bugs'''
** fb_const0 commands to channel 0 do not work. The value is stored in the register, but not applied to the DAC. Thus, read-back returns the correct value, but the DAC does not.
** reading flx_quanta and adc_offset right after power up hangs the reply datapath to CC. resetmce clears this error as temporary solution. the problem is caused by first read ack of the wishbone slave.

== Revision 4.0.8 ==
* '''Filename''' : rc_v04000008_26jun2008.sof
* '''Features'''
** The gaini, gainp, gaind resolution increased to 12-bit, i.e. -2048 to 2047 (formerly 10-bit).

* '''Bug fix'''
** the bug associated with gainpid read before mce_reset is fixed.

* ''' Synthesis note '''
** Quartus.ini removed.

== Revision 4.3.7 ==
* '''Filename''' : rc_v04030007_26may2008_raw.sof
* '''Features'''
** 14-bit raw mode enabled to buffer a snapshot of 50MHz samples for 2 frames of row_len * num_rows samples.
** In order to extend the raw-mode to 14-bit, an assumption is made that the raw buffer is not written to while being read. Therefore, make sure there is at least 2*row_len*num_rows*20ns between issuing captr_raw command and reading back the raw data.
** In order to save RAM for raw mode, two memory-intensive features are disabled:
*** low-pass filter disabled ( mixed filtfb data modes 6, 7, 9 are also disabled)
*** PID (gainp0, gaini0, gaind0) readback disabled. one can still set PID values and run servo, but can not read back the values.

== Revision 4.2.7 ==
* '''Filename''' : rc_v04020007_24may2008_raw.sof
* '''Features'''
** raw mode enabled to buffer a snapshot of 50MHz samples for 2 frames of row_len * num_rows samples.
** In order to save RAM for raw mode, two memory-intensive features are disabled:
*** low-pass filter disabled ( mixed filtfb data modes 6, 7, 9 are also disabled)
*** PID (gainp0, gaini0, gaind0) readback disabled. one can still set PID values and run servo, but can not read back the values.
* '''Bug fix'''
** the bug associated with reading from raw-buffer is fixed.

== Revision 4.1.7 ==
* '''Filename''' : rc_v04010007_25apr2008_raw.sof
* '''Features'''
** raw mode enabled to buffer a snapshot of 50MHz samples for 2 frames of row_len * num_rows samples.
** In order to save RAM for raw mode, two memory-intensive features are disabled:
*** low-pass filter disabled ( mixed filtfb data modes 6, 7, 9 are also disabled)
*** PID (gainp0, gaini0, gaind0) readback disabled. one can still set PID values and run servo, but can not read back the values.
* '''Bugs'''
** after each readout frame, raw-buffer readout counter falls behind by 3 and this causes skipping 3 50MHz samples in the data stream and column-data being messed up in subsequent frames. Data can be rearranged by post processing.

== Revision 4.0.6 (buggy) ==
* '''Filename''' : rc_v04000006_15feb2008.sof or .pof
* '''Features'''
** '''bugfix''': unreliable reset due to unsafe and incomplete state machines is fixed.
** '''bugfix''': flux_jump sign problem fixed, so far proved in const_mode, to be tested in servo_mode with cold setup.
** servo_mode=2 or ramp previously only went from 0 to ramp_amp, but now goes from -8192 to -8192+ramp_amp
** new commands are added: ''scratch'' and ''card_type''. Scratch takes 8 values and can be used by software to detect reset.
** slot_id and fw_rev are now integrated as part of all_cards.vhd
** lvds_tx_b=0, This will allow Clock Card to use the secondary backplane lvds line and check whether RC is plugged in.
** filter_coeff in misc_banks_admin commented as it is not implemented and causes timing problems.

* '''Bugs'''
** reading gainp/gaini/gaind right after power up hangs the reply datapath to CC. resetmce clears this error as temporary solution. the problem is caused by first read ack of pid_ram_admin.
** slot_id is only set after a resetmce is issued. (using the latest all_cards in the next revision will fix this)
** has spurious spikes on channel 7 data, which max out the integral, and cause the detectors to come unlocked. This firmware officially meets timing requirements, but the bug could be due to marginal timing on the longest data paths, i.e. ~0.1 ns in some cases.

== Revision 4.0.5 ==
* '''Filename''' : rc_v04000005_01nov2007.sof or .pof
* '''Features'''
** data mode 9 (mixed filt + flux jump) with windowing readjusted compared to data mode 8

* '''Bugs'''
** unreliable resetmce. Sometimes, firmware waked up non-responsive on lvds lines.
** In data mode 5 and 9, flux-jump counter is not reported properly due to a sign error. However, flux jumping works fine.

== Revision 3.0.19 ==
* '''Filename''' : rc_v03000019_16feb2007_raw.sof (no pof as one is not likely to run with this as regular firmware)
* '''Features'''
** data mode 3 is enabled.
** filter is disabled as a compromise to fit the raw-mode buffer.

* '''Bugs'''
** unreliable resetmce. Sometimes, firmware waked up non-responsive on lvds lines.

== Old Firmware Revisions ==
* '''4.0.4''': rc_v04000004_11oct2007.sof data mode 8 added (mixed filt + flux jump)
* '''4.0.3''': rc_v04000003_19sep2007.sof data mode 7 bit split readjusted to 10b error being bit 4 to 14
* '''4.0.2''': rc_v04000002_11sep2007.sof pid resolution increased to 10b, data mode 7 added
* '''4.0.1''': rc_v04000001_06sep2007.sof
* '''4.0.0''': rc_v04000000_29aug2007.sof supports readout_row_index * [[ bugs ]]

= To-Do List =
* the starting point for the servo is currently zero and it would be nice to have it programmable.

= RC Synthesis Notes =
# The following note applies when using Quartus versions earlier than Q7: Quartus.ini file had to exist in synth directory up to revision 4.0.a due to a bug that started in Quartus 6.1 and would synthesize away arbitrary parts of readout card. We contacted Altera at the time and they provided us the ini file.
# Timing: There is no "lock region" defined for readout card. Timing on readout card is tight and since version 3 or so any new feature would initially fail timing till some synthesis options were tweaked. One path that remains to be consistently marginal is from addr_gen counter (i.e. tga_o counter) in dispatch_wishbone.vhd to wishbone slaves particularly misc_banks_admin.vhd. Modules that are rewritten to address timing concerns are fsfb_corr, all_cards, misc_banks_admin, and finally instantiating an lpm counter instead of a counter from components library. Surprisingly, the lpm counter reduced 87 failures to 37, although looking at the technology map viewer, it seemed that they were both synthesized the same.
# Compile time: This was at some point 4.5 hours, after going to dual core PC, this was reduced to 35 minutes. After extending pid gains to 12b and fixing offset/sa_bias update code, the compile time increased to 1.5hr again with utilization up to ~70%.
# wbs_fb_storage, ram_8x64, pid_ram had to be regenerated using latest (Q7.2) MegaWizard to get rid of the bug associated with failure to read after power up until a reset was issued.
# During simulations, the initialization of RAM block with .hex files needs to be disabled. This is done by commenting out the following lines from the MegaWizard generated Megafunction files (remember to un-comment them before synthesizing the code):
lpm_file => "C:/scuba2_repository/cards/readout_card/fsfb_calc/source/rtl/ram_40x64.hex", and
lpm_file : STRING;
#Starting Q10.0 use TimeQuest timing analyzer as oppose to the classic one. The classic one is being phased out by Altera. In order to use TimeQuest, you need to have an sdc file present in your project directory.
----
[http://e-mode.phas.ubc.ca/mcewiki/index.php/Main_Page MCE Main Page]

Readout Card firmware

2011-05-04T21:43:36Z

Bburger: /* Revision 5.0.f */

* Synthesis Reminders (for firmware developers)
** quartus.ini is not needed anymore (Fixed as of Q7, Altera SR10783580 2010-10-24)
** Remember that readout_card/fsfb_clac/source/rtl/ram_40x64.vhd must be initialized with the ram_40x64.hex file in the same directory.
== Revision 5.1.2 ==
* '''Filename:'''
** rc_stratix3_v05010002_18jan2011.sof (for Rev. E cards)
** rc_stratix3_v05010002_18jan2011.jic (for Rev. E cards)
** rc_v05010002_03feb2011.sof (for Rev. B cards)
** rc_v05010002_03feb2011.pof (for Rev. B cards)

* '''Features:'''
** based on 5.1.1 with k1 and k2 (filter params) limited to k1<16 and k2<32 in order to resolve the timing when compiling for smaller Stratix FPGA on RC Rev. B.

* '''Bug fix:'''
** the 2-rows-off filtered data readout introduced with configurable filter in rev. 5.1.0 and 5.1.1 is fixed now.

* '''Bugs:'''
** none so far.

* '''FPGA Resource Usage''' (readout_card.fit.rpt)
; Total logic elements ; 33,285 / 41,250 ( 81 % ) ;
; Total pins ; 358 / 616 ( 58 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt)
; Fast Model Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 6.591 ns
; Fast Model Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 7.206 ns
; Fast Model Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 18.299 ns

== Revision 5.1.1 (not recommended) ==
* '''Filename:'''
** rc_v05010001_01dec2010.sof (for Rev. B cards)

* '''Features:'''
** based on 5.1.0, but k1 and k2 (filter params) are now limited to k1<16 and k2<32 in order to resolve the timing failures of compiling 5.1.0 for smaller Stratix FPGA on RC Rev. B.

* '''Bugs:'''
** filter mode data is off by 2 rows.

== Revision 5.1.0 (not recommended) ==
* '''Filename:'''
** rc_stratix3_v05010000_01nov2010.sof (for Rev. E cards)
** rc_v05010000_01nov2010.sof (for Rev. B cards) has timing failures '''do not use!!!'''

* '''Features:'''
** added configurable filter parameters specified by ''fltr_coeff'', default is the fcutoff/fsampl=122Hz/15kHz. see [[ Digital 4-pole Butterworth Low-pass filter ]].
** ''fltr_type'' is set to 255 to indicate configurable filter parameters.
** see [http://www.phas.ubc.ca/~mce/mcedocs/software/SC2_ELE_S580_515_mce_command_description.pdf MCE command description]
** development notes:
*** It is built on Quartus10.1.
*** tcl files had to be updated as cmp syntax is not supported in Q10 anymore.
*** Rev. E cards now can be identified by reading back pcb_rev as part of card_type, therefore both stratix I and III sof/pof/jic are generated from the same source.

* '''Bugs:'''
** rc_v05010000_01nov2010.sof has timing failures that were overlooked, do not use this firmware for Rev.B cards.
** '''filter mode data is off by 2 rows.'''

* '''FPGA Resource Usage and Timing Report''' (readout_card.fit.rpt and readout_card.tan.rpt): logic usage is upto 85% from 66% in 5.0.d/e/f

= Revision 5.0.f =
* '''Filename:'''
** rc_v0500000f_22oct2010.sof (for Rev. B cards)
** rc_stratix3_v0500000f_22oct2010.sof (for Rev. E cards)

* '''Features:'''
** Bugfix: integral clamp should work now. only positive integral_clamp values are valid!

* '''Details:''':
** SQ1FB is applied 18 clock cycles after start of a row visit (SQ1_Bias being applied) regardless of flux-jump being enabled or not. In pre-5.0.b firmware SQ1FB was being applied after 7 clock cycles when flux-jump was disabled and after 18 clock cycles when flux-jump was enabled.
** available for both Rev. E and Rev. B cards, the upper byte of card_type parameter now reports the pcb revision.
** development note: It is built on Quartus10.1.

* '''Bugs:'''
**none yet!

* '''FPGA Resource Usage and Timing Report''' (readout_card.fit.rpt and readout_card.tan.rpt): no change compared to 5.0.a/b/c/d

== Revision 5.0.e (not recommended) ==
* '''Filename:'''
** rc_v0500000e_06oct2010.sof

* '''Details:'''
** an unsuccessful attempt to fix integral_clamp, but changed the functionality so that it clamps at the value, but it doesn't hold the clamp. i.e., if the calculated sq1fb becomes less than the specified clamp value, the sq1fb is not clamped anymore. This is not a desired functionality!

= Revision 5.0.d =
* '''Filename:'''
** rc_v0500000d_04aug2010.sof

* '''Features:'''
** Bugfix: To fix the bug associated with negative flux-jumps, reverted to signed multiplier and hence, incremented the width of the flux-quanta multiplier input by 1.

* '''Details:''': SQ1FB is applied 18 clock cycles after start of a row visit (SQ1_Bias being applied) regardless of flux-jump being enabled or not. In pre-5.0.b firmware SQ1FB was being applied after 7 clock cycles when flux-jump was disabled and after 18 clock cycles when flux-jump was enabled.

* '''Bugs:'''
** '''integral_clamping is broken'''. To test the clamping, a servo-locked ramp was initiated on the sq1fb and then flux-jumping was turned on and observed by attaching a scope to the SQ1FB output. With integral_clamp=80000000, flux_quanta=8000, gaini=1, flux-jump enabled, we see [[http://e-mode.phas.ubc.ca/mcewiki/index.php/Image:Clamp_unstable.png scope snapshot]] used slow_fb_ramp.py script for testing.

* '''FPGA Resource Usage and Timing Report''' (readout_card.fit.rpt and readout_card.tan.rpt): no change compared to 5.0.a/b/c

== Revision 5.0.c (not recommended) ==
* '''Filename:'''
** rc_v0500000c_16jun2010.sof

* '''Features:'''
** Based on rev. 5.0.b
** Re-introduced flux-jump counter clamping to maintain continuity in behavior from past versions of firmware in the field.
** '''Important''': SQ1FB is applied 18 clock cycles after start of a row visit (SQ1_Bias being applied) regardless of flux-jump being enabled or not. In pre-5.0.b firmware SQ1FB was being applied after 7 clock cycles when flux-jump was disabled and after 18 clock cycles when flux-jump was enabled.

* '''Details:'''
* '''Bugs:'''
** '''flux-jump is broken'''. flux-jumping block misbehaves at the first jump in the negative range.

* '''FPGA Resource Usage''' (readout_card.fit.rpt): [[rc_5.0.c_fit_rpt]]
; Total logic elements ; 26,800 / 41,250 ( 65 % ) ;
; Total pins ; 358 / 616 ( 58 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;
; DSP block 9-bit elements ; 76 / 112 ( 68 % ) ;
; Total PLLs ; 1 / 6 ( 17 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt): [[rc_5.0.c_tan_rpt]]
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.964 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 4.382 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 15.924 ns ;

== Revision 5.0.b (not recommended) ==
* '''Filename:'''
** rc_v0500000b_03jun2010.sof

* '''Features:'''
** Based on rev. 5.0.a
** A bug that caused jumps in first-stage feedback, and detected as spikes in the raw data of pixels that were in servo_mode=0,1,2 was fixed. The jumps in FSFB were due to flux-jumping being enabled on live pixes with non-zero flx_quanta, and being disabled on the fly on dead pixels with flx_quanta=0. Flux-jumping is now disabled on a column-by-column basis if a column is in servo_mode = 0,1,2.
** Ineffective clamping was removed from the flux-jumping block (as per 5.0.9), as it is now replaced by the clamping that was perfected in rev. 5.0.10
** A sticky bit that only affected servo_mode=0,1,2 was also removed from the flux-jumping block.
** flx_lp_init commands now also clear the flux-jumping block as well.
** The 11-clock-cycle delay (in applying SQ1_FB) that in previous firmware only occurred when flux-jumping was enabled, now (in this version) is in effect all the time. Due to the bug-fix above, flux-jumping can be disabled on a column-by-column basis by setting servo_mode=0,1,2 when en_fb_jump=1. Before the change, this meant that constant values could be applied with or without the 11-cycle delay if en_fb_jump=1 or 0. To make the delay consistent, it is now always 11 cycles. As background, the flux-jumping block is pipelined, meaning that it does calculations for all 8 channels serially. The serialization is because of DSP-block limitations in the Readout Card FPGA that prevent us from doing all 8 channels in parallel. The reason that it takes 11 cycles to complete the flux-jumping calculations is because the values are computed for the eight channels in three ALU stages: 8 + 3 = 11 cycles. Adding 11 cycles to the 7 cycles of latency from other stages in the system results in: 11 + 7 = 18 cycles of latency from the start of a row dwell period before the first-stage feedback is applied. In rc_v5.0.c, I enforce the 18-cycle delay even when flux-jumping is not enabled to maintain uniformity across all eight channels, because flux-jumping is enabled/disabled on a per-channel basis. In other words, if I hadn't enforced the 18-cycle delay, some channels could have their feedback applied after 7 cycles, while others could have it applied after 18 cycles. I wasn't a fan of this non-uniformity. I realize that 18 cycles is a long time. In fact, so is 7. In the last few months, we have been discussing how to reduce these times to 1 cycle, because every experiment out there wants to multiplex as fast as possible, and the 7/18-delay is a rate limiting step.
** The flux-jumping code was re-arranged in the flux-jumping block to reflect the flow of data through the pipeline and make it easier to understand.

* '''Details:'''

* '''Bugs:'''
** flux-jump does not work when jumping to negative values.

* '''FPGA Resource Usage''' (readout_card.fit.rpt): [[rc_5.0.b_fit_rpt]]
; Total logic elements ; 26,745 / 41,250 ( 65 % ) ;
; Total pins ; 358 / 616 ( 58 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;
; DSP block 9-bit elements ; 76 / 112 ( 68 % ) ;
; Total PLLs ; 1 / 6 ( 17 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;
* '''FPGA Timing Analysis''' (readout_card.tan.rpt): [[rc_5.0.b_tan_rpt]]
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.459 ns
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.895 ns
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 15.956 ns

= Revision 5.0.a =
* '''Filename:'''
** rc_v0500000a_12mar2010.sof

* '''Features:'''
** Based on the merger of rev. 5.0.8 and 5.0.9.
** '''integral_clamp''' command is added where a clamp value is set for the integral term and once the integral term hits that value, the integral-term is clamped to that value and p-term and d-term are clamped to zero. When integral_term=0 then no clamping is in effect, similar to previous releases of firmware.
** The low pass filter has 20-bit input and f_3dB/f_samp = 122Hz/15kHz .
** The flux-jump clamping that was removed in 5.0.9 is included once again here, as we decided this is safer for now.

* '''Details:'''
** "lock_dat_left" parameter that was removed in 5.0.9 is now implemented as "lock_dat_lsb"

* '''Bugs:'''
** flx_lp_init does not reinitialize the flux-jump block

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis
** tag name: rc_v0500000a_12mar2009! years were mixed up!

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
* '''FPGA Timing Analysis''' (readout_card.tan.rpt):

== Revision 5.0.9 (buggy) ==
* '''Filename:'''
** rc_v05000009_13nov2009.sof

* '''Features:'''
** Based on rev. 5.0.4
** Removes a sticky bit in pid calculation result storage -- in fsfb_processor.
** Adds a command to clamp the growth of the I-term to prevent wrapping and track down the source of Caltech's FSFB jumps.
** Removed the unused lock_dat_left parameter. The ability to shift left was moved to the fsfb_corr block some time ago.
** Fixed a sign extension bug acting on the flux quanta, which limited the value to 8191. Changed the extension from signed to unsigned.
** Removed ineffective clamping in the flux-jump calculation block.
** IMPORTANT: Must be used in conjunction with firmware rev. 5.0.0+ of all other cards.

* '''Details:'''

* '''Bugs:'''
** integral_clamp read/write command does not work.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 27,960 / 41,250 ( 68 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.825 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.878 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 14.397 ns ;

== Revision 5.0.8 (UBC only) ==
* '''Filename:'''
** rc_v05000008_09oct2009.sof

* '''Features:'''
** Based on rev. 5.0.4
** type 1 low-pass filter: f3dB=122Hz for fsample=15kHz
** Filter-input-width changed from 18b to 20b with no sticky bits!
** removed sticky bits in internal arithmetic of the filter.

= Revision 5.0.7 (type-2 filter) =
* '''Filename:'''
** rc_v05000007_09oct2009.sof

* '''Features:'''
** Based on rev. 5.0.4
** type-2 low-pass-filter: f3dB=75Hz for fsample=30000.
** Filter-input-width changed from 18b to 20b with no sticky bits!
** inter-biquad-gain-scaling for the filter is 2^14
** filter results are scaled down by 2^3 in the output of the filter.
** removed sticky bits in internal arithmetics
** _correction_ disabled in fsfb_proc_pidz

* '''Details:'''
** quartus.ini file was '''not''' present in synth directory.

* '''Bugs:'''
** none to report

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
== Revision 5.0.6 (UBC only) ==
* '''Filename:'''
** rc_stratix3_v05000006_15sep2009.sof

* '''Features:'''
** Only Valid for Rev. C/D Cards
** Based on rev. 5.0.3
** tcl file updated for Rev. D and aligned with top-level and qsf (project file).
** flux loop commented, just to try sampling the ADC.
** compiled with Q9.1

== Revision 5.0.5 (UBC only) ==
* '''Filename:'''
** rc_v05000005_04sep2009.sof

* '''Features:'''
** Based on rev. 5.0.2
** changed the low-pass-filter to f(3db)=75Hz for f(sample)=30000.

* '''Details:'''
** quartus.ini file was '''not''' present in synth directory.

* '''Bugs:'''
** negative inputs to the filter cause filter to have a non-flat pass-band region. may have to do with sign-handling...

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
* '''FPGA Timing Analysis''' (readout_card.tan.rpt):

= Revision 5.0.4 =
* '''Filename:'''
** rc_v05000004_28aug2009.sof

* '''Features:'''
** Based on rev. 5.0.2
** BUG Fix: handles 14-bit flux quanta (changed the multiplier to unsigned)
** BUG Fix: changed standard logic vector extension from signed to unsigned in flux-jumping slave.
** IMPORTANT: Must be used in conjunction with firmware rev. 5.0.0+ of all other cards.

* '''Details:'''

* '''Bugs:'''
** None so far.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,170 / 41,250 ( 63 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.541 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.612 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 15.398 ns ;

= Revision 5.0.3 =
* '''Filename:'''
** rc_stratix3_v05000003_21aug2009.sof

* '''Features:'''
** ONLY valid REV C/D RC Cards
** Based on rev. 5.0.2
** flux loop commented, just to try sampling the ADC.
** updated tcl file, but still need to rely on project file as well as qsf file.
** changed default level of adc_sclk to '1'
** dac_clr_n was changed from an output to an input.
** added 'locked' interface to rc_pll_stratix_iii
** renamed the adc_pll clock signals to more explanitory names
** added the FPGA_DEVICE_FAMILY generic to the dispatch interace for synthesis of the dc_fifo in lvds_rx
** uncommented DDR interface to force the syntesizer to use correct left and right PLLs (in conjunction with ADC and DDR PLLs)
** added test signals to test_status to see clocks on the scope.
== Revision 5.0.2 (buggy) ==
* '''Filename:'''
** rc_v05000002_test00_tagged.sof

* '''Features:'''
** Based on rev. 5.0.1
** Fixed a bug in wbs_frame_data that stored data incorrectly if reporting 1 or 2 pixels only.
** IMPORTANT: Must be used in conjunction with firmware rev. 5.0.0+ of all other cards.

* '''Details:'''

* '''Bugs:'''
** None so far.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,186 / 41,250 ( 63 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.755 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.979 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.067 ns ;

== Revision 5.0.1 (buggy) (Filter + Raw + Rectangle, 2 LVDS) ==
* '''Filename:'''
** rc_v05000001_26may2009.sof

* '''Features:'''
** Combines features in rev. 5.0.0 (2 LVDS Lines) and rev. 4.0.e (Filtered + Raw), with the NEW rectangle mode.
** IMPORTANT: Must be used in conjunction with firmware rev. 5.0.0+ of all other cards.

* '''Details:'''
** [[CVS Diff Between sys_v05000000 and rc_v05000001]]

* '''Bugs:'''
** Has a bug in wbs_frame_data that stored data incorrectly if reporting 1 or 2 pixels only.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,565 / 41,250 ( 64 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.656 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.861 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 14.167 ns ;

== Revision 5.0.0 (Filter Only, 2 LVDS) ==
* '''Filename:'''
** rc_v05000000_22dec2008.sof (tagged as sys_v05000000_22dec2008)

* '''Features:'''
** IMPORTANT: Must be used in conjunction with firmware v05000000+ of all other cards!!!
** Adds the ability to read out one column of data continuously from readout cards
** Adds data mode 11, which is an engineering mode. Data points are 32-bits, and bits [9..3]=row_index, [2..0]=column_index. This mode is useful for determining which pixels one is reading out in the array, in column mode for example.

* '''Details:'''
** [[CVS Diff Between rc_v0400000c and sys_v05000000]]

* '''Bugs:'''
** None so far.

* '''Synthesis Notes:'''
** The quartus.ini file was not present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,607 / 41,250 ( 65 % ) ;
; Total memory bits ; 406,016 / 3,423,744 ( 12 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.558 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.892 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.987 ns ;

== Revision 4.0.f (Filter + Raw, 1 LVDS) ==
* '''Filename:'''
** rc_v0400000f_12feb2010.sof

* '''Features:'''
** Based on 4.0.e and in parallel with 5.0.9 (equivalent version, clamping is not included)
** Incorporates fixes that were done to flux-jumping between 5.0.2 - 5.0.4 - 5.0.9. Namely:
*** Changes a multiplier from signed to unsigned (in fsfb_corr_multplier.vhd).
*** Changes sign extension from signed to unsigned (in flux_quanta_ram_admin.vhd).

* '''Details:'''

* '''Bugs:'''
** None reported yet.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,773 / 41,250 ( 65 % ) ;
; Total memory bits ; 1,321,984 / 3,423,744 ( 39 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.539 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 4.118 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 17.318 ns ;

== Revision 4.0.e (Filter + Raw, 1 LVDS) ==
* '''Filename:'''
** rc_v0400000e_27apr2009.sof

* '''Features:'''
** Based on 4.0.d
** Combines both raw- and filtered-data modes.
** fpga_temp, card_temp, card_id commands are disabled.
** Tested by Matt Hasselfield.

* '''Details:'''

* '''Bugs:'''
** fpga_temp, card_temp, card_id commands are disabled.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 27,048 / 41,250 ( 66 % ) ;
; Total memory bits ; 1,321,984 / 3,423,744 ( 39 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.675 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.907 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.728 ns ;

== Revision 4.0.d (Raw Only, 1 LVDS) ==
* '''Filename:''' rc_v0400000d_20090417.sof

* '''Features:'''
** Based on v4.0.c, but has the filter removed, and implements a single 65536-index RAM block for storing 50 MHz raw-data samples.
** The firmware takes a new command called readout_col_index which specifies which column to capture raw data from.
** Other than readout_col_index, the firmware functions the same as previous raw-data firmware, including then need to issue a capture_raw command.
** For more information on raw-data, see: http://e-mode.phas.ubc.ca/mcewiki/index.php/Raw-mode_readout
** This firmware also integrates some of the improvements that were implemented in 4.4.0, like the removal of the tga_o signal from an FSM in dispatch_wishbone.vhd.

* '''Details:'''
** Differences between 4.0.c and 4.0.d
U system/test/source/tb/tb_cc_rcs_bcs_ac.vhd
U all_cards/dispatch/source/rtl/dispatch_wishbone.vhd
U library/sys_param/source/rtl/wishbone_pack.vhd
U readout_card/adc_sample_coadd/source/rtl/adc_sample_coadd.vhd
U readout_card/adc_sample_coadd/source/rtl/adc_sample_coadd_pack.vhd
U readout_card/flux_loop/source/rtl/flux_loop.vhd
U readout_card/flux_loop/source/rtl/flux_loop_pack.vhd
U readout_card/flux_loop_ctrl/source/rtl/flux_loop_ctrl.vhd
U readout_card/flux_loop_ctrl/source/rtl/flux_loop_ctrl_pack.vhd
U readout_card/flux_loop_ctrl/source/tb/tb1_flux_loop_ctrl.vhd
U readout_card/flux_loop_ctrl/source/tb/tb2_flux_loop_ctrl.vhd
U readout_card/fsfb_calc/source/rtl/fsfb_fltr_regs.vhd
U readout_card/fsfb_corr/source/rtl/fsfb_corr.vhd
U readout_card/readout_card/source/rtl/readout_card.vhd
U readout_card/readout_card/source/rtl/readout_card_pack.vhd
U readout_card/wbs_frame_data/source/rtl/wbs_frame_data.vhd
U readout_card/wbs_frame_data/source/rtl/wbs_frame_data_pack.vhd

* '''Bugs:'''
** None so far.
** fpga_temp, card_temp, card_id commands are not supported.

* '''Synthesis Notes:'''
** The quartus.ini file was present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 24,554 / 41,250 ( 60 % ) ;
; Total memory bits ; 1,262,592 / 3,423,744 ( 37 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.991 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.864 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 17.052 ns ;

== Revision 4.4.1 ==
* '''Filename:''' rc_v04040001_21nov2008

* '''Features:'''
** Fixes a bug that froze up the firmware if any of the following commands were issued: CARD_ID_ADDR, CARD_TEMP_ADDR, FPGA_TEMP_ADDR in 4.4.0 only.

* '''Details:'''
** The bug fix include adding more logic to the wishbone ack path (readout_card.vhd), which subsequently decreased the minimum clock setup time to 1.588ns. The new logic will catch errors that the old logic wouldn't have, and is now consistent with the firmware on all the other cards. However, if timing becomes an issue, the logic may have to revert back to that which was in version 4.0.c.

* '''Bugs:'''
** None so far.

* '''Synthesis Notes:'''
** The quartus.ini file was not present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 27,241 / 41,250 ( 66 % ) ;
; Total memory bits ; 405,504 / 3,423,744 ( 12 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.588 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.585 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 17.057 ns ;

== Revision 4.4.0 (buggy) ==
* '''Filename:''' rc_v04040000_02oct2008
* '''Features:'''
** Reinstated the data modes in wbs_frame_data.vhd that were removed in 4.0.c. This firmware has the following modes: '''0, 1, 2, 4, 5, 7, 10'''. The modes that are not present are: '''3''' (raw data), '''6''' (replaced by data_mode = 7), '''8''' (replaced by data_mode = 10), '''9''' (replaced by data_mode = 10). For more information on data modes, see [[Data mode]].
** Re-integrated the id_thermo and fpga_thermo block in the readout_card.vhd top level that was removed in 4.0.c.
** Removed the sticky bit in fsfb_corr.vhd, which was enabled when flux-jumping was turned on. Because the feedback is signed, the sticky bit would usually reflect the value of the 14th bit, except in situations when the number of flux quanta to jump was greater than 1 (i.e. cosmic rays, IV-curves, etc). Flux jumps are made at a maximum rate of one per frame period, so that if the First-Stage Feedback increased past the 13th bit, it would not be reflected in the feedback applied. Now it is.
* '''Details:'''
** Simplified the FSM logic in wbs_frame_data.vhd that determines when to transition from IDLE to WSS1. This was done to lower the number of gates in that path, and ease the timing.
** Removed the z_dat_i port in fsfb_processor.vhd and fsfb_calc_pack.vhd to the fsfb_proc_pidz block, in an effort to make it clearer within that block that the z-term is always = 0.
** Removed the z-term sign extension in fsfb_proc_pidz.vhd, and the [d-term + z-term] adder to free up DSP resources since the z-term is always = 0.
** Adjusted the indentation in fsfb_io_controller.vhd to make the file more readable.
** Moved the tga_o signal out of the dispatch_wishbone.vhd FSM, and made it a continuous assignment. This signal had one of the highest fan-out counts in the RTL design, and actually was impossible to route in Stratix III chips in its previous configuration because of the number of gates on the fan-out. As a consequence of making it a continuous assignment, the Stratix III fitter was able to succeed, and the Stratix I timing characteristics were greatly improved. This is the most significant change in this revision. This change single-handedly increased the minimum slack from 1.282 ns in v0400000c to 2.372 ns (or 56.7 MHz max) in this revision.
* '''Bugs:'''
** The following commands lock up the Readout Card firmware: CARD_ID_ADDR, CARD_TEMP_ADDR, FPGA_TEMP_ADDR.
** fb_const0 commands to channel 0 do not work. The value is stored in the register, but not applied to the DAC. Thus, read-back returns the correct value, but the DAC does not
* '''Synthesis Notes:'''
** The quartus.ini file was not present in the synth directory during synthesis.
* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 27,099 / 41,250 ( 66 % ) ;
; Total memory bits ; 406,016 / 3,423,744 ( 12 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.372 ns ;
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 4.052 ns ;
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.066 ns ;

== Revision 4.0.c ==
* '''Filename:''' rc_v0400000c_15aug2008.sof
* '''Features:'''
** Only has data modes 0, 1, 4, and 10.
** Fixed the bug that exists in 4.0.b, 4.0.a, and 4.0.9 that prevented the fb_const value from being applied to channel zero (wbs_fb_data.vhd).
* '''Details:'''
** Changed a counter in the dispatch block to ease timing constraints in synthesis (dispatch_wishbone.vhd)
** Updated the tagged versions of dispatch.vhd , dispatch_cmd_receive.vhd, and dispatch_reply_transmit.vhd to the version that is used by all the other cards.
** '''Removed''' the fpga_termo (command: '''fpga_temp''') and id_thermo (commands: '''card_temp, card_id''') to ease timing constraints in synthesis (readout_card.vhd)
** Updated the tagged version of fpga_termo.vhd to include the new 'stale bit' feature
** Updated the tagged version of frame_timing_core.vhd to include the new 'err_o' interface
* '''Bugs:'''
** None reported yet
* '''Synthesis Notes:'''
** The quartus.ini file was not present in the synth directory during synthesis.
* '''FPGA Resource Usage:'''
Total logic elements : 25,058 / 41,250 ( 61 % )
Total memory bits : 400,896 / 3,423,744 ( 12 % )

* '''Timing Analysis''' (readout_card.tan.rpt):
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.282 ns ;
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.736 ns ;
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.665 ns ;

== Revision 4.0.b (buggy) ==
Note: This revision is on a watch list, after the bug detected 15 July 2008. See the bug section for more details.
* '''Filename''' : rc_v0400000b_04aug2008.sof
* '''Features'''
** data_mode 10 is added to provide more filtfb bits (compared to data mode 9) for planet observations. filtered_dat(27 downto 3) & flux_cnt_dat(6 downto 0)

* '''Bugs'''
** An unexplained bug that appeared in 4.0.a and may still be present in 4.0.b is a problem with the readout of channels being clipped out of data reporting. [[Bug 1 Notes]]

* ''' Synthesis note '''
** Quartus.ini removed.

== Revision 4.0.a (buggy) ==
Note: This revision is on a watch list, after the bug detected 15 July 2008. See the bug section for more details.
* '''Filename''' : rc_v0400000a_07jul2008.sof
* '''Bug Fix'''
** mce_status and adc_offset/flx_quanta commands do not fail after power up.
* ''' Synthesis note '''
** Quartus.ini removed.

* '''Bugs'''
** Seems to clip out channel 0 from data reporting.

== Revision 4.0.9 (buggy) ==
* '''Filename''' : rc_v04000009_26jun2008.sof
* '''Features'''
** sa_bias and offset DACs only refreshed when new values are written. (in previous versions, DACs were refreshed every frame)
* '''Bugs'''
** fb_const0 commands to channel 0 do not work. The value is stored in the register, but not applied to the DAC. Thus, read-back returns the correct value, but the DAC does not.
** reading flx_quanta and adc_offset right after power up hangs the reply datapath to CC. resetmce clears this error as temporary solution. the problem is caused by first read ack of the wishbone slave.

== Revision 4.0.8 ==
* '''Filename''' : rc_v04000008_26jun2008.sof
* '''Features'''
** The gaini, gainp, gaind resolution increased to 12-bit, i.e. -2048 to 2047 (formerly 10-bit).

* '''Bug fix'''
** the bug associated with gainpid read before mce_reset is fixed.

* ''' Synthesis note '''
** Quartus.ini removed.

== Revision 4.3.7 ==
* '''Filename''' : rc_v04030007_26may2008_raw.sof
* '''Features'''
** 14-bit raw mode enabled to buffer a snapshot of 50MHz samples for 2 frames of row_len * num_rows samples.
** In order to extend the raw-mode to 14-bit, an assumption is made that the raw buffer is not written to while being read. Therefore, make sure there is at least 2*row_len*num_rows*20ns between issuing captr_raw command and reading back the raw data.
** In order to save RAM for raw mode, two memory-intensive features are disabled:
*** low-pass filter disabled ( mixed filtfb data modes 6, 7, 9 are also disabled)
*** PID (gainp0, gaini0, gaind0) readback disabled. one can still set PID values and run servo, but can not read back the values.

== Revision 4.2.7 ==
* '''Filename''' : rc_v04020007_24may2008_raw.sof
* '''Features'''
** raw mode enabled to buffer a snapshot of 50MHz samples for 2 frames of row_len * num_rows samples.
** In order to save RAM for raw mode, two memory-intensive features are disabled:
*** low-pass filter disabled ( mixed filtfb data modes 6, 7, 9 are also disabled)
*** PID (gainp0, gaini0, gaind0) readback disabled. one can still set PID values and run servo, but can not read back the values.
* '''Bug fix'''
** the bug associated with reading from raw-buffer is fixed.

== Revision 4.1.7 ==
* '''Filename''' : rc_v04010007_25apr2008_raw.sof
* '''Features'''
** raw mode enabled to buffer a snapshot of 50MHz samples for 2 frames of row_len * num_rows samples.
** In order to save RAM for raw mode, two memory-intensive features are disabled:
*** low-pass filter disabled ( mixed filtfb data modes 6, 7, 9 are also disabled)
*** PID (gainp0, gaini0, gaind0) readback disabled. one can still set PID values and run servo, but can not read back the values.
* '''Bugs'''
** after each readout frame, raw-buffer readout counter falls behind by 3 and this causes skipping 3 50MHz samples in the data stream and column-data being messed up in subsequent frames. Data can be rearranged by post processing.

== Revision 4.0.6 (buggy) ==
* '''Filename''' : rc_v04000006_15feb2008.sof or .pof
* '''Features'''
** '''bugfix''': unreliable reset due to unsafe and incomplete state machines is fixed.
** '''bugfix''': flux_jump sign problem fixed, so far proved in const_mode, to be tested in servo_mode with cold setup.
** servo_mode=2 or ramp previously only went from 0 to ramp_amp, but now goes from -8192 to -8192+ramp_amp
** new commands are added: ''scratch'' and ''card_type''. Scratch takes 8 values and can be used by software to detect reset.
** slot_id and fw_rev are now integrated as part of all_cards.vhd
** lvds_tx_b=0, This will allow Clock Card to use the secondary backplane lvds line and check whether RC is plugged in.
** filter_coeff in misc_banks_admin commented as it is not implemented and causes timing problems.

* '''Bugs'''
** reading gainp/gaini/gaind right after power up hangs the reply datapath to CC. resetmce clears this error as temporary solution. the problem is caused by first read ack of pid_ram_admin.
** slot_id is only set after a resetmce is issued. (using the latest all_cards in the next revision will fix this)
** has spurious spikes on channel 7 data, which max out the integral, and cause the detectors to come unlocked. This firmware officially meets timing requirements, but the bug could be due to marginal timing on the longest data paths, i.e. ~0.1 ns in some cases.

== Revision 4.0.5 ==
* '''Filename''' : rc_v04000005_01nov2007.sof or .pof
* '''Features'''
** data mode 9 (mixed filt + flux jump) with windowing readjusted compared to data mode 8

* '''Bugs'''
** unreliable resetmce. Sometimes, firmware waked up non-responsive on lvds lines.
** In data mode 5 and 9, flux-jump counter is not reported properly due to a sign error. However, flux jumping works fine.

== Revision 3.0.19 ==
* '''Filename''' : rc_v03000019_16feb2007_raw.sof (no pof as one is not likely to run with this as regular firmware)
* '''Features'''
** data mode 3 is enabled.
** filter is disabled as a compromise to fit the raw-mode buffer.

* '''Bugs'''
** unreliable resetmce. Sometimes, firmware waked up non-responsive on lvds lines.

== Old Firmware Revisions ==
* '''4.0.4''': rc_v04000004_11oct2007.sof data mode 8 added (mixed filt + flux jump)
* '''4.0.3''': rc_v04000003_19sep2007.sof data mode 7 bit split readjusted to 10b error being bit 4 to 14
* '''4.0.2''': rc_v04000002_11sep2007.sof pid resolution increased to 10b, data mode 7 added
* '''4.0.1''': rc_v04000001_06sep2007.sof
* '''4.0.0''': rc_v04000000_29aug2007.sof supports readout_row_index * [[ bugs ]]

= To-Do List =
* the starting point for the servo is currently zero and it would be nice to have it programmable.

= RC Synthesis Notes =
# The following note applies when using Quartus versions earlier than Q7: Quartus.ini file had to exist in synth directory up to revision 4.0.a due to a bug that started in Quartus 6.1 and would synthesize away arbitrary parts of readout card. We contacted Altera at the time and they provided us the ini file.
# Timing: There is no "lock region" defined for readout card. Timing on readout card is tight and since version 3 or so any new feature would initially fail timing till some synthesis options were tweaked. One path that remains to be consistently marginal is from addr_gen counter (i.e. tga_o counter) in dispatch_wishbone.vhd to wishbone slaves particularly misc_banks_admin.vhd. Modules that are rewritten to address timing concerns are fsfb_corr, all_cards, misc_banks_admin, and finally instantiating an lpm counter instead of a counter from components library. Surprisingly, the lpm counter reduced 87 failures to 37, although looking at the technology map viewer, it seemed that they were both synthesized the same.
# Compile time: This was at some point 4.5 hours, after going to dual core PC, this was reduced to 35 minutes. After extending pid gains to 12b and fixing offset/sa_bias update code, the compile time increased to 1.5hr again with utilization up to ~70%.
# wbs_fb_storage, ram_8x64, pid_ram had to be regenerated using latest (Q7.2) MegaWizard to get rid of the bug associated with failure to read after power up until a reset was issued.
# During simulations, the initialization of RAM block with .hex files needs to be disabled. This is done by commenting out the following lines from the MegaWizard generated Megafunction files (remember to un-comment them before synthesizing the code):
lpm_file => "C:/scuba2_repository/cards/readout_card/fsfb_calc/source/rtl/ram_40x64.hex", and
lpm_file : STRING;
#Starting Q10.0 use TimeQuest timing analyzer as oppose to the classic one. The classic one is being phased out by Altera. In order to use TimeQuest, you need to have an sdc file present in your project directory.
----
[http://e-mode.phas.ubc.ca/mcewiki/index.php/Main_Page MCE Main Page]

Readout Card firmware

2011-05-04T21:36:42Z

Bburger: /* Revision 5.1.2 */

* Synthesis Reminders (for firmware developers)
** quartus.ini is not needed anymore (Fixed as of Q7, Altera SR10783580 2010-10-24)
** Remember that readout_card/fsfb_clac/source/rtl/ram_40x64.vhd must be initialized with the ram_40x64.hex file in the same directory.
== Revision 5.1.2 ==
* '''Filename:'''
** rc_stratix3_v05010002_18jan2011.sof (for Rev. E cards)
** rc_stratix3_v05010002_18jan2011.jic (for Rev. E cards)
** rc_v05010002_03feb2011.sof (for Rev. B cards)
** rc_v05010002_03feb2011.pof (for Rev. B cards)

* '''Features:'''
** based on 5.1.1 with k1 and k2 (filter params) limited to k1<16 and k2<32 in order to resolve the timing when compiling for smaller Stratix FPGA on RC Rev. B.

* '''Bug fix:'''
** the 2-rows-off filtered data readout introduced with configurable filter in rev. 5.1.0 and 5.1.1 is fixed now.

* '''Bugs:'''
** none so far.

* '''FPGA Resource Usage''' (readout_card.fit.rpt)
; Total logic elements ; 33,285 / 41,250 ( 81 % ) ;
; Total pins ; 358 / 616 ( 58 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt)
; Fast Model Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 6.591 ns
; Fast Model Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 7.206 ns
; Fast Model Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 18.299 ns

== Revision 5.1.1 (not recommended) ==
* '''Filename:'''
** rc_v05010001_01dec2010.sof (for Rev. B cards)

* '''Features:'''
** based on 5.1.0, but k1 and k2 (filter params) are now limited to k1<16 and k2<32 in order to resolve the timing failures of compiling 5.1.0 for smaller Stratix FPGA on RC Rev. B.

* '''Bugs:'''
** filter mode data is off by 2 rows.

== Revision 5.1.0 (not recommended) ==
* '''Filename:'''
** rc_stratix3_v05010000_01nov2010.sof (for Rev. E cards)
** rc_v05010000_01nov2010.sof (for Rev. B cards) has timing failures '''do not use!!!'''

* '''Features:'''
** added configurable filter parameters specified by ''fltr_coeff'', default is the fcutoff/fsampl=122Hz/15kHz. see [[ Digital 4-pole Butterworth Low-pass filter ]].
** ''fltr_type'' is set to 255 to indicate configurable filter parameters.
** see [http://www.phas.ubc.ca/~mce/mcedocs/software/SC2_ELE_S580_515_mce_command_description.pdf MCE command description]
** development notes:
*** It is built on Quartus10.1.
*** tcl files had to be updated as cmp syntax is not supported in Q10 anymore.
*** Rev. E cards now can be identified by reading back pcb_rev as part of card_type, therefore both stratix I and III sof/pof/jic are generated from the same source.

* '''Bugs:'''
** rc_v05010000_01nov2010.sof has timing failures that were overlooked, do not use this firmware for Rev.B cards.
** '''filter mode data is off by 2 rows.'''

* '''FPGA Resource Usage and Timing Report''' (readout_card.fit.rpt and readout_card.tan.rpt): logic usage is upto 85% from 66% in 5.0.d/e/f

= Revision 5.0.f =
* '''Filename:'''
** rc_v0500000f_22oct2010.sof (for Rev. B cards)
** rc_stratix3_v0500000f_22oct2010.sof (for Rev. E cards)

* '''Features:'''
** Bugfix: integral clamp should work now. only positive integral_clamp values are valid!

* '''Details:''': SQ1FB is applied 18 clock cycles after start of a row visit (SQ1_Bias being applied) regardless of flux-jump being enabled or not. In pre-5.0.b firmware SQ1FB was being applied after 7 clock cycles when flux-jump was disabled and after 18 clock cycles when flux-jump was enabled.
** available for both Rev. E and Rev. B cards, the upper byte of card_type parameter now reports the pcb revision.
** development note: It is built on Quartus10.1.

* '''Bugs:'''
**none yet!

* '''FPGA Resource Usage and Timing Report''' (readout_card.fit.rpt and readout_card.tan.rpt): no change compared to 5.0.a/b/c/d

== Revision 5.0.e (not recommended) ==
* '''Filename:'''
** rc_v0500000e_06oct2010.sof

* '''Details:'''
** an unsuccessful attempt to fix integral_clamp, but changed the functionality so that it clamps at the value, but it doesn't hold the clamp. i.e., if the calculated sq1fb becomes less than the specified clamp value, the sq1fb is not clamped anymore. This is not a desired functionality!

= Revision 5.0.d =
* '''Filename:'''
** rc_v0500000d_04aug2010.sof

* '''Features:'''
** Bugfix: To fix the bug associated with negative flux-jumps, reverted to signed multiplier and hence, incremented the width of the flux-quanta multiplier input by 1.

* '''Details:''': SQ1FB is applied 18 clock cycles after start of a row visit (SQ1_Bias being applied) regardless of flux-jump being enabled or not. In pre-5.0.b firmware SQ1FB was being applied after 7 clock cycles when flux-jump was disabled and after 18 clock cycles when flux-jump was enabled.

* '''Bugs:'''
** '''integral_clamping is broken'''. To test the clamping, a servo-locked ramp was initiated on the sq1fb and then flux-jumping was turned on and observed by attaching a scope to the SQ1FB output. With integral_clamp=80000000, flux_quanta=8000, gaini=1, flux-jump enabled, we see [[http://e-mode.phas.ubc.ca/mcewiki/index.php/Image:Clamp_unstable.png scope snapshot]] used slow_fb_ramp.py script for testing.

* '''FPGA Resource Usage and Timing Report''' (readout_card.fit.rpt and readout_card.tan.rpt): no change compared to 5.0.a/b/c

== Revision 5.0.c (not recommended) ==
* '''Filename:'''
** rc_v0500000c_16jun2010.sof

* '''Features:'''
** Based on rev. 5.0.b
** Re-introduced flux-jump counter clamping to maintain continuity in behavior from past versions of firmware in the field.
** '''Important''': SQ1FB is applied 18 clock cycles after start of a row visit (SQ1_Bias being applied) regardless of flux-jump being enabled or not. In pre-5.0.b firmware SQ1FB was being applied after 7 clock cycles when flux-jump was disabled and after 18 clock cycles when flux-jump was enabled.

* '''Details:'''
* '''Bugs:'''
** '''flux-jump is broken'''. flux-jumping block misbehaves at the first jump in the negative range.

* '''FPGA Resource Usage''' (readout_card.fit.rpt): [[rc_5.0.c_fit_rpt]]
; Total logic elements ; 26,800 / 41,250 ( 65 % ) ;
; Total pins ; 358 / 616 ( 58 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;
; DSP block 9-bit elements ; 76 / 112 ( 68 % ) ;
; Total PLLs ; 1 / 6 ( 17 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt): [[rc_5.0.c_tan_rpt]]
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.964 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 4.382 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 15.924 ns ;

== Revision 5.0.b (not recommended) ==
* '''Filename:'''
** rc_v0500000b_03jun2010.sof

* '''Features:'''
** Based on rev. 5.0.a
** A bug that caused jumps in first-stage feedback, and detected as spikes in the raw data of pixels that were in servo_mode=0,1,2 was fixed. The jumps in FSFB were due to flux-jumping being enabled on live pixes with non-zero flx_quanta, and being disabled on the fly on dead pixels with flx_quanta=0. Flux-jumping is now disabled on a column-by-column basis if a column is in servo_mode = 0,1,2.
** Ineffective clamping was removed from the flux-jumping block (as per 5.0.9), as it is now replaced by the clamping that was perfected in rev. 5.0.10
** A sticky bit that only affected servo_mode=0,1,2 was also removed from the flux-jumping block.
** flx_lp_init commands now also clear the flux-jumping block as well.
** The 11-clock-cycle delay (in applying SQ1_FB) that in previous firmware only occurred when flux-jumping was enabled, now (in this version) is in effect all the time. Due to the bug-fix above, flux-jumping can be disabled on a column-by-column basis by setting servo_mode=0,1,2 when en_fb_jump=1. Before the change, this meant that constant values could be applied with or without the 11-cycle delay if en_fb_jump=1 or 0. To make the delay consistent, it is now always 11 cycles. As background, the flux-jumping block is pipelined, meaning that it does calculations for all 8 channels serially. The serialization is because of DSP-block limitations in the Readout Card FPGA that prevent us from doing all 8 channels in parallel. The reason that it takes 11 cycles to complete the flux-jumping calculations is because the values are computed for the eight channels in three ALU stages: 8 + 3 = 11 cycles. Adding 11 cycles to the 7 cycles of latency from other stages in the system results in: 11 + 7 = 18 cycles of latency from the start of a row dwell period before the first-stage feedback is applied. In rc_v5.0.c, I enforce the 18-cycle delay even when flux-jumping is not enabled to maintain uniformity across all eight channels, because flux-jumping is enabled/disabled on a per-channel basis. In other words, if I hadn't enforced the 18-cycle delay, some channels could have their feedback applied after 7 cycles, while others could have it applied after 18 cycles. I wasn't a fan of this non-uniformity. I realize that 18 cycles is a long time. In fact, so is 7. In the last few months, we have been discussing how to reduce these times to 1 cycle, because every experiment out there wants to multiplex as fast as possible, and the 7/18-delay is a rate limiting step.
** The flux-jumping code was re-arranged in the flux-jumping block to reflect the flow of data through the pipeline and make it easier to understand.

* '''Details:'''

* '''Bugs:'''
** flux-jump does not work when jumping to negative values.

* '''FPGA Resource Usage''' (readout_card.fit.rpt): [[rc_5.0.b_fit_rpt]]
; Total logic elements ; 26,745 / 41,250 ( 65 % ) ;
; Total pins ; 358 / 616 ( 58 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;
; DSP block 9-bit elements ; 76 / 112 ( 68 % ) ;
; Total PLLs ; 1 / 6 ( 17 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;
* '''FPGA Timing Analysis''' (readout_card.tan.rpt): [[rc_5.0.b_tan_rpt]]
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.459 ns
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.895 ns
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 15.956 ns

= Revision 5.0.a =
* '''Filename:'''
** rc_v0500000a_12mar2010.sof

* '''Features:'''
** Based on the merger of rev. 5.0.8 and 5.0.9.
** '''integral_clamp''' command is added where a clamp value is set for the integral term and once the integral term hits that value, the integral-term is clamped to that value and p-term and d-term are clamped to zero. When integral_term=0 then no clamping is in effect, similar to previous releases of firmware.
** The low pass filter has 20-bit input and f_3dB/f_samp = 122Hz/15kHz .
** The flux-jump clamping that was removed in 5.0.9 is included once again here, as we decided this is safer for now.

* '''Details:'''
** "lock_dat_left" parameter that was removed in 5.0.9 is now implemented as "lock_dat_lsb"

* '''Bugs:'''
** flx_lp_init does not reinitialize the flux-jump block

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis
** tag name: rc_v0500000a_12mar2009! years were mixed up!

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
* '''FPGA Timing Analysis''' (readout_card.tan.rpt):

== Revision 5.0.9 (buggy) ==
* '''Filename:'''
** rc_v05000009_13nov2009.sof

* '''Features:'''
** Based on rev. 5.0.4
** Removes a sticky bit in pid calculation result storage -- in fsfb_processor.
** Adds a command to clamp the growth of the I-term to prevent wrapping and track down the source of Caltech's FSFB jumps.
** Removed the unused lock_dat_left parameter. The ability to shift left was moved to the fsfb_corr block some time ago.
** Fixed a sign extension bug acting on the flux quanta, which limited the value to 8191. Changed the extension from signed to unsigned.
** Removed ineffective clamping in the flux-jump calculation block.
** IMPORTANT: Must be used in conjunction with firmware rev. 5.0.0+ of all other cards.

* '''Details:'''

* '''Bugs:'''
** integral_clamp read/write command does not work.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 27,960 / 41,250 ( 68 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.825 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.878 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 14.397 ns ;

== Revision 5.0.8 (UBC only) ==
* '''Filename:'''
** rc_v05000008_09oct2009.sof

* '''Features:'''
** Based on rev. 5.0.4
** type 1 low-pass filter: f3dB=122Hz for fsample=15kHz
** Filter-input-width changed from 18b to 20b with no sticky bits!
** removed sticky bits in internal arithmetic of the filter.

= Revision 5.0.7 (type-2 filter) =
* '''Filename:'''
** rc_v05000007_09oct2009.sof

* '''Features:'''
** Based on rev. 5.0.4
** type-2 low-pass-filter: f3dB=75Hz for fsample=30000.
** Filter-input-width changed from 18b to 20b with no sticky bits!
** inter-biquad-gain-scaling for the filter is 2^14
** filter results are scaled down by 2^3 in the output of the filter.
** removed sticky bits in internal arithmetics
** _correction_ disabled in fsfb_proc_pidz

* '''Details:'''
** quartus.ini file was '''not''' present in synth directory.

* '''Bugs:'''
** none to report

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
== Revision 5.0.6 (UBC only) ==
* '''Filename:'''
** rc_stratix3_v05000006_15sep2009.sof

* '''Features:'''
** Only Valid for Rev. C/D Cards
** Based on rev. 5.0.3
** tcl file updated for Rev. D and aligned with top-level and qsf (project file).
** flux loop commented, just to try sampling the ADC.
** compiled with Q9.1

== Revision 5.0.5 (UBC only) ==
* '''Filename:'''
** rc_v05000005_04sep2009.sof

* '''Features:'''
** Based on rev. 5.0.2
** changed the low-pass-filter to f(3db)=75Hz for f(sample)=30000.

* '''Details:'''
** quartus.ini file was '''not''' present in synth directory.

* '''Bugs:'''
** negative inputs to the filter cause filter to have a non-flat pass-band region. may have to do with sign-handling...

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
* '''FPGA Timing Analysis''' (readout_card.tan.rpt):

= Revision 5.0.4 =
* '''Filename:'''
** rc_v05000004_28aug2009.sof

* '''Features:'''
** Based on rev. 5.0.2
** BUG Fix: handles 14-bit flux quanta (changed the multiplier to unsigned)
** BUG Fix: changed standard logic vector extension from signed to unsigned in flux-jumping slave.
** IMPORTANT: Must be used in conjunction with firmware rev. 5.0.0+ of all other cards.

* '''Details:'''

* '''Bugs:'''
** None so far.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,170 / 41,250 ( 63 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.541 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.612 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 15.398 ns ;

= Revision 5.0.3 =
* '''Filename:'''
** rc_stratix3_v05000003_21aug2009.sof

* '''Features:'''
** ONLY valid REV C/D RC Cards
** Based on rev. 5.0.2
** flux loop commented, just to try sampling the ADC.
** updated tcl file, but still need to rely on project file as well as qsf file.
** changed default level of adc_sclk to '1'
** dac_clr_n was changed from an output to an input.
** added 'locked' interface to rc_pll_stratix_iii
** renamed the adc_pll clock signals to more explanitory names
** added the FPGA_DEVICE_FAMILY generic to the dispatch interace for synthesis of the dc_fifo in lvds_rx
** uncommented DDR interface to force the syntesizer to use correct left and right PLLs (in conjunction with ADC and DDR PLLs)
** added test signals to test_status to see clocks on the scope.
== Revision 5.0.2 (buggy) ==
* '''Filename:'''
** rc_v05000002_test00_tagged.sof

* '''Features:'''
** Based on rev. 5.0.1
** Fixed a bug in wbs_frame_data that stored data incorrectly if reporting 1 or 2 pixels only.
** IMPORTANT: Must be used in conjunction with firmware rev. 5.0.0+ of all other cards.

* '''Details:'''

* '''Bugs:'''
** None so far.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,186 / 41,250 ( 63 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.755 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.979 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.067 ns ;

== Revision 5.0.1 (buggy) (Filter + Raw + Rectangle, 2 LVDS) ==
* '''Filename:'''
** rc_v05000001_26may2009.sof

* '''Features:'''
** Combines features in rev. 5.0.0 (2 LVDS Lines) and rev. 4.0.e (Filtered + Raw), with the NEW rectangle mode.
** IMPORTANT: Must be used in conjunction with firmware rev. 5.0.0+ of all other cards.

* '''Details:'''
** [[CVS Diff Between sys_v05000000 and rc_v05000001]]

* '''Bugs:'''
** Has a bug in wbs_frame_data that stored data incorrectly if reporting 1 or 2 pixels only.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,565 / 41,250 ( 64 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.656 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.861 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 14.167 ns ;

== Revision 5.0.0 (Filter Only, 2 LVDS) ==
* '''Filename:'''
** rc_v05000000_22dec2008.sof (tagged as sys_v05000000_22dec2008)

* '''Features:'''
** IMPORTANT: Must be used in conjunction with firmware v05000000+ of all other cards!!!
** Adds the ability to read out one column of data continuously from readout cards
** Adds data mode 11, which is an engineering mode. Data points are 32-bits, and bits [9..3]=row_index, [2..0]=column_index. This mode is useful for determining which pixels one is reading out in the array, in column mode for example.

* '''Details:'''
** [[CVS Diff Between rc_v0400000c and sys_v05000000]]

* '''Bugs:'''
** None so far.

* '''Synthesis Notes:'''
** The quartus.ini file was not present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,607 / 41,250 ( 65 % ) ;
; Total memory bits ; 406,016 / 3,423,744 ( 12 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.558 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.892 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.987 ns ;

== Revision 4.0.f (Filter + Raw, 1 LVDS) ==
* '''Filename:'''
** rc_v0400000f_12feb2010.sof

* '''Features:'''
** Based on 4.0.e and in parallel with 5.0.9 (equivalent version, clamping is not included)
** Incorporates fixes that were done to flux-jumping between 5.0.2 - 5.0.4 - 5.0.9. Namely:
*** Changes a multiplier from signed to unsigned (in fsfb_corr_multplier.vhd).
*** Changes sign extension from signed to unsigned (in flux_quanta_ram_admin.vhd).

* '''Details:'''

* '''Bugs:'''
** None reported yet.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,773 / 41,250 ( 65 % ) ;
; Total memory bits ; 1,321,984 / 3,423,744 ( 39 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.539 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 4.118 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 17.318 ns ;

== Revision 4.0.e (Filter + Raw, 1 LVDS) ==
* '''Filename:'''
** rc_v0400000e_27apr2009.sof

* '''Features:'''
** Based on 4.0.d
** Combines both raw- and filtered-data modes.
** fpga_temp, card_temp, card_id commands are disabled.
** Tested by Matt Hasselfield.

* '''Details:'''

* '''Bugs:'''
** fpga_temp, card_temp, card_id commands are disabled.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 27,048 / 41,250 ( 66 % ) ;
; Total memory bits ; 1,321,984 / 3,423,744 ( 39 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.675 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.907 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.728 ns ;

== Revision 4.0.d (Raw Only, 1 LVDS) ==
* '''Filename:''' rc_v0400000d_20090417.sof

* '''Features:'''
** Based on v4.0.c, but has the filter removed, and implements a single 65536-index RAM block for storing 50 MHz raw-data samples.
** The firmware takes a new command called readout_col_index which specifies which column to capture raw data from.
** Other than readout_col_index, the firmware functions the same as previous raw-data firmware, including then need to issue a capture_raw command.
** For more information on raw-data, see: http://e-mode.phas.ubc.ca/mcewiki/index.php/Raw-mode_readout
** This firmware also integrates some of the improvements that were implemented in 4.4.0, like the removal of the tga_o signal from an FSM in dispatch_wishbone.vhd.

* '''Details:'''
** Differences between 4.0.c and 4.0.d
U system/test/source/tb/tb_cc_rcs_bcs_ac.vhd
U all_cards/dispatch/source/rtl/dispatch_wishbone.vhd
U library/sys_param/source/rtl/wishbone_pack.vhd
U readout_card/adc_sample_coadd/source/rtl/adc_sample_coadd.vhd
U readout_card/adc_sample_coadd/source/rtl/adc_sample_coadd_pack.vhd
U readout_card/flux_loop/source/rtl/flux_loop.vhd
U readout_card/flux_loop/source/rtl/flux_loop_pack.vhd
U readout_card/flux_loop_ctrl/source/rtl/flux_loop_ctrl.vhd
U readout_card/flux_loop_ctrl/source/rtl/flux_loop_ctrl_pack.vhd
U readout_card/flux_loop_ctrl/source/tb/tb1_flux_loop_ctrl.vhd
U readout_card/flux_loop_ctrl/source/tb/tb2_flux_loop_ctrl.vhd
U readout_card/fsfb_calc/source/rtl/fsfb_fltr_regs.vhd
U readout_card/fsfb_corr/source/rtl/fsfb_corr.vhd
U readout_card/readout_card/source/rtl/readout_card.vhd
U readout_card/readout_card/source/rtl/readout_card_pack.vhd
U readout_card/wbs_frame_data/source/rtl/wbs_frame_data.vhd
U readout_card/wbs_frame_data/source/rtl/wbs_frame_data_pack.vhd

* '''Bugs:'''
** None so far.
** fpga_temp, card_temp, card_id commands are not supported.

* '''Synthesis Notes:'''
** The quartus.ini file was present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 24,554 / 41,250 ( 60 % ) ;
; Total memory bits ; 1,262,592 / 3,423,744 ( 37 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.991 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.864 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 17.052 ns ;

== Revision 4.4.1 ==
* '''Filename:''' rc_v04040001_21nov2008

* '''Features:'''
** Fixes a bug that froze up the firmware if any of the following commands were issued: CARD_ID_ADDR, CARD_TEMP_ADDR, FPGA_TEMP_ADDR in 4.4.0 only.

* '''Details:'''
** The bug fix include adding more logic to the wishbone ack path (readout_card.vhd), which subsequently decreased the minimum clock setup time to 1.588ns. The new logic will catch errors that the old logic wouldn't have, and is now consistent with the firmware on all the other cards. However, if timing becomes an issue, the logic may have to revert back to that which was in version 4.0.c.

* '''Bugs:'''
** None so far.

* '''Synthesis Notes:'''
** The quartus.ini file was not present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 27,241 / 41,250 ( 66 % ) ;
; Total memory bits ; 405,504 / 3,423,744 ( 12 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.588 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.585 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 17.057 ns ;

== Revision 4.4.0 (buggy) ==
* '''Filename:''' rc_v04040000_02oct2008
* '''Features:'''
** Reinstated the data modes in wbs_frame_data.vhd that were removed in 4.0.c. This firmware has the following modes: '''0, 1, 2, 4, 5, 7, 10'''. The modes that are not present are: '''3''' (raw data), '''6''' (replaced by data_mode = 7), '''8''' (replaced by data_mode = 10), '''9''' (replaced by data_mode = 10). For more information on data modes, see [[Data mode]].
** Re-integrated the id_thermo and fpga_thermo block in the readout_card.vhd top level that was removed in 4.0.c.
** Removed the sticky bit in fsfb_corr.vhd, which was enabled when flux-jumping was turned on. Because the feedback is signed, the sticky bit would usually reflect the value of the 14th bit, except in situations when the number of flux quanta to jump was greater than 1 (i.e. cosmic rays, IV-curves, etc). Flux jumps are made at a maximum rate of one per frame period, so that if the First-Stage Feedback increased past the 13th bit, it would not be reflected in the feedback applied. Now it is.
* '''Details:'''
** Simplified the FSM logic in wbs_frame_data.vhd that determines when to transition from IDLE to WSS1. This was done to lower the number of gates in that path, and ease the timing.
** Removed the z_dat_i port in fsfb_processor.vhd and fsfb_calc_pack.vhd to the fsfb_proc_pidz block, in an effort to make it clearer within that block that the z-term is always = 0.
** Removed the z-term sign extension in fsfb_proc_pidz.vhd, and the [d-term + z-term] adder to free up DSP resources since the z-term is always = 0.
** Adjusted the indentation in fsfb_io_controller.vhd to make the file more readable.
** Moved the tga_o signal out of the dispatch_wishbone.vhd FSM, and made it a continuous assignment. This signal had one of the highest fan-out counts in the RTL design, and actually was impossible to route in Stratix III chips in its previous configuration because of the number of gates on the fan-out. As a consequence of making it a continuous assignment, the Stratix III fitter was able to succeed, and the Stratix I timing characteristics were greatly improved. This is the most significant change in this revision. This change single-handedly increased the minimum slack from 1.282 ns in v0400000c to 2.372 ns (or 56.7 MHz max) in this revision.
* '''Bugs:'''
** The following commands lock up the Readout Card firmware: CARD_ID_ADDR, CARD_TEMP_ADDR, FPGA_TEMP_ADDR.
** fb_const0 commands to channel 0 do not work. The value is stored in the register, but not applied to the DAC. Thus, read-back returns the correct value, but the DAC does not
* '''Synthesis Notes:'''
** The quartus.ini file was not present in the synth directory during synthesis.
* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 27,099 / 41,250 ( 66 % ) ;
; Total memory bits ; 406,016 / 3,423,744 ( 12 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.372 ns ;
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 4.052 ns ;
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.066 ns ;

== Revision 4.0.c ==
* '''Filename:''' rc_v0400000c_15aug2008.sof
* '''Features:'''
** Only has data modes 0, 1, 4, and 10.
** Fixed the bug that exists in 4.0.b, 4.0.a, and 4.0.9 that prevented the fb_const value from being applied to channel zero (wbs_fb_data.vhd).
* '''Details:'''
** Changed a counter in the dispatch block to ease timing constraints in synthesis (dispatch_wishbone.vhd)
** Updated the tagged versions of dispatch.vhd , dispatch_cmd_receive.vhd, and dispatch_reply_transmit.vhd to the version that is used by all the other cards.
** '''Removed''' the fpga_termo (command: '''fpga_temp''') and id_thermo (commands: '''card_temp, card_id''') to ease timing constraints in synthesis (readout_card.vhd)
** Updated the tagged version of fpga_termo.vhd to include the new 'stale bit' feature
** Updated the tagged version of frame_timing_core.vhd to include the new 'err_o' interface
* '''Bugs:'''
** None reported yet
* '''Synthesis Notes:'''
** The quartus.ini file was not present in the synth directory during synthesis.
* '''FPGA Resource Usage:'''
Total logic elements : 25,058 / 41,250 ( 61 % )
Total memory bits : 400,896 / 3,423,744 ( 12 % )

* '''Timing Analysis''' (readout_card.tan.rpt):
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.282 ns ;
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.736 ns ;
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.665 ns ;

== Revision 4.0.b (buggy) ==
Note: This revision is on a watch list, after the bug detected 15 July 2008. See the bug section for more details.
* '''Filename''' : rc_v0400000b_04aug2008.sof
* '''Features'''
** data_mode 10 is added to provide more filtfb bits (compared to data mode 9) for planet observations. filtered_dat(27 downto 3) & flux_cnt_dat(6 downto 0)

* '''Bugs'''
** An unexplained bug that appeared in 4.0.a and may still be present in 4.0.b is a problem with the readout of channels being clipped out of data reporting. [[Bug 1 Notes]]

* ''' Synthesis note '''
** Quartus.ini removed.

== Revision 4.0.a (buggy) ==
Note: This revision is on a watch list, after the bug detected 15 July 2008. See the bug section for more details.
* '''Filename''' : rc_v0400000a_07jul2008.sof
* '''Bug Fix'''
** mce_status and adc_offset/flx_quanta commands do not fail after power up.
* ''' Synthesis note '''
** Quartus.ini removed.

* '''Bugs'''
** Seems to clip out channel 0 from data reporting.

== Revision 4.0.9 (buggy) ==
* '''Filename''' : rc_v04000009_26jun2008.sof
* '''Features'''
** sa_bias and offset DACs only refreshed when new values are written. (in previous versions, DACs were refreshed every frame)
* '''Bugs'''
** fb_const0 commands to channel 0 do not work. The value is stored in the register, but not applied to the DAC. Thus, read-back returns the correct value, but the DAC does not.
** reading flx_quanta and adc_offset right after power up hangs the reply datapath to CC. resetmce clears this error as temporary solution. the problem is caused by first read ack of the wishbone slave.

== Revision 4.0.8 ==
* '''Filename''' : rc_v04000008_26jun2008.sof
* '''Features'''
** The gaini, gainp, gaind resolution increased to 12-bit, i.e. -2048 to 2047 (formerly 10-bit).

* '''Bug fix'''
** the bug associated with gainpid read before mce_reset is fixed.

* ''' Synthesis note '''
** Quartus.ini removed.

== Revision 4.3.7 ==
* '''Filename''' : rc_v04030007_26may2008_raw.sof
* '''Features'''
** 14-bit raw mode enabled to buffer a snapshot of 50MHz samples for 2 frames of row_len * num_rows samples.
** In order to extend the raw-mode to 14-bit, an assumption is made that the raw buffer is not written to while being read. Therefore, make sure there is at least 2*row_len*num_rows*20ns between issuing captr_raw command and reading back the raw data.
** In order to save RAM for raw mode, two memory-intensive features are disabled:
*** low-pass filter disabled ( mixed filtfb data modes 6, 7, 9 are also disabled)
*** PID (gainp0, gaini0, gaind0) readback disabled. one can still set PID values and run servo, but can not read back the values.

== Revision 4.2.7 ==
* '''Filename''' : rc_v04020007_24may2008_raw.sof
* '''Features'''
** raw mode enabled to buffer a snapshot of 50MHz samples for 2 frames of row_len * num_rows samples.
** In order to save RAM for raw mode, two memory-intensive features are disabled:
*** low-pass filter disabled ( mixed filtfb data modes 6, 7, 9 are also disabled)
*** PID (gainp0, gaini0, gaind0) readback disabled. one can still set PID values and run servo, but can not read back the values.
* '''Bug fix'''
** the bug associated with reading from raw-buffer is fixed.

== Revision 4.1.7 ==
* '''Filename''' : rc_v04010007_25apr2008_raw.sof
* '''Features'''
** raw mode enabled to buffer a snapshot of 50MHz samples for 2 frames of row_len * num_rows samples.
** In order to save RAM for raw mode, two memory-intensive features are disabled:
*** low-pass filter disabled ( mixed filtfb data modes 6, 7, 9 are also disabled)
*** PID (gainp0, gaini0, gaind0) readback disabled. one can still set PID values and run servo, but can not read back the values.
* '''Bugs'''
** after each readout frame, raw-buffer readout counter falls behind by 3 and this causes skipping 3 50MHz samples in the data stream and column-data being messed up in subsequent frames. Data can be rearranged by post processing.

== Revision 4.0.6 (buggy) ==
* '''Filename''' : rc_v04000006_15feb2008.sof or .pof
* '''Features'''
** '''bugfix''': unreliable reset due to unsafe and incomplete state machines is fixed.
** '''bugfix''': flux_jump sign problem fixed, so far proved in const_mode, to be tested in servo_mode with cold setup.
** servo_mode=2 or ramp previously only went from 0 to ramp_amp, but now goes from -8192 to -8192+ramp_amp
** new commands are added: ''scratch'' and ''card_type''. Scratch takes 8 values and can be used by software to detect reset.
** slot_id and fw_rev are now integrated as part of all_cards.vhd
** lvds_tx_b=0, This will allow Clock Card to use the secondary backplane lvds line and check whether RC is plugged in.
** filter_coeff in misc_banks_admin commented as it is not implemented and causes timing problems.

* '''Bugs'''
** reading gainp/gaini/gaind right after power up hangs the reply datapath to CC. resetmce clears this error as temporary solution. the problem is caused by first read ack of pid_ram_admin.
** slot_id is only set after a resetmce is issued. (using the latest all_cards in the next revision will fix this)
** has spurious spikes on channel 7 data, which max out the integral, and cause the detectors to come unlocked. This firmware officially meets timing requirements, but the bug could be due to marginal timing on the longest data paths, i.e. ~0.1 ns in some cases.

== Revision 4.0.5 ==
* '''Filename''' : rc_v04000005_01nov2007.sof or .pof
* '''Features'''
** data mode 9 (mixed filt + flux jump) with windowing readjusted compared to data mode 8

* '''Bugs'''
** unreliable resetmce. Sometimes, firmware waked up non-responsive on lvds lines.
** In data mode 5 and 9, flux-jump counter is not reported properly due to a sign error. However, flux jumping works fine.

== Revision 3.0.19 ==
* '''Filename''' : rc_v03000019_16feb2007_raw.sof (no pof as one is not likely to run with this as regular firmware)
* '''Features'''
** data mode 3 is enabled.
** filter is disabled as a compromise to fit the raw-mode buffer.

* '''Bugs'''
** unreliable resetmce. Sometimes, firmware waked up non-responsive on lvds lines.

== Old Firmware Revisions ==
* '''4.0.4''': rc_v04000004_11oct2007.sof data mode 8 added (mixed filt + flux jump)
* '''4.0.3''': rc_v04000003_19sep2007.sof data mode 7 bit split readjusted to 10b error being bit 4 to 14
* '''4.0.2''': rc_v04000002_11sep2007.sof pid resolution increased to 10b, data mode 7 added
* '''4.0.1''': rc_v04000001_06sep2007.sof
* '''4.0.0''': rc_v04000000_29aug2007.sof supports readout_row_index * [[ bugs ]]

= To-Do List =
* the starting point for the servo is currently zero and it would be nice to have it programmable.

= RC Synthesis Notes =
# The following note applies when using Quartus versions earlier than Q7: Quartus.ini file had to exist in synth directory up to revision 4.0.a due to a bug that started in Quartus 6.1 and would synthesize away arbitrary parts of readout card. We contacted Altera at the time and they provided us the ini file.
# Timing: There is no "lock region" defined for readout card. Timing on readout card is tight and since version 3 or so any new feature would initially fail timing till some synthesis options were tweaked. One path that remains to be consistently marginal is from addr_gen counter (i.e. tga_o counter) in dispatch_wishbone.vhd to wishbone slaves particularly misc_banks_admin.vhd. Modules that are rewritten to address timing concerns are fsfb_corr, all_cards, misc_banks_admin, and finally instantiating an lpm counter instead of a counter from components library. Surprisingly, the lpm counter reduced 87 failures to 37, although looking at the technology map viewer, it seemed that they were both synthesized the same.
# Compile time: This was at some point 4.5 hours, after going to dual core PC, this was reduced to 35 minutes. After extending pid gains to 12b and fixing offset/sa_bias update code, the compile time increased to 1.5hr again with utilization up to ~70%.
# wbs_fb_storage, ram_8x64, pid_ram had to be regenerated using latest (Q7.2) MegaWizard to get rid of the bug associated with failure to read after power up until a reset was issued.
# During simulations, the initialization of RAM block with .hex files needs to be disabled. This is done by commenting out the following lines from the MegaWizard generated Megafunction files (remember to un-comment them before synthesizing the code):
lpm_file => "C:/scuba2_repository/cards/readout_card/fsfb_calc/source/rtl/ram_40x64.hex", and
lpm_file : STRING;
#Starting Q10.0 use TimeQuest timing analyzer as oppose to the classic one. The classic one is being phased out by Altera. In order to use TimeQuest, you need to have an sdc file present in your project directory.
----
[http://e-mode.phas.ubc.ca/mcewiki/index.php/Main_Page MCE Main Page]

Readout Card firmware

2011-05-04T21:35:39Z

Bburger: /* Revision 5.0.b (not recommended) */

* Synthesis Reminders (for firmware developers)
** quartus.ini is not needed anymore (Fixed as of Q7, Altera SR10783580 2010-10-24)
** Remember that readout_card/fsfb_clac/source/rtl/ram_40x64.vhd must be initialized with the ram_40x64.hex file in the same directory.
== Revision 5.1.2 ==
* '''Filename:'''
** rc_stratix3_v05010002_18jan2011.sof (for Rev. E cards)
** rc_stratix3_v05010002_18jan2011.jic (for Rev. E cards)
** rc_v05010002_03feb2011.sof (for Rev. B cards)
** rc_v05010002_03feb2011.pof (for Rev. B cards)

* '''Features:'''
** based on 5.1.1 with k1 and k2 (filter params) limited to k1<16 and k2<32 in order to resolve the timing when compiling for smaller Stratix FPGA on RC Rev. B.

* '''Bug fix:'''
** the 2-rows-off filtered data readout introduced with configurable filter in rev. 5.1.0 and 5.1.1 is fixed now.

* '''Bugs:'''
** none so far.

* '''FPGA Resource Usage''' (readout_card.fit.rpt)
; Total logic elements ; 33,285 / 41,250 ( 81 % ) ;
; Total pins ; 358 / 616 ( 58 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt)
; Fast Model Clock Hold: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 0.364 ns
; Fast Model Clock Hold: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 0.365 ns
; Fast Model Clock Hold: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 0.379 ns

== Revision 5.1.1 (not recommended) ==
* '''Filename:'''
** rc_v05010001_01dec2010.sof (for Rev. B cards)

* '''Features:'''
** based on 5.1.0, but k1 and k2 (filter params) are now limited to k1<16 and k2<32 in order to resolve the timing failures of compiling 5.1.0 for smaller Stratix FPGA on RC Rev. B.

* '''Bugs:'''
** filter mode data is off by 2 rows.

== Revision 5.1.0 (not recommended) ==
* '''Filename:'''
** rc_stratix3_v05010000_01nov2010.sof (for Rev. E cards)
** rc_v05010000_01nov2010.sof (for Rev. B cards) has timing failures '''do not use!!!'''

* '''Features:'''
** added configurable filter parameters specified by ''fltr_coeff'', default is the fcutoff/fsampl=122Hz/15kHz. see [[ Digital 4-pole Butterworth Low-pass filter ]].
** ''fltr_type'' is set to 255 to indicate configurable filter parameters.
** see [http://www.phas.ubc.ca/~mce/mcedocs/software/SC2_ELE_S580_515_mce_command_description.pdf MCE command description]
** development notes:
*** It is built on Quartus10.1.
*** tcl files had to be updated as cmp syntax is not supported in Q10 anymore.
*** Rev. E cards now can be identified by reading back pcb_rev as part of card_type, therefore both stratix I and III sof/pof/jic are generated from the same source.

* '''Bugs:'''
** rc_v05010000_01nov2010.sof has timing failures that were overlooked, do not use this firmware for Rev.B cards.
** '''filter mode data is off by 2 rows.'''

* '''FPGA Resource Usage and Timing Report''' (readout_card.fit.rpt and readout_card.tan.rpt): logic usage is upto 85% from 66% in 5.0.d/e/f

= Revision 5.0.f =
* '''Filename:'''
** rc_v0500000f_22oct2010.sof (for Rev. B cards)
** rc_stratix3_v0500000f_22oct2010.sof (for Rev. E cards)

* '''Features:'''
** Bugfix: integral clamp should work now. only positive integral_clamp values are valid!

* '''Details:''': SQ1FB is applied 18 clock cycles after start of a row visit (SQ1_Bias being applied) regardless of flux-jump being enabled or not. In pre-5.0.b firmware SQ1FB was being applied after 7 clock cycles when flux-jump was disabled and after 18 clock cycles when flux-jump was enabled.
** available for both Rev. E and Rev. B cards, the upper byte of card_type parameter now reports the pcb revision.
** development note: It is built on Quartus10.1.

* '''Bugs:'''
**none yet!

* '''FPGA Resource Usage and Timing Report''' (readout_card.fit.rpt and readout_card.tan.rpt): no change compared to 5.0.a/b/c/d

== Revision 5.0.e (not recommended) ==
* '''Filename:'''
** rc_v0500000e_06oct2010.sof

* '''Details:'''
** an unsuccessful attempt to fix integral_clamp, but changed the functionality so that it clamps at the value, but it doesn't hold the clamp. i.e., if the calculated sq1fb becomes less than the specified clamp value, the sq1fb is not clamped anymore. This is not a desired functionality!

= Revision 5.0.d =
* '''Filename:'''
** rc_v0500000d_04aug2010.sof

* '''Features:'''
** Bugfix: To fix the bug associated with negative flux-jumps, reverted to signed multiplier and hence, incremented the width of the flux-quanta multiplier input by 1.

* '''Details:''': SQ1FB is applied 18 clock cycles after start of a row visit (SQ1_Bias being applied) regardless of flux-jump being enabled or not. In pre-5.0.b firmware SQ1FB was being applied after 7 clock cycles when flux-jump was disabled and after 18 clock cycles when flux-jump was enabled.

* '''Bugs:'''
** '''integral_clamping is broken'''. To test the clamping, a servo-locked ramp was initiated on the sq1fb and then flux-jumping was turned on and observed by attaching a scope to the SQ1FB output. With integral_clamp=80000000, flux_quanta=8000, gaini=1, flux-jump enabled, we see [[http://e-mode.phas.ubc.ca/mcewiki/index.php/Image:Clamp_unstable.png scope snapshot]] used slow_fb_ramp.py script for testing.

* '''FPGA Resource Usage and Timing Report''' (readout_card.fit.rpt and readout_card.tan.rpt): no change compared to 5.0.a/b/c

== Revision 5.0.c (not recommended) ==
* '''Filename:'''
** rc_v0500000c_16jun2010.sof

* '''Features:'''
** Based on rev. 5.0.b
** Re-introduced flux-jump counter clamping to maintain continuity in behavior from past versions of firmware in the field.
** '''Important''': SQ1FB is applied 18 clock cycles after start of a row visit (SQ1_Bias being applied) regardless of flux-jump being enabled or not. In pre-5.0.b firmware SQ1FB was being applied after 7 clock cycles when flux-jump was disabled and after 18 clock cycles when flux-jump was enabled.

* '''Details:'''
* '''Bugs:'''
** '''flux-jump is broken'''. flux-jumping block misbehaves at the first jump in the negative range.

* '''FPGA Resource Usage''' (readout_card.fit.rpt): [[rc_5.0.c_fit_rpt]]
; Total logic elements ; 26,800 / 41,250 ( 65 % ) ;
; Total pins ; 358 / 616 ( 58 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;
; DSP block 9-bit elements ; 76 / 112 ( 68 % ) ;
; Total PLLs ; 1 / 6 ( 17 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt): [[rc_5.0.c_tan_rpt]]
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.964 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 4.382 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 15.924 ns ;

== Revision 5.0.b (not recommended) ==
* '''Filename:'''
** rc_v0500000b_03jun2010.sof

* '''Features:'''
** Based on rev. 5.0.a
** A bug that caused jumps in first-stage feedback, and detected as spikes in the raw data of pixels that were in servo_mode=0,1,2 was fixed. The jumps in FSFB were due to flux-jumping being enabled on live pixes with non-zero flx_quanta, and being disabled on the fly on dead pixels with flx_quanta=0. Flux-jumping is now disabled on a column-by-column basis if a column is in servo_mode = 0,1,2.
** Ineffective clamping was removed from the flux-jumping block (as per 5.0.9), as it is now replaced by the clamping that was perfected in rev. 5.0.10
** A sticky bit that only affected servo_mode=0,1,2 was also removed from the flux-jumping block.
** flx_lp_init commands now also clear the flux-jumping block as well.
** The 11-clock-cycle delay (in applying SQ1_FB) that in previous firmware only occurred when flux-jumping was enabled, now (in this version) is in effect all the time. Due to the bug-fix above, flux-jumping can be disabled on a column-by-column basis by setting servo_mode=0,1,2 when en_fb_jump=1. Before the change, this meant that constant values could be applied with or without the 11-cycle delay if en_fb_jump=1 or 0. To make the delay consistent, it is now always 11 cycles. As background, the flux-jumping block is pipelined, meaning that it does calculations for all 8 channels serially. The serialization is because of DSP-block limitations in the Readout Card FPGA that prevent us from doing all 8 channels in parallel. The reason that it takes 11 cycles to complete the flux-jumping calculations is because the values are computed for the eight channels in three ALU stages: 8 + 3 = 11 cycles. Adding 11 cycles to the 7 cycles of latency from other stages in the system results in: 11 + 7 = 18 cycles of latency from the start of a row dwell period before the first-stage feedback is applied. In rc_v5.0.c, I enforce the 18-cycle delay even when flux-jumping is not enabled to maintain uniformity across all eight channels, because flux-jumping is enabled/disabled on a per-channel basis. In other words, if I hadn't enforced the 18-cycle delay, some channels could have their feedback applied after 7 cycles, while others could have it applied after 18 cycles. I wasn't a fan of this non-uniformity. I realize that 18 cycles is a long time. In fact, so is 7. In the last few months, we have been discussing how to reduce these times to 1 cycle, because every experiment out there wants to multiplex as fast as possible, and the 7/18-delay is a rate limiting step.
** The flux-jumping code was re-arranged in the flux-jumping block to reflect the flow of data through the pipeline and make it easier to understand.

* '''Details:'''

* '''Bugs:'''
** flux-jump does not work when jumping to negative values.

* '''FPGA Resource Usage''' (readout_card.fit.rpt): [[rc_5.0.b_fit_rpt]]
; Total logic elements ; 26,745 / 41,250 ( 65 % ) ;
; Total pins ; 358 / 616 ( 58 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;
; DSP block 9-bit elements ; 76 / 112 ( 68 % ) ;
; Total PLLs ; 1 / 6 ( 17 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;
* '''FPGA Timing Analysis''' (readout_card.tan.rpt): [[rc_5.0.b_tan_rpt]]
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.459 ns
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.895 ns
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 15.956 ns

= Revision 5.0.a =
* '''Filename:'''
** rc_v0500000a_12mar2010.sof

* '''Features:'''
** Based on the merger of rev. 5.0.8 and 5.0.9.
** '''integral_clamp''' command is added where a clamp value is set for the integral term and once the integral term hits that value, the integral-term is clamped to that value and p-term and d-term are clamped to zero. When integral_term=0 then no clamping is in effect, similar to previous releases of firmware.
** The low pass filter has 20-bit input and f_3dB/f_samp = 122Hz/15kHz .
** The flux-jump clamping that was removed in 5.0.9 is included once again here, as we decided this is safer for now.

* '''Details:'''
** "lock_dat_left" parameter that was removed in 5.0.9 is now implemented as "lock_dat_lsb"

* '''Bugs:'''
** flx_lp_init does not reinitialize the flux-jump block

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis
** tag name: rc_v0500000a_12mar2009! years were mixed up!

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
* '''FPGA Timing Analysis''' (readout_card.tan.rpt):

== Revision 5.0.9 (buggy) ==
* '''Filename:'''
** rc_v05000009_13nov2009.sof

* '''Features:'''
** Based on rev. 5.0.4
** Removes a sticky bit in pid calculation result storage -- in fsfb_processor.
** Adds a command to clamp the growth of the I-term to prevent wrapping and track down the source of Caltech's FSFB jumps.
** Removed the unused lock_dat_left parameter. The ability to shift left was moved to the fsfb_corr block some time ago.
** Fixed a sign extension bug acting on the flux quanta, which limited the value to 8191. Changed the extension from signed to unsigned.
** Removed ineffective clamping in the flux-jump calculation block.
** IMPORTANT: Must be used in conjunction with firmware rev. 5.0.0+ of all other cards.

* '''Details:'''

* '''Bugs:'''
** integral_clamp read/write command does not work.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 27,960 / 41,250 ( 68 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.825 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.878 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 14.397 ns ;

== Revision 5.0.8 (UBC only) ==
* '''Filename:'''
** rc_v05000008_09oct2009.sof

* '''Features:'''
** Based on rev. 5.0.4
** type 1 low-pass filter: f3dB=122Hz for fsample=15kHz
** Filter-input-width changed from 18b to 20b with no sticky bits!
** removed sticky bits in internal arithmetic of the filter.

= Revision 5.0.7 (type-2 filter) =
* '''Filename:'''
** rc_v05000007_09oct2009.sof

* '''Features:'''
** Based on rev. 5.0.4
** type-2 low-pass-filter: f3dB=75Hz for fsample=30000.
** Filter-input-width changed from 18b to 20b with no sticky bits!
** inter-biquad-gain-scaling for the filter is 2^14
** filter results are scaled down by 2^3 in the output of the filter.
** removed sticky bits in internal arithmetics
** _correction_ disabled in fsfb_proc_pidz

* '''Details:'''
** quartus.ini file was '''not''' present in synth directory.

* '''Bugs:'''
** none to report

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
== Revision 5.0.6 (UBC only) ==
* '''Filename:'''
** rc_stratix3_v05000006_15sep2009.sof

* '''Features:'''
** Only Valid for Rev. C/D Cards
** Based on rev. 5.0.3
** tcl file updated for Rev. D and aligned with top-level and qsf (project file).
** flux loop commented, just to try sampling the ADC.
** compiled with Q9.1

== Revision 5.0.5 (UBC only) ==
* '''Filename:'''
** rc_v05000005_04sep2009.sof

* '''Features:'''
** Based on rev. 5.0.2
** changed the low-pass-filter to f(3db)=75Hz for f(sample)=30000.

* '''Details:'''
** quartus.ini file was '''not''' present in synth directory.

* '''Bugs:'''
** negative inputs to the filter cause filter to have a non-flat pass-band region. may have to do with sign-handling...

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
* '''FPGA Timing Analysis''' (readout_card.tan.rpt):

= Revision 5.0.4 =
* '''Filename:'''
** rc_v05000004_28aug2009.sof

* '''Features:'''
** Based on rev. 5.0.2
** BUG Fix: handles 14-bit flux quanta (changed the multiplier to unsigned)
** BUG Fix: changed standard logic vector extension from signed to unsigned in flux-jumping slave.
** IMPORTANT: Must be used in conjunction with firmware rev. 5.0.0+ of all other cards.

* '''Details:'''

* '''Bugs:'''
** None so far.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,170 / 41,250 ( 63 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.541 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.612 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 15.398 ns ;

= Revision 5.0.3 =
* '''Filename:'''
** rc_stratix3_v05000003_21aug2009.sof

* '''Features:'''
** ONLY valid REV C/D RC Cards
** Based on rev. 5.0.2
** flux loop commented, just to try sampling the ADC.
** updated tcl file, but still need to rely on project file as well as qsf file.
** changed default level of adc_sclk to '1'
** dac_clr_n was changed from an output to an input.
** added 'locked' interface to rc_pll_stratix_iii
** renamed the adc_pll clock signals to more explanitory names
** added the FPGA_DEVICE_FAMILY generic to the dispatch interace for synthesis of the dc_fifo in lvds_rx
** uncommented DDR interface to force the syntesizer to use correct left and right PLLs (in conjunction with ADC and DDR PLLs)
** added test signals to test_status to see clocks on the scope.
== Revision 5.0.2 (buggy) ==
* '''Filename:'''
** rc_v05000002_test00_tagged.sof

* '''Features:'''
** Based on rev. 5.0.1
** Fixed a bug in wbs_frame_data that stored data incorrectly if reporting 1 or 2 pixels only.
** IMPORTANT: Must be used in conjunction with firmware rev. 5.0.0+ of all other cards.

* '''Details:'''

* '''Bugs:'''
** None so far.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,186 / 41,250 ( 63 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.755 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.979 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.067 ns ;

== Revision 5.0.1 (buggy) (Filter + Raw + Rectangle, 2 LVDS) ==
* '''Filename:'''
** rc_v05000001_26may2009.sof

* '''Features:'''
** Combines features in rev. 5.0.0 (2 LVDS Lines) and rev. 4.0.e (Filtered + Raw), with the NEW rectangle mode.
** IMPORTANT: Must be used in conjunction with firmware rev. 5.0.0+ of all other cards.

* '''Details:'''
** [[CVS Diff Between sys_v05000000 and rc_v05000001]]

* '''Bugs:'''
** Has a bug in wbs_frame_data that stored data incorrectly if reporting 1 or 2 pixels only.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,565 / 41,250 ( 64 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.656 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.861 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 14.167 ns ;

== Revision 5.0.0 (Filter Only, 2 LVDS) ==
* '''Filename:'''
** rc_v05000000_22dec2008.sof (tagged as sys_v05000000_22dec2008)

* '''Features:'''
** IMPORTANT: Must be used in conjunction with firmware v05000000+ of all other cards!!!
** Adds the ability to read out one column of data continuously from readout cards
** Adds data mode 11, which is an engineering mode. Data points are 32-bits, and bits [9..3]=row_index, [2..0]=column_index. This mode is useful for determining which pixels one is reading out in the array, in column mode for example.

* '''Details:'''
** [[CVS Diff Between rc_v0400000c and sys_v05000000]]

* '''Bugs:'''
** None so far.

* '''Synthesis Notes:'''
** The quartus.ini file was not present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,607 / 41,250 ( 65 % ) ;
; Total memory bits ; 406,016 / 3,423,744 ( 12 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.558 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.892 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.987 ns ;

== Revision 4.0.f (Filter + Raw, 1 LVDS) ==
* '''Filename:'''
** rc_v0400000f_12feb2010.sof

* '''Features:'''
** Based on 4.0.e and in parallel with 5.0.9 (equivalent version, clamping is not included)
** Incorporates fixes that were done to flux-jumping between 5.0.2 - 5.0.4 - 5.0.9. Namely:
*** Changes a multiplier from signed to unsigned (in fsfb_corr_multplier.vhd).
*** Changes sign extension from signed to unsigned (in flux_quanta_ram_admin.vhd).

* '''Details:'''

* '''Bugs:'''
** None reported yet.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,773 / 41,250 ( 65 % ) ;
; Total memory bits ; 1,321,984 / 3,423,744 ( 39 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.539 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 4.118 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 17.318 ns ;

== Revision 4.0.e (Filter + Raw, 1 LVDS) ==
* '''Filename:'''
** rc_v0400000e_27apr2009.sof

* '''Features:'''
** Based on 4.0.d
** Combines both raw- and filtered-data modes.
** fpga_temp, card_temp, card_id commands are disabled.
** Tested by Matt Hasselfield.

* '''Details:'''

* '''Bugs:'''
** fpga_temp, card_temp, card_id commands are disabled.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 27,048 / 41,250 ( 66 % ) ;
; Total memory bits ; 1,321,984 / 3,423,744 ( 39 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.675 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.907 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.728 ns ;

== Revision 4.0.d (Raw Only, 1 LVDS) ==
* '''Filename:''' rc_v0400000d_20090417.sof

* '''Features:'''
** Based on v4.0.c, but has the filter removed, and implements a single 65536-index RAM block for storing 50 MHz raw-data samples.
** The firmware takes a new command called readout_col_index which specifies which column to capture raw data from.
** Other than readout_col_index, the firmware functions the same as previous raw-data firmware, including then need to issue a capture_raw command.
** For more information on raw-data, see: http://e-mode.phas.ubc.ca/mcewiki/index.php/Raw-mode_readout
** This firmware also integrates some of the improvements that were implemented in 4.4.0, like the removal of the tga_o signal from an FSM in dispatch_wishbone.vhd.

* '''Details:'''
** Differences between 4.0.c and 4.0.d
U system/test/source/tb/tb_cc_rcs_bcs_ac.vhd
U all_cards/dispatch/source/rtl/dispatch_wishbone.vhd
U library/sys_param/source/rtl/wishbone_pack.vhd
U readout_card/adc_sample_coadd/source/rtl/adc_sample_coadd.vhd
U readout_card/adc_sample_coadd/source/rtl/adc_sample_coadd_pack.vhd
U readout_card/flux_loop/source/rtl/flux_loop.vhd
U readout_card/flux_loop/source/rtl/flux_loop_pack.vhd
U readout_card/flux_loop_ctrl/source/rtl/flux_loop_ctrl.vhd
U readout_card/flux_loop_ctrl/source/rtl/flux_loop_ctrl_pack.vhd
U readout_card/flux_loop_ctrl/source/tb/tb1_flux_loop_ctrl.vhd
U readout_card/flux_loop_ctrl/source/tb/tb2_flux_loop_ctrl.vhd
U readout_card/fsfb_calc/source/rtl/fsfb_fltr_regs.vhd
U readout_card/fsfb_corr/source/rtl/fsfb_corr.vhd
U readout_card/readout_card/source/rtl/readout_card.vhd
U readout_card/readout_card/source/rtl/readout_card_pack.vhd
U readout_card/wbs_frame_data/source/rtl/wbs_frame_data.vhd
U readout_card/wbs_frame_data/source/rtl/wbs_frame_data_pack.vhd

* '''Bugs:'''
** None so far.
** fpga_temp, card_temp, card_id commands are not supported.

* '''Synthesis Notes:'''
** The quartus.ini file was present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 24,554 / 41,250 ( 60 % ) ;
; Total memory bits ; 1,262,592 / 3,423,744 ( 37 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.991 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.864 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 17.052 ns ;

== Revision 4.4.1 ==
* '''Filename:''' rc_v04040001_21nov2008

* '''Features:'''
** Fixes a bug that froze up the firmware if any of the following commands were issued: CARD_ID_ADDR, CARD_TEMP_ADDR, FPGA_TEMP_ADDR in 4.4.0 only.

* '''Details:'''
** The bug fix include adding more logic to the wishbone ack path (readout_card.vhd), which subsequently decreased the minimum clock setup time to 1.588ns. The new logic will catch errors that the old logic wouldn't have, and is now consistent with the firmware on all the other cards. However, if timing becomes an issue, the logic may have to revert back to that which was in version 4.0.c.

* '''Bugs:'''
** None so far.

* '''Synthesis Notes:'''
** The quartus.ini file was not present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 27,241 / 41,250 ( 66 % ) ;
; Total memory bits ; 405,504 / 3,423,744 ( 12 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.588 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.585 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 17.057 ns ;

== Revision 4.4.0 (buggy) ==
* '''Filename:''' rc_v04040000_02oct2008
* '''Features:'''
** Reinstated the data modes in wbs_frame_data.vhd that were removed in 4.0.c. This firmware has the following modes: '''0, 1, 2, 4, 5, 7, 10'''. The modes that are not present are: '''3''' (raw data), '''6''' (replaced by data_mode = 7), '''8''' (replaced by data_mode = 10), '''9''' (replaced by data_mode = 10). For more information on data modes, see [[Data mode]].
** Re-integrated the id_thermo and fpga_thermo block in the readout_card.vhd top level that was removed in 4.0.c.
** Removed the sticky bit in fsfb_corr.vhd, which was enabled when flux-jumping was turned on. Because the feedback is signed, the sticky bit would usually reflect the value of the 14th bit, except in situations when the number of flux quanta to jump was greater than 1 (i.e. cosmic rays, IV-curves, etc). Flux jumps are made at a maximum rate of one per frame period, so that if the First-Stage Feedback increased past the 13th bit, it would not be reflected in the feedback applied. Now it is.
* '''Details:'''
** Simplified the FSM logic in wbs_frame_data.vhd that determines when to transition from IDLE to WSS1. This was done to lower the number of gates in that path, and ease the timing.
** Removed the z_dat_i port in fsfb_processor.vhd and fsfb_calc_pack.vhd to the fsfb_proc_pidz block, in an effort to make it clearer within that block that the z-term is always = 0.
** Removed the z-term sign extension in fsfb_proc_pidz.vhd, and the [d-term + z-term] adder to free up DSP resources since the z-term is always = 0.
** Adjusted the indentation in fsfb_io_controller.vhd to make the file more readable.
** Moved the tga_o signal out of the dispatch_wishbone.vhd FSM, and made it a continuous assignment. This signal had one of the highest fan-out counts in the RTL design, and actually was impossible to route in Stratix III chips in its previous configuration because of the number of gates on the fan-out. As a consequence of making it a continuous assignment, the Stratix III fitter was able to succeed, and the Stratix I timing characteristics were greatly improved. This is the most significant change in this revision. This change single-handedly increased the minimum slack from 1.282 ns in v0400000c to 2.372 ns (or 56.7 MHz max) in this revision.
* '''Bugs:'''
** The following commands lock up the Readout Card firmware: CARD_ID_ADDR, CARD_TEMP_ADDR, FPGA_TEMP_ADDR.
** fb_const0 commands to channel 0 do not work. The value is stored in the register, but not applied to the DAC. Thus, read-back returns the correct value, but the DAC does not
* '''Synthesis Notes:'''
** The quartus.ini file was not present in the synth directory during synthesis.
* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 27,099 / 41,250 ( 66 % ) ;
; Total memory bits ; 406,016 / 3,423,744 ( 12 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.372 ns ;
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 4.052 ns ;
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.066 ns ;

== Revision 4.0.c ==
* '''Filename:''' rc_v0400000c_15aug2008.sof
* '''Features:'''
** Only has data modes 0, 1, 4, and 10.
** Fixed the bug that exists in 4.0.b, 4.0.a, and 4.0.9 that prevented the fb_const value from being applied to channel zero (wbs_fb_data.vhd).
* '''Details:'''
** Changed a counter in the dispatch block to ease timing constraints in synthesis (dispatch_wishbone.vhd)
** Updated the tagged versions of dispatch.vhd , dispatch_cmd_receive.vhd, and dispatch_reply_transmit.vhd to the version that is used by all the other cards.
** '''Removed''' the fpga_termo (command: '''fpga_temp''') and id_thermo (commands: '''card_temp, card_id''') to ease timing constraints in synthesis (readout_card.vhd)
** Updated the tagged version of fpga_termo.vhd to include the new 'stale bit' feature
** Updated the tagged version of frame_timing_core.vhd to include the new 'err_o' interface
* '''Bugs:'''
** None reported yet
* '''Synthesis Notes:'''
** The quartus.ini file was not present in the synth directory during synthesis.
* '''FPGA Resource Usage:'''
Total logic elements : 25,058 / 41,250 ( 61 % )
Total memory bits : 400,896 / 3,423,744 ( 12 % )

* '''Timing Analysis''' (readout_card.tan.rpt):
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.282 ns ;
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.736 ns ;
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.665 ns ;

== Revision 4.0.b (buggy) ==
Note: This revision is on a watch list, after the bug detected 15 July 2008. See the bug section for more details.
* '''Filename''' : rc_v0400000b_04aug2008.sof
* '''Features'''
** data_mode 10 is added to provide more filtfb bits (compared to data mode 9) for planet observations. filtered_dat(27 downto 3) & flux_cnt_dat(6 downto 0)

* '''Bugs'''
** An unexplained bug that appeared in 4.0.a and may still be present in 4.0.b is a problem with the readout of channels being clipped out of data reporting. [[Bug 1 Notes]]

* ''' Synthesis note '''
** Quartus.ini removed.

== Revision 4.0.a (buggy) ==
Note: This revision is on a watch list, after the bug detected 15 July 2008. See the bug section for more details.
* '''Filename''' : rc_v0400000a_07jul2008.sof
* '''Bug Fix'''
** mce_status and adc_offset/flx_quanta commands do not fail after power up.
* ''' Synthesis note '''
** Quartus.ini removed.

* '''Bugs'''
** Seems to clip out channel 0 from data reporting.

== Revision 4.0.9 (buggy) ==
* '''Filename''' : rc_v04000009_26jun2008.sof
* '''Features'''
** sa_bias and offset DACs only refreshed when new values are written. (in previous versions, DACs were refreshed every frame)
* '''Bugs'''
** fb_const0 commands to channel 0 do not work. The value is stored in the register, but not applied to the DAC. Thus, read-back returns the correct value, but the DAC does not.
** reading flx_quanta and adc_offset right after power up hangs the reply datapath to CC. resetmce clears this error as temporary solution. the problem is caused by first read ack of the wishbone slave.

== Revision 4.0.8 ==
* '''Filename''' : rc_v04000008_26jun2008.sof
* '''Features'''
** The gaini, gainp, gaind resolution increased to 12-bit, i.e. -2048 to 2047 (formerly 10-bit).

* '''Bug fix'''
** the bug associated with gainpid read before mce_reset is fixed.

* ''' Synthesis note '''
** Quartus.ini removed.

== Revision 4.3.7 ==
* '''Filename''' : rc_v04030007_26may2008_raw.sof
* '''Features'''
** 14-bit raw mode enabled to buffer a snapshot of 50MHz samples for 2 frames of row_len * num_rows samples.
** In order to extend the raw-mode to 14-bit, an assumption is made that the raw buffer is not written to while being read. Therefore, make sure there is at least 2*row_len*num_rows*20ns between issuing captr_raw command and reading back the raw data.
** In order to save RAM for raw mode, two memory-intensive features are disabled:
*** low-pass filter disabled ( mixed filtfb data modes 6, 7, 9 are also disabled)
*** PID (gainp0, gaini0, gaind0) readback disabled. one can still set PID values and run servo, but can not read back the values.

== Revision 4.2.7 ==
* '''Filename''' : rc_v04020007_24may2008_raw.sof
* '''Features'''
** raw mode enabled to buffer a snapshot of 50MHz samples for 2 frames of row_len * num_rows samples.
** In order to save RAM for raw mode, two memory-intensive features are disabled:
*** low-pass filter disabled ( mixed filtfb data modes 6, 7, 9 are also disabled)
*** PID (gainp0, gaini0, gaind0) readback disabled. one can still set PID values and run servo, but can not read back the values.
* '''Bug fix'''
** the bug associated with reading from raw-buffer is fixed.

== Revision 4.1.7 ==
* '''Filename''' : rc_v04010007_25apr2008_raw.sof
* '''Features'''
** raw mode enabled to buffer a snapshot of 50MHz samples for 2 frames of row_len * num_rows samples.
** In order to save RAM for raw mode, two memory-intensive features are disabled:
*** low-pass filter disabled ( mixed filtfb data modes 6, 7, 9 are also disabled)
*** PID (gainp0, gaini0, gaind0) readback disabled. one can still set PID values and run servo, but can not read back the values.
* '''Bugs'''
** after each readout frame, raw-buffer readout counter falls behind by 3 and this causes skipping 3 50MHz samples in the data stream and column-data being messed up in subsequent frames. Data can be rearranged by post processing.

== Revision 4.0.6 (buggy) ==
* '''Filename''' : rc_v04000006_15feb2008.sof or .pof
* '''Features'''
** '''bugfix''': unreliable reset due to unsafe and incomplete state machines is fixed.
** '''bugfix''': flux_jump sign problem fixed, so far proved in const_mode, to be tested in servo_mode with cold setup.
** servo_mode=2 or ramp previously only went from 0 to ramp_amp, but now goes from -8192 to -8192+ramp_amp
** new commands are added: ''scratch'' and ''card_type''. Scratch takes 8 values and can be used by software to detect reset.
** slot_id and fw_rev are now integrated as part of all_cards.vhd
** lvds_tx_b=0, This will allow Clock Card to use the secondary backplane lvds line and check whether RC is plugged in.
** filter_coeff in misc_banks_admin commented as it is not implemented and causes timing problems.

* '''Bugs'''
** reading gainp/gaini/gaind right after power up hangs the reply datapath to CC. resetmce clears this error as temporary solution. the problem is caused by first read ack of pid_ram_admin.
** slot_id is only set after a resetmce is issued. (using the latest all_cards in the next revision will fix this)
** has spurious spikes on channel 7 data, which max out the integral, and cause the detectors to come unlocked. This firmware officially meets timing requirements, but the bug could be due to marginal timing on the longest data paths, i.e. ~0.1 ns in some cases.

== Revision 4.0.5 ==
* '''Filename''' : rc_v04000005_01nov2007.sof or .pof
* '''Features'''
** data mode 9 (mixed filt + flux jump) with windowing readjusted compared to data mode 8

* '''Bugs'''
** unreliable resetmce. Sometimes, firmware waked up non-responsive on lvds lines.
** In data mode 5 and 9, flux-jump counter is not reported properly due to a sign error. However, flux jumping works fine.

== Revision 3.0.19 ==
* '''Filename''' : rc_v03000019_16feb2007_raw.sof (no pof as one is not likely to run with this as regular firmware)
* '''Features'''
** data mode 3 is enabled.
** filter is disabled as a compromise to fit the raw-mode buffer.

* '''Bugs'''
** unreliable resetmce. Sometimes, firmware waked up non-responsive on lvds lines.

== Old Firmware Revisions ==
* '''4.0.4''': rc_v04000004_11oct2007.sof data mode 8 added (mixed filt + flux jump)
* '''4.0.3''': rc_v04000003_19sep2007.sof data mode 7 bit split readjusted to 10b error being bit 4 to 14
* '''4.0.2''': rc_v04000002_11sep2007.sof pid resolution increased to 10b, data mode 7 added
* '''4.0.1''': rc_v04000001_06sep2007.sof
* '''4.0.0''': rc_v04000000_29aug2007.sof supports readout_row_index * [[ bugs ]]

= To-Do List =
* the starting point for the servo is currently zero and it would be nice to have it programmable.

= RC Synthesis Notes =
# The following note applies when using Quartus versions earlier than Q7: Quartus.ini file had to exist in synth directory up to revision 4.0.a due to a bug that started in Quartus 6.1 and would synthesize away arbitrary parts of readout card. We contacted Altera at the time and they provided us the ini file.
# Timing: There is no "lock region" defined for readout card. Timing on readout card is tight and since version 3 or so any new feature would initially fail timing till some synthesis options were tweaked. One path that remains to be consistently marginal is from addr_gen counter (i.e. tga_o counter) in dispatch_wishbone.vhd to wishbone slaves particularly misc_banks_admin.vhd. Modules that are rewritten to address timing concerns are fsfb_corr, all_cards, misc_banks_admin, and finally instantiating an lpm counter instead of a counter from components library. Surprisingly, the lpm counter reduced 87 failures to 37, although looking at the technology map viewer, it seemed that they were both synthesized the same.
# Compile time: This was at some point 4.5 hours, after going to dual core PC, this was reduced to 35 minutes. After extending pid gains to 12b and fixing offset/sa_bias update code, the compile time increased to 1.5hr again with utilization up to ~70%.
# wbs_fb_storage, ram_8x64, pid_ram had to be regenerated using latest (Q7.2) MegaWizard to get rid of the bug associated with failure to read after power up until a reset was issued.
# During simulations, the initialization of RAM block with .hex files needs to be disabled. This is done by commenting out the following lines from the MegaWizard generated Megafunction files (remember to un-comment them before synthesizing the code):
lpm_file => "C:/scuba2_repository/cards/readout_card/fsfb_calc/source/rtl/ram_40x64.hex", and
lpm_file : STRING;
#Starting Q10.0 use TimeQuest timing analyzer as oppose to the classic one. The classic one is being phased out by Altera. In order to use TimeQuest, you need to have an sdc file present in your project directory.
----
[http://e-mode.phas.ubc.ca/mcewiki/index.php/Main_Page MCE Main Page]

Readout Card firmware

2011-05-04T21:35:14Z

Bburger: /* Revision 5.0.b (not recommended) */

* Synthesis Reminders (for firmware developers)
** quartus.ini is not needed anymore (Fixed as of Q7, Altera SR10783580 2010-10-24)
** Remember that readout_card/fsfb_clac/source/rtl/ram_40x64.vhd must be initialized with the ram_40x64.hex file in the same directory.
== Revision 5.1.2 ==
* '''Filename:'''
** rc_stratix3_v05010002_18jan2011.sof (for Rev. E cards)
** rc_stratix3_v05010002_18jan2011.jic (for Rev. E cards)
** rc_v05010002_03feb2011.sof (for Rev. B cards)
** rc_v05010002_03feb2011.pof (for Rev. B cards)

* '''Features:'''
** based on 5.1.1 with k1 and k2 (filter params) limited to k1<16 and k2<32 in order to resolve the timing when compiling for smaller Stratix FPGA on RC Rev. B.

* '''Bug fix:'''
** the 2-rows-off filtered data readout introduced with configurable filter in rev. 5.1.0 and 5.1.1 is fixed now.

* '''Bugs:'''
** none so far.

* '''FPGA Resource Usage''' (readout_card.fit.rpt)
; Total logic elements ; 33,285 / 41,250 ( 81 % ) ;
; Total pins ; 358 / 616 ( 58 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt)
; Fast Model Clock Hold: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 0.364 ns
; Fast Model Clock Hold: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 0.365 ns
; Fast Model Clock Hold: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 0.379 ns

== Revision 5.1.1 (not recommended) ==
* '''Filename:'''
** rc_v05010001_01dec2010.sof (for Rev. B cards)

* '''Features:'''
** based on 5.1.0, but k1 and k2 (filter params) are now limited to k1<16 and k2<32 in order to resolve the timing failures of compiling 5.1.0 for smaller Stratix FPGA on RC Rev. B.

* '''Bugs:'''
** filter mode data is off by 2 rows.

== Revision 5.1.0 (not recommended) ==
* '''Filename:'''
** rc_stratix3_v05010000_01nov2010.sof (for Rev. E cards)
** rc_v05010000_01nov2010.sof (for Rev. B cards) has timing failures '''do not use!!!'''

* '''Features:'''
** added configurable filter parameters specified by ''fltr_coeff'', default is the fcutoff/fsampl=122Hz/15kHz. see [[ Digital 4-pole Butterworth Low-pass filter ]].
** ''fltr_type'' is set to 255 to indicate configurable filter parameters.
** see [http://www.phas.ubc.ca/~mce/mcedocs/software/SC2_ELE_S580_515_mce_command_description.pdf MCE command description]
** development notes:
*** It is built on Quartus10.1.
*** tcl files had to be updated as cmp syntax is not supported in Q10 anymore.
*** Rev. E cards now can be identified by reading back pcb_rev as part of card_type, therefore both stratix I and III sof/pof/jic are generated from the same source.

* '''Bugs:'''
** rc_v05010000_01nov2010.sof has timing failures that were overlooked, do not use this firmware for Rev.B cards.
** '''filter mode data is off by 2 rows.'''

* '''FPGA Resource Usage and Timing Report''' (readout_card.fit.rpt and readout_card.tan.rpt): logic usage is upto 85% from 66% in 5.0.d/e/f

= Revision 5.0.f =
* '''Filename:'''
** rc_v0500000f_22oct2010.sof (for Rev. B cards)
** rc_stratix3_v0500000f_22oct2010.sof (for Rev. E cards)

* '''Features:'''
** Bugfix: integral clamp should work now. only positive integral_clamp values are valid!

* '''Details:''': SQ1FB is applied 18 clock cycles after start of a row visit (SQ1_Bias being applied) regardless of flux-jump being enabled or not. In pre-5.0.b firmware SQ1FB was being applied after 7 clock cycles when flux-jump was disabled and after 18 clock cycles when flux-jump was enabled.
** available for both Rev. E and Rev. B cards, the upper byte of card_type parameter now reports the pcb revision.
** development note: It is built on Quartus10.1.

* '''Bugs:'''
**none yet!

* '''FPGA Resource Usage and Timing Report''' (readout_card.fit.rpt and readout_card.tan.rpt): no change compared to 5.0.a/b/c/d

== Revision 5.0.e (not recommended) ==
* '''Filename:'''
** rc_v0500000e_06oct2010.sof

* '''Details:'''
** an unsuccessful attempt to fix integral_clamp, but changed the functionality so that it clamps at the value, but it doesn't hold the clamp. i.e., if the calculated sq1fb becomes less than the specified clamp value, the sq1fb is not clamped anymore. This is not a desired functionality!

= Revision 5.0.d =
* '''Filename:'''
** rc_v0500000d_04aug2010.sof

* '''Features:'''
** Bugfix: To fix the bug associated with negative flux-jumps, reverted to signed multiplier and hence, incremented the width of the flux-quanta multiplier input by 1.

* '''Details:''': SQ1FB is applied 18 clock cycles after start of a row visit (SQ1_Bias being applied) regardless of flux-jump being enabled or not. In pre-5.0.b firmware SQ1FB was being applied after 7 clock cycles when flux-jump was disabled and after 18 clock cycles when flux-jump was enabled.

* '''Bugs:'''
** '''integral_clamping is broken'''. To test the clamping, a servo-locked ramp was initiated on the sq1fb and then flux-jumping was turned on and observed by attaching a scope to the SQ1FB output. With integral_clamp=80000000, flux_quanta=8000, gaini=1, flux-jump enabled, we see [[http://e-mode.phas.ubc.ca/mcewiki/index.php/Image:Clamp_unstable.png scope snapshot]] used slow_fb_ramp.py script for testing.

* '''FPGA Resource Usage and Timing Report''' (readout_card.fit.rpt and readout_card.tan.rpt): no change compared to 5.0.a/b/c

== Revision 5.0.c (not recommended) ==
* '''Filename:'''
** rc_v0500000c_16jun2010.sof

* '''Features:'''
** Based on rev. 5.0.b
** Re-introduced flux-jump counter clamping to maintain continuity in behavior from past versions of firmware in the field.
** '''Important''': SQ1FB is applied 18 clock cycles after start of a row visit (SQ1_Bias being applied) regardless of flux-jump being enabled or not. In pre-5.0.b firmware SQ1FB was being applied after 7 clock cycles when flux-jump was disabled and after 18 clock cycles when flux-jump was enabled.

* '''Details:'''
* '''Bugs:'''
** '''flux-jump is broken'''. flux-jumping block misbehaves at the first jump in the negative range.

* '''FPGA Resource Usage''' (readout_card.fit.rpt): [[rc_5.0.c_fit_rpt]]
; Total logic elements ; 26,800 / 41,250 ( 65 % ) ;
; Total pins ; 358 / 616 ( 58 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;
; DSP block 9-bit elements ; 76 / 112 ( 68 % ) ;
; Total PLLs ; 1 / 6 ( 17 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt): [[rc_5.0.c_tan_rpt]]
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.964 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 4.382 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 15.924 ns ;

== Revision 5.0.b (not recommended) ==
* '''Filename:'''
** rc_v0500000b_03jun2010.sof

* '''Features:'''
** Based on rev. 5.0.a
** A bug that caused jumps in first-stage feedback, and detected as spikes in the raw data of pixels that were in servo_mode=0,1,2 was fixed. The jumps in FSFB were due to flux-jumping being enabled on live pixes with non-zero flx_quanta, and being disabled on the fly on dead pixels with flx_quanta=0. Flux-jumping is now disabled on a column-by-column basis if a column is in servo_mode = 0,1,2.
** Ineffective clamping was removed from the flux-jumping block (as per 5.0.9), as it is now replaced by the clamping that was perfected in rev. 5.0.10
** A sticky bit that only affected servo_mode=0,1,2 was also removed from the flux-jumping block.
** flx_lp_init commands now also clear the flux-jumping block as well.
** The 11-clock-cycle delay (in applying SQ1_FB) that in previous firmware only occurred when flux-jumping was enabled, now (in this version) is in effect all the time. Due to the bug-fix above, flux-jumping can be disabled on a column-by-column basis by setting servo_mode=0,1,2 when en_fb_jump=1. Before the change, this meant that constant values could be applied with or without the 11-cycle delay if en_fb_jump=1 or 0. To make the delay consistent, it is now always 11 cycles. As background, the flux-jumping block is pipelined, meaning that it does calculations for all 8 channels serially. The serialization is because of DSP-block limitations in the Readout Card FPGA that prevent us from doing all 8 channels in parallel. The reason that it takes 11 cycles to complete the flux-jumping calculations is because the values are computed for the eight channels in three ALU stages: 8 + 3 = 11 cycles. Adding 11 cycles to the 7 cycles of latency from other stages in the system results in: 11 + 7 = 18 cycles of latency from the start of a row dwell period before the first-stage feedback is applied. In rc_v5.0.c, I enforce the 18-cycle delay even when flux-jumping is not enabled to maintain uniformity across all eight channels, because flux-jumping is enabled/disabled on a per-channel basis. In other words, if I hadn't enforced the 18-cycle delay, some channels could have their feedback applied after 7 cycles, while others could have it applied after 18 cycles. I wasn't a fan of this non-uniformity. I realize that 18 cycles is a long time. In fact, so is 7. In the last few months, we have been discussing how to reduce these times to 1 cycle, because every experiment out there wants to multiplex as fast as possible, and the 7/18-delay is a rate limiting step.
** The flux-jumping code was re-arranged in the flux-jumping block to reflect the flow of data through the pipeline and make it easier to understand.

* '''Details:'''

* '''Bugs:'''
** flux-jump does not work when jumping to negative values.

* '''FPGA Resource Usage''' (readout_card.fit.rpt): [[rc_5.0.b_fit_rpt]]
; Total logic elements ; 26,745 / 41,250 ( 65 % ) ;
; Total pins ; 358 / 616 ( 58 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;
; DSP block 9-bit elements ; 76 / 112 ( 68 % ) ;
; Total PLLs ; 1 / 6 ( 17 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;
* '''FPGA Timing Analysis''' (readout_card.tan.rpt): [[rc_5.0.b_tan_rpt]]

= Revision 5.0.a =
* '''Filename:'''
** rc_v0500000a_12mar2010.sof

* '''Features:'''
** Based on the merger of rev. 5.0.8 and 5.0.9.
** '''integral_clamp''' command is added where a clamp value is set for the integral term and once the integral term hits that value, the integral-term is clamped to that value and p-term and d-term are clamped to zero. When integral_term=0 then no clamping is in effect, similar to previous releases of firmware.
** The low pass filter has 20-bit input and f_3dB/f_samp = 122Hz/15kHz .
** The flux-jump clamping that was removed in 5.0.9 is included once again here, as we decided this is safer for now.

* '''Details:'''
** "lock_dat_left" parameter that was removed in 5.0.9 is now implemented as "lock_dat_lsb"

* '''Bugs:'''
** flx_lp_init does not reinitialize the flux-jump block

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis
** tag name: rc_v0500000a_12mar2009! years were mixed up!

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
* '''FPGA Timing Analysis''' (readout_card.tan.rpt):

== Revision 5.0.9 (buggy) ==
* '''Filename:'''
** rc_v05000009_13nov2009.sof

* '''Features:'''
** Based on rev. 5.0.4
** Removes a sticky bit in pid calculation result storage -- in fsfb_processor.
** Adds a command to clamp the growth of the I-term to prevent wrapping and track down the source of Caltech's FSFB jumps.
** Removed the unused lock_dat_left parameter. The ability to shift left was moved to the fsfb_corr block some time ago.
** Fixed a sign extension bug acting on the flux quanta, which limited the value to 8191. Changed the extension from signed to unsigned.
** Removed ineffective clamping in the flux-jump calculation block.
** IMPORTANT: Must be used in conjunction with firmware rev. 5.0.0+ of all other cards.

* '''Details:'''

* '''Bugs:'''
** integral_clamp read/write command does not work.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 27,960 / 41,250 ( 68 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.825 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.878 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 14.397 ns ;

== Revision 5.0.8 (UBC only) ==
* '''Filename:'''
** rc_v05000008_09oct2009.sof

* '''Features:'''
** Based on rev. 5.0.4
** type 1 low-pass filter: f3dB=122Hz for fsample=15kHz
** Filter-input-width changed from 18b to 20b with no sticky bits!
** removed sticky bits in internal arithmetic of the filter.

= Revision 5.0.7 (type-2 filter) =
* '''Filename:'''
** rc_v05000007_09oct2009.sof

* '''Features:'''
** Based on rev. 5.0.4
** type-2 low-pass-filter: f3dB=75Hz for fsample=30000.
** Filter-input-width changed from 18b to 20b with no sticky bits!
** inter-biquad-gain-scaling for the filter is 2^14
** filter results are scaled down by 2^3 in the output of the filter.
** removed sticky bits in internal arithmetics
** _correction_ disabled in fsfb_proc_pidz

* '''Details:'''
** quartus.ini file was '''not''' present in synth directory.

* '''Bugs:'''
** none to report

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
== Revision 5.0.6 (UBC only) ==
* '''Filename:'''
** rc_stratix3_v05000006_15sep2009.sof

* '''Features:'''
** Only Valid for Rev. C/D Cards
** Based on rev. 5.0.3
** tcl file updated for Rev. D and aligned with top-level and qsf (project file).
** flux loop commented, just to try sampling the ADC.
** compiled with Q9.1

== Revision 5.0.5 (UBC only) ==
* '''Filename:'''
** rc_v05000005_04sep2009.sof

* '''Features:'''
** Based on rev. 5.0.2
** changed the low-pass-filter to f(3db)=75Hz for f(sample)=30000.

* '''Details:'''
** quartus.ini file was '''not''' present in synth directory.

* '''Bugs:'''
** negative inputs to the filter cause filter to have a non-flat pass-band region. may have to do with sign-handling...

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
* '''FPGA Timing Analysis''' (readout_card.tan.rpt):

= Revision 5.0.4 =
* '''Filename:'''
** rc_v05000004_28aug2009.sof

* '''Features:'''
** Based on rev. 5.0.2
** BUG Fix: handles 14-bit flux quanta (changed the multiplier to unsigned)
** BUG Fix: changed standard logic vector extension from signed to unsigned in flux-jumping slave.
** IMPORTANT: Must be used in conjunction with firmware rev. 5.0.0+ of all other cards.

* '''Details:'''

* '''Bugs:'''
** None so far.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,170 / 41,250 ( 63 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.541 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.612 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 15.398 ns ;

= Revision 5.0.3 =
* '''Filename:'''
** rc_stratix3_v05000003_21aug2009.sof

* '''Features:'''
** ONLY valid REV C/D RC Cards
** Based on rev. 5.0.2
** flux loop commented, just to try sampling the ADC.
** updated tcl file, but still need to rely on project file as well as qsf file.
** changed default level of adc_sclk to '1'
** dac_clr_n was changed from an output to an input.
** added 'locked' interface to rc_pll_stratix_iii
** renamed the adc_pll clock signals to more explanitory names
** added the FPGA_DEVICE_FAMILY generic to the dispatch interace for synthesis of the dc_fifo in lvds_rx
** uncommented DDR interface to force the syntesizer to use correct left and right PLLs (in conjunction with ADC and DDR PLLs)
** added test signals to test_status to see clocks on the scope.
== Revision 5.0.2 (buggy) ==
* '''Filename:'''
** rc_v05000002_test00_tagged.sof

* '''Features:'''
** Based on rev. 5.0.1
** Fixed a bug in wbs_frame_data that stored data incorrectly if reporting 1 or 2 pixels only.
** IMPORTANT: Must be used in conjunction with firmware rev. 5.0.0+ of all other cards.

* '''Details:'''

* '''Bugs:'''
** None so far.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,186 / 41,250 ( 63 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.755 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.979 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.067 ns ;

== Revision 5.0.1 (buggy) (Filter + Raw + Rectangle, 2 LVDS) ==
* '''Filename:'''
** rc_v05000001_26may2009.sof

* '''Features:'''
** Combines features in rev. 5.0.0 (2 LVDS Lines) and rev. 4.0.e (Filtered + Raw), with the NEW rectangle mode.
** IMPORTANT: Must be used in conjunction with firmware rev. 5.0.0+ of all other cards.

* '''Details:'''
** [[CVS Diff Between sys_v05000000 and rc_v05000001]]

* '''Bugs:'''
** Has a bug in wbs_frame_data that stored data incorrectly if reporting 1 or 2 pixels only.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,565 / 41,250 ( 64 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.656 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.861 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 14.167 ns ;

== Revision 5.0.0 (Filter Only, 2 LVDS) ==
* '''Filename:'''
** rc_v05000000_22dec2008.sof (tagged as sys_v05000000_22dec2008)

* '''Features:'''
** IMPORTANT: Must be used in conjunction with firmware v05000000+ of all other cards!!!
** Adds the ability to read out one column of data continuously from readout cards
** Adds data mode 11, which is an engineering mode. Data points are 32-bits, and bits [9..3]=row_index, [2..0]=column_index. This mode is useful for determining which pixels one is reading out in the array, in column mode for example.

* '''Details:'''
** [[CVS Diff Between rc_v0400000c and sys_v05000000]]

* '''Bugs:'''
** None so far.

* '''Synthesis Notes:'''
** The quartus.ini file was not present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,607 / 41,250 ( 65 % ) ;
; Total memory bits ; 406,016 / 3,423,744 ( 12 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.558 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.892 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.987 ns ;

== Revision 4.0.f (Filter + Raw, 1 LVDS) ==
* '''Filename:'''
** rc_v0400000f_12feb2010.sof

* '''Features:'''
** Based on 4.0.e and in parallel with 5.0.9 (equivalent version, clamping is not included)
** Incorporates fixes that were done to flux-jumping between 5.0.2 - 5.0.4 - 5.0.9. Namely:
*** Changes a multiplier from signed to unsigned (in fsfb_corr_multplier.vhd).
*** Changes sign extension from signed to unsigned (in flux_quanta_ram_admin.vhd).

* '''Details:'''

* '''Bugs:'''
** None reported yet.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,773 / 41,250 ( 65 % ) ;
; Total memory bits ; 1,321,984 / 3,423,744 ( 39 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.539 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 4.118 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 17.318 ns ;

== Revision 4.0.e (Filter + Raw, 1 LVDS) ==
* '''Filename:'''
** rc_v0400000e_27apr2009.sof

* '''Features:'''
** Based on 4.0.d
** Combines both raw- and filtered-data modes.
** fpga_temp, card_temp, card_id commands are disabled.
** Tested by Matt Hasselfield.

* '''Details:'''

* '''Bugs:'''
** fpga_temp, card_temp, card_id commands are disabled.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 27,048 / 41,250 ( 66 % ) ;
; Total memory bits ; 1,321,984 / 3,423,744 ( 39 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.675 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.907 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.728 ns ;

== Revision 4.0.d (Raw Only, 1 LVDS) ==
* '''Filename:''' rc_v0400000d_20090417.sof

* '''Features:'''
** Based on v4.0.c, but has the filter removed, and implements a single 65536-index RAM block for storing 50 MHz raw-data samples.
** The firmware takes a new command called readout_col_index which specifies which column to capture raw data from.
** Other than readout_col_index, the firmware functions the same as previous raw-data firmware, including then need to issue a capture_raw command.
** For more information on raw-data, see: http://e-mode.phas.ubc.ca/mcewiki/index.php/Raw-mode_readout
** This firmware also integrates some of the improvements that were implemented in 4.4.0, like the removal of the tga_o signal from an FSM in dispatch_wishbone.vhd.

* '''Details:'''
** Differences between 4.0.c and 4.0.d
U system/test/source/tb/tb_cc_rcs_bcs_ac.vhd
U all_cards/dispatch/source/rtl/dispatch_wishbone.vhd
U library/sys_param/source/rtl/wishbone_pack.vhd
U readout_card/adc_sample_coadd/source/rtl/adc_sample_coadd.vhd
U readout_card/adc_sample_coadd/source/rtl/adc_sample_coadd_pack.vhd
U readout_card/flux_loop/source/rtl/flux_loop.vhd
U readout_card/flux_loop/source/rtl/flux_loop_pack.vhd
U readout_card/flux_loop_ctrl/source/rtl/flux_loop_ctrl.vhd
U readout_card/flux_loop_ctrl/source/rtl/flux_loop_ctrl_pack.vhd
U readout_card/flux_loop_ctrl/source/tb/tb1_flux_loop_ctrl.vhd
U readout_card/flux_loop_ctrl/source/tb/tb2_flux_loop_ctrl.vhd
U readout_card/fsfb_calc/source/rtl/fsfb_fltr_regs.vhd
U readout_card/fsfb_corr/source/rtl/fsfb_corr.vhd
U readout_card/readout_card/source/rtl/readout_card.vhd
U readout_card/readout_card/source/rtl/readout_card_pack.vhd
U readout_card/wbs_frame_data/source/rtl/wbs_frame_data.vhd
U readout_card/wbs_frame_data/source/rtl/wbs_frame_data_pack.vhd

* '''Bugs:'''
** None so far.
** fpga_temp, card_temp, card_id commands are not supported.

* '''Synthesis Notes:'''
** The quartus.ini file was present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 24,554 / 41,250 ( 60 % ) ;
; Total memory bits ; 1,262,592 / 3,423,744 ( 37 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.991 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.864 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 17.052 ns ;

== Revision 4.4.1 ==
* '''Filename:''' rc_v04040001_21nov2008

* '''Features:'''
** Fixes a bug that froze up the firmware if any of the following commands were issued: CARD_ID_ADDR, CARD_TEMP_ADDR, FPGA_TEMP_ADDR in 4.4.0 only.

* '''Details:'''
** The bug fix include adding more logic to the wishbone ack path (readout_card.vhd), which subsequently decreased the minimum clock setup time to 1.588ns. The new logic will catch errors that the old logic wouldn't have, and is now consistent with the firmware on all the other cards. However, if timing becomes an issue, the logic may have to revert back to that which was in version 4.0.c.

* '''Bugs:'''
** None so far.

* '''Synthesis Notes:'''
** The quartus.ini file was not present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 27,241 / 41,250 ( 66 % ) ;
; Total memory bits ; 405,504 / 3,423,744 ( 12 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.588 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.585 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 17.057 ns ;

== Revision 4.4.0 (buggy) ==
* '''Filename:''' rc_v04040000_02oct2008
* '''Features:'''
** Reinstated the data modes in wbs_frame_data.vhd that were removed in 4.0.c. This firmware has the following modes: '''0, 1, 2, 4, 5, 7, 10'''. The modes that are not present are: '''3''' (raw data), '''6''' (replaced by data_mode = 7), '''8''' (replaced by data_mode = 10), '''9''' (replaced by data_mode = 10). For more information on data modes, see [[Data mode]].
** Re-integrated the id_thermo and fpga_thermo block in the readout_card.vhd top level that was removed in 4.0.c.
** Removed the sticky bit in fsfb_corr.vhd, which was enabled when flux-jumping was turned on. Because the feedback is signed, the sticky bit would usually reflect the value of the 14th bit, except in situations when the number of flux quanta to jump was greater than 1 (i.e. cosmic rays, IV-curves, etc). Flux jumps are made at a maximum rate of one per frame period, so that if the First-Stage Feedback increased past the 13th bit, it would not be reflected in the feedback applied. Now it is.
* '''Details:'''
** Simplified the FSM logic in wbs_frame_data.vhd that determines when to transition from IDLE to WSS1. This was done to lower the number of gates in that path, and ease the timing.
** Removed the z_dat_i port in fsfb_processor.vhd and fsfb_calc_pack.vhd to the fsfb_proc_pidz block, in an effort to make it clearer within that block that the z-term is always = 0.
** Removed the z-term sign extension in fsfb_proc_pidz.vhd, and the [d-term + z-term] adder to free up DSP resources since the z-term is always = 0.
** Adjusted the indentation in fsfb_io_controller.vhd to make the file more readable.
** Moved the tga_o signal out of the dispatch_wishbone.vhd FSM, and made it a continuous assignment. This signal had one of the highest fan-out counts in the RTL design, and actually was impossible to route in Stratix III chips in its previous configuration because of the number of gates on the fan-out. As a consequence of making it a continuous assignment, the Stratix III fitter was able to succeed, and the Stratix I timing characteristics were greatly improved. This is the most significant change in this revision. This change single-handedly increased the minimum slack from 1.282 ns in v0400000c to 2.372 ns (or 56.7 MHz max) in this revision.
* '''Bugs:'''
** The following commands lock up the Readout Card firmware: CARD_ID_ADDR, CARD_TEMP_ADDR, FPGA_TEMP_ADDR.
** fb_const0 commands to channel 0 do not work. The value is stored in the register, but not applied to the DAC. Thus, read-back returns the correct value, but the DAC does not
* '''Synthesis Notes:'''
** The quartus.ini file was not present in the synth directory during synthesis.
* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 27,099 / 41,250 ( 66 % ) ;
; Total memory bits ; 406,016 / 3,423,744 ( 12 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.372 ns ;
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 4.052 ns ;
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.066 ns ;

== Revision 4.0.c ==
* '''Filename:''' rc_v0400000c_15aug2008.sof
* '''Features:'''
** Only has data modes 0, 1, 4, and 10.
** Fixed the bug that exists in 4.0.b, 4.0.a, and 4.0.9 that prevented the fb_const value from being applied to channel zero (wbs_fb_data.vhd).
* '''Details:'''
** Changed a counter in the dispatch block to ease timing constraints in synthesis (dispatch_wishbone.vhd)
** Updated the tagged versions of dispatch.vhd , dispatch_cmd_receive.vhd, and dispatch_reply_transmit.vhd to the version that is used by all the other cards.
** '''Removed''' the fpga_termo (command: '''fpga_temp''') and id_thermo (commands: '''card_temp, card_id''') to ease timing constraints in synthesis (readout_card.vhd)
** Updated the tagged version of fpga_termo.vhd to include the new 'stale bit' feature
** Updated the tagged version of frame_timing_core.vhd to include the new 'err_o' interface
* '''Bugs:'''
** None reported yet
* '''Synthesis Notes:'''
** The quartus.ini file was not present in the synth directory during synthesis.
* '''FPGA Resource Usage:'''
Total logic elements : 25,058 / 41,250 ( 61 % )
Total memory bits : 400,896 / 3,423,744 ( 12 % )

* '''Timing Analysis''' (readout_card.tan.rpt):
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.282 ns ;
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.736 ns ;
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.665 ns ;

== Revision 4.0.b (buggy) ==
Note: This revision is on a watch list, after the bug detected 15 July 2008. See the bug section for more details.
* '''Filename''' : rc_v0400000b_04aug2008.sof
* '''Features'''
** data_mode 10 is added to provide more filtfb bits (compared to data mode 9) for planet observations. filtered_dat(27 downto 3) & flux_cnt_dat(6 downto 0)

* '''Bugs'''
** An unexplained bug that appeared in 4.0.a and may still be present in 4.0.b is a problem with the readout of channels being clipped out of data reporting. [[Bug 1 Notes]]

* ''' Synthesis note '''
** Quartus.ini removed.

== Revision 4.0.a (buggy) ==
Note: This revision is on a watch list, after the bug detected 15 July 2008. See the bug section for more details.
* '''Filename''' : rc_v0400000a_07jul2008.sof
* '''Bug Fix'''
** mce_status and adc_offset/flx_quanta commands do not fail after power up.
* ''' Synthesis note '''
** Quartus.ini removed.

* '''Bugs'''
** Seems to clip out channel 0 from data reporting.

== Revision 4.0.9 (buggy) ==
* '''Filename''' : rc_v04000009_26jun2008.sof
* '''Features'''
** sa_bias and offset DACs only refreshed when new values are written. (in previous versions, DACs were refreshed every frame)
* '''Bugs'''
** fb_const0 commands to channel 0 do not work. The value is stored in the register, but not applied to the DAC. Thus, read-back returns the correct value, but the DAC does not.
** reading flx_quanta and adc_offset right after power up hangs the reply datapath to CC. resetmce clears this error as temporary solution. the problem is caused by first read ack of the wishbone slave.

== Revision 4.0.8 ==
* '''Filename''' : rc_v04000008_26jun2008.sof
* '''Features'''
** The gaini, gainp, gaind resolution increased to 12-bit, i.e. -2048 to 2047 (formerly 10-bit).

* '''Bug fix'''
** the bug associated with gainpid read before mce_reset is fixed.

* ''' Synthesis note '''
** Quartus.ini removed.

== Revision 4.3.7 ==
* '''Filename''' : rc_v04030007_26may2008_raw.sof
* '''Features'''
** 14-bit raw mode enabled to buffer a snapshot of 50MHz samples for 2 frames of row_len * num_rows samples.
** In order to extend the raw-mode to 14-bit, an assumption is made that the raw buffer is not written to while being read. Therefore, make sure there is at least 2*row_len*num_rows*20ns between issuing captr_raw command and reading back the raw data.
** In order to save RAM for raw mode, two memory-intensive features are disabled:
*** low-pass filter disabled ( mixed filtfb data modes 6, 7, 9 are also disabled)
*** PID (gainp0, gaini0, gaind0) readback disabled. one can still set PID values and run servo, but can not read back the values.

== Revision 4.2.7 ==
* '''Filename''' : rc_v04020007_24may2008_raw.sof
* '''Features'''
** raw mode enabled to buffer a snapshot of 50MHz samples for 2 frames of row_len * num_rows samples.
** In order to save RAM for raw mode, two memory-intensive features are disabled:
*** low-pass filter disabled ( mixed filtfb data modes 6, 7, 9 are also disabled)
*** PID (gainp0, gaini0, gaind0) readback disabled. one can still set PID values and run servo, but can not read back the values.
* '''Bug fix'''
** the bug associated with reading from raw-buffer is fixed.

== Revision 4.1.7 ==
* '''Filename''' : rc_v04010007_25apr2008_raw.sof
* '''Features'''
** raw mode enabled to buffer a snapshot of 50MHz samples for 2 frames of row_len * num_rows samples.
** In order to save RAM for raw mode, two memory-intensive features are disabled:
*** low-pass filter disabled ( mixed filtfb data modes 6, 7, 9 are also disabled)
*** PID (gainp0, gaini0, gaind0) readback disabled. one can still set PID values and run servo, but can not read back the values.
* '''Bugs'''
** after each readout frame, raw-buffer readout counter falls behind by 3 and this causes skipping 3 50MHz samples in the data stream and column-data being messed up in subsequent frames. Data can be rearranged by post processing.

== Revision 4.0.6 (buggy) ==
* '''Filename''' : rc_v04000006_15feb2008.sof or .pof
* '''Features'''
** '''bugfix''': unreliable reset due to unsafe and incomplete state machines is fixed.
** '''bugfix''': flux_jump sign problem fixed, so far proved in const_mode, to be tested in servo_mode with cold setup.
** servo_mode=2 or ramp previously only went from 0 to ramp_amp, but now goes from -8192 to -8192+ramp_amp
** new commands are added: ''scratch'' and ''card_type''. Scratch takes 8 values and can be used by software to detect reset.
** slot_id and fw_rev are now integrated as part of all_cards.vhd
** lvds_tx_b=0, This will allow Clock Card to use the secondary backplane lvds line and check whether RC is plugged in.
** filter_coeff in misc_banks_admin commented as it is not implemented and causes timing problems.

* '''Bugs'''
** reading gainp/gaini/gaind right after power up hangs the reply datapath to CC. resetmce clears this error as temporary solution. the problem is caused by first read ack of pid_ram_admin.
** slot_id is only set after a resetmce is issued. (using the latest all_cards in the next revision will fix this)
** has spurious spikes on channel 7 data, which max out the integral, and cause the detectors to come unlocked. This firmware officially meets timing requirements, but the bug could be due to marginal timing on the longest data paths, i.e. ~0.1 ns in some cases.

== Revision 4.0.5 ==
* '''Filename''' : rc_v04000005_01nov2007.sof or .pof
* '''Features'''
** data mode 9 (mixed filt + flux jump) with windowing readjusted compared to data mode 8

* '''Bugs'''
** unreliable resetmce. Sometimes, firmware waked up non-responsive on lvds lines.
** In data mode 5 and 9, flux-jump counter is not reported properly due to a sign error. However, flux jumping works fine.

== Revision 3.0.19 ==
* '''Filename''' : rc_v03000019_16feb2007_raw.sof (no pof as one is not likely to run with this as regular firmware)
* '''Features'''
** data mode 3 is enabled.
** filter is disabled as a compromise to fit the raw-mode buffer.

* '''Bugs'''
** unreliable resetmce. Sometimes, firmware waked up non-responsive on lvds lines.

== Old Firmware Revisions ==
* '''4.0.4''': rc_v04000004_11oct2007.sof data mode 8 added (mixed filt + flux jump)
* '''4.0.3''': rc_v04000003_19sep2007.sof data mode 7 bit split readjusted to 10b error being bit 4 to 14
* '''4.0.2''': rc_v04000002_11sep2007.sof pid resolution increased to 10b, data mode 7 added
* '''4.0.1''': rc_v04000001_06sep2007.sof
* '''4.0.0''': rc_v04000000_29aug2007.sof supports readout_row_index * [[ bugs ]]

= To-Do List =
* the starting point for the servo is currently zero and it would be nice to have it programmable.

= RC Synthesis Notes =
# The following note applies when using Quartus versions earlier than Q7: Quartus.ini file had to exist in synth directory up to revision 4.0.a due to a bug that started in Quartus 6.1 and would synthesize away arbitrary parts of readout card. We contacted Altera at the time and they provided us the ini file.
# Timing: There is no "lock region" defined for readout card. Timing on readout card is tight and since version 3 or so any new feature would initially fail timing till some synthesis options were tweaked. One path that remains to be consistently marginal is from addr_gen counter (i.e. tga_o counter) in dispatch_wishbone.vhd to wishbone slaves particularly misc_banks_admin.vhd. Modules that are rewritten to address timing concerns are fsfb_corr, all_cards, misc_banks_admin, and finally instantiating an lpm counter instead of a counter from components library. Surprisingly, the lpm counter reduced 87 failures to 37, although looking at the technology map viewer, it seemed that they were both synthesized the same.
# Compile time: This was at some point 4.5 hours, after going to dual core PC, this was reduced to 35 minutes. After extending pid gains to 12b and fixing offset/sa_bias update code, the compile time increased to 1.5hr again with utilization up to ~70%.
# wbs_fb_storage, ram_8x64, pid_ram had to be regenerated using latest (Q7.2) MegaWizard to get rid of the bug associated with failure to read after power up until a reset was issued.
# During simulations, the initialization of RAM block with .hex files needs to be disabled. This is done by commenting out the following lines from the MegaWizard generated Megafunction files (remember to un-comment them before synthesizing the code):
lpm_file => "C:/scuba2_repository/cards/readout_card/fsfb_calc/source/rtl/ram_40x64.hex", and
lpm_file : STRING;
#Starting Q10.0 use TimeQuest timing analyzer as oppose to the classic one. The classic one is being phased out by Altera. In order to use TimeQuest, you need to have an sdc file present in your project directory.
----
[http://e-mode.phas.ubc.ca/mcewiki/index.php/Main_Page MCE Main Page]

Readout Card firmware

2011-05-04T21:33:47Z

Bburger: /* Revision 5.1.2 */

* Synthesis Reminders (for firmware developers)
** quartus.ini is not needed anymore (Fixed as of Q7, Altera SR10783580 2010-10-24)
** Remember that readout_card/fsfb_clac/source/rtl/ram_40x64.vhd must be initialized with the ram_40x64.hex file in the same directory.
== Revision 5.1.2 ==
* '''Filename:'''
** rc_stratix3_v05010002_18jan2011.sof (for Rev. E cards)
** rc_stratix3_v05010002_18jan2011.jic (for Rev. E cards)
** rc_v05010002_03feb2011.sof (for Rev. B cards)
** rc_v05010002_03feb2011.pof (for Rev. B cards)

* '''Features:'''
** based on 5.1.1 with k1 and k2 (filter params) limited to k1<16 and k2<32 in order to resolve the timing when compiling for smaller Stratix FPGA on RC Rev. B.

* '''Bug fix:'''
** the 2-rows-off filtered data readout introduced with configurable filter in rev. 5.1.0 and 5.1.1 is fixed now.

* '''Bugs:'''
** none so far.

* '''FPGA Resource Usage''' (readout_card.fit.rpt)
; Total logic elements ; 33,285 / 41,250 ( 81 % ) ;
; Total pins ; 358 / 616 ( 58 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt)
; Fast Model Clock Hold: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 0.364 ns
; Fast Model Clock Hold: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 0.365 ns
; Fast Model Clock Hold: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 0.379 ns

== Revision 5.1.1 (not recommended) ==
* '''Filename:'''
** rc_v05010001_01dec2010.sof (for Rev. B cards)

* '''Features:'''
** based on 5.1.0, but k1 and k2 (filter params) are now limited to k1<16 and k2<32 in order to resolve the timing failures of compiling 5.1.0 for smaller Stratix FPGA on RC Rev. B.

* '''Bugs:'''
** filter mode data is off by 2 rows.

== Revision 5.1.0 (not recommended) ==
* '''Filename:'''
** rc_stratix3_v05010000_01nov2010.sof (for Rev. E cards)
** rc_v05010000_01nov2010.sof (for Rev. B cards) has timing failures '''do not use!!!'''

* '''Features:'''
** added configurable filter parameters specified by ''fltr_coeff'', default is the fcutoff/fsampl=122Hz/15kHz. see [[ Digital 4-pole Butterworth Low-pass filter ]].
** ''fltr_type'' is set to 255 to indicate configurable filter parameters.
** see [http://www.phas.ubc.ca/~mce/mcedocs/software/SC2_ELE_S580_515_mce_command_description.pdf MCE command description]
** development notes:
*** It is built on Quartus10.1.
*** tcl files had to be updated as cmp syntax is not supported in Q10 anymore.
*** Rev. E cards now can be identified by reading back pcb_rev as part of card_type, therefore both stratix I and III sof/pof/jic are generated from the same source.

* '''Bugs:'''
** rc_v05010000_01nov2010.sof has timing failures that were overlooked, do not use this firmware for Rev.B cards.
** '''filter mode data is off by 2 rows.'''

* '''FPGA Resource Usage and Timing Report''' (readout_card.fit.rpt and readout_card.tan.rpt): logic usage is upto 85% from 66% in 5.0.d/e/f

= Revision 5.0.f =
* '''Filename:'''
** rc_v0500000f_22oct2010.sof (for Rev. B cards)
** rc_stratix3_v0500000f_22oct2010.sof (for Rev. E cards)

* '''Features:'''
** Bugfix: integral clamp should work now. only positive integral_clamp values are valid!

* '''Details:''': SQ1FB is applied 18 clock cycles after start of a row visit (SQ1_Bias being applied) regardless of flux-jump being enabled or not. In pre-5.0.b firmware SQ1FB was being applied after 7 clock cycles when flux-jump was disabled and after 18 clock cycles when flux-jump was enabled.
** available for both Rev. E and Rev. B cards, the upper byte of card_type parameter now reports the pcb revision.
** development note: It is built on Quartus10.1.

* '''Bugs:'''
**none yet!

* '''FPGA Resource Usage and Timing Report''' (readout_card.fit.rpt and readout_card.tan.rpt): no change compared to 5.0.a/b/c/d

== Revision 5.0.e (not recommended) ==
* '''Filename:'''
** rc_v0500000e_06oct2010.sof

* '''Details:'''
** an unsuccessful attempt to fix integral_clamp, but changed the functionality so that it clamps at the value, but it doesn't hold the clamp. i.e., if the calculated sq1fb becomes less than the specified clamp value, the sq1fb is not clamped anymore. This is not a desired functionality!

= Revision 5.0.d =
* '''Filename:'''
** rc_v0500000d_04aug2010.sof

* '''Features:'''
** Bugfix: To fix the bug associated with negative flux-jumps, reverted to signed multiplier and hence, incremented the width of the flux-quanta multiplier input by 1.

* '''Details:''': SQ1FB is applied 18 clock cycles after start of a row visit (SQ1_Bias being applied) regardless of flux-jump being enabled or not. In pre-5.0.b firmware SQ1FB was being applied after 7 clock cycles when flux-jump was disabled and after 18 clock cycles when flux-jump was enabled.

* '''Bugs:'''
** '''integral_clamping is broken'''. To test the clamping, a servo-locked ramp was initiated on the sq1fb and then flux-jumping was turned on and observed by attaching a scope to the SQ1FB output. With integral_clamp=80000000, flux_quanta=8000, gaini=1, flux-jump enabled, we see [[http://e-mode.phas.ubc.ca/mcewiki/index.php/Image:Clamp_unstable.png scope snapshot]] used slow_fb_ramp.py script for testing.

* '''FPGA Resource Usage and Timing Report''' (readout_card.fit.rpt and readout_card.tan.rpt): no change compared to 5.0.a/b/c

== Revision 5.0.c (not recommended) ==
* '''Filename:'''
** rc_v0500000c_16jun2010.sof

* '''Features:'''
** Based on rev. 5.0.b
** Re-introduced flux-jump counter clamping to maintain continuity in behavior from past versions of firmware in the field.
** '''Important''': SQ1FB is applied 18 clock cycles after start of a row visit (SQ1_Bias being applied) regardless of flux-jump being enabled or not. In pre-5.0.b firmware SQ1FB was being applied after 7 clock cycles when flux-jump was disabled and after 18 clock cycles when flux-jump was enabled.

* '''Details:'''
* '''Bugs:'''
** '''flux-jump is broken'''. flux-jumping block misbehaves at the first jump in the negative range.

* '''FPGA Resource Usage''' (readout_card.fit.rpt): [[rc_5.0.c_fit_rpt]]
; Total logic elements ; 26,800 / 41,250 ( 65 % ) ;
; Total pins ; 358 / 616 ( 58 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;
; DSP block 9-bit elements ; 76 / 112 ( 68 % ) ;
; Total PLLs ; 1 / 6 ( 17 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt): [[rc_5.0.c_tan_rpt]]
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.964 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 4.382 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 15.924 ns ;

== Revision 5.0.b (not recommended) ==
* '''Filename:'''
** rc_v0500000b_03jun2010.sof

* '''Features:'''
** Based on rev. 5.0.a
** A bug that caused jumps in first-stage feedback, and detected as spikes in the raw data of pixels that were in servo_mode=0,1,2 was fixed. The jumps in FSFB were due to flux-jumping being enabled on live pixes with non-zero flx_quanta, and being disabled on the fly on dead pixels with flx_quanta=0. Flux-jumping is now disabled on a column-by-column basis if a column is in servo_mode = 0,1,2.
** Ineffective clamping was removed from the flux-jumping block (as per 5.0.9), as it is now replaced by the clamping that was perfected in rev. 5.0.10
** A sticky bit that only affected servo_mode=0,1,2 was also removed from the flux-jumping block.
** flx_lp_init commands now also clear the flux-jumping block as well.
** The 11-clock-cycle delay (in applying SQ1_FB) that in previous firmware only occurred when flux-jumping was enabled, now (in this version) is in effect all the time. Due to the bug-fix above, flux-jumping can be disabled on a column-by-column basis by setting servo_mode=0,1,2 when en_fb_jump=1. Before the change, this meant that constant values could be applied with or without the 11-cycle delay if en_fb_jump=1 or 0. To make the delay consistent, it is now always 11 cycles. As background, the flux-jumping block is pipelined, meaning that it does calculations for all 8 channels serially. The serialization is because of DSP-block limitations in the Readout Card FPGA that prevent us from doing all 8 channels in parallel. The reason that it takes 11 cycles to complete the flux-jumping calculations is because the values are computed for the eight channels in three ALU stages: 8 + 3 = 11 cycles. Adding 11 cycles to the 7 cycles of latency from other stages in the system results in: 11 + 7 = 18 cycles of latency from the start of a row dwell period before the first-stage feedback is applied. In rc_v5.0.c, I enforce the 18-cycle delay even when flux-jumping is not enabled to maintain uniformity across all eight channels, because flux-jumping is enabled/disabled on a per-channel basis. In other words, if I hadn't enforced the 18-cycle delay, some channels could have their feedback applied after 7 cycles, while others could have it applied after 18 cycles. I wasn't a fan of this non-uniformity. I realize that 18 cycles is a long time. In fact, so is 7. In the last few months, we have been discussing how to reduce these times to 1 cycle, because every experiment out there wants to multiplex as fast as possible, and the 7/18-delay is a rate limiting step.
** The flux-jumping code was re-arranged in the flux-jumping block to reflect the flow of data through the pipeline and make it easier to understand.

* '''Details:'''

* '''Bugs:'''
** flux-jump does not work when jumping to negative values.

* '''FPGA Resource Usage''' (readout_card.fit.rpt): [[rc_5.0.b_fit_rpt]]
* '''FPGA Timing Analysis''' (readout_card.tan.rpt): [[rc_5.0.b_tan_rpt]]

= Revision 5.0.a =
* '''Filename:'''
** rc_v0500000a_12mar2010.sof

* '''Features:'''
** Based on the merger of rev. 5.0.8 and 5.0.9.
** '''integral_clamp''' command is added where a clamp value is set for the integral term and once the integral term hits that value, the integral-term is clamped to that value and p-term and d-term are clamped to zero. When integral_term=0 then no clamping is in effect, similar to previous releases of firmware.
** The low pass filter has 20-bit input and f_3dB/f_samp = 122Hz/15kHz .
** The flux-jump clamping that was removed in 5.0.9 is included once again here, as we decided this is safer for now.

* '''Details:'''
** "lock_dat_left" parameter that was removed in 5.0.9 is now implemented as "lock_dat_lsb"

* '''Bugs:'''
** flx_lp_init does not reinitialize the flux-jump block

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis
** tag name: rc_v0500000a_12mar2009! years were mixed up!

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
* '''FPGA Timing Analysis''' (readout_card.tan.rpt):

== Revision 5.0.9 (buggy) ==
* '''Filename:'''
** rc_v05000009_13nov2009.sof

* '''Features:'''
** Based on rev. 5.0.4
** Removes a sticky bit in pid calculation result storage -- in fsfb_processor.
** Adds a command to clamp the growth of the I-term to prevent wrapping and track down the source of Caltech's FSFB jumps.
** Removed the unused lock_dat_left parameter. The ability to shift left was moved to the fsfb_corr block some time ago.
** Fixed a sign extension bug acting on the flux quanta, which limited the value to 8191. Changed the extension from signed to unsigned.
** Removed ineffective clamping in the flux-jump calculation block.
** IMPORTANT: Must be used in conjunction with firmware rev. 5.0.0+ of all other cards.

* '''Details:'''

* '''Bugs:'''
** integral_clamp read/write command does not work.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 27,960 / 41,250 ( 68 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.825 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.878 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 14.397 ns ;

== Revision 5.0.8 (UBC only) ==
* '''Filename:'''
** rc_v05000008_09oct2009.sof

* '''Features:'''
** Based on rev. 5.0.4
** type 1 low-pass filter: f3dB=122Hz for fsample=15kHz
** Filter-input-width changed from 18b to 20b with no sticky bits!
** removed sticky bits in internal arithmetic of the filter.

= Revision 5.0.7 (type-2 filter) =
* '''Filename:'''
** rc_v05000007_09oct2009.sof

* '''Features:'''
** Based on rev. 5.0.4
** type-2 low-pass-filter: f3dB=75Hz for fsample=30000.
** Filter-input-width changed from 18b to 20b with no sticky bits!
** inter-biquad-gain-scaling for the filter is 2^14
** filter results are scaled down by 2^3 in the output of the filter.
** removed sticky bits in internal arithmetics
** _correction_ disabled in fsfb_proc_pidz

* '''Details:'''
** quartus.ini file was '''not''' present in synth directory.

* '''Bugs:'''
** none to report

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
== Revision 5.0.6 (UBC only) ==
* '''Filename:'''
** rc_stratix3_v05000006_15sep2009.sof

* '''Features:'''
** Only Valid for Rev. C/D Cards
** Based on rev. 5.0.3
** tcl file updated for Rev. D and aligned with top-level and qsf (project file).
** flux loop commented, just to try sampling the ADC.
** compiled with Q9.1

== Revision 5.0.5 (UBC only) ==
* '''Filename:'''
** rc_v05000005_04sep2009.sof

* '''Features:'''
** Based on rev. 5.0.2
** changed the low-pass-filter to f(3db)=75Hz for f(sample)=30000.

* '''Details:'''
** quartus.ini file was '''not''' present in synth directory.

* '''Bugs:'''
** negative inputs to the filter cause filter to have a non-flat pass-band region. may have to do with sign-handling...

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
* '''FPGA Timing Analysis''' (readout_card.tan.rpt):

= Revision 5.0.4 =
* '''Filename:'''
** rc_v05000004_28aug2009.sof

* '''Features:'''
** Based on rev. 5.0.2
** BUG Fix: handles 14-bit flux quanta (changed the multiplier to unsigned)
** BUG Fix: changed standard logic vector extension from signed to unsigned in flux-jumping slave.
** IMPORTANT: Must be used in conjunction with firmware rev. 5.0.0+ of all other cards.

* '''Details:'''

* '''Bugs:'''
** None so far.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,170 / 41,250 ( 63 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.541 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.612 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 15.398 ns ;

= Revision 5.0.3 =
* '''Filename:'''
** rc_stratix3_v05000003_21aug2009.sof

* '''Features:'''
** ONLY valid REV C/D RC Cards
** Based on rev. 5.0.2
** flux loop commented, just to try sampling the ADC.
** updated tcl file, but still need to rely on project file as well as qsf file.
** changed default level of adc_sclk to '1'
** dac_clr_n was changed from an output to an input.
** added 'locked' interface to rc_pll_stratix_iii
** renamed the adc_pll clock signals to more explanitory names
** added the FPGA_DEVICE_FAMILY generic to the dispatch interace for synthesis of the dc_fifo in lvds_rx
** uncommented DDR interface to force the syntesizer to use correct left and right PLLs (in conjunction with ADC and DDR PLLs)
** added test signals to test_status to see clocks on the scope.
== Revision 5.0.2 (buggy) ==
* '''Filename:'''
** rc_v05000002_test00_tagged.sof

* '''Features:'''
** Based on rev. 5.0.1
** Fixed a bug in wbs_frame_data that stored data incorrectly if reporting 1 or 2 pixels only.
** IMPORTANT: Must be used in conjunction with firmware rev. 5.0.0+ of all other cards.

* '''Details:'''

* '''Bugs:'''
** None so far.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,186 / 41,250 ( 63 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.755 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.979 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.067 ns ;

== Revision 5.0.1 (buggy) (Filter + Raw + Rectangle, 2 LVDS) ==
* '''Filename:'''
** rc_v05000001_26may2009.sof

* '''Features:'''
** Combines features in rev. 5.0.0 (2 LVDS Lines) and rev. 4.0.e (Filtered + Raw), with the NEW rectangle mode.
** IMPORTANT: Must be used in conjunction with firmware rev. 5.0.0+ of all other cards.

* '''Details:'''
** [[CVS Diff Between sys_v05000000 and rc_v05000001]]

* '''Bugs:'''
** Has a bug in wbs_frame_data that stored data incorrectly if reporting 1 or 2 pixels only.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,565 / 41,250 ( 64 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.656 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.861 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 14.167 ns ;

== Revision 5.0.0 (Filter Only, 2 LVDS) ==
* '''Filename:'''
** rc_v05000000_22dec2008.sof (tagged as sys_v05000000_22dec2008)

* '''Features:'''
** IMPORTANT: Must be used in conjunction with firmware v05000000+ of all other cards!!!
** Adds the ability to read out one column of data continuously from readout cards
** Adds data mode 11, which is an engineering mode. Data points are 32-bits, and bits [9..3]=row_index, [2..0]=column_index. This mode is useful for determining which pixels one is reading out in the array, in column mode for example.

* '''Details:'''
** [[CVS Diff Between rc_v0400000c and sys_v05000000]]

* '''Bugs:'''
** None so far.

* '''Synthesis Notes:'''
** The quartus.ini file was not present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,607 / 41,250 ( 65 % ) ;
; Total memory bits ; 406,016 / 3,423,744 ( 12 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.558 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.892 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.987 ns ;

== Revision 4.0.f (Filter + Raw, 1 LVDS) ==
* '''Filename:'''
** rc_v0400000f_12feb2010.sof

* '''Features:'''
** Based on 4.0.e and in parallel with 5.0.9 (equivalent version, clamping is not included)
** Incorporates fixes that were done to flux-jumping between 5.0.2 - 5.0.4 - 5.0.9. Namely:
*** Changes a multiplier from signed to unsigned (in fsfb_corr_multplier.vhd).
*** Changes sign extension from signed to unsigned (in flux_quanta_ram_admin.vhd).

* '''Details:'''

* '''Bugs:'''
** None reported yet.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,773 / 41,250 ( 65 % ) ;
; Total memory bits ; 1,321,984 / 3,423,744 ( 39 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.539 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 4.118 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 17.318 ns ;

== Revision 4.0.e (Filter + Raw, 1 LVDS) ==
* '''Filename:'''
** rc_v0400000e_27apr2009.sof

* '''Features:'''
** Based on 4.0.d
** Combines both raw- and filtered-data modes.
** fpga_temp, card_temp, card_id commands are disabled.
** Tested by Matt Hasselfield.

* '''Details:'''

* '''Bugs:'''
** fpga_temp, card_temp, card_id commands are disabled.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 27,048 / 41,250 ( 66 % ) ;
; Total memory bits ; 1,321,984 / 3,423,744 ( 39 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.675 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.907 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.728 ns ;

== Revision 4.0.d (Raw Only, 1 LVDS) ==
* '''Filename:''' rc_v0400000d_20090417.sof

* '''Features:'''
** Based on v4.0.c, but has the filter removed, and implements a single 65536-index RAM block for storing 50 MHz raw-data samples.
** The firmware takes a new command called readout_col_index which specifies which column to capture raw data from.
** Other than readout_col_index, the firmware functions the same as previous raw-data firmware, including then need to issue a capture_raw command.
** For more information on raw-data, see: http://e-mode.phas.ubc.ca/mcewiki/index.php/Raw-mode_readout
** This firmware also integrates some of the improvements that were implemented in 4.4.0, like the removal of the tga_o signal from an FSM in dispatch_wishbone.vhd.

* '''Details:'''
** Differences between 4.0.c and 4.0.d
U system/test/source/tb/tb_cc_rcs_bcs_ac.vhd
U all_cards/dispatch/source/rtl/dispatch_wishbone.vhd
U library/sys_param/source/rtl/wishbone_pack.vhd
U readout_card/adc_sample_coadd/source/rtl/adc_sample_coadd.vhd
U readout_card/adc_sample_coadd/source/rtl/adc_sample_coadd_pack.vhd
U readout_card/flux_loop/source/rtl/flux_loop.vhd
U readout_card/flux_loop/source/rtl/flux_loop_pack.vhd
U readout_card/flux_loop_ctrl/source/rtl/flux_loop_ctrl.vhd
U readout_card/flux_loop_ctrl/source/rtl/flux_loop_ctrl_pack.vhd
U readout_card/flux_loop_ctrl/source/tb/tb1_flux_loop_ctrl.vhd
U readout_card/flux_loop_ctrl/source/tb/tb2_flux_loop_ctrl.vhd
U readout_card/fsfb_calc/source/rtl/fsfb_fltr_regs.vhd
U readout_card/fsfb_corr/source/rtl/fsfb_corr.vhd
U readout_card/readout_card/source/rtl/readout_card.vhd
U readout_card/readout_card/source/rtl/readout_card_pack.vhd
U readout_card/wbs_frame_data/source/rtl/wbs_frame_data.vhd
U readout_card/wbs_frame_data/source/rtl/wbs_frame_data_pack.vhd

* '''Bugs:'''
** None so far.
** fpga_temp, card_temp, card_id commands are not supported.

* '''Synthesis Notes:'''
** The quartus.ini file was present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 24,554 / 41,250 ( 60 % ) ;
; Total memory bits ; 1,262,592 / 3,423,744 ( 37 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.991 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.864 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 17.052 ns ;

== Revision 4.4.1 ==
* '''Filename:''' rc_v04040001_21nov2008

* '''Features:'''
** Fixes a bug that froze up the firmware if any of the following commands were issued: CARD_ID_ADDR, CARD_TEMP_ADDR, FPGA_TEMP_ADDR in 4.4.0 only.

* '''Details:'''
** The bug fix include adding more logic to the wishbone ack path (readout_card.vhd), which subsequently decreased the minimum clock setup time to 1.588ns. The new logic will catch errors that the old logic wouldn't have, and is now consistent with the firmware on all the other cards. However, if timing becomes an issue, the logic may have to revert back to that which was in version 4.0.c.

* '''Bugs:'''
** None so far.

* '''Synthesis Notes:'''
** The quartus.ini file was not present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 27,241 / 41,250 ( 66 % ) ;
; Total memory bits ; 405,504 / 3,423,744 ( 12 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.588 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.585 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 17.057 ns ;

== Revision 4.4.0 (buggy) ==
* '''Filename:''' rc_v04040000_02oct2008
* '''Features:'''
** Reinstated the data modes in wbs_frame_data.vhd that were removed in 4.0.c. This firmware has the following modes: '''0, 1, 2, 4, 5, 7, 10'''. The modes that are not present are: '''3''' (raw data), '''6''' (replaced by data_mode = 7), '''8''' (replaced by data_mode = 10), '''9''' (replaced by data_mode = 10). For more information on data modes, see [[Data mode]].
** Re-integrated the id_thermo and fpga_thermo block in the readout_card.vhd top level that was removed in 4.0.c.
** Removed the sticky bit in fsfb_corr.vhd, which was enabled when flux-jumping was turned on. Because the feedback is signed, the sticky bit would usually reflect the value of the 14th bit, except in situations when the number of flux quanta to jump was greater than 1 (i.e. cosmic rays, IV-curves, etc). Flux jumps are made at a maximum rate of one per frame period, so that if the First-Stage Feedback increased past the 13th bit, it would not be reflected in the feedback applied. Now it is.
* '''Details:'''
** Simplified the FSM logic in wbs_frame_data.vhd that determines when to transition from IDLE to WSS1. This was done to lower the number of gates in that path, and ease the timing.
** Removed the z_dat_i port in fsfb_processor.vhd and fsfb_calc_pack.vhd to the fsfb_proc_pidz block, in an effort to make it clearer within that block that the z-term is always = 0.
** Removed the z-term sign extension in fsfb_proc_pidz.vhd, and the [d-term + z-term] adder to free up DSP resources since the z-term is always = 0.
** Adjusted the indentation in fsfb_io_controller.vhd to make the file more readable.
** Moved the tga_o signal out of the dispatch_wishbone.vhd FSM, and made it a continuous assignment. This signal had one of the highest fan-out counts in the RTL design, and actually was impossible to route in Stratix III chips in its previous configuration because of the number of gates on the fan-out. As a consequence of making it a continuous assignment, the Stratix III fitter was able to succeed, and the Stratix I timing characteristics were greatly improved. This is the most significant change in this revision. This change single-handedly increased the minimum slack from 1.282 ns in v0400000c to 2.372 ns (or 56.7 MHz max) in this revision.
* '''Bugs:'''
** The following commands lock up the Readout Card firmware: CARD_ID_ADDR, CARD_TEMP_ADDR, FPGA_TEMP_ADDR.
** fb_const0 commands to channel 0 do not work. The value is stored in the register, but not applied to the DAC. Thus, read-back returns the correct value, but the DAC does not
* '''Synthesis Notes:'''
** The quartus.ini file was not present in the synth directory during synthesis.
* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 27,099 / 41,250 ( 66 % ) ;
; Total memory bits ; 406,016 / 3,423,744 ( 12 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.372 ns ;
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 4.052 ns ;
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.066 ns ;

== Revision 4.0.c ==
* '''Filename:''' rc_v0400000c_15aug2008.sof
* '''Features:'''
** Only has data modes 0, 1, 4, and 10.
** Fixed the bug that exists in 4.0.b, 4.0.a, and 4.0.9 that prevented the fb_const value from being applied to channel zero (wbs_fb_data.vhd).
* '''Details:'''
** Changed a counter in the dispatch block to ease timing constraints in synthesis (dispatch_wishbone.vhd)
** Updated the tagged versions of dispatch.vhd , dispatch_cmd_receive.vhd, and dispatch_reply_transmit.vhd to the version that is used by all the other cards.
** '''Removed''' the fpga_termo (command: '''fpga_temp''') and id_thermo (commands: '''card_temp, card_id''') to ease timing constraints in synthesis (readout_card.vhd)
** Updated the tagged version of fpga_termo.vhd to include the new 'stale bit' feature
** Updated the tagged version of frame_timing_core.vhd to include the new 'err_o' interface
* '''Bugs:'''
** None reported yet
* '''Synthesis Notes:'''
** The quartus.ini file was not present in the synth directory during synthesis.
* '''FPGA Resource Usage:'''
Total logic elements : 25,058 / 41,250 ( 61 % )
Total memory bits : 400,896 / 3,423,744 ( 12 % )

* '''Timing Analysis''' (readout_card.tan.rpt):
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.282 ns ;
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.736 ns ;
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.665 ns ;

== Revision 4.0.b (buggy) ==
Note: This revision is on a watch list, after the bug detected 15 July 2008. See the bug section for more details.
* '''Filename''' : rc_v0400000b_04aug2008.sof
* '''Features'''
** data_mode 10 is added to provide more filtfb bits (compared to data mode 9) for planet observations. filtered_dat(27 downto 3) & flux_cnt_dat(6 downto 0)

* '''Bugs'''
** An unexplained bug that appeared in 4.0.a and may still be present in 4.0.b is a problem with the readout of channels being clipped out of data reporting. [[Bug 1 Notes]]

* ''' Synthesis note '''
** Quartus.ini removed.

== Revision 4.0.a (buggy) ==
Note: This revision is on a watch list, after the bug detected 15 July 2008. See the bug section for more details.
* '''Filename''' : rc_v0400000a_07jul2008.sof
* '''Bug Fix'''
** mce_status and adc_offset/flx_quanta commands do not fail after power up.
* ''' Synthesis note '''
** Quartus.ini removed.

* '''Bugs'''
** Seems to clip out channel 0 from data reporting.

== Revision 4.0.9 (buggy) ==
* '''Filename''' : rc_v04000009_26jun2008.sof
* '''Features'''
** sa_bias and offset DACs only refreshed when new values are written. (in previous versions, DACs were refreshed every frame)
* '''Bugs'''
** fb_const0 commands to channel 0 do not work. The value is stored in the register, but not applied to the DAC. Thus, read-back returns the correct value, but the DAC does not.
** reading flx_quanta and adc_offset right after power up hangs the reply datapath to CC. resetmce clears this error as temporary solution. the problem is caused by first read ack of the wishbone slave.

== Revision 4.0.8 ==
* '''Filename''' : rc_v04000008_26jun2008.sof
* '''Features'''
** The gaini, gainp, gaind resolution increased to 12-bit, i.e. -2048 to 2047 (formerly 10-bit).

* '''Bug fix'''
** the bug associated with gainpid read before mce_reset is fixed.

* ''' Synthesis note '''
** Quartus.ini removed.

== Revision 4.3.7 ==
* '''Filename''' : rc_v04030007_26may2008_raw.sof
* '''Features'''
** 14-bit raw mode enabled to buffer a snapshot of 50MHz samples for 2 frames of row_len * num_rows samples.
** In order to extend the raw-mode to 14-bit, an assumption is made that the raw buffer is not written to while being read. Therefore, make sure there is at least 2*row_len*num_rows*20ns between issuing captr_raw command and reading back the raw data.
** In order to save RAM for raw mode, two memory-intensive features are disabled:
*** low-pass filter disabled ( mixed filtfb data modes 6, 7, 9 are also disabled)
*** PID (gainp0, gaini0, gaind0) readback disabled. one can still set PID values and run servo, but can not read back the values.

== Revision 4.2.7 ==
* '''Filename''' : rc_v04020007_24may2008_raw.sof
* '''Features'''
** raw mode enabled to buffer a snapshot of 50MHz samples for 2 frames of row_len * num_rows samples.
** In order to save RAM for raw mode, two memory-intensive features are disabled:
*** low-pass filter disabled ( mixed filtfb data modes 6, 7, 9 are also disabled)
*** PID (gainp0, gaini0, gaind0) readback disabled. one can still set PID values and run servo, but can not read back the values.
* '''Bug fix'''
** the bug associated with reading from raw-buffer is fixed.

== Revision 4.1.7 ==
* '''Filename''' : rc_v04010007_25apr2008_raw.sof
* '''Features'''
** raw mode enabled to buffer a snapshot of 50MHz samples for 2 frames of row_len * num_rows samples.
** In order to save RAM for raw mode, two memory-intensive features are disabled:
*** low-pass filter disabled ( mixed filtfb data modes 6, 7, 9 are also disabled)
*** PID (gainp0, gaini0, gaind0) readback disabled. one can still set PID values and run servo, but can not read back the values.
* '''Bugs'''
** after each readout frame, raw-buffer readout counter falls behind by 3 and this causes skipping 3 50MHz samples in the data stream and column-data being messed up in subsequent frames. Data can be rearranged by post processing.

== Revision 4.0.6 (buggy) ==
* '''Filename''' : rc_v04000006_15feb2008.sof or .pof
* '''Features'''
** '''bugfix''': unreliable reset due to unsafe and incomplete state machines is fixed.
** '''bugfix''': flux_jump sign problem fixed, so far proved in const_mode, to be tested in servo_mode with cold setup.
** servo_mode=2 or ramp previously only went from 0 to ramp_amp, but now goes from -8192 to -8192+ramp_amp
** new commands are added: ''scratch'' and ''card_type''. Scratch takes 8 values and can be used by software to detect reset.
** slot_id and fw_rev are now integrated as part of all_cards.vhd
** lvds_tx_b=0, This will allow Clock Card to use the secondary backplane lvds line and check whether RC is plugged in.
** filter_coeff in misc_banks_admin commented as it is not implemented and causes timing problems.

* '''Bugs'''
** reading gainp/gaini/gaind right after power up hangs the reply datapath to CC. resetmce clears this error as temporary solution. the problem is caused by first read ack of pid_ram_admin.
** slot_id is only set after a resetmce is issued. (using the latest all_cards in the next revision will fix this)
** has spurious spikes on channel 7 data, which max out the integral, and cause the detectors to come unlocked. This firmware officially meets timing requirements, but the bug could be due to marginal timing on the longest data paths, i.e. ~0.1 ns in some cases.

== Revision 4.0.5 ==
* '''Filename''' : rc_v04000005_01nov2007.sof or .pof
* '''Features'''
** data mode 9 (mixed filt + flux jump) with windowing readjusted compared to data mode 8

* '''Bugs'''
** unreliable resetmce. Sometimes, firmware waked up non-responsive on lvds lines.
** In data mode 5 and 9, flux-jump counter is not reported properly due to a sign error. However, flux jumping works fine.

== Revision 3.0.19 ==
* '''Filename''' : rc_v03000019_16feb2007_raw.sof (no pof as one is not likely to run with this as regular firmware)
* '''Features'''
** data mode 3 is enabled.
** filter is disabled as a compromise to fit the raw-mode buffer.

* '''Bugs'''
** unreliable resetmce. Sometimes, firmware waked up non-responsive on lvds lines.

== Old Firmware Revisions ==
* '''4.0.4''': rc_v04000004_11oct2007.sof data mode 8 added (mixed filt + flux jump)
* '''4.0.3''': rc_v04000003_19sep2007.sof data mode 7 bit split readjusted to 10b error being bit 4 to 14
* '''4.0.2''': rc_v04000002_11sep2007.sof pid resolution increased to 10b, data mode 7 added
* '''4.0.1''': rc_v04000001_06sep2007.sof
* '''4.0.0''': rc_v04000000_29aug2007.sof supports readout_row_index * [[ bugs ]]

= To-Do List =
* the starting point for the servo is currently zero and it would be nice to have it programmable.

= RC Synthesis Notes =
# The following note applies when using Quartus versions earlier than Q7: Quartus.ini file had to exist in synth directory up to revision 4.0.a due to a bug that started in Quartus 6.1 and would synthesize away arbitrary parts of readout card. We contacted Altera at the time and they provided us the ini file.
# Timing: There is no "lock region" defined for readout card. Timing on readout card is tight and since version 3 or so any new feature would initially fail timing till some synthesis options were tweaked. One path that remains to be consistently marginal is from addr_gen counter (i.e. tga_o counter) in dispatch_wishbone.vhd to wishbone slaves particularly misc_banks_admin.vhd. Modules that are rewritten to address timing concerns are fsfb_corr, all_cards, misc_banks_admin, and finally instantiating an lpm counter instead of a counter from components library. Surprisingly, the lpm counter reduced 87 failures to 37, although looking at the technology map viewer, it seemed that they were both synthesized the same.
# Compile time: This was at some point 4.5 hours, after going to dual core PC, this was reduced to 35 minutes. After extending pid gains to 12b and fixing offset/sa_bias update code, the compile time increased to 1.5hr again with utilization up to ~70%.
# wbs_fb_storage, ram_8x64, pid_ram had to be regenerated using latest (Q7.2) MegaWizard to get rid of the bug associated with failure to read after power up until a reset was issued.
# During simulations, the initialization of RAM block with .hex files needs to be disabled. This is done by commenting out the following lines from the MegaWizard generated Megafunction files (remember to un-comment them before synthesizing the code):
lpm_file => "C:/scuba2_repository/cards/readout_card/fsfb_calc/source/rtl/ram_40x64.hex", and
lpm_file : STRING;
#Starting Q10.0 use TimeQuest timing analyzer as oppose to the classic one. The classic one is being phased out by Altera. In order to use TimeQuest, you need to have an sdc file present in your project directory.
----
[http://e-mode.phas.ubc.ca/mcewiki/index.php/Main_Page MCE Main Page]

Readout Card firmware

2011-05-04T21:32:49Z

Bburger:

* Synthesis Reminders (for firmware developers)
** quartus.ini is not needed anymore (Fixed as of Q7, Altera SR10783580 2010-10-24)
** Remember that readout_card/fsfb_clac/source/rtl/ram_40x64.vhd must be initialized with the ram_40x64.hex file in the same directory.
== Revision 5.1.2 ==
* '''Filename:'''
** rc_stratix3_v05010002_18jan2011.sof (for Rev. E cards)
** rc_stratix3_v05010002_18jan2011.jic (for Rev. E cards)
** rc_v05010002_03feb2011.sof (for Rev. B cards)
** rc_v05010002_03feb2011.pof (for Rev. B cards)

* '''Features:'''
** based on 5.1.1 with k1 and k2 (filter params) limited to k1<16 and k2<32 in order to resolve the timing when compiling for smaller Stratix FPGA on RC Rev. B.

* '''Bug fix:'''
** the 2-rows-off filtered data readout introduced with configurable filter in rev. 5.1.0 and 5.1.1 is fixed now.

* '''Bugs:'''
** none so far.

* '''FPGA Resource Usage and Timing Report''' (readout_card.fit.rpt and readout_card.tan.rpt): TO BE UPDATED LATER
; Total logic elements ; 33,285 / 41,250 ( 81 % ) ;
; Total pins ; 358 / 616 ( 58 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;
; Fast Model Clock Hold: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 0.364 ns
; Fast Model Clock Hold: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 0.365 ns
; Fast Model Clock Hold: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 0.379 ns

== Revision 5.1.1 (not recommended) ==
* '''Filename:'''
** rc_v05010001_01dec2010.sof (for Rev. B cards)

* '''Features:'''
** based on 5.1.0, but k1 and k2 (filter params) are now limited to k1<16 and k2<32 in order to resolve the timing failures of compiling 5.1.0 for smaller Stratix FPGA on RC Rev. B.

* '''Bugs:'''
** filter mode data is off by 2 rows.

== Revision 5.1.0 (not recommended) ==
* '''Filename:'''
** rc_stratix3_v05010000_01nov2010.sof (for Rev. E cards)
** rc_v05010000_01nov2010.sof (for Rev. B cards) has timing failures '''do not use!!!'''

* '''Features:'''
** added configurable filter parameters specified by ''fltr_coeff'', default is the fcutoff/fsampl=122Hz/15kHz. see [[ Digital 4-pole Butterworth Low-pass filter ]].
** ''fltr_type'' is set to 255 to indicate configurable filter parameters.
** see [http://www.phas.ubc.ca/~mce/mcedocs/software/SC2_ELE_S580_515_mce_command_description.pdf MCE command description]
** development notes:
*** It is built on Quartus10.1.
*** tcl files had to be updated as cmp syntax is not supported in Q10 anymore.
*** Rev. E cards now can be identified by reading back pcb_rev as part of card_type, therefore both stratix I and III sof/pof/jic are generated from the same source.

* '''Bugs:'''
** rc_v05010000_01nov2010.sof has timing failures that were overlooked, do not use this firmware for Rev.B cards.
** '''filter mode data is off by 2 rows.'''

* '''FPGA Resource Usage and Timing Report''' (readout_card.fit.rpt and readout_card.tan.rpt): logic usage is upto 85% from 66% in 5.0.d/e/f

= Revision 5.0.f =
* '''Filename:'''
** rc_v0500000f_22oct2010.sof (for Rev. B cards)
** rc_stratix3_v0500000f_22oct2010.sof (for Rev. E cards)

* '''Features:'''
** Bugfix: integral clamp should work now. only positive integral_clamp values are valid!

* '''Details:''': SQ1FB is applied 18 clock cycles after start of a row visit (SQ1_Bias being applied) regardless of flux-jump being enabled or not. In pre-5.0.b firmware SQ1FB was being applied after 7 clock cycles when flux-jump was disabled and after 18 clock cycles when flux-jump was enabled.
** available for both Rev. E and Rev. B cards, the upper byte of card_type parameter now reports the pcb revision.
** development note: It is built on Quartus10.1.

* '''Bugs:'''
**none yet!

* '''FPGA Resource Usage and Timing Report''' (readout_card.fit.rpt and readout_card.tan.rpt): no change compared to 5.0.a/b/c/d

== Revision 5.0.e (not recommended) ==
* '''Filename:'''
** rc_v0500000e_06oct2010.sof

* '''Details:'''
** an unsuccessful attempt to fix integral_clamp, but changed the functionality so that it clamps at the value, but it doesn't hold the clamp. i.e., if the calculated sq1fb becomes less than the specified clamp value, the sq1fb is not clamped anymore. This is not a desired functionality!

= Revision 5.0.d =
* '''Filename:'''
** rc_v0500000d_04aug2010.sof

* '''Features:'''
** Bugfix: To fix the bug associated with negative flux-jumps, reverted to signed multiplier and hence, incremented the width of the flux-quanta multiplier input by 1.

* '''Details:''': SQ1FB is applied 18 clock cycles after start of a row visit (SQ1_Bias being applied) regardless of flux-jump being enabled or not. In pre-5.0.b firmware SQ1FB was being applied after 7 clock cycles when flux-jump was disabled and after 18 clock cycles when flux-jump was enabled.

* '''Bugs:'''
** '''integral_clamping is broken'''. To test the clamping, a servo-locked ramp was initiated on the sq1fb and then flux-jumping was turned on and observed by attaching a scope to the SQ1FB output. With integral_clamp=80000000, flux_quanta=8000, gaini=1, flux-jump enabled, we see [[http://e-mode.phas.ubc.ca/mcewiki/index.php/Image:Clamp_unstable.png scope snapshot]] used slow_fb_ramp.py script for testing.

* '''FPGA Resource Usage and Timing Report''' (readout_card.fit.rpt and readout_card.tan.rpt): no change compared to 5.0.a/b/c

== Revision 5.0.c (not recommended) ==
* '''Filename:'''
** rc_v0500000c_16jun2010.sof

* '''Features:'''
** Based on rev. 5.0.b
** Re-introduced flux-jump counter clamping to maintain continuity in behavior from past versions of firmware in the field.
** '''Important''': SQ1FB is applied 18 clock cycles after start of a row visit (SQ1_Bias being applied) regardless of flux-jump being enabled or not. In pre-5.0.b firmware SQ1FB was being applied after 7 clock cycles when flux-jump was disabled and after 18 clock cycles when flux-jump was enabled.

* '''Details:'''
* '''Bugs:'''
** '''flux-jump is broken'''. flux-jumping block misbehaves at the first jump in the negative range.

* '''FPGA Resource Usage''' (readout_card.fit.rpt): [[rc_5.0.c_fit_rpt]]
; Total logic elements ; 26,800 / 41,250 ( 65 % ) ;
; Total pins ; 358 / 616 ( 58 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;
; DSP block 9-bit elements ; 76 / 112 ( 68 % ) ;
; Total PLLs ; 1 / 6 ( 17 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt): [[rc_5.0.c_tan_rpt]]
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.964 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 4.382 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 15.924 ns ;

== Revision 5.0.b (not recommended) ==
* '''Filename:'''
** rc_v0500000b_03jun2010.sof

* '''Features:'''
** Based on rev. 5.0.a
** A bug that caused jumps in first-stage feedback, and detected as spikes in the raw data of pixels that were in servo_mode=0,1,2 was fixed. The jumps in FSFB were due to flux-jumping being enabled on live pixes with non-zero flx_quanta, and being disabled on the fly on dead pixels with flx_quanta=0. Flux-jumping is now disabled on a column-by-column basis if a column is in servo_mode = 0,1,2.
** Ineffective clamping was removed from the flux-jumping block (as per 5.0.9), as it is now replaced by the clamping that was perfected in rev. 5.0.10
** A sticky bit that only affected servo_mode=0,1,2 was also removed from the flux-jumping block.
** flx_lp_init commands now also clear the flux-jumping block as well.
** The 11-clock-cycle delay (in applying SQ1_FB) that in previous firmware only occurred when flux-jumping was enabled, now (in this version) is in effect all the time. Due to the bug-fix above, flux-jumping can be disabled on a column-by-column basis by setting servo_mode=0,1,2 when en_fb_jump=1. Before the change, this meant that constant values could be applied with or without the 11-cycle delay if en_fb_jump=1 or 0. To make the delay consistent, it is now always 11 cycles. As background, the flux-jumping block is pipelined, meaning that it does calculations for all 8 channels serially. The serialization is because of DSP-block limitations in the Readout Card FPGA that prevent us from doing all 8 channels in parallel. The reason that it takes 11 cycles to complete the flux-jumping calculations is because the values are computed for the eight channels in three ALU stages: 8 + 3 = 11 cycles. Adding 11 cycles to the 7 cycles of latency from other stages in the system results in: 11 + 7 = 18 cycles of latency from the start of a row dwell period before the first-stage feedback is applied. In rc_v5.0.c, I enforce the 18-cycle delay even when flux-jumping is not enabled to maintain uniformity across all eight channels, because flux-jumping is enabled/disabled on a per-channel basis. In other words, if I hadn't enforced the 18-cycle delay, some channels could have their feedback applied after 7 cycles, while others could have it applied after 18 cycles. I wasn't a fan of this non-uniformity. I realize that 18 cycles is a long time. In fact, so is 7. In the last few months, we have been discussing how to reduce these times to 1 cycle, because every experiment out there wants to multiplex as fast as possible, and the 7/18-delay is a rate limiting step.
** The flux-jumping code was re-arranged in the flux-jumping block to reflect the flow of data through the pipeline and make it easier to understand.

* '''Details:'''

* '''Bugs:'''
** flux-jump does not work when jumping to negative values.

* '''FPGA Resource Usage''' (readout_card.fit.rpt): [[rc_5.0.b_fit_rpt]]
* '''FPGA Timing Analysis''' (readout_card.tan.rpt): [[rc_5.0.b_tan_rpt]]

= Revision 5.0.a =
* '''Filename:'''
** rc_v0500000a_12mar2010.sof

* '''Features:'''
** Based on the merger of rev. 5.0.8 and 5.0.9.
** '''integral_clamp''' command is added where a clamp value is set for the integral term and once the integral term hits that value, the integral-term is clamped to that value and p-term and d-term are clamped to zero. When integral_term=0 then no clamping is in effect, similar to previous releases of firmware.
** The low pass filter has 20-bit input and f_3dB/f_samp = 122Hz/15kHz .
** The flux-jump clamping that was removed in 5.0.9 is included once again here, as we decided this is safer for now.

* '''Details:'''
** "lock_dat_left" parameter that was removed in 5.0.9 is now implemented as "lock_dat_lsb"

* '''Bugs:'''
** flx_lp_init does not reinitialize the flux-jump block

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis
** tag name: rc_v0500000a_12mar2009! years were mixed up!

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
* '''FPGA Timing Analysis''' (readout_card.tan.rpt):

== Revision 5.0.9 (buggy) ==
* '''Filename:'''
** rc_v05000009_13nov2009.sof

* '''Features:'''
** Based on rev. 5.0.4
** Removes a sticky bit in pid calculation result storage -- in fsfb_processor.
** Adds a command to clamp the growth of the I-term to prevent wrapping and track down the source of Caltech's FSFB jumps.
** Removed the unused lock_dat_left parameter. The ability to shift left was moved to the fsfb_corr block some time ago.
** Fixed a sign extension bug acting on the flux quanta, which limited the value to 8191. Changed the extension from signed to unsigned.
** Removed ineffective clamping in the flux-jump calculation block.
** IMPORTANT: Must be used in conjunction with firmware rev. 5.0.0+ of all other cards.

* '''Details:'''

* '''Bugs:'''
** integral_clamp read/write command does not work.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 27,960 / 41,250 ( 68 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.825 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.878 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 14.397 ns ;

== Revision 5.0.8 (UBC only) ==
* '''Filename:'''
** rc_v05000008_09oct2009.sof

* '''Features:'''
** Based on rev. 5.0.4
** type 1 low-pass filter: f3dB=122Hz for fsample=15kHz
** Filter-input-width changed from 18b to 20b with no sticky bits!
** removed sticky bits in internal arithmetic of the filter.

= Revision 5.0.7 (type-2 filter) =
* '''Filename:'''
** rc_v05000007_09oct2009.sof

* '''Features:'''
** Based on rev. 5.0.4
** type-2 low-pass-filter: f3dB=75Hz for fsample=30000.
** Filter-input-width changed from 18b to 20b with no sticky bits!
** inter-biquad-gain-scaling for the filter is 2^14
** filter results are scaled down by 2^3 in the output of the filter.
** removed sticky bits in internal arithmetics
** _correction_ disabled in fsfb_proc_pidz

* '''Details:'''
** quartus.ini file was '''not''' present in synth directory.

* '''Bugs:'''
** none to report

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
== Revision 5.0.6 (UBC only) ==
* '''Filename:'''
** rc_stratix3_v05000006_15sep2009.sof

* '''Features:'''
** Only Valid for Rev. C/D Cards
** Based on rev. 5.0.3
** tcl file updated for Rev. D and aligned with top-level and qsf (project file).
** flux loop commented, just to try sampling the ADC.
** compiled with Q9.1

== Revision 5.0.5 (UBC only) ==
* '''Filename:'''
** rc_v05000005_04sep2009.sof

* '''Features:'''
** Based on rev. 5.0.2
** changed the low-pass-filter to f(3db)=75Hz for f(sample)=30000.

* '''Details:'''
** quartus.ini file was '''not''' present in synth directory.

* '''Bugs:'''
** negative inputs to the filter cause filter to have a non-flat pass-band region. may have to do with sign-handling...

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
* '''FPGA Timing Analysis''' (readout_card.tan.rpt):

= Revision 5.0.4 =
* '''Filename:'''
** rc_v05000004_28aug2009.sof

* '''Features:'''
** Based on rev. 5.0.2
** BUG Fix: handles 14-bit flux quanta (changed the multiplier to unsigned)
** BUG Fix: changed standard logic vector extension from signed to unsigned in flux-jumping slave.
** IMPORTANT: Must be used in conjunction with firmware rev. 5.0.0+ of all other cards.

* '''Details:'''

* '''Bugs:'''
** None so far.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,170 / 41,250 ( 63 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.541 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.612 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 15.398 ns ;

= Revision 5.0.3 =
* '''Filename:'''
** rc_stratix3_v05000003_21aug2009.sof

* '''Features:'''
** ONLY valid REV C/D RC Cards
** Based on rev. 5.0.2
** flux loop commented, just to try sampling the ADC.
** updated tcl file, but still need to rely on project file as well as qsf file.
** changed default level of adc_sclk to '1'
** dac_clr_n was changed from an output to an input.
** added 'locked' interface to rc_pll_stratix_iii
** renamed the adc_pll clock signals to more explanitory names
** added the FPGA_DEVICE_FAMILY generic to the dispatch interace for synthesis of the dc_fifo in lvds_rx
** uncommented DDR interface to force the syntesizer to use correct left and right PLLs (in conjunction with ADC and DDR PLLs)
** added test signals to test_status to see clocks on the scope.
== Revision 5.0.2 (buggy) ==
* '''Filename:'''
** rc_v05000002_test00_tagged.sof

* '''Features:'''
** Based on rev. 5.0.1
** Fixed a bug in wbs_frame_data that stored data incorrectly if reporting 1 or 2 pixels only.
** IMPORTANT: Must be used in conjunction with firmware rev. 5.0.0+ of all other cards.

* '''Details:'''

* '''Bugs:'''
** None so far.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,186 / 41,250 ( 63 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.755 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.979 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.067 ns ;

== Revision 5.0.1 (buggy) (Filter + Raw + Rectangle, 2 LVDS) ==
* '''Filename:'''
** rc_v05000001_26may2009.sof

* '''Features:'''
** Combines features in rev. 5.0.0 (2 LVDS Lines) and rev. 4.0.e (Filtered + Raw), with the NEW rectangle mode.
** IMPORTANT: Must be used in conjunction with firmware rev. 5.0.0+ of all other cards.

* '''Details:'''
** [[CVS Diff Between sys_v05000000 and rc_v05000001]]

* '''Bugs:'''
** Has a bug in wbs_frame_data that stored data incorrectly if reporting 1 or 2 pixels only.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,565 / 41,250 ( 64 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.656 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.861 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 14.167 ns ;

== Revision 5.0.0 (Filter Only, 2 LVDS) ==
* '''Filename:'''
** rc_v05000000_22dec2008.sof (tagged as sys_v05000000_22dec2008)

* '''Features:'''
** IMPORTANT: Must be used in conjunction with firmware v05000000+ of all other cards!!!
** Adds the ability to read out one column of data continuously from readout cards
** Adds data mode 11, which is an engineering mode. Data points are 32-bits, and bits [9..3]=row_index, [2..0]=column_index. This mode is useful for determining which pixels one is reading out in the array, in column mode for example.

* '''Details:'''
** [[CVS Diff Between rc_v0400000c and sys_v05000000]]

* '''Bugs:'''
** None so far.

* '''Synthesis Notes:'''
** The quartus.ini file was not present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,607 / 41,250 ( 65 % ) ;
; Total memory bits ; 406,016 / 3,423,744 ( 12 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.558 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.892 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.987 ns ;

== Revision 4.0.f (Filter + Raw, 1 LVDS) ==
* '''Filename:'''
** rc_v0400000f_12feb2010.sof

* '''Features:'''
** Based on 4.0.e and in parallel with 5.0.9 (equivalent version, clamping is not included)
** Incorporates fixes that were done to flux-jumping between 5.0.2 - 5.0.4 - 5.0.9. Namely:
*** Changes a multiplier from signed to unsigned (in fsfb_corr_multplier.vhd).
*** Changes sign extension from signed to unsigned (in flux_quanta_ram_admin.vhd).

* '''Details:'''

* '''Bugs:'''
** None reported yet.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,773 / 41,250 ( 65 % ) ;
; Total memory bits ; 1,321,984 / 3,423,744 ( 39 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.539 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 4.118 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 17.318 ns ;

== Revision 4.0.e (Filter + Raw, 1 LVDS) ==
* '''Filename:'''
** rc_v0400000e_27apr2009.sof

* '''Features:'''
** Based on 4.0.d
** Combines both raw- and filtered-data modes.
** fpga_temp, card_temp, card_id commands are disabled.
** Tested by Matt Hasselfield.

* '''Details:'''

* '''Bugs:'''
** fpga_temp, card_temp, card_id commands are disabled.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 27,048 / 41,250 ( 66 % ) ;
; Total memory bits ; 1,321,984 / 3,423,744 ( 39 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.675 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.907 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.728 ns ;

== Revision 4.0.d (Raw Only, 1 LVDS) ==
* '''Filename:''' rc_v0400000d_20090417.sof

* '''Features:'''
** Based on v4.0.c, but has the filter removed, and implements a single 65536-index RAM block for storing 50 MHz raw-data samples.
** The firmware takes a new command called readout_col_index which specifies which column to capture raw data from.
** Other than readout_col_index, the firmware functions the same as previous raw-data firmware, including then need to issue a capture_raw command.
** For more information on raw-data, see: http://e-mode.phas.ubc.ca/mcewiki/index.php/Raw-mode_readout
** This firmware also integrates some of the improvements that were implemented in 4.4.0, like the removal of the tga_o signal from an FSM in dispatch_wishbone.vhd.

* '''Details:'''
** Differences between 4.0.c and 4.0.d
U system/test/source/tb/tb_cc_rcs_bcs_ac.vhd
U all_cards/dispatch/source/rtl/dispatch_wishbone.vhd
U library/sys_param/source/rtl/wishbone_pack.vhd
U readout_card/adc_sample_coadd/source/rtl/adc_sample_coadd.vhd
U readout_card/adc_sample_coadd/source/rtl/adc_sample_coadd_pack.vhd
U readout_card/flux_loop/source/rtl/flux_loop.vhd
U readout_card/flux_loop/source/rtl/flux_loop_pack.vhd
U readout_card/flux_loop_ctrl/source/rtl/flux_loop_ctrl.vhd
U readout_card/flux_loop_ctrl/source/rtl/flux_loop_ctrl_pack.vhd
U readout_card/flux_loop_ctrl/source/tb/tb1_flux_loop_ctrl.vhd
U readout_card/flux_loop_ctrl/source/tb/tb2_flux_loop_ctrl.vhd
U readout_card/fsfb_calc/source/rtl/fsfb_fltr_regs.vhd
U readout_card/fsfb_corr/source/rtl/fsfb_corr.vhd
U readout_card/readout_card/source/rtl/readout_card.vhd
U readout_card/readout_card/source/rtl/readout_card_pack.vhd
U readout_card/wbs_frame_data/source/rtl/wbs_frame_data.vhd
U readout_card/wbs_frame_data/source/rtl/wbs_frame_data_pack.vhd

* '''Bugs:'''
** None so far.
** fpga_temp, card_temp, card_id commands are not supported.

* '''Synthesis Notes:'''
** The quartus.ini file was present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 24,554 / 41,250 ( 60 % ) ;
; Total memory bits ; 1,262,592 / 3,423,744 ( 37 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.991 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.864 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 17.052 ns ;

== Revision 4.4.1 ==
* '''Filename:''' rc_v04040001_21nov2008

* '''Features:'''
** Fixes a bug that froze up the firmware if any of the following commands were issued: CARD_ID_ADDR, CARD_TEMP_ADDR, FPGA_TEMP_ADDR in 4.4.0 only.

* '''Details:'''
** The bug fix include adding more logic to the wishbone ack path (readout_card.vhd), which subsequently decreased the minimum clock setup time to 1.588ns. The new logic will catch errors that the old logic wouldn't have, and is now consistent with the firmware on all the other cards. However, if timing becomes an issue, the logic may have to revert back to that which was in version 4.0.c.

* '''Bugs:'''
** None so far.

* '''Synthesis Notes:'''
** The quartus.ini file was not present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 27,241 / 41,250 ( 66 % ) ;
; Total memory bits ; 405,504 / 3,423,744 ( 12 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.588 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.585 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 17.057 ns ;

== Revision 4.4.0 (buggy) ==
* '''Filename:''' rc_v04040000_02oct2008
* '''Features:'''
** Reinstated the data modes in wbs_frame_data.vhd that were removed in 4.0.c. This firmware has the following modes: '''0, 1, 2, 4, 5, 7, 10'''. The modes that are not present are: '''3''' (raw data), '''6''' (replaced by data_mode = 7), '''8''' (replaced by data_mode = 10), '''9''' (replaced by data_mode = 10). For more information on data modes, see [[Data mode]].
** Re-integrated the id_thermo and fpga_thermo block in the readout_card.vhd top level that was removed in 4.0.c.
** Removed the sticky bit in fsfb_corr.vhd, which was enabled when flux-jumping was turned on. Because the feedback is signed, the sticky bit would usually reflect the value of the 14th bit, except in situations when the number of flux quanta to jump was greater than 1 (i.e. cosmic rays, IV-curves, etc). Flux jumps are made at a maximum rate of one per frame period, so that if the First-Stage Feedback increased past the 13th bit, it would not be reflected in the feedback applied. Now it is.
* '''Details:'''
** Simplified the FSM logic in wbs_frame_data.vhd that determines when to transition from IDLE to WSS1. This was done to lower the number of gates in that path, and ease the timing.
** Removed the z_dat_i port in fsfb_processor.vhd and fsfb_calc_pack.vhd to the fsfb_proc_pidz block, in an effort to make it clearer within that block that the z-term is always = 0.
** Removed the z-term sign extension in fsfb_proc_pidz.vhd, and the [d-term + z-term] adder to free up DSP resources since the z-term is always = 0.
** Adjusted the indentation in fsfb_io_controller.vhd to make the file more readable.
** Moved the tga_o signal out of the dispatch_wishbone.vhd FSM, and made it a continuous assignment. This signal had one of the highest fan-out counts in the RTL design, and actually was impossible to route in Stratix III chips in its previous configuration because of the number of gates on the fan-out. As a consequence of making it a continuous assignment, the Stratix III fitter was able to succeed, and the Stratix I timing characteristics were greatly improved. This is the most significant change in this revision. This change single-handedly increased the minimum slack from 1.282 ns in v0400000c to 2.372 ns (or 56.7 MHz max) in this revision.
* '''Bugs:'''
** The following commands lock up the Readout Card firmware: CARD_ID_ADDR, CARD_TEMP_ADDR, FPGA_TEMP_ADDR.
** fb_const0 commands to channel 0 do not work. The value is stored in the register, but not applied to the DAC. Thus, read-back returns the correct value, but the DAC does not
* '''Synthesis Notes:'''
** The quartus.ini file was not present in the synth directory during synthesis.
* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 27,099 / 41,250 ( 66 % ) ;
; Total memory bits ; 406,016 / 3,423,744 ( 12 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.372 ns ;
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 4.052 ns ;
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.066 ns ;

== Revision 4.0.c ==
* '''Filename:''' rc_v0400000c_15aug2008.sof
* '''Features:'''
** Only has data modes 0, 1, 4, and 10.
** Fixed the bug that exists in 4.0.b, 4.0.a, and 4.0.9 that prevented the fb_const value from being applied to channel zero (wbs_fb_data.vhd).
* '''Details:'''
** Changed a counter in the dispatch block to ease timing constraints in synthesis (dispatch_wishbone.vhd)
** Updated the tagged versions of dispatch.vhd , dispatch_cmd_receive.vhd, and dispatch_reply_transmit.vhd to the version that is used by all the other cards.
** '''Removed''' the fpga_termo (command: '''fpga_temp''') and id_thermo (commands: '''card_temp, card_id''') to ease timing constraints in synthesis (readout_card.vhd)
** Updated the tagged version of fpga_termo.vhd to include the new 'stale bit' feature
** Updated the tagged version of frame_timing_core.vhd to include the new 'err_o' interface
* '''Bugs:'''
** None reported yet
* '''Synthesis Notes:'''
** The quartus.ini file was not present in the synth directory during synthesis.
* '''FPGA Resource Usage:'''
Total logic elements : 25,058 / 41,250 ( 61 % )
Total memory bits : 400,896 / 3,423,744 ( 12 % )

* '''Timing Analysis''' (readout_card.tan.rpt):
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.282 ns ;
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.736 ns ;
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.665 ns ;

== Revision 4.0.b (buggy) ==
Note: This revision is on a watch list, after the bug detected 15 July 2008. See the bug section for more details.
* '''Filename''' : rc_v0400000b_04aug2008.sof
* '''Features'''
** data_mode 10 is added to provide more filtfb bits (compared to data mode 9) for planet observations. filtered_dat(27 downto 3) & flux_cnt_dat(6 downto 0)

* '''Bugs'''
** An unexplained bug that appeared in 4.0.a and may still be present in 4.0.b is a problem with the readout of channels being clipped out of data reporting. [[Bug 1 Notes]]

* ''' Synthesis note '''
** Quartus.ini removed.

== Revision 4.0.a (buggy) ==
Note: This revision is on a watch list, after the bug detected 15 July 2008. See the bug section for more details.
* '''Filename''' : rc_v0400000a_07jul2008.sof
* '''Bug Fix'''
** mce_status and adc_offset/flx_quanta commands do not fail after power up.
* ''' Synthesis note '''
** Quartus.ini removed.

* '''Bugs'''
** Seems to clip out channel 0 from data reporting.

== Revision 4.0.9 (buggy) ==
* '''Filename''' : rc_v04000009_26jun2008.sof
* '''Features'''
** sa_bias and offset DACs only refreshed when new values are written. (in previous versions, DACs were refreshed every frame)
* '''Bugs'''
** fb_const0 commands to channel 0 do not work. The value is stored in the register, but not applied to the DAC. Thus, read-back returns the correct value, but the DAC does not.
** reading flx_quanta and adc_offset right after power up hangs the reply datapath to CC. resetmce clears this error as temporary solution. the problem is caused by first read ack of the wishbone slave.

== Revision 4.0.8 ==
* '''Filename''' : rc_v04000008_26jun2008.sof
* '''Features'''
** The gaini, gainp, gaind resolution increased to 12-bit, i.e. -2048 to 2047 (formerly 10-bit).

* '''Bug fix'''
** the bug associated with gainpid read before mce_reset is fixed.

* ''' Synthesis note '''
** Quartus.ini removed.

== Revision 4.3.7 ==
* '''Filename''' : rc_v04030007_26may2008_raw.sof
* '''Features'''
** 14-bit raw mode enabled to buffer a snapshot of 50MHz samples for 2 frames of row_len * num_rows samples.
** In order to extend the raw-mode to 14-bit, an assumption is made that the raw buffer is not written to while being read. Therefore, make sure there is at least 2*row_len*num_rows*20ns between issuing captr_raw command and reading back the raw data.
** In order to save RAM for raw mode, two memory-intensive features are disabled:
*** low-pass filter disabled ( mixed filtfb data modes 6, 7, 9 are also disabled)
*** PID (gainp0, gaini0, gaind0) readback disabled. one can still set PID values and run servo, but can not read back the values.

== Revision 4.2.7 ==
* '''Filename''' : rc_v04020007_24may2008_raw.sof
* '''Features'''
** raw mode enabled to buffer a snapshot of 50MHz samples for 2 frames of row_len * num_rows samples.
** In order to save RAM for raw mode, two memory-intensive features are disabled:
*** low-pass filter disabled ( mixed filtfb data modes 6, 7, 9 are also disabled)
*** PID (gainp0, gaini0, gaind0) readback disabled. one can still set PID values and run servo, but can not read back the values.
* '''Bug fix'''
** the bug associated with reading from raw-buffer is fixed.

== Revision 4.1.7 ==
* '''Filename''' : rc_v04010007_25apr2008_raw.sof
* '''Features'''
** raw mode enabled to buffer a snapshot of 50MHz samples for 2 frames of row_len * num_rows samples.
** In order to save RAM for raw mode, two memory-intensive features are disabled:
*** low-pass filter disabled ( mixed filtfb data modes 6, 7, 9 are also disabled)
*** PID (gainp0, gaini0, gaind0) readback disabled. one can still set PID values and run servo, but can not read back the values.
* '''Bugs'''
** after each readout frame, raw-buffer readout counter falls behind by 3 and this causes skipping 3 50MHz samples in the data stream and column-data being messed up in subsequent frames. Data can be rearranged by post processing.

== Revision 4.0.6 (buggy) ==
* '''Filename''' : rc_v04000006_15feb2008.sof or .pof
* '''Features'''
** '''bugfix''': unreliable reset due to unsafe and incomplete state machines is fixed.
** '''bugfix''': flux_jump sign problem fixed, so far proved in const_mode, to be tested in servo_mode with cold setup.
** servo_mode=2 or ramp previously only went from 0 to ramp_amp, but now goes from -8192 to -8192+ramp_amp
** new commands are added: ''scratch'' and ''card_type''. Scratch takes 8 values and can be used by software to detect reset.
** slot_id and fw_rev are now integrated as part of all_cards.vhd
** lvds_tx_b=0, This will allow Clock Card to use the secondary backplane lvds line and check whether RC is plugged in.
** filter_coeff in misc_banks_admin commented as it is not implemented and causes timing problems.

* '''Bugs'''
** reading gainp/gaini/gaind right after power up hangs the reply datapath to CC. resetmce clears this error as temporary solution. the problem is caused by first read ack of pid_ram_admin.
** slot_id is only set after a resetmce is issued. (using the latest all_cards in the next revision will fix this)
** has spurious spikes on channel 7 data, which max out the integral, and cause the detectors to come unlocked. This firmware officially meets timing requirements, but the bug could be due to marginal timing on the longest data paths, i.e. ~0.1 ns in some cases.

== Revision 4.0.5 ==
* '''Filename''' : rc_v04000005_01nov2007.sof or .pof
* '''Features'''
** data mode 9 (mixed filt + flux jump) with windowing readjusted compared to data mode 8

* '''Bugs'''
** unreliable resetmce. Sometimes, firmware waked up non-responsive on lvds lines.
** In data mode 5 and 9, flux-jump counter is not reported properly due to a sign error. However, flux jumping works fine.

== Revision 3.0.19 ==
* '''Filename''' : rc_v03000019_16feb2007_raw.sof (no pof as one is not likely to run with this as regular firmware)
* '''Features'''
** data mode 3 is enabled.
** filter is disabled as a compromise to fit the raw-mode buffer.

* '''Bugs'''
** unreliable resetmce. Sometimes, firmware waked up non-responsive on lvds lines.

== Old Firmware Revisions ==
* '''4.0.4''': rc_v04000004_11oct2007.sof data mode 8 added (mixed filt + flux jump)
* '''4.0.3''': rc_v04000003_19sep2007.sof data mode 7 bit split readjusted to 10b error being bit 4 to 14
* '''4.0.2''': rc_v04000002_11sep2007.sof pid resolution increased to 10b, data mode 7 added
* '''4.0.1''': rc_v04000001_06sep2007.sof
* '''4.0.0''': rc_v04000000_29aug2007.sof supports readout_row_index * [[ bugs ]]

= To-Do List =
* the starting point for the servo is currently zero and it would be nice to have it programmable.

= RC Synthesis Notes =
# The following note applies when using Quartus versions earlier than Q7: Quartus.ini file had to exist in synth directory up to revision 4.0.a due to a bug that started in Quartus 6.1 and would synthesize away arbitrary parts of readout card. We contacted Altera at the time and they provided us the ini file.
# Timing: There is no "lock region" defined for readout card. Timing on readout card is tight and since version 3 or so any new feature would initially fail timing till some synthesis options were tweaked. One path that remains to be consistently marginal is from addr_gen counter (i.e. tga_o counter) in dispatch_wishbone.vhd to wishbone slaves particularly misc_banks_admin.vhd. Modules that are rewritten to address timing concerns are fsfb_corr, all_cards, misc_banks_admin, and finally instantiating an lpm counter instead of a counter from components library. Surprisingly, the lpm counter reduced 87 failures to 37, although looking at the technology map viewer, it seemed that they were both synthesized the same.
# Compile time: This was at some point 4.5 hours, after going to dual core PC, this was reduced to 35 minutes. After extending pid gains to 12b and fixing offset/sa_bias update code, the compile time increased to 1.5hr again with utilization up to ~70%.
# wbs_fb_storage, ram_8x64, pid_ram had to be regenerated using latest (Q7.2) MegaWizard to get rid of the bug associated with failure to read after power up until a reset was issued.
# During simulations, the initialization of RAM block with .hex files needs to be disabled. This is done by commenting out the following lines from the MegaWizard generated Megafunction files (remember to un-comment them before synthesizing the code):
lpm_file => "C:/scuba2_repository/cards/readout_card/fsfb_calc/source/rtl/ram_40x64.hex", and
lpm_file : STRING;
#Starting Q10.0 use TimeQuest timing analyzer as oppose to the classic one. The classic one is being phased out by Altera. In order to use TimeQuest, you need to have an sdc file present in your project directory.
----
[http://e-mode.phas.ubc.ca/mcewiki/index.php/Main_Page MCE Main Page]

Readout Card firmware

2011-05-04T21:28:23Z

Bburger: /* Revision 5.0.c (not recommended) */

* Synthesis Reminders (for firmware developers)
** quartus.ini is not needed anymore (Fixed as of Q7, Altera SR10783580 2010-10-24)
** Remember that readout_card/fsfb_clac/source/rtl/ram_40x64.vhd must be initialized with the ram_40x64.hex file in the same directory.
= Revision 5.1.2 =
* '''Filename:'''
** rc_stratix3_v05010002_18jan2011.sof (for Rev. E cards)
** rc_stratix3_v05010002_18jan2011.jic (for Rev. E cards)
** rc_v05010002_03feb2011.sof (for Rev. B cards)
** rc_v05010002_03feb2011.pof (for Rev. B cards)

* '''Features:'''
** based on 5.1.1 with k1 and k2 (filter params) limited to k1<16 and k2<32 in order to resolve the timing when compiling for smaller Stratix FPGA on RC Rev. B.

* '''Bug fix:'''
** the 2-rows-off filtered data readout introduced with configurable filter in rev. 5.1.0 and 5.1.1 is fixed now.

* '''Bugs:'''
** none so far.

* '''FPGA Resource Usage and Timing Report''' (readout_card.fit.rpt and readout_card.tan.rpt): TO BE UPDATED LATER

== Revision 5.1.1 (not recommended) ==
* '''Filename:'''
** rc_v05010001_01dec2010.sof (for Rev. B cards)

* '''Features:'''
** based on 5.1.0, but k1 and k2 (filter params) are now limited to k1<16 and k2<32 in order to resolve the timing failures of compiling 5.1.0 for smaller Stratix FPGA on RC Rev. B.

* '''Bugs:'''
** filter mode data is off by 2 rows.

== Revision 5.1.0 (not recommended) ==
* '''Filename:'''
** rc_stratix3_v05010000_01nov2010.sof (for Rev. E cards)
** rc_v05010000_01nov2010.sof (for Rev. B cards) has timing failures '''do not use!!!'''

* '''Features:'''
** added configurable filter parameters specified by ''fltr_coeff'', default is the fcutoff/fsampl=122Hz/15kHz. see [[ Digital 4-pole Butterworth Low-pass filter ]].
** ''fltr_type'' is set to 255 to indicate configurable filter parameters.
** see [http://www.phas.ubc.ca/~mce/mcedocs/software/SC2_ELE_S580_515_mce_command_description.pdf MCE command description]
** development notes:
*** It is built on Quartus10.1.
*** tcl files had to be updated as cmp syntax is not supported in Q10 anymore.
*** Rev. E cards now can be identified by reading back pcb_rev as part of card_type, therefore both stratix I and III sof/pof/jic are generated from the same source.

* '''Bugs:'''
** rc_v05010000_01nov2010.sof has timing failures that were overlooked, do not use this firmware for Rev.B cards.
** '''filter mode data is off by 2 rows.'''

* '''FPGA Resource Usage and Timing Report''' (readout_card.fit.rpt and readout_card.tan.rpt): logic usage is upto 85% from 66% in 5.0.d/e/f

= Revision 5.0.f =
* '''Filename:'''
** rc_v0500000f_22oct2010.sof (for Rev. B cards)
** rc_stratix3_v0500000f_22oct2010.sof (for Rev. E cards)

* '''Features:'''
** Bugfix: integral clamp should work now. only positive integral_clamp values are valid!

* '''Details:''': SQ1FB is applied 18 clock cycles after start of a row visit (SQ1_Bias being applied) regardless of flux-jump being enabled or not. In pre-5.0.b firmware SQ1FB was being applied after 7 clock cycles when flux-jump was disabled and after 18 clock cycles when flux-jump was enabled.
** available for both Rev. E and Rev. B cards, the upper byte of card_type parameter now reports the pcb revision.
** development note: It is built on Quartus10.1.

* '''Bugs:'''
**none yet!

* '''FPGA Resource Usage and Timing Report''' (readout_card.fit.rpt and readout_card.tan.rpt): no change compared to 5.0.a/b/c/d

== Revision 5.0.e (not recommended) ==
* '''Filename:'''
** rc_v0500000e_06oct2010.sof

* '''Details:'''
** an unsuccessful attempt to fix integral_clamp, but changed the functionality so that it clamps at the value, but it doesn't hold the clamp. i.e., if the calculated sq1fb becomes less than the specified clamp value, the sq1fb is not clamped anymore. This is not a desired functionality!

= Revision 5.0.d =
* '''Filename:'''
** rc_v0500000d_04aug2010.sof

* '''Features:'''
** Bugfix: To fix the bug associated with negative flux-jumps, reverted to signed multiplier and hence, incremented the width of the flux-quanta multiplier input by 1.

* '''Details:''': SQ1FB is applied 18 clock cycles after start of a row visit (SQ1_Bias being applied) regardless of flux-jump being enabled or not. In pre-5.0.b firmware SQ1FB was being applied after 7 clock cycles when flux-jump was disabled and after 18 clock cycles when flux-jump was enabled.

* '''Bugs:'''
** '''integral_clamping is broken'''. To test the clamping, a servo-locked ramp was initiated on the sq1fb and then flux-jumping was turned on and observed by attaching a scope to the SQ1FB output. With integral_clamp=80000000, flux_quanta=8000, gaini=1, flux-jump enabled, we see [[http://e-mode.phas.ubc.ca/mcewiki/index.php/Image:Clamp_unstable.png scope snapshot]] used slow_fb_ramp.py script for testing.

* '''FPGA Resource Usage and Timing Report''' (readout_card.fit.rpt and readout_card.tan.rpt): no change compared to 5.0.a/b/c

== Revision 5.0.c (not recommended) ==
* '''Filename:'''
** rc_v0500000c_16jun2010.sof

* '''Features:'''
** Based on rev. 5.0.b
** Re-introduced flux-jump counter clamping to maintain continuity in behavior from past versions of firmware in the field.
** '''Important''': SQ1FB is applied 18 clock cycles after start of a row visit (SQ1_Bias being applied) regardless of flux-jump being enabled or not. In pre-5.0.b firmware SQ1FB was being applied after 7 clock cycles when flux-jump was disabled and after 18 clock cycles when flux-jump was enabled.

* '''Details:'''
* '''Bugs:'''
** '''flux-jump is broken'''. flux-jumping block misbehaves at the first jump in the negative range.

* '''FPGA Resource Usage''' (readout_card.fit.rpt): [[rc_5.0.c_fit_rpt]]
; Total logic elements ; 26,800 / 41,250 ( 65 % ) ;
; Total pins ; 358 / 616 ( 58 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;
; DSP block 9-bit elements ; 76 / 112 ( 68 % ) ;
; Total PLLs ; 1 / 6 ( 17 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt): [[rc_5.0.c_tan_rpt]]
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.964 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 4.382 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 15.924 ns ;

== Revision 5.0.b (not recommended) ==
* '''Filename:'''
** rc_v0500000b_03jun2010.sof

* '''Features:'''
** Based on rev. 5.0.a
** A bug that caused jumps in first-stage feedback, and detected as spikes in the raw data of pixels that were in servo_mode=0,1,2 was fixed. The jumps in FSFB were due to flux-jumping being enabled on live pixes with non-zero flx_quanta, and being disabled on the fly on dead pixels with flx_quanta=0. Flux-jumping is now disabled on a column-by-column basis if a column is in servo_mode = 0,1,2.
** Ineffective clamping was removed from the flux-jumping block (as per 5.0.9), as it is now replaced by the clamping that was perfected in rev. 5.0.10
** A sticky bit that only affected servo_mode=0,1,2 was also removed from the flux-jumping block.
** flx_lp_init commands now also clear the flux-jumping block as well.
** The 11-clock-cycle delay (in applying SQ1_FB) that in previous firmware only occurred when flux-jumping was enabled, now (in this version) is in effect all the time. Due to the bug-fix above, flux-jumping can be disabled on a column-by-column basis by setting servo_mode=0,1,2 when en_fb_jump=1. Before the change, this meant that constant values could be applied with or without the 11-cycle delay if en_fb_jump=1 or 0. To make the delay consistent, it is now always 11 cycles. As background, the flux-jumping block is pipelined, meaning that it does calculations for all 8 channels serially. The serialization is because of DSP-block limitations in the Readout Card FPGA that prevent us from doing all 8 channels in parallel. The reason that it takes 11 cycles to complete the flux-jumping calculations is because the values are computed for the eight channels in three ALU stages: 8 + 3 = 11 cycles. Adding 11 cycles to the 7 cycles of latency from other stages in the system results in: 11 + 7 = 18 cycles of latency from the start of a row dwell period before the first-stage feedback is applied. In rc_v5.0.c, I enforce the 18-cycle delay even when flux-jumping is not enabled to maintain uniformity across all eight channels, because flux-jumping is enabled/disabled on a per-channel basis. In other words, if I hadn't enforced the 18-cycle delay, some channels could have their feedback applied after 7 cycles, while others could have it applied after 18 cycles. I wasn't a fan of this non-uniformity. I realize that 18 cycles is a long time. In fact, so is 7. In the last few months, we have been discussing how to reduce these times to 1 cycle, because every experiment out there wants to multiplex as fast as possible, and the 7/18-delay is a rate limiting step.
** The flux-jumping code was re-arranged in the flux-jumping block to reflect the flow of data through the pipeline and make it easier to understand.

* '''Details:'''

* '''Bugs:'''
** flux-jump does not work when jumping to negative values.

* '''FPGA Resource Usage''' (readout_card.fit.rpt): [[rc_5.0.b_fit_rpt]]
* '''FPGA Timing Analysis''' (readout_card.tan.rpt): [[rc_5.0.b_tan_rpt]]

= Revision 5.0.a =
* '''Filename:'''
** rc_v0500000a_12mar2010.sof

* '''Features:'''
** Based on the merger of rev. 5.0.8 and 5.0.9.
** '''integral_clamp''' command is added where a clamp value is set for the integral term and once the integral term hits that value, the integral-term is clamped to that value and p-term and d-term are clamped to zero. When integral_term=0 then no clamping is in effect, similar to previous releases of firmware.
** The low pass filter has 20-bit input and f_3dB/f_samp = 122Hz/15kHz .
** The flux-jump clamping that was removed in 5.0.9 is included once again here, as we decided this is safer for now.

* '''Details:'''
** "lock_dat_left" parameter that was removed in 5.0.9 is now implemented as "lock_dat_lsb"

* '''Bugs:'''
** flx_lp_init does not reinitialize the flux-jump block

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis
** tag name: rc_v0500000a_12mar2009! years were mixed up!

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
* '''FPGA Timing Analysis''' (readout_card.tan.rpt):

== Revision 5.0.9 (buggy) ==
* '''Filename:'''
** rc_v05000009_13nov2009.sof

* '''Features:'''
** Based on rev. 5.0.4
** Removes a sticky bit in pid calculation result storage -- in fsfb_processor.
** Adds a command to clamp the growth of the I-term to prevent wrapping and track down the source of Caltech's FSFB jumps.
** Removed the unused lock_dat_left parameter. The ability to shift left was moved to the fsfb_corr block some time ago.
** Fixed a sign extension bug acting on the flux quanta, which limited the value to 8191. Changed the extension from signed to unsigned.
** Removed ineffective clamping in the flux-jump calculation block.
** IMPORTANT: Must be used in conjunction with firmware rev. 5.0.0+ of all other cards.

* '''Details:'''

* '''Bugs:'''
** integral_clamp read/write command does not work.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 27,960 / 41,250 ( 68 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.825 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.878 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 14.397 ns ;

== Revision 5.0.8 (UBC only) ==
* '''Filename:'''
** rc_v05000008_09oct2009.sof

* '''Features:'''
** Based on rev. 5.0.4
** type 1 low-pass filter: f3dB=122Hz for fsample=15kHz
** Filter-input-width changed from 18b to 20b with no sticky bits!
** removed sticky bits in internal arithmetic of the filter.

= Revision 5.0.7 (type-2 filter) =
* '''Filename:'''
** rc_v05000007_09oct2009.sof

* '''Features:'''
** Based on rev. 5.0.4
** type-2 low-pass-filter: f3dB=75Hz for fsample=30000.
** Filter-input-width changed from 18b to 20b with no sticky bits!
** inter-biquad-gain-scaling for the filter is 2^14
** filter results are scaled down by 2^3 in the output of the filter.
** removed sticky bits in internal arithmetics
** _correction_ disabled in fsfb_proc_pidz

* '''Details:'''
** quartus.ini file was '''not''' present in synth directory.

* '''Bugs:'''
** none to report

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
== Revision 5.0.6 (UBC only) ==
* '''Filename:'''
** rc_stratix3_v05000006_15sep2009.sof

* '''Features:'''
** Only Valid for Rev. C/D Cards
** Based on rev. 5.0.3
** tcl file updated for Rev. D and aligned with top-level and qsf (project file).
** flux loop commented, just to try sampling the ADC.
** compiled with Q9.1

== Revision 5.0.5 (UBC only) ==
* '''Filename:'''
** rc_v05000005_04sep2009.sof

* '''Features:'''
** Based on rev. 5.0.2
** changed the low-pass-filter to f(3db)=75Hz for f(sample)=30000.

* '''Details:'''
** quartus.ini file was '''not''' present in synth directory.

* '''Bugs:'''
** negative inputs to the filter cause filter to have a non-flat pass-band region. may have to do with sign-handling...

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
* '''FPGA Timing Analysis''' (readout_card.tan.rpt):

= Revision 5.0.4 =
* '''Filename:'''
** rc_v05000004_28aug2009.sof

* '''Features:'''
** Based on rev. 5.0.2
** BUG Fix: handles 14-bit flux quanta (changed the multiplier to unsigned)
** BUG Fix: changed standard logic vector extension from signed to unsigned in flux-jumping slave.
** IMPORTANT: Must be used in conjunction with firmware rev. 5.0.0+ of all other cards.

* '''Details:'''

* '''Bugs:'''
** None so far.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,170 / 41,250 ( 63 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.541 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.612 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 15.398 ns ;

= Revision 5.0.3 =
* '''Filename:'''
** rc_stratix3_v05000003_21aug2009.sof

* '''Features:'''
** ONLY valid REV C/D RC Cards
** Based on rev. 5.0.2
** flux loop commented, just to try sampling the ADC.
** updated tcl file, but still need to rely on project file as well as qsf file.
** changed default level of adc_sclk to '1'
** dac_clr_n was changed from an output to an input.
** added 'locked' interface to rc_pll_stratix_iii
** renamed the adc_pll clock signals to more explanitory names
** added the FPGA_DEVICE_FAMILY generic to the dispatch interace for synthesis of the dc_fifo in lvds_rx
** uncommented DDR interface to force the syntesizer to use correct left and right PLLs (in conjunction with ADC and DDR PLLs)
** added test signals to test_status to see clocks on the scope.
== Revision 5.0.2 (buggy) ==
* '''Filename:'''
** rc_v05000002_test00_tagged.sof

* '''Features:'''
** Based on rev. 5.0.1
** Fixed a bug in wbs_frame_data that stored data incorrectly if reporting 1 or 2 pixels only.
** IMPORTANT: Must be used in conjunction with firmware rev. 5.0.0+ of all other cards.

* '''Details:'''

* '''Bugs:'''
** None so far.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,186 / 41,250 ( 63 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.755 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.979 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.067 ns ;

== Revision 5.0.1 (buggy) (Filter + Raw + Rectangle, 2 LVDS) ==
* '''Filename:'''
** rc_v05000001_26may2009.sof

* '''Features:'''
** Combines features in rev. 5.0.0 (2 LVDS Lines) and rev. 4.0.e (Filtered + Raw), with the NEW rectangle mode.
** IMPORTANT: Must be used in conjunction with firmware rev. 5.0.0+ of all other cards.

* '''Details:'''
** [[CVS Diff Between sys_v05000000 and rc_v05000001]]

* '''Bugs:'''
** Has a bug in wbs_frame_data that stored data incorrectly if reporting 1 or 2 pixels only.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,565 / 41,250 ( 64 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.656 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.861 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 14.167 ns ;

== Revision 5.0.0 (Filter Only, 2 LVDS) ==
* '''Filename:'''
** rc_v05000000_22dec2008.sof (tagged as sys_v05000000_22dec2008)

* '''Features:'''
** IMPORTANT: Must be used in conjunction with firmware v05000000+ of all other cards!!!
** Adds the ability to read out one column of data continuously from readout cards
** Adds data mode 11, which is an engineering mode. Data points are 32-bits, and bits [9..3]=row_index, [2..0]=column_index. This mode is useful for determining which pixels one is reading out in the array, in column mode for example.

* '''Details:'''
** [[CVS Diff Between rc_v0400000c and sys_v05000000]]

* '''Bugs:'''
** None so far.

* '''Synthesis Notes:'''
** The quartus.ini file was not present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,607 / 41,250 ( 65 % ) ;
; Total memory bits ; 406,016 / 3,423,744 ( 12 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.558 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.892 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.987 ns ;

== Revision 4.0.f (Filter + Raw, 1 LVDS) ==
* '''Filename:'''
** rc_v0400000f_12feb2010.sof

* '''Features:'''
** Based on 4.0.e and in parallel with 5.0.9 (equivalent version, clamping is not included)
** Incorporates fixes that were done to flux-jumping between 5.0.2 - 5.0.4 - 5.0.9. Namely:
*** Changes a multiplier from signed to unsigned (in fsfb_corr_multplier.vhd).
*** Changes sign extension from signed to unsigned (in flux_quanta_ram_admin.vhd).

* '''Details:'''

* '''Bugs:'''
** None reported yet.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,773 / 41,250 ( 65 % ) ;
; Total memory bits ; 1,321,984 / 3,423,744 ( 39 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.539 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 4.118 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 17.318 ns ;

== Revision 4.0.e (Filter + Raw, 1 LVDS) ==
* '''Filename:'''
** rc_v0400000e_27apr2009.sof

* '''Features:'''
** Based on 4.0.d
** Combines both raw- and filtered-data modes.
** fpga_temp, card_temp, card_id commands are disabled.
** Tested by Matt Hasselfield.

* '''Details:'''

* '''Bugs:'''
** fpga_temp, card_temp, card_id commands are disabled.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 27,048 / 41,250 ( 66 % ) ;
; Total memory bits ; 1,321,984 / 3,423,744 ( 39 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.675 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.907 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.728 ns ;

== Revision 4.0.d (Raw Only, 1 LVDS) ==
* '''Filename:''' rc_v0400000d_20090417.sof

* '''Features:'''
** Based on v4.0.c, but has the filter removed, and implements a single 65536-index RAM block for storing 50 MHz raw-data samples.
** The firmware takes a new command called readout_col_index which specifies which column to capture raw data from.
** Other than readout_col_index, the firmware functions the same as previous raw-data firmware, including then need to issue a capture_raw command.
** For more information on raw-data, see: http://e-mode.phas.ubc.ca/mcewiki/index.php/Raw-mode_readout
** This firmware also integrates some of the improvements that were implemented in 4.4.0, like the removal of the tga_o signal from an FSM in dispatch_wishbone.vhd.

* '''Details:'''
** Differences between 4.0.c and 4.0.d
U system/test/source/tb/tb_cc_rcs_bcs_ac.vhd
U all_cards/dispatch/source/rtl/dispatch_wishbone.vhd
U library/sys_param/source/rtl/wishbone_pack.vhd
U readout_card/adc_sample_coadd/source/rtl/adc_sample_coadd.vhd
U readout_card/adc_sample_coadd/source/rtl/adc_sample_coadd_pack.vhd
U readout_card/flux_loop/source/rtl/flux_loop.vhd
U readout_card/flux_loop/source/rtl/flux_loop_pack.vhd
U readout_card/flux_loop_ctrl/source/rtl/flux_loop_ctrl.vhd
U readout_card/flux_loop_ctrl/source/rtl/flux_loop_ctrl_pack.vhd
U readout_card/flux_loop_ctrl/source/tb/tb1_flux_loop_ctrl.vhd
U readout_card/flux_loop_ctrl/source/tb/tb2_flux_loop_ctrl.vhd
U readout_card/fsfb_calc/source/rtl/fsfb_fltr_regs.vhd
U readout_card/fsfb_corr/source/rtl/fsfb_corr.vhd
U readout_card/readout_card/source/rtl/readout_card.vhd
U readout_card/readout_card/source/rtl/readout_card_pack.vhd
U readout_card/wbs_frame_data/source/rtl/wbs_frame_data.vhd
U readout_card/wbs_frame_data/source/rtl/wbs_frame_data_pack.vhd

* '''Bugs:'''
** None so far.
** fpga_temp, card_temp, card_id commands are not supported.

* '''Synthesis Notes:'''
** The quartus.ini file was present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 24,554 / 41,250 ( 60 % ) ;
; Total memory bits ; 1,262,592 / 3,423,744 ( 37 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.991 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.864 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 17.052 ns ;

== Revision 4.4.1 ==
* '''Filename:''' rc_v04040001_21nov2008

* '''Features:'''
** Fixes a bug that froze up the firmware if any of the following commands were issued: CARD_ID_ADDR, CARD_TEMP_ADDR, FPGA_TEMP_ADDR in 4.4.0 only.

* '''Details:'''
** The bug fix include adding more logic to the wishbone ack path (readout_card.vhd), which subsequently decreased the minimum clock setup time to 1.588ns. The new logic will catch errors that the old logic wouldn't have, and is now consistent with the firmware on all the other cards. However, if timing becomes an issue, the logic may have to revert back to that which was in version 4.0.c.

* '''Bugs:'''
** None so far.

* '''Synthesis Notes:'''
** The quartus.ini file was not present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 27,241 / 41,250 ( 66 % ) ;
; Total memory bits ; 405,504 / 3,423,744 ( 12 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.588 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.585 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 17.057 ns ;

== Revision 4.4.0 (buggy) ==
* '''Filename:''' rc_v04040000_02oct2008
* '''Features:'''
** Reinstated the data modes in wbs_frame_data.vhd that were removed in 4.0.c. This firmware has the following modes: '''0, 1, 2, 4, 5, 7, 10'''. The modes that are not present are: '''3''' (raw data), '''6''' (replaced by data_mode = 7), '''8''' (replaced by data_mode = 10), '''9''' (replaced by data_mode = 10). For more information on data modes, see [[Data mode]].
** Re-integrated the id_thermo and fpga_thermo block in the readout_card.vhd top level that was removed in 4.0.c.
** Removed the sticky bit in fsfb_corr.vhd, which was enabled when flux-jumping was turned on. Because the feedback is signed, the sticky bit would usually reflect the value of the 14th bit, except in situations when the number of flux quanta to jump was greater than 1 (i.e. cosmic rays, IV-curves, etc). Flux jumps are made at a maximum rate of one per frame period, so that if the First-Stage Feedback increased past the 13th bit, it would not be reflected in the feedback applied. Now it is.
* '''Details:'''
** Simplified the FSM logic in wbs_frame_data.vhd that determines when to transition from IDLE to WSS1. This was done to lower the number of gates in that path, and ease the timing.
** Removed the z_dat_i port in fsfb_processor.vhd and fsfb_calc_pack.vhd to the fsfb_proc_pidz block, in an effort to make it clearer within that block that the z-term is always = 0.
** Removed the z-term sign extension in fsfb_proc_pidz.vhd, and the [d-term + z-term] adder to free up DSP resources since the z-term is always = 0.
** Adjusted the indentation in fsfb_io_controller.vhd to make the file more readable.
** Moved the tga_o signal out of the dispatch_wishbone.vhd FSM, and made it a continuous assignment. This signal had one of the highest fan-out counts in the RTL design, and actually was impossible to route in Stratix III chips in its previous configuration because of the number of gates on the fan-out. As a consequence of making it a continuous assignment, the Stratix III fitter was able to succeed, and the Stratix I timing characteristics were greatly improved. This is the most significant change in this revision. This change single-handedly increased the minimum slack from 1.282 ns in v0400000c to 2.372 ns (or 56.7 MHz max) in this revision.
* '''Bugs:'''
** The following commands lock up the Readout Card firmware: CARD_ID_ADDR, CARD_TEMP_ADDR, FPGA_TEMP_ADDR.
** fb_const0 commands to channel 0 do not work. The value is stored in the register, but not applied to the DAC. Thus, read-back returns the correct value, but the DAC does not
* '''Synthesis Notes:'''
** The quartus.ini file was not present in the synth directory during synthesis.
* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 27,099 / 41,250 ( 66 % ) ;
; Total memory bits ; 406,016 / 3,423,744 ( 12 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.372 ns ;
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 4.052 ns ;
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.066 ns ;

== Revision 4.0.c ==
* '''Filename:''' rc_v0400000c_15aug2008.sof
* '''Features:'''
** Only has data modes 0, 1, 4, and 10.
** Fixed the bug that exists in 4.0.b, 4.0.a, and 4.0.9 that prevented the fb_const value from being applied to channel zero (wbs_fb_data.vhd).
* '''Details:'''
** Changed a counter in the dispatch block to ease timing constraints in synthesis (dispatch_wishbone.vhd)
** Updated the tagged versions of dispatch.vhd , dispatch_cmd_receive.vhd, and dispatch_reply_transmit.vhd to the version that is used by all the other cards.
** '''Removed''' the fpga_termo (command: '''fpga_temp''') and id_thermo (commands: '''card_temp, card_id''') to ease timing constraints in synthesis (readout_card.vhd)
** Updated the tagged version of fpga_termo.vhd to include the new 'stale bit' feature
** Updated the tagged version of frame_timing_core.vhd to include the new 'err_o' interface
* '''Bugs:'''
** None reported yet
* '''Synthesis Notes:'''
** The quartus.ini file was not present in the synth directory during synthesis.
* '''FPGA Resource Usage:'''
Total logic elements : 25,058 / 41,250 ( 61 % )
Total memory bits : 400,896 / 3,423,744 ( 12 % )

* '''Timing Analysis''' (readout_card.tan.rpt):
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.282 ns ;
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.736 ns ;
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.665 ns ;

== Revision 4.0.b (buggy) ==
Note: This revision is on a watch list, after the bug detected 15 July 2008. See the bug section for more details.
* '''Filename''' : rc_v0400000b_04aug2008.sof
* '''Features'''
** data_mode 10 is added to provide more filtfb bits (compared to data mode 9) for planet observations. filtered_dat(27 downto 3) & flux_cnt_dat(6 downto 0)

* '''Bugs'''
** An unexplained bug that appeared in 4.0.a and may still be present in 4.0.b is a problem with the readout of channels being clipped out of data reporting. [[Bug 1 Notes]]

* ''' Synthesis note '''
** Quartus.ini removed.

== Revision 4.0.a (buggy) ==
Note: This revision is on a watch list, after the bug detected 15 July 2008. See the bug section for more details.
* '''Filename''' : rc_v0400000a_07jul2008.sof
* '''Bug Fix'''
** mce_status and adc_offset/flx_quanta commands do not fail after power up.
* ''' Synthesis note '''
** Quartus.ini removed.

* '''Bugs'''
** Seems to clip out channel 0 from data reporting.

== Revision 4.0.9 (buggy) ==
* '''Filename''' : rc_v04000009_26jun2008.sof
* '''Features'''
** sa_bias and offset DACs only refreshed when new values are written. (in previous versions, DACs were refreshed every frame)
* '''Bugs'''
** fb_const0 commands to channel 0 do not work. The value is stored in the register, but not applied to the DAC. Thus, read-back returns the correct value, but the DAC does not.
** reading flx_quanta and adc_offset right after power up hangs the reply datapath to CC. resetmce clears this error as temporary solution. the problem is caused by first read ack of the wishbone slave.

== Revision 4.0.8 ==
* '''Filename''' : rc_v04000008_26jun2008.sof
* '''Features'''
** The gaini, gainp, gaind resolution increased to 12-bit, i.e. -2048 to 2047 (formerly 10-bit).

* '''Bug fix'''
** the bug associated with gainpid read before mce_reset is fixed.

* ''' Synthesis note '''
** Quartus.ini removed.

== Revision 4.3.7 ==
* '''Filename''' : rc_v04030007_26may2008_raw.sof
* '''Features'''
** 14-bit raw mode enabled to buffer a snapshot of 50MHz samples for 2 frames of row_len * num_rows samples.
** In order to extend the raw-mode to 14-bit, an assumption is made that the raw buffer is not written to while being read. Therefore, make sure there is at least 2*row_len*num_rows*20ns between issuing captr_raw command and reading back the raw data.
** In order to save RAM for raw mode, two memory-intensive features are disabled:
*** low-pass filter disabled ( mixed filtfb data modes 6, 7, 9 are also disabled)
*** PID (gainp0, gaini0, gaind0) readback disabled. one can still set PID values and run servo, but can not read back the values.

== Revision 4.2.7 ==
* '''Filename''' : rc_v04020007_24may2008_raw.sof
* '''Features'''
** raw mode enabled to buffer a snapshot of 50MHz samples for 2 frames of row_len * num_rows samples.
** In order to save RAM for raw mode, two memory-intensive features are disabled:
*** low-pass filter disabled ( mixed filtfb data modes 6, 7, 9 are also disabled)
*** PID (gainp0, gaini0, gaind0) readback disabled. one can still set PID values and run servo, but can not read back the values.
* '''Bug fix'''
** the bug associated with reading from raw-buffer is fixed.

== Revision 4.1.7 ==
* '''Filename''' : rc_v04010007_25apr2008_raw.sof
* '''Features'''
** raw mode enabled to buffer a snapshot of 50MHz samples for 2 frames of row_len * num_rows samples.
** In order to save RAM for raw mode, two memory-intensive features are disabled:
*** low-pass filter disabled ( mixed filtfb data modes 6, 7, 9 are also disabled)
*** PID (gainp0, gaini0, gaind0) readback disabled. one can still set PID values and run servo, but can not read back the values.
* '''Bugs'''
** after each readout frame, raw-buffer readout counter falls behind by 3 and this causes skipping 3 50MHz samples in the data stream and column-data being messed up in subsequent frames. Data can be rearranged by post processing.

== Revision 4.0.6 (buggy) ==
* '''Filename''' : rc_v04000006_15feb2008.sof or .pof
* '''Features'''
** '''bugfix''': unreliable reset due to unsafe and incomplete state machines is fixed.
** '''bugfix''': flux_jump sign problem fixed, so far proved in const_mode, to be tested in servo_mode with cold setup.
** servo_mode=2 or ramp previously only went from 0 to ramp_amp, but now goes from -8192 to -8192+ramp_amp
** new commands are added: ''scratch'' and ''card_type''. Scratch takes 8 values and can be used by software to detect reset.
** slot_id and fw_rev are now integrated as part of all_cards.vhd
** lvds_tx_b=0, This will allow Clock Card to use the secondary backplane lvds line and check whether RC is plugged in.
** filter_coeff in misc_banks_admin commented as it is not implemented and causes timing problems.

* '''Bugs'''
** reading gainp/gaini/gaind right after power up hangs the reply datapath to CC. resetmce clears this error as temporary solution. the problem is caused by first read ack of pid_ram_admin.
** slot_id is only set after a resetmce is issued. (using the latest all_cards in the next revision will fix this)
** has spurious spikes on channel 7 data, which max out the integral, and cause the detectors to come unlocked. This firmware officially meets timing requirements, but the bug could be due to marginal timing on the longest data paths, i.e. ~0.1 ns in some cases.

== Revision 4.0.5 ==
* '''Filename''' : rc_v04000005_01nov2007.sof or .pof
* '''Features'''
** data mode 9 (mixed filt + flux jump) with windowing readjusted compared to data mode 8

* '''Bugs'''
** unreliable resetmce. Sometimes, firmware waked up non-responsive on lvds lines.
** In data mode 5 and 9, flux-jump counter is not reported properly due to a sign error. However, flux jumping works fine.

== Revision 3.0.19 ==
* '''Filename''' : rc_v03000019_16feb2007_raw.sof (no pof as one is not likely to run with this as regular firmware)
* '''Features'''
** data mode 3 is enabled.
** filter is disabled as a compromise to fit the raw-mode buffer.

* '''Bugs'''
** unreliable resetmce. Sometimes, firmware waked up non-responsive on lvds lines.

== Old Firmware Revisions ==
* '''4.0.4''': rc_v04000004_11oct2007.sof data mode 8 added (mixed filt + flux jump)
* '''4.0.3''': rc_v04000003_19sep2007.sof data mode 7 bit split readjusted to 10b error being bit 4 to 14
* '''4.0.2''': rc_v04000002_11sep2007.sof pid resolution increased to 10b, data mode 7 added
* '''4.0.1''': rc_v04000001_06sep2007.sof
* '''4.0.0''': rc_v04000000_29aug2007.sof supports readout_row_index * [[ bugs ]]

= To-Do List =
* the starting point for the servo is currently zero and it would be nice to have it programmable.

= RC Synthesis Notes =
# The following note applies when using Quartus versions earlier than Q7: Quartus.ini file had to exist in synth directory up to revision 4.0.a due to a bug that started in Quartus 6.1 and would synthesize away arbitrary parts of readout card. We contacted Altera at the time and they provided us the ini file.
# Timing: There is no "lock region" defined for readout card. Timing on readout card is tight and since version 3 or so any new feature would initially fail timing till some synthesis options were tweaked. One path that remains to be consistently marginal is from addr_gen counter (i.e. tga_o counter) in dispatch_wishbone.vhd to wishbone slaves particularly misc_banks_admin.vhd. Modules that are rewritten to address timing concerns are fsfb_corr, all_cards, misc_banks_admin, and finally instantiating an lpm counter instead of a counter from components library. Surprisingly, the lpm counter reduced 87 failures to 37, although looking at the technology map viewer, it seemed that they were both synthesized the same.
# Compile time: This was at some point 4.5 hours, after going to dual core PC, this was reduced to 35 minutes. After extending pid gains to 12b and fixing offset/sa_bias update code, the compile time increased to 1.5hr again with utilization up to ~70%.
# wbs_fb_storage, ram_8x64, pid_ram had to be regenerated using latest (Q7.2) MegaWizard to get rid of the bug associated with failure to read after power up until a reset was issued.
# During simulations, the initialization of RAM block with .hex files needs to be disabled. This is done by commenting out the following lines from the MegaWizard generated Megafunction files (remember to un-comment them before synthesizing the code):
lpm_file => "C:/scuba2_repository/cards/readout_card/fsfb_calc/source/rtl/ram_40x64.hex", and
lpm_file : STRING;
#Starting Q10.0 use TimeQuest timing analyzer as oppose to the classic one. The classic one is being phased out by Altera. In order to use TimeQuest, you need to have an sdc file present in your project directory.
----
[http://e-mode.phas.ubc.ca/mcewiki/index.php/Main_Page MCE Main Page]

Readout Card firmware

2011-05-04T21:28:03Z

Bburger: /* Revision 5.0.c (not recommended) */

* Synthesis Reminders (for firmware developers)
** quartus.ini is not needed anymore (Fixed as of Q7, Altera SR10783580 2010-10-24)
** Remember that readout_card/fsfb_clac/source/rtl/ram_40x64.vhd must be initialized with the ram_40x64.hex file in the same directory.
= Revision 5.1.2 =
* '''Filename:'''
** rc_stratix3_v05010002_18jan2011.sof (for Rev. E cards)
** rc_stratix3_v05010002_18jan2011.jic (for Rev. E cards)
** rc_v05010002_03feb2011.sof (for Rev. B cards)
** rc_v05010002_03feb2011.pof (for Rev. B cards)

* '''Features:'''
** based on 5.1.1 with k1 and k2 (filter params) limited to k1<16 and k2<32 in order to resolve the timing when compiling for smaller Stratix FPGA on RC Rev. B.

* '''Bug fix:'''
** the 2-rows-off filtered data readout introduced with configurable filter in rev. 5.1.0 and 5.1.1 is fixed now.

* '''Bugs:'''
** none so far.

* '''FPGA Resource Usage and Timing Report''' (readout_card.fit.rpt and readout_card.tan.rpt): TO BE UPDATED LATER

== Revision 5.1.1 (not recommended) ==
* '''Filename:'''
** rc_v05010001_01dec2010.sof (for Rev. B cards)

* '''Features:'''
** based on 5.1.0, but k1 and k2 (filter params) are now limited to k1<16 and k2<32 in order to resolve the timing failures of compiling 5.1.0 for smaller Stratix FPGA on RC Rev. B.

* '''Bugs:'''
** filter mode data is off by 2 rows.

== Revision 5.1.0 (not recommended) ==
* '''Filename:'''
** rc_stratix3_v05010000_01nov2010.sof (for Rev. E cards)
** rc_v05010000_01nov2010.sof (for Rev. B cards) has timing failures '''do not use!!!'''

* '''Features:'''
** added configurable filter parameters specified by ''fltr_coeff'', default is the fcutoff/fsampl=122Hz/15kHz. see [[ Digital 4-pole Butterworth Low-pass filter ]].
** ''fltr_type'' is set to 255 to indicate configurable filter parameters.
** see [http://www.phas.ubc.ca/~mce/mcedocs/software/SC2_ELE_S580_515_mce_command_description.pdf MCE command description]
** development notes:
*** It is built on Quartus10.1.
*** tcl files had to be updated as cmp syntax is not supported in Q10 anymore.
*** Rev. E cards now can be identified by reading back pcb_rev as part of card_type, therefore both stratix I and III sof/pof/jic are generated from the same source.

* '''Bugs:'''
** rc_v05010000_01nov2010.sof has timing failures that were overlooked, do not use this firmware for Rev.B cards.
** '''filter mode data is off by 2 rows.'''

* '''FPGA Resource Usage and Timing Report''' (readout_card.fit.rpt and readout_card.tan.rpt): logic usage is upto 85% from 66% in 5.0.d/e/f

= Revision 5.0.f =
* '''Filename:'''
** rc_v0500000f_22oct2010.sof (for Rev. B cards)
** rc_stratix3_v0500000f_22oct2010.sof (for Rev. E cards)

* '''Features:'''
** Bugfix: integral clamp should work now. only positive integral_clamp values are valid!

* '''Details:''': SQ1FB is applied 18 clock cycles after start of a row visit (SQ1_Bias being applied) regardless of flux-jump being enabled or not. In pre-5.0.b firmware SQ1FB was being applied after 7 clock cycles when flux-jump was disabled and after 18 clock cycles when flux-jump was enabled.
** available for both Rev. E and Rev. B cards, the upper byte of card_type parameter now reports the pcb revision.
** development note: It is built on Quartus10.1.

* '''Bugs:'''
**none yet!

* '''FPGA Resource Usage and Timing Report''' (readout_card.fit.rpt and readout_card.tan.rpt): no change compared to 5.0.a/b/c/d

== Revision 5.0.e (not recommended) ==
* '''Filename:'''
** rc_v0500000e_06oct2010.sof

* '''Details:'''
** an unsuccessful attempt to fix integral_clamp, but changed the functionality so that it clamps at the value, but it doesn't hold the clamp. i.e., if the calculated sq1fb becomes less than the specified clamp value, the sq1fb is not clamped anymore. This is not a desired functionality!

= Revision 5.0.d =
* '''Filename:'''
** rc_v0500000d_04aug2010.sof

* '''Features:'''
** Bugfix: To fix the bug associated with negative flux-jumps, reverted to signed multiplier and hence, incremented the width of the flux-quanta multiplier input by 1.

* '''Details:''': SQ1FB is applied 18 clock cycles after start of a row visit (SQ1_Bias being applied) regardless of flux-jump being enabled or not. In pre-5.0.b firmware SQ1FB was being applied after 7 clock cycles when flux-jump was disabled and after 18 clock cycles when flux-jump was enabled.

* '''Bugs:'''
** '''integral_clamping is broken'''. To test the clamping, a servo-locked ramp was initiated on the sq1fb and then flux-jumping was turned on and observed by attaching a scope to the SQ1FB output. With integral_clamp=80000000, flux_quanta=8000, gaini=1, flux-jump enabled, we see [[http://e-mode.phas.ubc.ca/mcewiki/index.php/Image:Clamp_unstable.png scope snapshot]] used slow_fb_ramp.py script for testing.

* '''FPGA Resource Usage and Timing Report''' (readout_card.fit.rpt and readout_card.tan.rpt): no change compared to 5.0.a/b/c

== Revision 5.0.c (not recommended) ==
* '''Filename:'''
** rc_v0500000c_16jun2010.sof

* '''Features:'''
** Based on rev. 5.0.b
** Re-introduced flux-jump counter clamping to maintain continuity in behavior from past versions of firmware in the field.
** '''Important''': SQ1FB is applied 18 clock cycles after start of a row visit (SQ1_Bias being applied) regardless of flux-jump being enabled or not. In pre-5.0.b firmware SQ1FB was being applied after 7 clock cycles when flux-jump was disabled and after 18 clock cycles when flux-jump was enabled.

* '''Details:'''
* '''Bugs:'''
** '''flux-jump is broken'''. flux-jumping block misbehaves at the first jump in the negative range.

* '''FPGA Resource Usage''' (readout_card.fit.rpt): [[rc_5.0.c_fit_rpt]]
; Total logic elements ; 26,800 / 41,250 ( 65 % ) ;
; Total pins ; 358 / 616 ( 58 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;
; DSP block 9-bit elements ; 76 / 112 ( 68 % ) ;
; Total PLLs ; 1 / 6 ( 17 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt): [[rc_5.0.c_tan_rpt]]

== Revision 5.0.b (not recommended) ==
* '''Filename:'''
** rc_v0500000b_03jun2010.sof

* '''Features:'''
** Based on rev. 5.0.a
** A bug that caused jumps in first-stage feedback, and detected as spikes in the raw data of pixels that were in servo_mode=0,1,2 was fixed. The jumps in FSFB were due to flux-jumping being enabled on live pixes with non-zero flx_quanta, and being disabled on the fly on dead pixels with flx_quanta=0. Flux-jumping is now disabled on a column-by-column basis if a column is in servo_mode = 0,1,2.
** Ineffective clamping was removed from the flux-jumping block (as per 5.0.9), as it is now replaced by the clamping that was perfected in rev. 5.0.10
** A sticky bit that only affected servo_mode=0,1,2 was also removed from the flux-jumping block.
** flx_lp_init commands now also clear the flux-jumping block as well.
** The 11-clock-cycle delay (in applying SQ1_FB) that in previous firmware only occurred when flux-jumping was enabled, now (in this version) is in effect all the time. Due to the bug-fix above, flux-jumping can be disabled on a column-by-column basis by setting servo_mode=0,1,2 when en_fb_jump=1. Before the change, this meant that constant values could be applied with or without the 11-cycle delay if en_fb_jump=1 or 0. To make the delay consistent, it is now always 11 cycles. As background, the flux-jumping block is pipelined, meaning that it does calculations for all 8 channels serially. The serialization is because of DSP-block limitations in the Readout Card FPGA that prevent us from doing all 8 channels in parallel. The reason that it takes 11 cycles to complete the flux-jumping calculations is because the values are computed for the eight channels in three ALU stages: 8 + 3 = 11 cycles. Adding 11 cycles to the 7 cycles of latency from other stages in the system results in: 11 + 7 = 18 cycles of latency from the start of a row dwell period before the first-stage feedback is applied. In rc_v5.0.c, I enforce the 18-cycle delay even when flux-jumping is not enabled to maintain uniformity across all eight channels, because flux-jumping is enabled/disabled on a per-channel basis. In other words, if I hadn't enforced the 18-cycle delay, some channels could have their feedback applied after 7 cycles, while others could have it applied after 18 cycles. I wasn't a fan of this non-uniformity. I realize that 18 cycles is a long time. In fact, so is 7. In the last few months, we have been discussing how to reduce these times to 1 cycle, because every experiment out there wants to multiplex as fast as possible, and the 7/18-delay is a rate limiting step.
** The flux-jumping code was re-arranged in the flux-jumping block to reflect the flow of data through the pipeline and make it easier to understand.

* '''Details:'''

* '''Bugs:'''
** flux-jump does not work when jumping to negative values.

* '''FPGA Resource Usage''' (readout_card.fit.rpt): [[rc_5.0.b_fit_rpt]]
* '''FPGA Timing Analysis''' (readout_card.tan.rpt): [[rc_5.0.b_tan_rpt]]

= Revision 5.0.a =
* '''Filename:'''
** rc_v0500000a_12mar2010.sof

* '''Features:'''
** Based on the merger of rev. 5.0.8 and 5.0.9.
** '''integral_clamp''' command is added where a clamp value is set for the integral term and once the integral term hits that value, the integral-term is clamped to that value and p-term and d-term are clamped to zero. When integral_term=0 then no clamping is in effect, similar to previous releases of firmware.
** The low pass filter has 20-bit input and f_3dB/f_samp = 122Hz/15kHz .
** The flux-jump clamping that was removed in 5.0.9 is included once again here, as we decided this is safer for now.

* '''Details:'''
** "lock_dat_left" parameter that was removed in 5.0.9 is now implemented as "lock_dat_lsb"

* '''Bugs:'''
** flx_lp_init does not reinitialize the flux-jump block

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis
** tag name: rc_v0500000a_12mar2009! years were mixed up!

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
* '''FPGA Timing Analysis''' (readout_card.tan.rpt):

== Revision 5.0.9 (buggy) ==
* '''Filename:'''
** rc_v05000009_13nov2009.sof

* '''Features:'''
** Based on rev. 5.0.4
** Removes a sticky bit in pid calculation result storage -- in fsfb_processor.
** Adds a command to clamp the growth of the I-term to prevent wrapping and track down the source of Caltech's FSFB jumps.
** Removed the unused lock_dat_left parameter. The ability to shift left was moved to the fsfb_corr block some time ago.
** Fixed a sign extension bug acting on the flux quanta, which limited the value to 8191. Changed the extension from signed to unsigned.
** Removed ineffective clamping in the flux-jump calculation block.
** IMPORTANT: Must be used in conjunction with firmware rev. 5.0.0+ of all other cards.

* '''Details:'''

* '''Bugs:'''
** integral_clamp read/write command does not work.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 27,960 / 41,250 ( 68 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.825 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.878 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 14.397 ns ;

== Revision 5.0.8 (UBC only) ==
* '''Filename:'''
** rc_v05000008_09oct2009.sof

* '''Features:'''
** Based on rev. 5.0.4
** type 1 low-pass filter: f3dB=122Hz for fsample=15kHz
** Filter-input-width changed from 18b to 20b with no sticky bits!
** removed sticky bits in internal arithmetic of the filter.

= Revision 5.0.7 (type-2 filter) =
* '''Filename:'''
** rc_v05000007_09oct2009.sof

* '''Features:'''
** Based on rev. 5.0.4
** type-2 low-pass-filter: f3dB=75Hz for fsample=30000.
** Filter-input-width changed from 18b to 20b with no sticky bits!
** inter-biquad-gain-scaling for the filter is 2^14
** filter results are scaled down by 2^3 in the output of the filter.
** removed sticky bits in internal arithmetics
** _correction_ disabled in fsfb_proc_pidz

* '''Details:'''
** quartus.ini file was '''not''' present in synth directory.

* '''Bugs:'''
** none to report

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
== Revision 5.0.6 (UBC only) ==
* '''Filename:'''
** rc_stratix3_v05000006_15sep2009.sof

* '''Features:'''
** Only Valid for Rev. C/D Cards
** Based on rev. 5.0.3
** tcl file updated for Rev. D and aligned with top-level and qsf (project file).
** flux loop commented, just to try sampling the ADC.
** compiled with Q9.1

== Revision 5.0.5 (UBC only) ==
* '''Filename:'''
** rc_v05000005_04sep2009.sof

* '''Features:'''
** Based on rev. 5.0.2
** changed the low-pass-filter to f(3db)=75Hz for f(sample)=30000.

* '''Details:'''
** quartus.ini file was '''not''' present in synth directory.

* '''Bugs:'''
** negative inputs to the filter cause filter to have a non-flat pass-band region. may have to do with sign-handling...

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
* '''FPGA Timing Analysis''' (readout_card.tan.rpt):

= Revision 5.0.4 =
* '''Filename:'''
** rc_v05000004_28aug2009.sof

* '''Features:'''
** Based on rev. 5.0.2
** BUG Fix: handles 14-bit flux quanta (changed the multiplier to unsigned)
** BUG Fix: changed standard logic vector extension from signed to unsigned in flux-jumping slave.
** IMPORTANT: Must be used in conjunction with firmware rev. 5.0.0+ of all other cards.

* '''Details:'''

* '''Bugs:'''
** None so far.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,170 / 41,250 ( 63 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.541 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.612 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 15.398 ns ;

= Revision 5.0.3 =
* '''Filename:'''
** rc_stratix3_v05000003_21aug2009.sof

* '''Features:'''
** ONLY valid REV C/D RC Cards
** Based on rev. 5.0.2
** flux loop commented, just to try sampling the ADC.
** updated tcl file, but still need to rely on project file as well as qsf file.
** changed default level of adc_sclk to '1'
** dac_clr_n was changed from an output to an input.
** added 'locked' interface to rc_pll_stratix_iii
** renamed the adc_pll clock signals to more explanitory names
** added the FPGA_DEVICE_FAMILY generic to the dispatch interace for synthesis of the dc_fifo in lvds_rx
** uncommented DDR interface to force the syntesizer to use correct left and right PLLs (in conjunction with ADC and DDR PLLs)
** added test signals to test_status to see clocks on the scope.
== Revision 5.0.2 (buggy) ==
* '''Filename:'''
** rc_v05000002_test00_tagged.sof

* '''Features:'''
** Based on rev. 5.0.1
** Fixed a bug in wbs_frame_data that stored data incorrectly if reporting 1 or 2 pixels only.
** IMPORTANT: Must be used in conjunction with firmware rev. 5.0.0+ of all other cards.

* '''Details:'''

* '''Bugs:'''
** None so far.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,186 / 41,250 ( 63 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.755 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.979 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.067 ns ;

== Revision 5.0.1 (buggy) (Filter + Raw + Rectangle, 2 LVDS) ==
* '''Filename:'''
** rc_v05000001_26may2009.sof

* '''Features:'''
** Combines features in rev. 5.0.0 (2 LVDS Lines) and rev. 4.0.e (Filtered + Raw), with the NEW rectangle mode.
** IMPORTANT: Must be used in conjunction with firmware rev. 5.0.0+ of all other cards.

* '''Details:'''
** [[CVS Diff Between sys_v05000000 and rc_v05000001]]

* '''Bugs:'''
** Has a bug in wbs_frame_data that stored data incorrectly if reporting 1 or 2 pixels only.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,565 / 41,250 ( 64 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.656 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.861 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 14.167 ns ;

== Revision 5.0.0 (Filter Only, 2 LVDS) ==
* '''Filename:'''
** rc_v05000000_22dec2008.sof (tagged as sys_v05000000_22dec2008)

* '''Features:'''
** IMPORTANT: Must be used in conjunction with firmware v05000000+ of all other cards!!!
** Adds the ability to read out one column of data continuously from readout cards
** Adds data mode 11, which is an engineering mode. Data points are 32-bits, and bits [9..3]=row_index, [2..0]=column_index. This mode is useful for determining which pixels one is reading out in the array, in column mode for example.

* '''Details:'''
** [[CVS Diff Between rc_v0400000c and sys_v05000000]]

* '''Bugs:'''
** None so far.

* '''Synthesis Notes:'''
** The quartus.ini file was not present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,607 / 41,250 ( 65 % ) ;
; Total memory bits ; 406,016 / 3,423,744 ( 12 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.558 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.892 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.987 ns ;

== Revision 4.0.f (Filter + Raw, 1 LVDS) ==
* '''Filename:'''
** rc_v0400000f_12feb2010.sof

* '''Features:'''
** Based on 4.0.e and in parallel with 5.0.9 (equivalent version, clamping is not included)
** Incorporates fixes that were done to flux-jumping between 5.0.2 - 5.0.4 - 5.0.9. Namely:
*** Changes a multiplier from signed to unsigned (in fsfb_corr_multplier.vhd).
*** Changes sign extension from signed to unsigned (in flux_quanta_ram_admin.vhd).

* '''Details:'''

* '''Bugs:'''
** None reported yet.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,773 / 41,250 ( 65 % ) ;
; Total memory bits ; 1,321,984 / 3,423,744 ( 39 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.539 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 4.118 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 17.318 ns ;

== Revision 4.0.e (Filter + Raw, 1 LVDS) ==
* '''Filename:'''
** rc_v0400000e_27apr2009.sof

* '''Features:'''
** Based on 4.0.d
** Combines both raw- and filtered-data modes.
** fpga_temp, card_temp, card_id commands are disabled.
** Tested by Matt Hasselfield.

* '''Details:'''

* '''Bugs:'''
** fpga_temp, card_temp, card_id commands are disabled.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 27,048 / 41,250 ( 66 % ) ;
; Total memory bits ; 1,321,984 / 3,423,744 ( 39 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.675 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.907 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.728 ns ;

== Revision 4.0.d (Raw Only, 1 LVDS) ==
* '''Filename:''' rc_v0400000d_20090417.sof

* '''Features:'''
** Based on v4.0.c, but has the filter removed, and implements a single 65536-index RAM block for storing 50 MHz raw-data samples.
** The firmware takes a new command called readout_col_index which specifies which column to capture raw data from.
** Other than readout_col_index, the firmware functions the same as previous raw-data firmware, including then need to issue a capture_raw command.
** For more information on raw-data, see: http://e-mode.phas.ubc.ca/mcewiki/index.php/Raw-mode_readout
** This firmware also integrates some of the improvements that were implemented in 4.4.0, like the removal of the tga_o signal from an FSM in dispatch_wishbone.vhd.

* '''Details:'''
** Differences between 4.0.c and 4.0.d
U system/test/source/tb/tb_cc_rcs_bcs_ac.vhd
U all_cards/dispatch/source/rtl/dispatch_wishbone.vhd
U library/sys_param/source/rtl/wishbone_pack.vhd
U readout_card/adc_sample_coadd/source/rtl/adc_sample_coadd.vhd
U readout_card/adc_sample_coadd/source/rtl/adc_sample_coadd_pack.vhd
U readout_card/flux_loop/source/rtl/flux_loop.vhd
U readout_card/flux_loop/source/rtl/flux_loop_pack.vhd
U readout_card/flux_loop_ctrl/source/rtl/flux_loop_ctrl.vhd
U readout_card/flux_loop_ctrl/source/rtl/flux_loop_ctrl_pack.vhd
U readout_card/flux_loop_ctrl/source/tb/tb1_flux_loop_ctrl.vhd
U readout_card/flux_loop_ctrl/source/tb/tb2_flux_loop_ctrl.vhd
U readout_card/fsfb_calc/source/rtl/fsfb_fltr_regs.vhd
U readout_card/fsfb_corr/source/rtl/fsfb_corr.vhd
U readout_card/readout_card/source/rtl/readout_card.vhd
U readout_card/readout_card/source/rtl/readout_card_pack.vhd
U readout_card/wbs_frame_data/source/rtl/wbs_frame_data.vhd
U readout_card/wbs_frame_data/source/rtl/wbs_frame_data_pack.vhd

* '''Bugs:'''
** None so far.
** fpga_temp, card_temp, card_id commands are not supported.

* '''Synthesis Notes:'''
** The quartus.ini file was present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 24,554 / 41,250 ( 60 % ) ;
; Total memory bits ; 1,262,592 / 3,423,744 ( 37 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.991 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.864 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 17.052 ns ;

== Revision 4.4.1 ==
* '''Filename:''' rc_v04040001_21nov2008

* '''Features:'''
** Fixes a bug that froze up the firmware if any of the following commands were issued: CARD_ID_ADDR, CARD_TEMP_ADDR, FPGA_TEMP_ADDR in 4.4.0 only.

* '''Details:'''
** The bug fix include adding more logic to the wishbone ack path (readout_card.vhd), which subsequently decreased the minimum clock setup time to 1.588ns. The new logic will catch errors that the old logic wouldn't have, and is now consistent with the firmware on all the other cards. However, if timing becomes an issue, the logic may have to revert back to that which was in version 4.0.c.

* '''Bugs:'''
** None so far.

* '''Synthesis Notes:'''
** The quartus.ini file was not present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 27,241 / 41,250 ( 66 % ) ;
; Total memory bits ; 405,504 / 3,423,744 ( 12 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.588 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.585 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 17.057 ns ;

== Revision 4.4.0 (buggy) ==
* '''Filename:''' rc_v04040000_02oct2008
* '''Features:'''
** Reinstated the data modes in wbs_frame_data.vhd that were removed in 4.0.c. This firmware has the following modes: '''0, 1, 2, 4, 5, 7, 10'''. The modes that are not present are: '''3''' (raw data), '''6''' (replaced by data_mode = 7), '''8''' (replaced by data_mode = 10), '''9''' (replaced by data_mode = 10). For more information on data modes, see [[Data mode]].
** Re-integrated the id_thermo and fpga_thermo block in the readout_card.vhd top level that was removed in 4.0.c.
** Removed the sticky bit in fsfb_corr.vhd, which was enabled when flux-jumping was turned on. Because the feedback is signed, the sticky bit would usually reflect the value of the 14th bit, except in situations when the number of flux quanta to jump was greater than 1 (i.e. cosmic rays, IV-curves, etc). Flux jumps are made at a maximum rate of one per frame period, so that if the First-Stage Feedback increased past the 13th bit, it would not be reflected in the feedback applied. Now it is.
* '''Details:'''
** Simplified the FSM logic in wbs_frame_data.vhd that determines when to transition from IDLE to WSS1. This was done to lower the number of gates in that path, and ease the timing.
** Removed the z_dat_i port in fsfb_processor.vhd and fsfb_calc_pack.vhd to the fsfb_proc_pidz block, in an effort to make it clearer within that block that the z-term is always = 0.
** Removed the z-term sign extension in fsfb_proc_pidz.vhd, and the [d-term + z-term] adder to free up DSP resources since the z-term is always = 0.
** Adjusted the indentation in fsfb_io_controller.vhd to make the file more readable.
** Moved the tga_o signal out of the dispatch_wishbone.vhd FSM, and made it a continuous assignment. This signal had one of the highest fan-out counts in the RTL design, and actually was impossible to route in Stratix III chips in its previous configuration because of the number of gates on the fan-out. As a consequence of making it a continuous assignment, the Stratix III fitter was able to succeed, and the Stratix I timing characteristics were greatly improved. This is the most significant change in this revision. This change single-handedly increased the minimum slack from 1.282 ns in v0400000c to 2.372 ns (or 56.7 MHz max) in this revision.
* '''Bugs:'''
** The following commands lock up the Readout Card firmware: CARD_ID_ADDR, CARD_TEMP_ADDR, FPGA_TEMP_ADDR.
** fb_const0 commands to channel 0 do not work. The value is stored in the register, but not applied to the DAC. Thus, read-back returns the correct value, but the DAC does not
* '''Synthesis Notes:'''
** The quartus.ini file was not present in the synth directory during synthesis.
* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 27,099 / 41,250 ( 66 % ) ;
; Total memory bits ; 406,016 / 3,423,744 ( 12 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.372 ns ;
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 4.052 ns ;
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.066 ns ;

== Revision 4.0.c ==
* '''Filename:''' rc_v0400000c_15aug2008.sof
* '''Features:'''
** Only has data modes 0, 1, 4, and 10.
** Fixed the bug that exists in 4.0.b, 4.0.a, and 4.0.9 that prevented the fb_const value from being applied to channel zero (wbs_fb_data.vhd).
* '''Details:'''
** Changed a counter in the dispatch block to ease timing constraints in synthesis (dispatch_wishbone.vhd)
** Updated the tagged versions of dispatch.vhd , dispatch_cmd_receive.vhd, and dispatch_reply_transmit.vhd to the version that is used by all the other cards.
** '''Removed''' the fpga_termo (command: '''fpga_temp''') and id_thermo (commands: '''card_temp, card_id''') to ease timing constraints in synthesis (readout_card.vhd)
** Updated the tagged version of fpga_termo.vhd to include the new 'stale bit' feature
** Updated the tagged version of frame_timing_core.vhd to include the new 'err_o' interface
* '''Bugs:'''
** None reported yet
* '''Synthesis Notes:'''
** The quartus.ini file was not present in the synth directory during synthesis.
* '''FPGA Resource Usage:'''
Total logic elements : 25,058 / 41,250 ( 61 % )
Total memory bits : 400,896 / 3,423,744 ( 12 % )

* '''Timing Analysis''' (readout_card.tan.rpt):
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.282 ns ;
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.736 ns ;
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.665 ns ;

== Revision 4.0.b (buggy) ==
Note: This revision is on a watch list, after the bug detected 15 July 2008. See the bug section for more details.
* '''Filename''' : rc_v0400000b_04aug2008.sof
* '''Features'''
** data_mode 10 is added to provide more filtfb bits (compared to data mode 9) for planet observations. filtered_dat(27 downto 3) & flux_cnt_dat(6 downto 0)

* '''Bugs'''
** An unexplained bug that appeared in 4.0.a and may still be present in 4.0.b is a problem with the readout of channels being clipped out of data reporting. [[Bug 1 Notes]]

* ''' Synthesis note '''
** Quartus.ini removed.

== Revision 4.0.a (buggy) ==
Note: This revision is on a watch list, after the bug detected 15 July 2008. See the bug section for more details.
* '''Filename''' : rc_v0400000a_07jul2008.sof
* '''Bug Fix'''
** mce_status and adc_offset/flx_quanta commands do not fail after power up.
* ''' Synthesis note '''
** Quartus.ini removed.

* '''Bugs'''
** Seems to clip out channel 0 from data reporting.

== Revision 4.0.9 (buggy) ==
* '''Filename''' : rc_v04000009_26jun2008.sof
* '''Features'''
** sa_bias and offset DACs only refreshed when new values are written. (in previous versions, DACs were refreshed every frame)
* '''Bugs'''
** fb_const0 commands to channel 0 do not work. The value is stored in the register, but not applied to the DAC. Thus, read-back returns the correct value, but the DAC does not.
** reading flx_quanta and adc_offset right after power up hangs the reply datapath to CC. resetmce clears this error as temporary solution. the problem is caused by first read ack of the wishbone slave.

== Revision 4.0.8 ==
* '''Filename''' : rc_v04000008_26jun2008.sof
* '''Features'''
** The gaini, gainp, gaind resolution increased to 12-bit, i.e. -2048 to 2047 (formerly 10-bit).

* '''Bug fix'''
** the bug associated with gainpid read before mce_reset is fixed.

* ''' Synthesis note '''
** Quartus.ini removed.

== Revision 4.3.7 ==
* '''Filename''' : rc_v04030007_26may2008_raw.sof
* '''Features'''
** 14-bit raw mode enabled to buffer a snapshot of 50MHz samples for 2 frames of row_len * num_rows samples.
** In order to extend the raw-mode to 14-bit, an assumption is made that the raw buffer is not written to while being read. Therefore, make sure there is at least 2*row_len*num_rows*20ns between issuing captr_raw command and reading back the raw data.
** In order to save RAM for raw mode, two memory-intensive features are disabled:
*** low-pass filter disabled ( mixed filtfb data modes 6, 7, 9 are also disabled)
*** PID (gainp0, gaini0, gaind0) readback disabled. one can still set PID values and run servo, but can not read back the values.

== Revision 4.2.7 ==
* '''Filename''' : rc_v04020007_24may2008_raw.sof
* '''Features'''
** raw mode enabled to buffer a snapshot of 50MHz samples for 2 frames of row_len * num_rows samples.
** In order to save RAM for raw mode, two memory-intensive features are disabled:
*** low-pass filter disabled ( mixed filtfb data modes 6, 7, 9 are also disabled)
*** PID (gainp0, gaini0, gaind0) readback disabled. one can still set PID values and run servo, but can not read back the values.
* '''Bug fix'''
** the bug associated with reading from raw-buffer is fixed.

== Revision 4.1.7 ==
* '''Filename''' : rc_v04010007_25apr2008_raw.sof
* '''Features'''
** raw mode enabled to buffer a snapshot of 50MHz samples for 2 frames of row_len * num_rows samples.
** In order to save RAM for raw mode, two memory-intensive features are disabled:
*** low-pass filter disabled ( mixed filtfb data modes 6, 7, 9 are also disabled)
*** PID (gainp0, gaini0, gaind0) readback disabled. one can still set PID values and run servo, but can not read back the values.
* '''Bugs'''
** after each readout frame, raw-buffer readout counter falls behind by 3 and this causes skipping 3 50MHz samples in the data stream and column-data being messed up in subsequent frames. Data can be rearranged by post processing.

== Revision 4.0.6 (buggy) ==
* '''Filename''' : rc_v04000006_15feb2008.sof or .pof
* '''Features'''
** '''bugfix''': unreliable reset due to unsafe and incomplete state machines is fixed.
** '''bugfix''': flux_jump sign problem fixed, so far proved in const_mode, to be tested in servo_mode with cold setup.
** servo_mode=2 or ramp previously only went from 0 to ramp_amp, but now goes from -8192 to -8192+ramp_amp
** new commands are added: ''scratch'' and ''card_type''. Scratch takes 8 values and can be used by software to detect reset.
** slot_id and fw_rev are now integrated as part of all_cards.vhd
** lvds_tx_b=0, This will allow Clock Card to use the secondary backplane lvds line and check whether RC is plugged in.
** filter_coeff in misc_banks_admin commented as it is not implemented and causes timing problems.

* '''Bugs'''
** reading gainp/gaini/gaind right after power up hangs the reply datapath to CC. resetmce clears this error as temporary solution. the problem is caused by first read ack of pid_ram_admin.
** slot_id is only set after a resetmce is issued. (using the latest all_cards in the next revision will fix this)
** has spurious spikes on channel 7 data, which max out the integral, and cause the detectors to come unlocked. This firmware officially meets timing requirements, but the bug could be due to marginal timing on the longest data paths, i.e. ~0.1 ns in some cases.

== Revision 4.0.5 ==
* '''Filename''' : rc_v04000005_01nov2007.sof or .pof
* '''Features'''
** data mode 9 (mixed filt + flux jump) with windowing readjusted compared to data mode 8

* '''Bugs'''
** unreliable resetmce. Sometimes, firmware waked up non-responsive on lvds lines.
** In data mode 5 and 9, flux-jump counter is not reported properly due to a sign error. However, flux jumping works fine.

== Revision 3.0.19 ==
* '''Filename''' : rc_v03000019_16feb2007_raw.sof (no pof as one is not likely to run with this as regular firmware)
* '''Features'''
** data mode 3 is enabled.
** filter is disabled as a compromise to fit the raw-mode buffer.

* '''Bugs'''
** unreliable resetmce. Sometimes, firmware waked up non-responsive on lvds lines.

== Old Firmware Revisions ==
* '''4.0.4''': rc_v04000004_11oct2007.sof data mode 8 added (mixed filt + flux jump)
* '''4.0.3''': rc_v04000003_19sep2007.sof data mode 7 bit split readjusted to 10b error being bit 4 to 14
* '''4.0.2''': rc_v04000002_11sep2007.sof pid resolution increased to 10b, data mode 7 added
* '''4.0.1''': rc_v04000001_06sep2007.sof
* '''4.0.0''': rc_v04000000_29aug2007.sof supports readout_row_index * [[ bugs ]]

= To-Do List =
* the starting point for the servo is currently zero and it would be nice to have it programmable.

= RC Synthesis Notes =
# The following note applies when using Quartus versions earlier than Q7: Quartus.ini file had to exist in synth directory up to revision 4.0.a due to a bug that started in Quartus 6.1 and would synthesize away arbitrary parts of readout card. We contacted Altera at the time and they provided us the ini file.
# Timing: There is no "lock region" defined for readout card. Timing on readout card is tight and since version 3 or so any new feature would initially fail timing till some synthesis options were tweaked. One path that remains to be consistently marginal is from addr_gen counter (i.e. tga_o counter) in dispatch_wishbone.vhd to wishbone slaves particularly misc_banks_admin.vhd. Modules that are rewritten to address timing concerns are fsfb_corr, all_cards, misc_banks_admin, and finally instantiating an lpm counter instead of a counter from components library. Surprisingly, the lpm counter reduced 87 failures to 37, although looking at the technology map viewer, it seemed that they were both synthesized the same.
# Compile time: This was at some point 4.5 hours, after going to dual core PC, this was reduced to 35 minutes. After extending pid gains to 12b and fixing offset/sa_bias update code, the compile time increased to 1.5hr again with utilization up to ~70%.
# wbs_fb_storage, ram_8x64, pid_ram had to be regenerated using latest (Q7.2) MegaWizard to get rid of the bug associated with failure to read after power up until a reset was issued.
# During simulations, the initialization of RAM block with .hex files needs to be disabled. This is done by commenting out the following lines from the MegaWizard generated Megafunction files (remember to un-comment them before synthesizing the code):
lpm_file => "C:/scuba2_repository/cards/readout_card/fsfb_calc/source/rtl/ram_40x64.hex", and
lpm_file : STRING;
#Starting Q10.0 use TimeQuest timing analyzer as oppose to the classic one. The classic one is being phased out by Altera. In order to use TimeQuest, you need to have an sdc file present in your project directory.
----
[http://e-mode.phas.ubc.ca/mcewiki/index.php/Main_Page MCE Main Page]

Integral clamp

2011-05-03T17:55:00Z

Bburger: /* Usage */

This feature was implemented in an effort to eliminate the effects of unlocked and ramping pixels on locked pixels on an array. This feature is available in rev. 5.0.e as a beta release. (A preliminary version was introduced starting RC firmware rev. 5.0.9, but it was not yet functional as of RC firmware 5.0.d.)

= Introduction =
* Typically, the dominant term in the MCE's PID-loop calculation is the accumulated integral. When the operating environment changes, it is possible that some pixels that were locked before can no longer. When this occurs, the integral-term in the PID-loop calculation grows linearly in time until it wraps. Because the FSFB affects the ground-plane level, a large change in the FSFB (i.e. wrapping) causes a considerable level shift in healthy pixels as well.
* Often, these unlocked/ ramping pixels are caught, but only after they ruin observing data. At that time, they are turned off manually, usually by setting p_coeff = i_coeff = d_coeff = 0.
* The goal of the FSFB clamping feature is to stop pixels from ramping at all by clamping them at a user-specified value. If their absolute value exceeds this value, then they are clamped. In this way, unlocked pixels no longer affect the rest of the array after they have reached that value.

= Usage =
* The '''integral_clamp''' parameter is a 32-bit positive number per Readout Card (8x41 pixels) and is set to 0 by default, meaning no clamping is performed by default. The '''integral_clamp''' parameter is used to clamp the calculated servo integral-term (before it is multiplied by the integral coefficient aka gaini) on both positive and negative ends. This prevents unlocked pixels from wrapping continuously in lock mode. The value needs to be determined based on different parameter settings like: gaini, flux-quanta, and other experiment dependent variables. Here is a guide to calculate what the value should be set to.

* Note that this calculation assumes that gainp = gaind = 0.
* No matter how large the calculated value is, it must still allow for a reasonable margin between it and the wrap-point of the I-term. If the margin is too small, then calculated values of the I-term will wrap if the I-term value jumps from I-term < integral_clamp to I-term > I_term_max.
* Note also that when integral_clamp = 0 (default), this feature is disabled.

//Typical for ACT:
wb rc1 gaini0 480 480 ..
wb rc1 flx_quanta0 6500 6500 ..
..(other PID-setup commands)
wb rc1 integral_clamp 6389760
wb rc1 flx_lp_init 1

* To calculate the right integral_clamp value, the maximum valid SQ1 FB value must be converted to an equivalent maximum I-term. Since
fb = gaini * I / 4096
we have
I_max = fb_max * 4096 / gaini

* With flux-jumping '''enabled''', the maximum FB value can be as large as the number of allowable flux jumps (127) times the flux quantum:
fb_max = 127 * flux_quantum
I_max = 127 * 4096 * flux_quantum / gaini

* When flux jumping is '''disabled''', the maximum FB can be taken to lie within a single DAC range (+-8192):
fb_max = 8192
I_max = 8192 * 4096 / gaini

* Including a factor of 0.9 (to keep the clamp value slightly lower than the critical cut-off), and rounding, we have the rules:
integral_clamp ~ I_max * 0.9

{ 30,000,000 / gaini (for flux jumping OFF)
= {
{ 470,000 * flux_quantum / gaini (for flux jumping ON)

* Typical Values (Calculated in data_mode_outputs.xls)
{| border="1"
|-
! Telescope !! Flux Quanta !! I Coefficient
! integral_clamp
(Flux Jumping ON)
! integral_clamp
(Flux Jumping OFF)
|-
| ACT || 6500 || 480 || 6389760 || 62915
|-
| SPIDER || 9500 || 50 || 89653248 || 603980
|-
| SCUBA-2 || 6500 || 2024 || 1515358 || 14920
|}

Integral clamp

2011-05-03T17:54:40Z

Bburger: /* Usage */

Integral clamp

2011-05-03T17:54:19Z

Bburger: /* Usage */

Integral clamp

2011-05-03T17:52:43Z

Bburger: /* Usage */

This feature was implemented in an effort to eliminate the effects of unlocked and ramping pixels on locked pixels on an array. This feature is available in rev. 5.0.e as a beta release. (A preliminary version was introduced starting RC firmware rev. 5.0.9, but it was not yet functional as of RC firmware 5.0.d.)

= Introduction =
* Typically, the dominant term in the MCE's PID-loop calculation is the accumulated integral. When the operating environment changes, it is possible that some pixels that were locked before can no longer. When this occurs, the integral-term in the PID-loop calculation grows linearly in time until it wraps. Because the FSFB affects the ground-plane level, a large change in the FSFB (i.e. wrapping) causes a considerable level shift in healthy pixels as well.
* Often, these unlocked/ ramping pixels are caught, but only after they ruin observing data. At that time, they are turned off manually, usually by setting p_coeff = i_coeff = d_coeff = 0.
* The goal of the FSFB clamping feature is to stop pixels from ramping at all by clamping them at a user-specified value. If their absolute value exceeds this value, then they are clamped. In this way, unlocked pixels no longer affect the rest of the array after they have reached that value.

= Usage =
* The '''integral_clamp''' parameter is a 32-bit positive number per Readout Card (8x41 pixels) and is set to 0 by default, meaning no clamping is performed by default. The '''integral_clamp''' parameter is used to clamp the calculated servo integral-term (before it is multiplied by the integral coefficient aka gaini) on both positive and negative ends. This prevents unlocked pixels from wrapping continuously in lock mode. The value needs to be determined based on different parameter settings like: gaini, flux-quanta, and other experiment dependent variables. Here is a guide to calculate what the value should be set to.

* Note that this calculation assumes that gainp = gaind = 0.
* No matter how large the calculated value is, it must still allow for a reasonable margin between it and the wrap-point of the I-term. If the margin is too small, then calculated values of the I-term will wrap if the I-term value jumps from I-term < integral_clamp to I-term > I_term_max.
* Note also that when integral_clamp = 0 (default), this feature is disabled.

//Typical for ACT:
wb rc1 gaini0 480 480 ..
wb rc1 flx_quanta0 6500 6500 ..
..(other PID-setup commands)
wb rc1 integral_clamp 6389760
wb rc1 flx_lp_init 1

* To calculate the right integral_clamp value, the maximum valid SQ1 FB value must be converted to an equivalent maximum I-term. Since
fb = gaini * I / 4096
we have
I_max = fb_max * 4096 / gaini

* With flux-jumping '''enabled''', the maximum FB value can be as large as the number of allowable flux jumps (127) times the flux quantum:
fb_max = 127 * flux_quantum
I_max = 127 * 4096 * flux_quantum / gaini

* When flux jumping is '''disabled''', the maximum FB can be taken to lie within a single DAC range (+-8192):
fb_max = 8192
I_max = 8192 * 4096 / gaini

* Including a factor of 0.9 (to keep the clamp value slightly lower than the critical cut-off), and rounding, we have the rules:
integral_clamp ~ I_max * 0.9

{ 30000000 / gaini (for flux jumping OFF)
= {
{ 470000 * flux_quantum / gaini (for flux jumping ON)

* Typical Values (Calculated in data_mode_outputs.xls)
{| border="1"
|-
! Telescope !! Flux Quanta !! I Coefficient
! integral_clamp
(Flux Jumping ON)
! integral_clamp
(Flux Jumping OFF)
|-
| ACT || 6500 || 480 || 6389760 || 62915
|-
| SPIDER || 9500 || 50 || 89653248 || 603980
|-
| SCUBA-2 || 6500 || 2024 || 1515358 || 14920
|}

Integral clamp

2011-05-03T17:52:14Z

Bburger: /* Usage */

This feature was implemented in an effort to eliminate the effects of unlocked and ramping pixels on locked pixels on an array. This feature is available in rev. 5.0.e as a beta release. (A preliminary version was introduced starting RC firmware rev. 5.0.9, but it was not yet functional as of RC firmware 5.0.d.)

= Introduction =
* Typically, the dominant term in the MCE's PID-loop calculation is the accumulated integral. When the operating environment changes, it is possible that some pixels that were locked before can no longer. When this occurs, the integral-term in the PID-loop calculation grows linearly in time until it wraps. Because the FSFB affects the ground-plane level, a large change in the FSFB (i.e. wrapping) causes a considerable level shift in healthy pixels as well.
* Often, these unlocked/ ramping pixels are caught, but only after they ruin observing data. At that time, they are turned off manually, usually by setting p_coeff = i_coeff = d_coeff = 0.
* The goal of the FSFB clamping feature is to stop pixels from ramping at all by clamping them at a user-specified value. If their absolute value exceeds this value, then they are clamped. In this way, unlocked pixels no longer affect the rest of the array after they have reached that value.

= Usage =
* The '''integral_clamp''' parameter is a 32-bit positive number per Readout Card (8x41 pixels) and is set to 0 by default, meaning no clamping is performed by default. The '''integral_clamp''' parameter is used to clamp the calculated servo integral-term (before it is multiplied by the integral coefficient aka gaini) on both positive and negative ends. This prevents unlocked pixels from wrapping continuously in lock mode. The value needs to be determined based on different parameter settings like: gaini, flux-quanta, and other experiment dependent variables. Here is a guide to calculate what the value should be set to.

* Note that this calculation assumes that gainp = gaind = 0.
* No matter how large the calculated value is, it must still allow for a reasonable margin between it and the wrap-point of the I-term. If the margin is too small, then calculated values of the I-term will wrap if the I-term value jumps from I-term < integral_clamp to I-term > I_term_max.
* Note also that when integral_clamp = 0 (default), this feature is disabled.

//Typical for ACT:
wb rc1 gaini0 480 480 ..
wb rc1 flx_quanta0 6500 6500 ..
..(other PID-setup commands)
wb rc1 integral_clamp 6389760
wb rc1 flx_lp_init 1

* To calculate the right integral_clamp value, the maximum valid SQ1 FB value must be converted to an equivalent maximum I-term. Since
fb = gaini * I / 4096
we have
I_max = fb_max * 4096 / gaini

* With flux-jumping '''enabled''', the maximum FB value can be as large as the number of allowable flux jumps (127) time the flux quantum:
fb_max = 127 * flux_quantum
I_max = 127 * 4096 * flux_quantum / gaini

* When flux jumping is '''disabled''', the maximum FB can be taken to lie within a single DAC range (+-8192):
fb_max = 8192
I_max = 8192 * 4096 / gaini

* Including a factor of 0.9 (to keep the clamp value slightly lower than the critical cut-off), and rounding, we have the rules:
integral_clamp ~ I_max * 0.9

{ 30000000 / gaini (for flux jumping OFF)
= {
{ 470000 * flux_quantum / gaini (for flux jumping ON)

* Typical Values (Calculated in data_mode_outputs.xls)
{| border="1"
|-
! Telescope !! Flux Quanta !! I Coefficient
! integral_clamp
(Flux Jumping ON)
! integral_clamp
(Flux Jumping OFF)
|-
| ACT || 6500 || 480 || 6389760 || 62915
|-
| SPIDER || 9500 || 50 || 89653248 || 603980
|-
| SCUBA-2 || 6500 || 2024 || 1515358 || 14920
|}

Integral clamp

2011-05-03T17:50:34Z

Bburger: /* Usage */

This feature was implemented in an effort to eliminate the effects of unlocked and ramping pixels on locked pixels on an array. This feature is available in rev. 5.0.e as a beta release. (A preliminary version was introduced starting RC firmware rev. 5.0.9, but it was not yet functional as of RC firmware 5.0.d.)

= Introduction =
* Typically, the dominant term in the MCE's PID-loop calculation is the accumulated integral. When the operating environment changes, it is possible that some pixels that were locked before can no longer. When this occurs, the integral-term in the PID-loop calculation grows linearly in time until it wraps. Because the FSFB affects the ground-plane level, a large change in the FSFB (i.e. wrapping) causes a considerable level shift in healthy pixels as well.
* Often, these unlocked/ ramping pixels are caught, but only after they ruin observing data. At that time, they are turned off manually, usually by setting p_coeff = i_coeff = d_coeff = 0.
* The goal of the FSFB clamping feature is to stop pixels from ramping at all by clamping them at a user-specified value. If their absolute value exceeds this value, then they are clamped. In this way, unlocked pixels no longer affect the rest of the array after they have reached that value.

= Usage =
* The '''integral_clamp''' parameter is a 32-bit positive number per Readout Card (8x41 pixels) and is set to 0 by default, meaning no clamping is performed by default. The '''integral_clamp''' parameter is used to clamp the calculated servo integral-term (before it is multiplied by the integral coefficient aka gaini) on both positive and negative ends. This prevents unlocked pixels from wrapping continuously in lock mode. The value needs to be determined based on different parameter settings like: gaini, flux-quanta, and other experiment dependent variables. Here is a guide to calculate what the value should be set to.

* Note that this calculation assumes that gainp = gaind = 0.
* No matter how large the calculated value is, it must still allow for a reasonable margin between it and the wrap-point of the I-term. If the margin is too small, then calculated values of the I-term will wrap if the I-term value jumps from I-term < integral_clamp to I-term > I_term_max.
* Note also that when integral_clamp = 0 (default), this feature is disabled.

//Typical for ACT:
wb rc1 gaini0 480 480 ..
wb rc1 flx_quanta0 6500 6500 ..
..(other PID-setup commands)
wb rc1 integral_clamp 6389760
wb rc1 flx_lp_init 1

* To calculate the right integral_clamp value, the maximum valid SQ1 FB value must be converted to an equivalent maximum I-term. Since
fb = gaini * I / 4096
we have
I_max = fb_max * 4096 / gaini

* With flux-jumping enabled, the maximum FB value can be as large as the number of allowable flux jumps (127) time the flux quantum:
fb_max = 127 * flux_quantum
I_max = 127 * 4096 * flux_quantum / gaini

* When flux jumping is disabled, the maximum FB can be taken to lie within a single DAC range (+-8192):
fb_max = 8192
I_max = 8192 * 4096 / gaini

* Including a factor of 0.9 (to keep the clamp value slightly lower than the critical cut-off), and rounding, we have the rules:
integral_clamp ~ I_max * 0.9

{ 30000000 / gaini (for flux jumping OFF)
= {
{ 470000 * flux_quantum / gaini (for flux jumping ON)

* Typical Values (Calculated in data_mode_outputs.xls)
{| border="1"
|-
! Telescope !! Flux Quanta !! I Coefficient
! integral_clamp
(Flux Jumping ON)
! integral_clamp
(Flux Jumping OFF)
|-
| ACT || 6500 || 480 || 6389760 || 62915
|-
| SPIDER || 9500 || 50 || 89653248 || 603980
|-
| SCUBA-2 || 6500 || 2024 || 1515358 || 14920
|}

Readout Card firmware

2011-04-21T18:52:46Z

Bburger: /* Revision 5.0.0 (Filter Only, 2 LVDS) */

* Synthesis Reminders (for firmware developers)
** quartus.ini is not needed anymore (Fixed as of Q7, Altera SR10783580 2010-10-24)
** Remember that readout_card/fsfb_clac/source/rtl/ram_40x64.vhd must be initialized with the ram_40x64.hex file in the same directory.
= Revision 5.1.2 =
* '''Filename:'''
** rc_stratix3_v05010002_18jan2011.sof (for Rev. E cards)
** rc_stratix3_v05010002_18jan2011.jic (for Rev. E cards)
** rc_v05010002_03feb2011.sof (for Rev. B cards)
** rc_v05010002_03feb2011.pof (for Rev. B cards)

* '''Features:'''
** based on 5.1.1 with k1 and k2 (filter params) limited to k1<16 and k2<32 in order to resolve the timing when compiling for smaller Stratix FPGA on RC Rev. B.

* '''Bug fix:'''
** the 2-rows-off filtered data readout introduced with configurable filter in rev. 5.1.0 and 5.1.1 is fixed now.

* '''Bugs:'''
** none so far.

* '''FPGA Resource Usage and Timing Report''' (readout_card.fit.rpt and readout_card.tan.rpt): TO BE UPDATED LATER

== Revision 5.1.1 (not recommended) ==
* '''Filename:'''
** rc_v05010001_01dec2010.sof (for Rev. B cards)

* '''Features:'''
** based on 5.1.0, but k1 and k2 (filter params) are now limited to k1<16 and k2<32 in order to resolve the timing failures of compiling 5.1.0 for smaller Stratix FPGA on RC Rev. B.

* '''Bugs:'''
** filter mode data is off by 2 rows.

== Revision 5.1.0 (not recommended) ==
* '''Filename:'''
** rc_stratix3_v05010000_01nov2010.sof (for Rev. E cards)
** rc_v05010000_01nov2010.sof (for Rev. B cards) has timing failures '''do not use!!!'''

* '''Features:'''
** added configurable filter parameters specified by ''fltr_coeff'', default is the fcutoff/fsampl=122Hz/15kHz. see [[ Digital 4-pole Butterworth Low-pass filter ]].
** ''fltr_type'' is set to 255 to indicate configurable filter parameters.
** see [http://www.phas.ubc.ca/~mce/mcedocs/software/SC2_ELE_S580_515_mce_command_description.pdf MCE command description]
** development notes:
*** It is built on Quartus10.1.
*** tcl files had to be updated as cmp syntax is not supported in Q10 anymore.
*** Rev. E cards now can be identified by reading back pcb_rev as part of card_type, therefore both stratix I and III sof/pof/jic are generated from the same source.

* '''Bugs:'''
** rc_v05010000_01nov2010.sof has timing failures that were overlooked, do not use this firmware for Rev.B cards.
** '''filter mode data is off by 2 rows.'''

* '''FPGA Resource Usage and Timing Report''' (readout_card.fit.rpt and readout_card.tan.rpt): logic usage is upto 85% from 66% in 5.0.d/e/f

= Revision 5.0.f =
* '''Filename:'''
** rc_v0500000f_22oct2010.sof (for Rev. B cards)
** rc_stratix3_v0500000f_22oct2010.sof (for Rev. E cards)

* '''Features:'''
** Bugfix: integral clamp should work now. only positive integral_clamp values are valid!

* '''Details:''': SQ1FB is applied 18 clock cycles after start of a row visit (SQ1_Bias being applied) regardless of flux-jump being enabled or not. In pre-5.0.b firmware SQ1FB was being applied after 7 clock cycles when flux-jump was disabled and after 18 clock cycles when flux-jump was enabled.
** available for both Rev. E and Rev. B cards, the upper byte of card_type parameter now reports the pcb revision.
** development note: It is built on Quartus10.1.

* '''Bugs:'''
**none yet!

* '''FPGA Resource Usage and Timing Report''' (readout_card.fit.rpt and readout_card.tan.rpt): no change compared to 5.0.a/b/c/d

== Revision 5.0.e (not recommended) ==
* '''Filename:'''
** rc_v0500000e_06oct2010.sof

* '''Details:'''
** an unsuccessful attempt to fix integral_clamp, but changed the functionality so that it clamps at the value, but it doesn't hold the clamp. i.e., if the calculated sq1fb becomes less than the specified clamp value, the sq1fb is not clamped anymore. This is not a desired functionality!

= Revision 5.0.d =
* '''Filename:'''
** rc_v0500000d_04aug2010.sof

* '''Features:'''
** Bugfix: To fix the bug associated with negative flux-jumps, reverted to signed multiplier and hence, incremented the width of the flux-quanta multiplier input by 1.

* '''Details:''': SQ1FB is applied 18 clock cycles after start of a row visit (SQ1_Bias being applied) regardless of flux-jump being enabled or not. In pre-5.0.b firmware SQ1FB was being applied after 7 clock cycles when flux-jump was disabled and after 18 clock cycles when flux-jump was enabled.

* '''Bugs:'''
** '''integral_clamping is broken'''. To test the clamping, a servo-locked ramp was initiated on the sq1fb and then flux-jumping was turned on and observed by attaching a scope to the SQ1FB output. With integral_clamp=80000000, flux_quanta=8000, gaini=1, flux-jump enabled, we see [[http://e-mode.phas.ubc.ca/mcewiki/index.php/Image:Clamp_unstable.png scope snapshot]] used slow_fb_ramp.py script for testing.

* '''FPGA Resource Usage and Timing Report''' (readout_card.fit.rpt and readout_card.tan.rpt): no change compared to 5.0.a/b/c

== Revision 5.0.c (not recommended) ==
* '''Filename:'''
** rc_v0500000c_16jun2010.sof

* '''Features:'''
** Based on rev. 5.0.b
** Re-introduced flux-jump counter clamping to maintain continuity in behavior from past versions of firmware in the field.
** '''Important''': SQ1FB is applied 18 clock cycles after start of a row visit (SQ1_Bias being applied) regardless of flux-jump being enabled or not. In pre-5.0.b firmware SQ1FB was being applied after 7 clock cycles when flux-jump was disabled and after 18 clock cycles when flux-jump was enabled.

* '''Details:'''
* '''Bugs:'''
** '''flux-jump is broken'''. flux-jumping block misbehaves at the first jump in the negative range.

* '''FPGA Resource Usage''' (readout_card.fit.rpt): [[rc_5.0.c_fit_rpt]]
* '''FPGA Timing Analysis''' (readout_card.tan.rpt): [[rc_5.0.c_tan_rpt]]

== Revision 5.0.b (not recommended) ==
* '''Filename:'''
** rc_v0500000b_03jun2010.sof

* '''Features:'''
** Based on rev. 5.0.a
** A bug that caused jumps in first-stage feedback, and detected as spikes in the raw data of pixels that were in servo_mode=0,1,2 was fixed. The jumps in FSFB were due to flux-jumping being enabled on live pixes with non-zero flx_quanta, and being disabled on the fly on dead pixels with flx_quanta=0. Flux-jumping is now disabled on a column-by-column basis if a column is in servo_mode = 0,1,2.
** Ineffective clamping was removed from the flux-jumping block (as per 5.0.9), as it is now replaced by the clamping that was perfected in rev. 5.0.10
** A sticky bit that only affected servo_mode=0,1,2 was also removed from the flux-jumping block.
** flx_lp_init commands now also clear the flux-jumping block as well.
** The 11-clock-cycle delay (in applying SQ1_FB) that in previous firmware only occurred when flux-jumping was enabled, now (in this version) is in effect all the time. Due to the bug-fix above, flux-jumping can be disabled on a column-by-column basis by setting servo_mode=0,1,2 when en_fb_jump=1. Before the change, this meant that constant values could be applied with or without the 11-cycle delay if en_fb_jump=1 or 0. To make the delay consistent, it is now always 11 cycles. As background, the flux-jumping block is pipelined, meaning that it does calculations for all 8 channels serially. The serialization is because of DSP-block limitations in the Readout Card FPGA that prevent us from doing all 8 channels in parallel. The reason that it takes 11 cycles to complete the flux-jumping calculations is because the values are computed for the eight channels in three ALU stages: 8 + 3 = 11 cycles. Adding 11 cycles to the 7 cycles of latency from other stages in the system results in: 11 + 7 = 18 cycles of latency from the start of a row dwell period before the first-stage feedback is applied. In rc_v5.0.c, I enforce the 18-cycle delay even when flux-jumping is not enabled to maintain uniformity across all eight channels, because flux-jumping is enabled/disabled on a per-channel basis. In other words, if I hadn't enforced the 18-cycle delay, some channels could have their feedback applied after 7 cycles, while others could have it applied after 18 cycles. I wasn't a fan of this non-uniformity. I realize that 18 cycles is a long time. In fact, so is 7. In the last few months, we have been discussing how to reduce these times to 1 cycle, because every experiment out there wants to multiplex as fast as possible, and the 7/18-delay is a rate limiting step.
** The flux-jumping code was re-arranged in the flux-jumping block to reflect the flow of data through the pipeline and make it easier to understand.

* '''Details:'''

* '''Bugs:'''
** flux-jump does not work when jumping to negative values.

* '''FPGA Resource Usage''' (readout_card.fit.rpt): [[rc_5.0.b_fit_rpt]]
* '''FPGA Timing Analysis''' (readout_card.tan.rpt): [[rc_5.0.b_tan_rpt]]

= Revision 5.0.a =
* '''Filename:'''
** rc_v0500000a_12mar2010.sof

* '''Features:'''
** Based on the merger of rev. 5.0.8 and 5.0.9.
** '''integral_clamp''' command is added where a clamp value is set for the integral term and once the integral term hits that value, the integral-term is clamped to that value and p-term and d-term are clamped to zero. When integral_term=0 then no clamping is in effect, similar to previous releases of firmware.
** The low pass filter has 20-bit input and f_3dB/f_samp = 122Hz/15kHz .
** The flux-jump clamping that was removed in 5.0.9 is included once again here, as we decided this is safer for now.

* '''Details:'''
** "lock_dat_left" parameter that was removed in 5.0.9 is now implemented as "lock_dat_lsb"

* '''Bugs:'''
** flx_lp_init does not reinitialize the flux-jump block

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis
** tag name: rc_v0500000a_12mar2009! years were mixed up!

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
* '''FPGA Timing Analysis''' (readout_card.tan.rpt):

== Revision 5.0.9 (buggy) ==
* '''Filename:'''
** rc_v05000009_13nov2009.sof

* '''Features:'''
** Based on rev. 5.0.4
** Removes a sticky bit in pid calculation result storage -- in fsfb_processor.
** Adds a command to clamp the growth of the I-term to prevent wrapping and track down the source of Caltech's FSFB jumps.
** Removed the unused lock_dat_left parameter. The ability to shift left was moved to the fsfb_corr block some time ago.
** Fixed a sign extension bug acting on the flux quanta, which limited the value to 8191. Changed the extension from signed to unsigned.
** Removed ineffective clamping in the flux-jump calculation block.
** IMPORTANT: Must be used in conjunction with firmware rev. 5.0.0+ of all other cards.

* '''Details:'''

* '''Bugs:'''
** integral_clamp read/write command does not work.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 27,960 / 41,250 ( 68 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.825 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.878 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 14.397 ns ;

== Revision 5.0.8 (UBC only) ==
* '''Filename:'''
** rc_v05000008_09oct2009.sof

* '''Features:'''
** Based on rev. 5.0.4
** type 1 low-pass filter: f3dB=122Hz for fsample=15kHz
** Filter-input-width changed from 18b to 20b with no sticky bits!
** removed sticky bits in internal arithmetic of the filter.

= Revision 5.0.7 (type-2 filter) =
* '''Filename:'''
** rc_v05000007_09oct2009.sof

* '''Features:'''
** Based on rev. 5.0.4
** type-2 low-pass-filter: f3dB=75Hz for fsample=30000.
** Filter-input-width changed from 18b to 20b with no sticky bits!
** inter-biquad-gain-scaling for the filter is 2^14
** filter results are scaled down by 2^3 in the output of the filter.
** removed sticky bits in internal arithmetics
** _correction_ disabled in fsfb_proc_pidz

* '''Details:'''
** quartus.ini file was '''not''' present in synth directory.

* '''Bugs:'''
** none to report

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
== Revision 5.0.6 (UBC only) ==
* '''Filename:'''
** rc_stratix3_v05000006_15sep2009.sof

* '''Features:'''
** Only Valid for Rev. C/D Cards
** Based on rev. 5.0.3
** tcl file updated for Rev. D and aligned with top-level and qsf (project file).
** flux loop commented, just to try sampling the ADC.
** compiled with Q9.1

== Revision 5.0.5 (UBC only) ==
* '''Filename:'''
** rc_v05000005_04sep2009.sof

* '''Features:'''
** Based on rev. 5.0.2
** changed the low-pass-filter to f(3db)=75Hz for f(sample)=30000.

* '''Details:'''
** quartus.ini file was '''not''' present in synth directory.

* '''Bugs:'''
** negative inputs to the filter cause filter to have a non-flat pass-band region. may have to do with sign-handling...

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
* '''FPGA Timing Analysis''' (readout_card.tan.rpt):

= Revision 5.0.4 =
* '''Filename:'''
** rc_v05000004_28aug2009.sof

* '''Features:'''
** Based on rev. 5.0.2
** BUG Fix: handles 14-bit flux quanta (changed the multiplier to unsigned)
** BUG Fix: changed standard logic vector extension from signed to unsigned in flux-jumping slave.
** IMPORTANT: Must be used in conjunction with firmware rev. 5.0.0+ of all other cards.

* '''Details:'''

* '''Bugs:'''
** None so far.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,170 / 41,250 ( 63 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.541 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.612 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 15.398 ns ;

= Revision 5.0.3 =
* '''Filename:'''
** rc_stratix3_v05000003_21aug2009.sof

* '''Features:'''
** ONLY valid REV C/D RC Cards
** Based on rev. 5.0.2
** flux loop commented, just to try sampling the ADC.
** updated tcl file, but still need to rely on project file as well as qsf file.
** changed default level of adc_sclk to '1'
** dac_clr_n was changed from an output to an input.
** added 'locked' interface to rc_pll_stratix_iii
** renamed the adc_pll clock signals to more explanitory names
** added the FPGA_DEVICE_FAMILY generic to the dispatch interace for synthesis of the dc_fifo in lvds_rx
** uncommented DDR interface to force the syntesizer to use correct left and right PLLs (in conjunction with ADC and DDR PLLs)
** added test signals to test_status to see clocks on the scope.
== Revision 5.0.2 (buggy) ==
* '''Filename:'''
** rc_v05000002_test00_tagged.sof

* '''Features:'''
** Based on rev. 5.0.1
** Fixed a bug in wbs_frame_data that stored data incorrectly if reporting 1 or 2 pixels only.
** IMPORTANT: Must be used in conjunction with firmware rev. 5.0.0+ of all other cards.

* '''Details:'''

* '''Bugs:'''
** None so far.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,186 / 41,250 ( 63 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.755 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.979 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.067 ns ;

== Revision 5.0.1 (buggy) (Filter + Raw + Rectangle, 2 LVDS) ==
* '''Filename:'''
** rc_v05000001_26may2009.sof

* '''Features:'''
** Combines features in rev. 5.0.0 (2 LVDS Lines) and rev. 4.0.e (Filtered + Raw), with the NEW rectangle mode.
** IMPORTANT: Must be used in conjunction with firmware rev. 5.0.0+ of all other cards.

* '''Details:'''
** [[CVS Diff Between sys_v05000000 and rc_v05000001]]

* '''Bugs:'''
** Has a bug in wbs_frame_data that stored data incorrectly if reporting 1 or 2 pixels only.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,565 / 41,250 ( 64 % ) ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.656 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.861 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 14.167 ns ;

== Revision 5.0.0 (Filter Only, 2 LVDS) ==
* '''Filename:'''
** rc_v05000000_22dec2008.sof (tagged as sys_v05000000_22dec2008)

* '''Features:'''
** IMPORTANT: Must be used in conjunction with firmware v05000000+ of all other cards!!!
** Adds the ability to read out one column of data continuously from readout cards
** Adds data mode 11, which is an engineering mode. Data points are 32-bits, and bits [9..3]=row_index, [2..0]=column_index. This mode is useful for determining which pixels one is reading out in the array, in column mode for example.

* '''Details:'''
** [[CVS Diff Between rc_v0400000c and sys_v05000000]]

* '''Bugs:'''
** None so far.

* '''Synthesis Notes:'''
** The quartus.ini file was not present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,607 / 41,250 ( 65 % ) ;
; Total memory bits ; 406,016 / 3,423,744 ( 12 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.558 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.892 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.987 ns ;

== Revision 4.0.f (Filter + Raw, 1 LVDS) ==
* '''Filename:'''
** rc_v0400000f_12feb2010.sof

* '''Features:'''
** Based on 4.0.e and in parallel with 5.0.9 (equivalent version, clamping is not included)
** Incorporates fixes that were done to flux-jumping between 5.0.2 - 5.0.4 - 5.0.9. Namely:
*** Changes a multiplier from signed to unsigned (in fsfb_corr_multplier.vhd).
*** Changes sign extension from signed to unsigned (in flux_quanta_ram_admin.vhd).

* '''Details:'''

* '''Bugs:'''
** None reported yet.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,773 / 41,250 ( 65 % ) ;
; Total memory bits ; 1,321,984 / 3,423,744 ( 39 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.539 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 4.118 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 17.318 ns ;

== Revision 4.0.e (Filter + Raw, 1 LVDS) ==
* '''Filename:'''
** rc_v0400000e_27apr2009.sof

* '''Features:'''
** Based on 4.0.d
** Combines both raw- and filtered-data modes.
** fpga_temp, card_temp, card_id commands are disabled.
** Tested by Matt Hasselfield.

* '''Details:'''

* '''Bugs:'''
** fpga_temp, card_temp, card_id commands are disabled.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 27,048 / 41,250 ( 66 % ) ;
; Total memory bits ; 1,321,984 / 3,423,744 ( 39 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.675 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.907 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.728 ns ;

== Revision 4.0.d (Raw Only, 1 LVDS) ==
* '''Filename:''' rc_v0400000d_20090417.sof

* '''Features:'''
** Based on v4.0.c, but has the filter removed, and implements a single 65536-index RAM block for storing 50 MHz raw-data samples.
** The firmware takes a new command called readout_col_index which specifies which column to capture raw data from.
** Other than readout_col_index, the firmware functions the same as previous raw-data firmware, including then need to issue a capture_raw command.
** For more information on raw-data, see: http://e-mode.phas.ubc.ca/mcewiki/index.php/Raw-mode_readout
** This firmware also integrates some of the improvements that were implemented in 4.4.0, like the removal of the tga_o signal from an FSM in dispatch_wishbone.vhd.

* '''Details:'''
** Differences between 4.0.c and 4.0.d
U system/test/source/tb/tb_cc_rcs_bcs_ac.vhd
U all_cards/dispatch/source/rtl/dispatch_wishbone.vhd
U library/sys_param/source/rtl/wishbone_pack.vhd
U readout_card/adc_sample_coadd/source/rtl/adc_sample_coadd.vhd
U readout_card/adc_sample_coadd/source/rtl/adc_sample_coadd_pack.vhd
U readout_card/flux_loop/source/rtl/flux_loop.vhd
U readout_card/flux_loop/source/rtl/flux_loop_pack.vhd
U readout_card/flux_loop_ctrl/source/rtl/flux_loop_ctrl.vhd
U readout_card/flux_loop_ctrl/source/rtl/flux_loop_ctrl_pack.vhd
U readout_card/flux_loop_ctrl/source/tb/tb1_flux_loop_ctrl.vhd
U readout_card/flux_loop_ctrl/source/tb/tb2_flux_loop_ctrl.vhd
U readout_card/fsfb_calc/source/rtl/fsfb_fltr_regs.vhd
U readout_card/fsfb_corr/source/rtl/fsfb_corr.vhd
U readout_card/readout_card/source/rtl/readout_card.vhd
U readout_card/readout_card/source/rtl/readout_card_pack.vhd
U readout_card/wbs_frame_data/source/rtl/wbs_frame_data.vhd
U readout_card/wbs_frame_data/source/rtl/wbs_frame_data_pack.vhd

* '''Bugs:'''
** None so far.
** fpga_temp, card_temp, card_id commands are not supported.

* '''Synthesis Notes:'''
** The quartus.ini file was present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 24,554 / 41,250 ( 60 % ) ;
; Total memory bits ; 1,262,592 / 3,423,744 ( 37 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.991 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.864 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 17.052 ns ;

== Revision 4.4.1 ==
* '''Filename:''' rc_v04040001_21nov2008

* '''Features:'''
** Fixes a bug that froze up the firmware if any of the following commands were issued: CARD_ID_ADDR, CARD_TEMP_ADDR, FPGA_TEMP_ADDR in 4.4.0 only.

* '''Details:'''
** The bug fix include adding more logic to the wishbone ack path (readout_card.vhd), which subsequently decreased the minimum clock setup time to 1.588ns. The new logic will catch errors that the old logic wouldn't have, and is now consistent with the firmware on all the other cards. However, if timing becomes an issue, the logic may have to revert back to that which was in version 4.0.c.

* '''Bugs:'''
** None so far.

* '''Synthesis Notes:'''
** The quartus.ini file was not present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 27,241 / 41,250 ( 66 % ) ;
; Total memory bits ; 405,504 / 3,423,744 ( 12 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.588 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.585 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 17.057 ns ;

== Revision 4.4.0 (buggy) ==
* '''Filename:''' rc_v04040000_02oct2008
* '''Features:'''
** Reinstated the data modes in wbs_frame_data.vhd that were removed in 4.0.c. This firmware has the following modes: '''0, 1, 2, 4, 5, 7, 10'''. The modes that are not present are: '''3''' (raw data), '''6''' (replaced by data_mode = 7), '''8''' (replaced by data_mode = 10), '''9''' (replaced by data_mode = 10). For more information on data modes, see [[Data mode]].
** Re-integrated the id_thermo and fpga_thermo block in the readout_card.vhd top level that was removed in 4.0.c.
** Removed the sticky bit in fsfb_corr.vhd, which was enabled when flux-jumping was turned on. Because the feedback is signed, the sticky bit would usually reflect the value of the 14th bit, except in situations when the number of flux quanta to jump was greater than 1 (i.e. cosmic rays, IV-curves, etc). Flux jumps are made at a maximum rate of one per frame period, so that if the First-Stage Feedback increased past the 13th bit, it would not be reflected in the feedback applied. Now it is.
* '''Details:'''
** Simplified the FSM logic in wbs_frame_data.vhd that determines when to transition from IDLE to WSS1. This was done to lower the number of gates in that path, and ease the timing.
** Removed the z_dat_i port in fsfb_processor.vhd and fsfb_calc_pack.vhd to the fsfb_proc_pidz block, in an effort to make it clearer within that block that the z-term is always = 0.
** Removed the z-term sign extension in fsfb_proc_pidz.vhd, and the [d-term + z-term] adder to free up DSP resources since the z-term is always = 0.
** Adjusted the indentation in fsfb_io_controller.vhd to make the file more readable.
** Moved the tga_o signal out of the dispatch_wishbone.vhd FSM, and made it a continuous assignment. This signal had one of the highest fan-out counts in the RTL design, and actually was impossible to route in Stratix III chips in its previous configuration because of the number of gates on the fan-out. As a consequence of making it a continuous assignment, the Stratix III fitter was able to succeed, and the Stratix I timing characteristics were greatly improved. This is the most significant change in this revision. This change single-handedly increased the minimum slack from 1.282 ns in v0400000c to 2.372 ns (or 56.7 MHz max) in this revision.
* '''Bugs:'''
** The following commands lock up the Readout Card firmware: CARD_ID_ADDR, CARD_TEMP_ADDR, FPGA_TEMP_ADDR.
** fb_const0 commands to channel 0 do not work. The value is stored in the register, but not applied to the DAC. Thus, read-back returns the correct value, but the DAC does not
* '''Synthesis Notes:'''
** The quartus.ini file was not present in the synth directory during synthesis.
* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 27,099 / 41,250 ( 66 % ) ;
; Total memory bits ; 406,016 / 3,423,744 ( 12 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.372 ns ;
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 4.052 ns ;
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.066 ns ;

== Revision 4.0.c ==
* '''Filename:''' rc_v0400000c_15aug2008.sof
* '''Features:'''
** Only has data modes 0, 1, 4, and 10.
** Fixed the bug that exists in 4.0.b, 4.0.a, and 4.0.9 that prevented the fb_const value from being applied to channel zero (wbs_fb_data.vhd).
* '''Details:'''
** Changed a counter in the dispatch block to ease timing constraints in synthesis (dispatch_wishbone.vhd)
** Updated the tagged versions of dispatch.vhd , dispatch_cmd_receive.vhd, and dispatch_reply_transmit.vhd to the version that is used by all the other cards.
** '''Removed''' the fpga_termo (command: '''fpga_temp''') and id_thermo (commands: '''card_temp, card_id''') to ease timing constraints in synthesis (readout_card.vhd)
** Updated the tagged version of fpga_termo.vhd to include the new 'stale bit' feature
** Updated the tagged version of frame_timing_core.vhd to include the new 'err_o' interface
* '''Bugs:'''
** None reported yet
* '''Synthesis Notes:'''
** The quartus.ini file was not present in the synth directory during synthesis.
* '''FPGA Resource Usage:'''
Total logic elements : 25,058 / 41,250 ( 61 % )
Total memory bits : 400,896 / 3,423,744 ( 12 % )

* '''Timing Analysis''' (readout_card.tan.rpt):
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.282 ns ;
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.736 ns ;
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.665 ns ;

== Revision 4.0.b (buggy) ==
Note: This revision is on a watch list, after the bug detected 15 July 2008. See the bug section for more details.
* '''Filename''' : rc_v0400000b_04aug2008.sof
* '''Features'''
** data_mode 10 is added to provide more filtfb bits (compared to data mode 9) for planet observations. filtered_dat(27 downto 3) & flux_cnt_dat(6 downto 0)

* '''Bugs'''
** An unexplained bug that appeared in 4.0.a and may still be present in 4.0.b is a problem with the readout of channels being clipped out of data reporting. [[Bug 1 Notes]]

* ''' Synthesis note '''
** Quartus.ini removed.

== Revision 4.0.a (buggy) ==
Note: This revision is on a watch list, after the bug detected 15 July 2008. See the bug section for more details.
* '''Filename''' : rc_v0400000a_07jul2008.sof
* '''Bug Fix'''
** mce_status and adc_offset/flx_quanta commands do not fail after power up.
* ''' Synthesis note '''
** Quartus.ini removed.

* '''Bugs'''
** Seems to clip out channel 0 from data reporting.

== Revision 4.0.9 (buggy) ==
* '''Filename''' : rc_v04000009_26jun2008.sof
* '''Features'''
** sa_bias and offset DACs only refreshed when new values are written. (in previous versions, DACs were refreshed every frame)
* '''Bugs'''
** fb_const0 commands to channel 0 do not work. The value is stored in the register, but not applied to the DAC. Thus, read-back returns the correct value, but the DAC does not.
** reading flx_quanta and adc_offset right after power up hangs the reply datapath to CC. resetmce clears this error as temporary solution. the problem is caused by first read ack of the wishbone slave.

== Revision 4.0.8 ==
* '''Filename''' : rc_v04000008_26jun2008.sof
* '''Features'''
** The gaini, gainp, gaind resolution increased to 12-bit, i.e. -2048 to 2047 (formerly 10-bit).

* '''Bug fix'''
** the bug associated with gainpid read before mce_reset is fixed.

* ''' Synthesis note '''
** Quartus.ini removed.

== Revision 4.3.7 ==
* '''Filename''' : rc_v04030007_26may2008_raw.sof
* '''Features'''
** 14-bit raw mode enabled to buffer a snapshot of 50MHz samples for 2 frames of row_len * num_rows samples.
** In order to extend the raw-mode to 14-bit, an assumption is made that the raw buffer is not written to while being read. Therefore, make sure there is at least 2*row_len*num_rows*20ns between issuing captr_raw command and reading back the raw data.
** In order to save RAM for raw mode, two memory-intensive features are disabled:
*** low-pass filter disabled ( mixed filtfb data modes 6, 7, 9 are also disabled)
*** PID (gainp0, gaini0, gaind0) readback disabled. one can still set PID values and run servo, but can not read back the values.

== Revision 4.2.7 ==
* '''Filename''' : rc_v04020007_24may2008_raw.sof
* '''Features'''
** raw mode enabled to buffer a snapshot of 50MHz samples for 2 frames of row_len * num_rows samples.
** In order to save RAM for raw mode, two memory-intensive features are disabled:
*** low-pass filter disabled ( mixed filtfb data modes 6, 7, 9 are also disabled)
*** PID (gainp0, gaini0, gaind0) readback disabled. one can still set PID values and run servo, but can not read back the values.
* '''Bug fix'''
** the bug associated with reading from raw-buffer is fixed.

== Revision 4.1.7 ==
* '''Filename''' : rc_v04010007_25apr2008_raw.sof
* '''Features'''
** raw mode enabled to buffer a snapshot of 50MHz samples for 2 frames of row_len * num_rows samples.
** In order to save RAM for raw mode, two memory-intensive features are disabled:
*** low-pass filter disabled ( mixed filtfb data modes 6, 7, 9 are also disabled)
*** PID (gainp0, gaini0, gaind0) readback disabled. one can still set PID values and run servo, but can not read back the values.
* '''Bugs'''
** after each readout frame, raw-buffer readout counter falls behind by 3 and this causes skipping 3 50MHz samples in the data stream and column-data being messed up in subsequent frames. Data can be rearranged by post processing.

== Revision 4.0.6 (buggy) ==
* '''Filename''' : rc_v04000006_15feb2008.sof or .pof
* '''Features'''
** '''bugfix''': unreliable reset due to unsafe and incomplete state machines is fixed.
** '''bugfix''': flux_jump sign problem fixed, so far proved in const_mode, to be tested in servo_mode with cold setup.
** servo_mode=2 or ramp previously only went from 0 to ramp_amp, but now goes from -8192 to -8192+ramp_amp
** new commands are added: ''scratch'' and ''card_type''. Scratch takes 8 values and can be used by software to detect reset.
** slot_id and fw_rev are now integrated as part of all_cards.vhd
** lvds_tx_b=0, This will allow Clock Card to use the secondary backplane lvds line and check whether RC is plugged in.
** filter_coeff in misc_banks_admin commented as it is not implemented and causes timing problems.

* '''Bugs'''
** reading gainp/gaini/gaind right after power up hangs the reply datapath to CC. resetmce clears this error as temporary solution. the problem is caused by first read ack of pid_ram_admin.
** slot_id is only set after a resetmce is issued. (using the latest all_cards in the next revision will fix this)
** has spurious spikes on channel 7 data, which max out the integral, and cause the detectors to come unlocked. This firmware officially meets timing requirements, but the bug could be due to marginal timing on the longest data paths, i.e. ~0.1 ns in some cases.

== Revision 4.0.5 ==
* '''Filename''' : rc_v04000005_01nov2007.sof or .pof
* '''Features'''
** data mode 9 (mixed filt + flux jump) with windowing readjusted compared to data mode 8

* '''Bugs'''
** unreliable resetmce. Sometimes, firmware waked up non-responsive on lvds lines.
** In data mode 5 and 9, flux-jump counter is not reported properly due to a sign error. However, flux jumping works fine.

== Revision 3.0.19 ==
* '''Filename''' : rc_v03000019_16feb2007_raw.sof (no pof as one is not likely to run with this as regular firmware)
* '''Features'''
** data mode 3 is enabled.
** filter is disabled as a compromise to fit the raw-mode buffer.

* '''Bugs'''
** unreliable resetmce. Sometimes, firmware waked up non-responsive on lvds lines.

== Old Firmware Revisions ==
* '''4.0.4''': rc_v04000004_11oct2007.sof data mode 8 added (mixed filt + flux jump)
* '''4.0.3''': rc_v04000003_19sep2007.sof data mode 7 bit split readjusted to 10b error being bit 4 to 14
* '''4.0.2''': rc_v04000002_11sep2007.sof pid resolution increased to 10b, data mode 7 added
* '''4.0.1''': rc_v04000001_06sep2007.sof
* '''4.0.0''': rc_v04000000_29aug2007.sof supports readout_row_index * [[ bugs ]]

= To-Do List =
* the starting point for the servo is currently zero and it would be nice to have it programmable.

= RC Synthesis Notes =
# The following note applies when using Quartus versions earlier than Q7: Quartus.ini file had to exist in synth directory up to revision 4.0.a due to a bug that started in Quartus 6.1 and would synthesize away arbitrary parts of readout card. We contacted Altera at the time and they provided us the ini file.
# Timing: There is no "lock region" defined for readout card. Timing on readout card is tight and since version 3 or so any new feature would initially fail timing till some synthesis options were tweaked. One path that remains to be consistently marginal is from addr_gen counter (i.e. tga_o counter) in dispatch_wishbone.vhd to wishbone slaves particularly misc_banks_admin.vhd. Modules that are rewritten to address timing concerns are fsfb_corr, all_cards, misc_banks_admin, and finally instantiating an lpm counter instead of a counter from components library. Surprisingly, the lpm counter reduced 87 failures to 37, although looking at the technology map viewer, it seemed that they were both synthesized the same.
# Compile time: This was at some point 4.5 hours, after going to dual core PC, this was reduced to 35 minutes. After extending pid gains to 12b and fixing offset/sa_bias update code, the compile time increased to 1.5hr again with utilization up to ~70%.
# wbs_fb_storage, ram_8x64, pid_ram had to be regenerated using latest (Q7.2) MegaWizard to get rid of the bug associated with failure to read after power up until a reset was issued.
# During simulations, the initialization of RAM block with .hex files needs to be disabled. This is done by commenting out the following lines from the MegaWizard generated Megafunction files (remember to un-comment them before synthesizing the code):
lpm_file => "C:/scuba2_repository/cards/readout_card/fsfb_calc/source/rtl/ram_40x64.hex", and
lpm_file : STRING;
#Starting Q10.0 use TimeQuest timing analyzer as oppose to the classic one. The classic one is being phased out by Altera. In order to use TimeQuest, you need to have an sdc file present in your project directory.
----
[http://e-mode.phas.ubc.ca/mcewiki/index.php/Main_Page MCE Main Page]

Main Page

2011-04-21T18:51:19Z

Bburger: /* Contact Info */

This Wiki is for users and developers of UBC's '''Multi-Channel Electronics''' (MCE), and the '''MCE Acquisition Software''' (MAS).

* To edit this wiki you will need an account; please get in touch with UBC.
* To stay up-to-date with MCE changes, consider subscribing to the MCE announcement mailing list: '''<code>mce-announce@phas.ubc.ca</code>'''.

= =
* [[ MCE firmware | MCE Firmware ]] - information on firmware versions, features, and tools
* [[ MCE hardware | MCE Hardware ]] - information on MCE hardware
* [http://www.phas.ubc.ca/~mce/mcedocs MCE main website] - hardware board descriptions and schematics
* [[ PCI card firmware ]] - MCE-compatible firmware for the astrocam ("SDSU") PCI card.
* [[ Sync Box ]]

= =
* [[ MAS | MCE Acquisition Software (MAS) ]] - kernel driver and low-level tools
* [[ Array setup programs | Array setup Programs (mce_script) ]]
* [[ Unix stuff ]]
* [[ DAS ]] - SCUBA2's data acquisition system

= Contact Info =

MCE Lab: 604-822-2585
Halpern's Lab: 604-822-6709

Hardware/firmware: mandana at phas.ubc.ca, bburger at phas.ubc.ca
Software: mhasse at phas.ubc.ca, dvw at phas.ubc.ca
Announcement Mailing List mce-announce at phas.ubc.ca

Readout Card firmware

2010-08-03T18:39:23Z

Bburger: /* Revision 5.0.c (mildly tested, but recommended!) */

* Recommended Firmware Revisions [http://e-mode.phas.ubc.ca/mcewiki/index.php/Compatible_Versions_(CC,RC,BC,AC) here]

* Synthesis Reminders (for firmware developers)
** Make sure quartus.ini is present in synth directory
** Remember that readout_card/fsfb_clac/source/rtl/ram_40x64.vhd must be initialized with the ram_40x64.hex file in the same directory.

= Revision Listing =
== Revision 5.0.c (buggy) ==
* '''Filename:'''
** rc_v0500000c_16jun2010.sof

* '''Features:'''
** Based on rev. 5.0.b
** Re-introduced flux-jump counter clamping to maintain continuity in behavior from past versions of firmware in the field.
** '''Important''': SQ1FB is applied 18 clock cycles after start of a row visit (SQ1_Bias being applied) regardless of flux-jump being enabled or not. In pre-5.0.b firmware SQ1FB was being applied after 7 clock cycles when flux-jump was disabled and after 18 clock cycles when flux-jump was enabled.

* '''Details:'''

* '''Bugs:'''
** There is a bug in the flux-jumping block related to jumps in the negative range.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,800 / 41,250 ( 65 % ) ;
; Total pins ; 358 / 616 ( 58 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;
; DSP block 9-bit elements ; 76 / 112 ( 68 % ) ;
; Total PLLs ; 1 / 6 ( 17 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.964 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 4.382 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 15.924 ns ;

== Revision 5.0.b (UBC only) ==
* '''Filename:'''
** rc_v0500000b_03jun2010.sof

* '''Features:'''
** Based on rev. 5.0.a
** A bug that caused jumps in first-stage feedback, and detected as spikes in the raw data of pixels that were in servo_mode=0,1,2 was fixed. The jumps in FSFB were due to flux-jumping being enabled on live pixes with non-zero flx_quanta, and being disabled on the fly on dead pixels with flx_quanta=0. Flux-jumping is now disabled on a column-by-column basis if a column is in servo_mode = 0,1,2.
** Ineffective clamping was removed from the flux-jumping block (as per 5.0.9), as it is now replaced by the clamping that was perfected in rev. 5.0.10
** A sticky bit that only affected servo_mode=0,1,2 was also removed from the flux-jumping block.
** flx_lp_init commands now also clear the flux-jumping block as well.
** The 11-clock-cycle delay (in applying SQ1_FB) that in previous firmware only occurred when flux-jumping was enabled, now (in this version) is in effect all the time. Due to the bug-fix above, flux-jumping can be disabled on a column-by-column basis by setting servo_mode=0,1,2 when en_fb_jump=1. Before the change, this meant that constant values could be applied with or without the 11-cycle delay if en_fb_jump=1 or 0. To make the delay consistent, it is now always 11 cycles. As background, the flux-jumping block is pipelined, meaning that it does calculations for all 8 channels serially. The serialization is because of DSP-block limitations in the Readout Card FPGA that prevent us from doing all 8 channels in parallel. The reason that it takes 11 cycles to complete the flux-jumping calculations is because the values are computed for the eight channels in three ALU stages: 8 + 3 = 11 cycles. Adding 11 cycles to the 7 cycles of latency from other stages in the system results in: 11 + 7 = 18 cycles of latency from the start of a row dwell period before the first-stage feedback is applied. In rc_v5.0.c, I enforce the 18-cycle delay even when flux-jumping is not enabled to maintain uniformity across all eight channels, because flux-jumping is enabled/disabled on a per-channel basis. In other words, if I hadn't enforced the 18-cycle delay, some channels could have their feedback applied after 7 cycles, while others could have it applied after 18 cycles. I wasn't a fan of this non-uniformity. I realize that 18 cycles is a long time. In fact, so is 7. In the last few months, we have been discussing how to reduce these times to 1 cycle, because every experiment out there wants to multiplex as fast as possible, and the 7/18-delay is a rate limiting step.
** The flux-jumping code was re-arranged in the flux-jumping block to reflect the flow of data through the pipeline and make it easier to understand.

* '''Details:'''

* '''Bugs:'''

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,745 / 41,250 ( 65 % ) ;
; Total pins ; 358 / 616 ( 58 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;
; DSP block 9-bit elements ; 76 / 112 ( 68 % ) ;
; Total PLLs ; 1 / 6 ( 17 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.459 ns
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.895 ns
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 15.956 ns

== Revision 5.0.a ==
* '''Filename:'''
** rc_v0500000a_12mar2010.sof

* '''Features:'''
** Based on the merger of rev. 5.0.8 and 5.0.9.
** integral_clamp command is added where a clamp value is set for the integral term and once the integral term hits that value, the integral-term is clamped to that value and p-term and d-term are clamped to zero. When integral_term=0 then no clamping is in effect, similar to previous releases of firmware.
** The low pass filter has 20-bit input and f_3dB/f_samp = 122Hz/15kHz .
** The flux-jump clamping that was removed in 5.0.9 is included once again here, as we decided this is safer for now.

* '''Details:'''
** "lock_dat_left" parameter that was removed in 5.0.9 is now implemented as "lock_dat_lsb"

* '''Bugs:'''

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis
** tag name: rc_v0500000a_12mar2009! years were mixed up!

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
* '''FPGA Timing Analysis''' (readout_card.tan.rpt):

== Revision 5.0.9 (buggy) ==
* '''Filename:'''
** rc_v05000009_13nov2009.sof

* '''Features:'''
** Based on rev. 5.0.4
** Removes a sticky bit in pid calculation result storage -- in fsfb_processor.
** Adds a command to clamp the growth of the I-term to prevent wrapping and track down the source of Caltech's FSFB jumps.
** Removed the unused lock_dat_left parameter. The ability to shift left was moved to the fsfb_corr block some time ago.
** Fixed a sign extension bug acting on the flux quanta, which limited the value to 8191. Changed the extension from signed to unsigned.
** Removed ineffective clamping in the flux-jump calculation block.
** IMPORTANT: Must be used in conjunction with firmware rev. 5.0.0+ of all other cards.

* '''Details:'''

* '''Bugs:'''
** integral_clamp read/write command does not work.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 27,960 / 41,250 ( 68 % ) ;
; Total pins ; 358 / 616 ( 58 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;
; DSP block 9-bit elements ; 76 / 112 ( 68 % ) ;
; Total PLLs ; 1 / 6 ( 17 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.825 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.878 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 14.397 ns ;

== Revision 5.0.8 (UBC only) ==
* '''Filename:'''
** rc_v05000008_09oct2009.sof

* '''Features:'''
** Based on rev. 5.0.4
** type 1 low-pass filter: f3dB=122Hz for fsample=15kHz
** Filter-input-width changed from 18b to 20b with no sticky bits!
** removed sticky bits in internal arithmetic of the filter.

== Revision 5.0.7 (UBC only) ==
* '''Filename:'''
** rc_v05000007_09oct2009.sof

* '''Features:'''
** Based on rev. 5.0.4
** type-2 low-pass-filter: f3dB=75Hz for fsample=30000.
** Filter-input-width changed from 18b to 20b with no sticky bits!
** inter-biquad-gain-scaling for the filter is 2^14
** filter results are scaled down by 2^3 in the output of the filter.
** removed sticky bits in internal arithmetics
** _correction_ disabled in fsfb_proc_pidz

* '''Details:'''
** quartus.ini file was '''not''' present in synth directory.

* '''Bugs:'''
** none to report

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
* '''FPGA Timing Analysis''' (readout_card.tan.rpt):

== Revision 5.0.5 (UBC only) ==
* '''Filename:'''
** rc_v05000005_04sep2009.sof

* '''Features:'''
** Based on rev. 5.0.2
** changed the low-pass-filter to f(3db)=75Hz for f(sample)=30000.

* '''Details:'''
** quartus.ini file was '''not''' present in synth directory.

* '''Bugs:'''
** negative inputs to the filter cause filter to have a non-flat pass-band region. may have to do with sign-handling...

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
* '''FPGA Timing Analysis''' (readout_card.tan.rpt):

== Revision 5.0.4 ==
* '''Filename:'''
** rc_v05000004_28aug2009.sof

* '''Features:'''
** Based on rev. 5.0.2
** BUG Fix: handles 14-bit flux quanta (changed the multiplier to unsigned)
** BUG Fix: changed standard logic vector extension from signed to unsigned in flux-jumping slave.
** IMPORTANT: Must be used in conjunction with firmware rev. 5.0.0+ of all other cards.

* '''Details:'''

* '''Bugs:'''
** None so far.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,170 / 41,250 ( 63 % ) ;
; Total pins ; 358 / 616 ( 58 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;
; DSP block 9-bit elements ; 76 / 112 ( 68 % ) ;
; Total PLLs ; 1 / 6 ( 17 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.541 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.612 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 15.398 ns ;

== Revision 5.0.2 (buggy) ==
* '''Filename:'''
** rc_v05000002_test00_tagged.sof

* '''Features:'''
** Based on rev. 5.0.1
** Fixed a bug in wbs_frame_data that stored data incorrectly if reporting 1 or 2 pixels only.
** IMPORTANT: Must be used in conjunction with firmware rev. 5.0.0+ of all other cards.

* '''Details:'''

* '''Bugs:'''
** None so far.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,186 / 41,250 ( 63 % ) ;
; Total pins ; 358 / 616 ( 58 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;
; DSP block 9-bit elements ; 76 / 112 ( 68 % ) ;
; Total PLLs ; 1 / 6 ( 17 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.755 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.979 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.067 ns ;

== Revision 5.0.1 (buggy) (Filter + Raw + Rectangle, 2 LVDS) ==
* '''Filename:'''
** rc_v05000001_26may2009.sof

* '''Features:'''
** Combines features in rev. 5.0.0 (2 LVDS Lines) and rev. 4.0.e (Filtered + Raw), with the NEW rectangle mode.
** IMPORTANT: Must be used in conjunction with firmware rev. 5.0.0+ of all other cards.

* '''Details:'''
** [[CVS Diff Between sys_v05000000 and rc_v05000001]]

* '''Bugs:'''
** Has a bug in wbs_frame_data that stored data incorrectly if reporting 1 or 2 pixels only.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,565 / 41,250 ( 64 % ) ;
; Total pins ; 358 / 616 ( 58 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 1,405,440 / 3,423,744 ( 41 % ) ;
; DSP block 9-bit elements ; 78 / 112 ( 70 % ) ;
; Total PLLs ; 1 / 6 ( 17 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.656 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.861 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 14.167 ns ;

== Revision 5.0.0 (Filter Only, 2 LVDS) ==
* '''Filename:'''
** rc_v05000000_22dec2008.sof (tagged as sys_v05000000_22dec2008)

* '''Features:'''
** IMPORTANT: Must be used in conjunction with firmware v05000000+ of all other cards!!!
** Adds the ability to read out one column of data continuously from readout cards
** Adds data mode 11, which is an engineering mode. Data points are 32-bits, and bits [9..3]=row_index, [2..0]=column_index. This mode is useful for determining which pixels one is reading out in the array, in column mode for example.

* '''Details:'''
** [[CVS Diff Between rc_v0400000c and sys_v05000000]]

* '''Bugs:'''
** None so far.

* '''Synthesis Notes:'''
** The quartus.ini file was not present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
+---------------------------------------------------------------------+
; Fitter Summary ;
; Total logic elements ; 26,607 / 41,250 ( 65 % ) ;
; Total pins ; 358 / 616 ( 58 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 406,016 / 3,423,744 ( 12 % ) ;
; DSP block 9-bit elements ; 76 / 112 ( 68 % ) ;
; Total PLLs ; 1 / 6 ( 17 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.558 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.892 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.987 ns ;

== Revision 4.0.f (Filter + Raw, 1 LVDS) ==
* '''Filename:'''
** rc_v0400000f_12feb2010.sof

* '''Features:'''
** Based on 4.0.e and in parallel with 5.0.9 (equivalent version, clamping is not included)
** Incorporates fixes that were done to flux-jumping between 5.0.2 - 5.0.4 - 5.0.9. Namely:
*** Changes a multiplier from signed to unsigned (in fsfb_corr_multplier.vhd).
*** Changes sign extension from signed to unsigned (in flux_quanta_ram_admin.vhd).

* '''Details:'''

* '''Bugs:'''
** None reported yet.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 26,773 / 41,250 ( 65 % ) ;
; Total pins ; 358 / 616 ( 58 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 1,321,984 / 3,423,744 ( 39 % ) ;
; DSP block 9-bit elements ; 76 / 112 ( 68 % ) ;
; Total PLLs ; 1 / 6 ( 17 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.539 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 4.118 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 17.318 ns ;

== Revision 4.0.e (Filter + Raw, 1 LVDS) ==
* '''Filename:'''
** rc_v0400000e_27apr2009.sof

* '''Features:'''
** Based on 4.0.d
** Combines both raw- and filtered-data modes.
** fpga_temp, card_temp, card_id commands are disabled.
** Tested by Matt Hasselfield.

* '''Details:'''

* '''Bugs:'''
** fpga_temp, card_temp, card_id commands are disabled.

* '''Synthesis Notes:'''
** The quartus.ini file '''was''' present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 27,048 / 41,250 ( 66 % ) ;
; Total pins ; 358 / 616 ( 58 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 1,321,984 / 3,423,744 ( 39 % ) ;
; DSP block 9-bit elements ; 76 / 112 ( 68 % ) ;
; Total PLLs ; 1 / 6 ( 17 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.675 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.907 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.728 ns ;

== Revision 4.0.d (Raw Only, 1 LVDS) ==
* '''Filename:''' rc_v0400000d_20090417.sof

* '''Features:'''
** Based on v4.0.c, but has the filter removed, and implements a single 65536-index RAM block for storing 50 MHz raw-data samples.
** The firmware takes a new command called readout_col_index which specifies which column to capture raw data from.
** Other than readout_col_index, the firmware functions the same as previous raw-data firmware, including then need to issue a capture_raw command.
** For more information on raw-data, see: http://e-mode.phas.ubc.ca/mcewiki/index.php/Raw-mode_readout
** This firmware also integrates some of the improvements that were implemented in 4.4.0, like the removal of the tga_o signal from an FSM in dispatch_wishbone.vhd.

* '''Details:'''
** Differences between 4.0.c and 4.0.d
U system/test/source/tb/tb_cc_rcs_bcs_ac.vhd
U all_cards/dispatch/source/rtl/dispatch_wishbone.vhd
U library/sys_param/source/rtl/wishbone_pack.vhd
U readout_card/adc_sample_coadd/source/rtl/adc_sample_coadd.vhd
U readout_card/adc_sample_coadd/source/rtl/adc_sample_coadd_pack.vhd
U readout_card/flux_loop/source/rtl/flux_loop.vhd
U readout_card/flux_loop/source/rtl/flux_loop_pack.vhd
U readout_card/flux_loop_ctrl/source/rtl/flux_loop_ctrl.vhd
U readout_card/flux_loop_ctrl/source/rtl/flux_loop_ctrl_pack.vhd
U readout_card/flux_loop_ctrl/source/tb/tb1_flux_loop_ctrl.vhd
U readout_card/flux_loop_ctrl/source/tb/tb2_flux_loop_ctrl.vhd
U readout_card/fsfb_calc/source/rtl/fsfb_fltr_regs.vhd
U readout_card/fsfb_corr/source/rtl/fsfb_corr.vhd
U readout_card/readout_card/source/rtl/readout_card.vhd
U readout_card/readout_card/source/rtl/readout_card_pack.vhd
U readout_card/wbs_frame_data/source/rtl/wbs_frame_data.vhd
U readout_card/wbs_frame_data/source/rtl/wbs_frame_data_pack.vhd

* '''Bugs:'''
** None so far.
** fpga_temp, card_temp, card_id commands are not supported.

* '''Synthesis Notes:'''
** The quartus.ini file was present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 24,554 / 41,250 ( 60 % ) ;
; Total pins ; 358 / 616 ( 58 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 1,262,592 / 3,423,744 ( 37 % ) ;
; DSP block 9-bit elements ; 76 / 112 ( 68 % ) ;
; Total PLLs ; 1 / 6 ( 17 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.991 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.864 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 17.052 ns ;

== Revision 4.4.1 ==
* '''Filename:''' rc_v04040001_21nov2008

* '''Features:'''
** Fixes a bug that froze up the firmware if any of the following commands were issued: CARD_ID_ADDR, CARD_TEMP_ADDR, FPGA_TEMP_ADDR in 4.4.0 only.

* '''Details:'''
** The bug fix include adding more logic to the wishbone ack path (readout_card.vhd), which subsequently decreased the minimum clock setup time to 1.588ns. The new logic will catch errors that the old logic wouldn't have, and is now consistent with the firmware on all the other cards. However, if timing becomes an issue, the logic may have to revert back to that which was in version 4.0.c.

* '''Bugs:'''
** None so far.

* '''Synthesis Notes:'''
** The quartus.ini file was not present in the synth directory during synthesis.

* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 27,241 / 41,250 ( 66 % ) ;
; Total pins ; 358 / 616 ( 58 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 405,504 / 3,423,744 ( 12 % ) ;
; DSP block 9-bit elements ; 76 / 112 ( 68 % ) ;
; Total PLLs ; 1 / 6 ( 17 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.588 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.585 ns ;
; Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 17.057 ns ;

== Revision 4.4.0 (buggy) ==
* '''Filename:''' rc_v04040000_02oct2008
* '''Features:'''
** Reinstated the data modes in wbs_frame_data.vhd that were removed in 4.0.c. This firmware has the following modes: '''0, 1, 2, 4, 5, 7, 10'''. The modes that are not present are: '''3''' (raw data), '''6''' (replaced by data_mode = 7), '''8''' (replaced by data_mode = 10), '''9''' (replaced by data_mode = 10). For more information on data modes, see [[Data mode]].
** Re-integrated the id_thermo and fpga_thermo block in the readout_card.vhd top level that was removed in 4.0.c.
** Removed the sticky bit in fsfb_corr.vhd, which was enabled when flux-jumping was turned on. Because the feedback is signed, the sticky bit would usually reflect the value of the 14th bit, except in situations when the number of flux quanta to jump was greater than 1 (i.e. cosmic rays, IV-curves, etc). Flux jumps are made at a maximum rate of one per frame period, so that if the First-Stage Feedback increased past the 13th bit, it would not be reflected in the feedback applied. Now it is.
* '''Details:'''
** Simplified the FSM logic in wbs_frame_data.vhd that determines when to transition from IDLE to WSS1. This was done to lower the number of gates in that path, and ease the timing.
** Removed the z_dat_i port in fsfb_processor.vhd and fsfb_calc_pack.vhd to the fsfb_proc_pidz block, in an effort to make it clearer within that block that the z-term is always = 0.
** Removed the z-term sign extension in fsfb_proc_pidz.vhd, and the [d-term + z-term] adder to free up DSP resources since the z-term is always = 0.
** Adjusted the indentation in fsfb_io_controller.vhd to make the file more readable.
** Moved the tga_o signal out of the dispatch_wishbone.vhd FSM, and made it a continuous assignment. This signal had one of the highest fan-out counts in the RTL design, and actually was impossible to route in Stratix III chips in its previous configuration because of the number of gates on the fan-out. As a consequence of making it a continuous assignment, the Stratix III fitter was able to succeed, and the Stratix I timing characteristics were greatly improved. This is the most significant change in this revision. This change single-handedly increased the minimum slack from 1.282 ns in v0400000c to 2.372 ns (or 56.7 MHz max) in this revision.
* '''Bugs:'''
** The following commands lock up the Readout Card firmware: CARD_ID_ADDR, CARD_TEMP_ADDR, FPGA_TEMP_ADDR.
** fb_const0 commands to channel 0 do not work. The value is stored in the register, but not applied to the DAC. Thus, read-back returns the correct value, but the DAC does not
* '''Synthesis Notes:'''
** The quartus.ini file was not present in the synth directory during synthesis.
* '''FPGA Resource Usage''' (readout_card.fit.rpt):
; Total logic elements ; 27,099 / 41,250 ( 66 % ) ;
; Total pins ; 358 / 616 ( 58 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 406,016 / 3,423,744 ( 12 % ) ;
; DSP block 9-bit elements ; 76 / 112 ( 68 % ) ;
; Total PLLs ; 1 / 6 ( 17 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;

* '''FPGA Timing Analysis''' (readout_card.tan.rpt):
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 2.372 ns ;
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 4.052 ns ;
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.066 ns ;

== Revision 4.0.c ==
* '''Filename:''' rc_v0400000c_15aug2008.sof
* '''Features:'''
** Only has data modes 0, 1, 4, and 10.
** Fixed the bug that exists in 4.0.b, 4.0.a, and 4.0.9 that prevented the fb_const value from being applied to channel zero (wbs_fb_data.vhd).
* '''Details:'''
** Changed a counter in the dispatch block to ease timing constraints in synthesis (dispatch_wishbone.vhd)
** Updated the tagged versions of dispatch.vhd , dispatch_cmd_receive.vhd, and dispatch_reply_transmit.vhd to the version that is used by all the other cards.
** '''Removed''' the fpga_termo (command: '''fpga_temp''') and id_thermo (commands: '''card_temp, card_id''') to ease timing constraints in synthesis (readout_card.vhd)
** Updated the tagged version of fpga_termo.vhd to include the new 'stale bit' feature
** Updated the tagged version of frame_timing_core.vhd to include the new 'err_o' interface
* '''Bugs:'''
** None reported yet
* '''Synthesis Notes:'''
** The quartus.ini file was not present in the synth directory during synthesis.
* '''FPGA Resource Usage:'''
Total logic elements : 25,058 / 41,250 ( 61 % )
Total pins : 358 / 616 ( 58 % )
Total virtual pins : 0
Total memory bits : 400,896 / 3,423,744 ( 12 % )
DSP block 9-bit elements : 76 / 112 ( 68 % )
Total PLLs : 1 / 6 ( 17 % )
Total DLLs : 0 / 2 ( 0 % )

* '''Timing Analysis''' (readout_card.tan.rpt):
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk0' ; 1.282 ns ;
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk2' ; 3.736 ns ;
Clock Setup: 'rc_pll:i_rc_pll|altpll:altpll_component|_clk3' ; 16.665 ns ;

== Revision 4.0.b (buggy) ==
Note: This revision is on a watch list, after the bug detected 15 July 2008. See the bug section for more details.
* '''Filename''' : rc_v0400000b_04aug2008.sof
* '''Features'''
** data_mode 10 is added to provide more filtfb bits (compared to data mode 9) for planet observations. filtered_dat(27 downto 3) & flux_cnt_dat(6 downto 0)

* '''Bugs'''
** An unexplained bug that appeared in 4.0.a and may still be present in 4.0.b is a problem with the readout of channels being clipped out of data reporting. [[Bug 1 Notes]]

* ''' Synthesis note '''
** Quartus.ini removed.

== Revision 4.0.a (buggy) ==
Note: This revision is on a watch list, after the bug detected 15 July 2008. See the bug section for more details.
* '''Filename''' : rc_v0400000a_07jul2008.sof
* '''Bug Fix'''
** mce_status and adc_offset/flx_quanta commands do not fail after power up.
* ''' Synthesis note '''
** Quartus.ini removed.

* '''Bugs'''
** Seems to clip out channel 0 from data reporting.

== Revision 4.0.9 (buggy) ==
* '''Filename''' : rc_v04000009_26jun2008.sof
* '''Features'''
** sa_bias and offset DACs only refreshed when new values are written. (in previous versions, DACs were refreshed every frame)
* '''Bugs'''
** fb_const0 commands to channel 0 do not work. The value is stored in the register, but not applied to the DAC. Thus, read-back returns the correct value, but the DAC does not.
** reading flx_quanta and adc_offset right after power up hangs the reply datapath to CC. resetmce clears this error as temporary solution. the problem is caused by first read ack of the wishbone slave.

== Revision 4.0.8 ==
* '''Filename''' : rc_v04000008_26jun2008.sof
* '''Features'''
** The gaini, gainp, gaind resolution increased to 12-bit, i.e. -2048 to 2047 (formerly 10-bit).

* '''Bug fix'''
** the bug associated with gainpid read before mce_reset is fixed.

* ''' Synthesis note '''
** Quartus.ini removed.

== Revision 4.3.7 ==
* '''Filename''' : rc_v04030007_26may2008_raw.sof
* '''Features'''
** 14-bit raw mode enabled to buffer a snapshot of 50MHz samples for 2 frames of row_len * num_rows samples.
** In order to extend the raw-mode to 14-bit, an assumption is made that the raw buffer is not written to while being read. Therefore, make sure there is at least 2*row_len*num_rows*20ns between issuing captr_raw command and reading back the raw data.
** In order to save RAM for raw mode, two memory-intensive features are disabled:
*** low-pass filter disabled ( mixed filtfb data modes 6, 7, 9 are also disabled)
*** PID (gainp0, gaini0, gaind0) readback disabled. one can still set PID values and run servo, but can not read back the values.

== Revision 4.2.7 ==
* '''Filename''' : rc_v04020007_24may2008_raw.sof
* '''Features'''
** raw mode enabled to buffer a snapshot of 50MHz samples for 2 frames of row_len * num_rows samples.
** In order to save RAM for raw mode, two memory-intensive features are disabled:
*** low-pass filter disabled ( mixed filtfb data modes 6, 7, 9 are also disabled)
*** PID (gainp0, gaini0, gaind0) readback disabled. one can still set PID values and run servo, but can not read back the values.
* '''Bug fix'''
** the bug associated with reading from raw-buffer is fixed.

== Revision 4.1.7 ==
* '''Filename''' : rc_v04010007_25apr2008_raw.sof
* '''Features'''
** raw mode enabled to buffer a snapshot of 50MHz samples for 2 frames of row_len * num_rows samples.
** In order to save RAM for raw mode, two memory-intensive features are disabled:
*** low-pass filter disabled ( mixed filtfb data modes 6, 7, 9 are also disabled)
*** PID (gainp0, gaini0, gaind0) readback disabled. one can still set PID values and run servo, but can not read back the values.
* '''Bugs'''
** after each readout frame, raw-buffer readout counter falls behind by 3 and this causes skipping 3 50MHz samples in the data stream and column-data being messed up in subsequent frames. Data can be rearranged by post processing.

== Revision 4.0.6 (buggy) ==
* '''Filename''' : rc_v04000006_15feb2008.sof or .pof
* '''Features'''
** '''bugfix''': unreliable reset due to unsafe and incomplete state machines is fixed.
** '''bugfix''': flux_jump sign problem fixed, so far proved in const_mode, to be tested in servo_mode with cold setup.
** servo_mode=2 or ramp previously only went from 0 to ramp_amp, but now goes from -8192 to -8192+ramp_amp
** new commands are added: ''scratch'' and ''card_type''. Scratch takes 8 values and can be used by software to detect reset.
** slot_id and fw_rev are now integrated as part of all_cards.vhd
** lvds_tx_b=0, This will allow Clock Card to use the secondary backplane lvds line and check whether RC is plugged in.
** filter_coeff in misc_banks_admin commented as it is not implemented and causes timing problems.

* '''Bugs'''
** reading gainp/gaini/gaind right after power up hangs the reply datapath to CC. resetmce clears this error as temporary solution. the problem is caused by first read ack of pid_ram_admin.
** slot_id is only set after a resetmce is issued. (using the latest all_cards in the next revision will fix this)
** has spurious spikes on channel 7 data, which max out the integral, and cause the detectors to come unlocked. This firmware officially meets timing requirements, but the bug could be due to marginal timing on the longest data paths, i.e. ~0.1 ns in some cases.

== Revision 4.0.5 ==
* '''Filename''' : rc_v04000005_01nov2007.sof or .pof
* '''Features'''
** data mode 9 (mixed filt + flux jump) with windowing readjusted compared to data mode 8

* '''Bugs'''
** unreliable resetmce. Sometimes, firmware waked up non-responsive on lvds lines.
** In data mode 5 and 9, flux-jump counter is not reported properly due to a sign error. However, flux jumping works fine.

== Revision 3.0.19 ==
* '''Filename''' : rc_v03000019_16feb2007_raw.sof (no pof as one is not likely to run with this as regular firmware)
* '''Features'''
** data mode 3 is enabled.
** filter is disabled as a compromise to fit the raw-mode buffer.

* '''Bugs'''
** unreliable resetmce. Sometimes, firmware waked up non-responsive on lvds lines.

== Old Firmware Revisions ==
* '''4.0.4''': rc_v04000004_11oct2007.sof data mode 8 added (mixed filt + flux jump)
* '''4.0.3''': rc_v04000003_19sep2007.sof data mode 7 bit split readjusted to 10b error being bit 4 to 14
* '''4.0.2''': rc_v04000002_11sep2007.sof pid resolution increased to 10b, data mode 7 added
* '''4.0.1''': rc_v04000001_06sep2007.sof
* '''4.0.0''': rc_v04000000_29aug2007.sof supports readout_row_index * [[ bugs ]]

= To-Do List =
* Moved to the Internal Wiki. Please do not list anything here.

= RC Synthesis Notes =
# Quartus.ini file had to exist in synth directory up to revision 4.0.a due to a bug that started in Quartus 6.1 and would synthesize away arbitrary parts of readout card. We contacted Altera at the time and they provided us the ini file. We have stopped using this file starting with rc_v04000008, although v04000009 does use it. This file needs to be used when Quartus synthesizes out blocks of firmware. If this occurs, the utilization drops well below 66%. If posssible, avoid using this file, because it causes timing violations.
# Timing: There is no "lock region" defined for readout card. Timing on readout card is tight and since version 3 or so any new feature would initially fail timing till some synthesis options were tweaked. One path that remains to be consistently marginal is from addr_gen counter (i.e. tga_o counter) in dispatch_wishbone.vhd to wishbone slaves particularly misc_banks_admin.vhd. Modules that are rewritten to address timing concerns are fsfb_corr, all_cards, misc_banks_admin, and finally instantiating an lpm counter instead of a counter from components library. Surprisingly, the lpm counter reduced 87 failures to 37, although looking at the technology map viewer, it seemed that they were both synthesized the same.
# Compile time: This was at some point 4.5 hours, after going to dual core PC, this was reduced to 35 minutes. After extending pid gains to 12b and fixing offset/sa_bias update code, the compile time increased to 1.5hr again with utilization up to ~70%.
# wbs_fb_storage, ram_8x64, pid_ram had to be regenerated using latest (Q7.2) MegaWizard to get rid of the bug associated with failure to read after power up until a reset was issued.
# During simulations, the initialization of RAM block with .hex files needs to be disabled. This is done by commenting out the following lines from the MegaWizard generated Megafunction files (remember to un-comment them before synthesizing the code):
lpm_file => "C:/scuba2_repository/cards/readout_card/fsfb_calc/source/rtl/ram_40x64.hex", and
lpm_file : STRING;

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